WO2017008410A1 - 一种薄膜晶体管结构及其制备方法 - Google Patents

一种薄膜晶体管结构及其制备方法 Download PDF

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WO2017008410A1
WO2017008410A1 PCT/CN2015/092566 CN2015092566W WO2017008410A1 WO 2017008410 A1 WO2017008410 A1 WO 2017008410A1 CN 2015092566 W CN2015092566 W CN 2015092566W WO 2017008410 A1 WO2017008410 A1 WO 2017008410A1
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layer
source
angstroms
semiconductor oxide
drain layers
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PCT/CN2015/092566
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English (en)
French (fr)
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李金明
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深圳市华星光电技术有限公司
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Priority to US14/892,650 priority Critical patent/US9899534B2/en
Publication of WO2017008410A1 publication Critical patent/WO2017008410A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/467—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the invention relates to the field of wafer manufacturing and display technology, in particular to a thin film transistor structure and a preparation method thereof.
  • LCD Display represents the rapid rise of flat panel display (FPD) technology.
  • TFT-LCD thin film transistor liquid crystal flat panel display
  • Thin film transistor liquid crystal flat panel display is a kind of active matrix liquid crystal display device. Each liquid crystal pixel on the display screen is driven by a thin film transistor integrated behind the pixel, and the reliability of the thin film transistor (TFT) for the display And color realism and other important influences, is an important part of this type of display.
  • TFT thin film transistor
  • a TFT Thin Film Transistor
  • the back channel etch structure TFT mainly comprises a substrate, a gate electrode, a gate insulating layer, a semiconductor layer, and a source and drain layer (including a drain and a source) located above the semiconductor layer and the gate insulating layer. ).
  • the source and drain layers are deposited on the gate insulating layer and the semiconductor layer, and are obtained by a wet etching process at a position corresponding to the semiconductor layer. Since the strong acid and its mixture are required in the wet etching process, the semiconductor layer at the back channel is easily destroyed.
  • a-IGZO film In the current TFT devices, a large amount of semiconductor layer material is used as an a-IGZO film, which has advantages such as high carrier mobility, stability and uniformity, and has a very broad application prospect.
  • a medium such as water, oxygen and light
  • a-IGZO film it has been reported that the contact of a medium such as water, oxygen and light with the a-IGZO film will affect the characteristics of the TFT element. Therefore, more technicians use a back channel protection structure TFT to provide a protective layer on the semiconductor layer.
  • the main difference between the back channel protection structure TFT and the back channel etch structure TFT is that an etch stop layer is further disposed on the semiconductor layer for protecting the semiconductor layer from damage due to the etching process.
  • the invention encompasses both aspects.
  • the present invention provides a thin film transistor structure including a substrate, a gate electrode, a gate insulating layer, a semiconductor oxide layer, a source/drain layer, a passivation layer, and a transparent conductive layer disposed in order from bottom to top.
  • a thin film transistor structure including a substrate, a gate electrode, a gate insulating layer, a semiconductor oxide layer, a source/drain layer, a passivation layer, and a transparent conductive layer disposed in order from bottom to top.
  • an etch barrier layer is formed by etching, and the semiconductor oxide layer and the etch barrier layer are respectively activated by heating to become a semiconductor layer and an insulating layer.
  • Floor Corresponding to the source and drain layers above the semiconductor oxide layer, an etch barrier layer is formed by etching, and the semiconductor oxide layer and the etch barrier layer are respectively activated by heating to become a semiconductor layer and an insulating layer.
  • the source and drain layers are recessed toward a window thereof, and the etch barrier layer is received in the window and connected to the source and drain layers, the etch barrier layer The thickness is smaller than the source and drain layers, and the passivation layer covers the etch barrier layer and the source and drain layers.
  • the source and drain layers refer to a layer structure for forming two electrodes of a source and a drain, and the source and drain layers are etched into the interior thereof to form a concave window.
  • the two sides of the window are the source and the drain, respectively.
  • the substrate is a glass substrate.
  • the material of the gate is a metal material.
  • the gate is one or more of Al, Mo, Nd.
  • the gate is Al/Mo.
  • the thickness of the gate is 2000 to 5500 angstroms, and the thickness range includes any specific point value thereof, for example, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms or 2,500 angstroms.
  • the gate insulating layer is an SiOx layer or a composite layer of SiNx and SiOx.
  • the gate insulating layer is a composite layer of SiNx and SiOx.
  • the thickness of the gate insulating layer is 1500 to 4000 angstroms, and the thickness range includes any specific point value thereof, for example, 1500 angstroms, 1800 angstroms, 2000 angstroms, 2200 angstroms, 2500 angstroms, 3000 angstroms, 3300 angstroms, 3500 angstroms, 3800 angstroms or 4000 angstroms.
  • the semiconductor oxide layer is a metal oxide layer.
  • the metal oxide layer is one or more of a ZnO layer, an In 2 O 3 layer, an IZO layer or an IGZO layer.
  • the semiconductor oxide layer is an IGZO layer.
  • the semiconductor oxide layer has a thickness of 400 to 1500 angstroms, and the thickness range includes any specific point value thereof, for example, 400 angstroms, 500 angstroms, 700 angstroms, 900 angstroms, 1000 angstroms, 1200 angstroms or 1500 angstroms
  • the source and drain layers are composite layers
  • the underlayer of the composite layer is a ZnO (Al) layer
  • the top layer is a metal material.
  • the metal material of the top layer of the source and drain layers is a mixture of one or more of Al, Mo, and Nd.
  • the metal material is Al/Mo.
  • the source and drain layers have a bottom layer thickness of 300 to 1000 angstroms, and the thickness range includes any specific point value thereof, for example, 300 angstroms, 400 angstroms, 500 angstroms, and 600 angstroms.
  • the top layer thickness of the source and drain layers is 1000-6000 angstroms, and the thickness range includes any specific point value thereof, for example, 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5,000 angstroms, 5,500 angstroms, or 6,000 angstroms.
  • the etch barrier layer is a ZnO (Al) layer.
  • the etching barrier layer has a thickness of 50 to 500 angstroms, and the thickness range includes any specific point value thereof, for example, 50 angstroms, 100 angstroms, 150 angstroms, 200 angstroms, 250 angstroms, 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms or 500 angstroms.
  • the passivation layer is an SiOx layer or a composite layer of SiNx and SiOx.
  • the passivation layer is a composite layer of SiNx and SiOx.
  • the SiOx layer in the passivation layer is in contact with the etch stop layer and the source drain layer.
  • the passivation layer has a thickness of 1500 to 4000 angstroms, and the thickness range includes any specific point value thereof, for example, 1500 angstroms, 1800 angstroms, 2000 angstroms, 2200 angstroms, 2500 angstroms. , 3000 angstroms, 3,300 angstroms, 3,500 angstroms, 3,800 angstroms, or 4,000 angstroms.
  • the material of the transparent conductive layer is one or more of ITO, nano silver wire, IMO, ATO, FTO or ATO.
  • ITO refers to a doping system of In 2 O 3 :Sn
  • IMO refers to a doping system of In 2 O 3 :Mo
  • ATO refers to a doping system of SnO 2 :Sb
  • FTO refers to a doping of SnO 2 :F
  • ZAO refers to a doping system of ZnO:Al.
  • the material of the transparent conductive layer is ITO.
  • the transparent conductive layer has a thickness of 300 to 1000 angstroms, and the thickness range includes any specific point value thereof, for example, 300 angstroms, 400 angstroms, 500 angstroms, 600 angstroms, and 700 angstroms. 800 angstroms, 900 angstroms or 1000 angstroms.
  • the present invention provides a method of fabricating the above-described thin film transistor structure, comprising the following steps:
  • a transparent conductive layer is deposited over the passivation layer.
  • the substrate is a glass substrate.
  • the gate electrode is deposited on a substrate by a physical vapor deposition method, and the gate electrode having a pattern is sequentially formed by a yellow light process and an etching process.
  • the gate is a metal material.
  • the gate is one or more of Al, Mo, Nd.
  • the gate is Al/Mo.
  • the thickness of the gate is 2000-5500 angstroms, and the thickness range includes any specific point value thereof, such as 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, or 2500 angstroms.
  • the gate insulating plate is deposited on the etched gate by a plasma enhanced chemical vapor deposition method.
  • the gate insulating layer is an SiOx layer or a composite layer of SiNx and SiOx.
  • the gate insulating layer is a composite layer of SiNx and SiOx.
  • the thickness of the gate insulating layer is 1500-4000 angstroms, and the thickness range includes any specific point value thereof, for example, 1500 angstroms, 1800 angstroms, 2000 angstroms, 2200 angstroms, 2500 angstroms, 3000 angstroms, 3300 angstroms. , 3,500 angstroms, 3,800 angstroms or 4000 angstroms.
  • the semiconductor oxide layer is deposited on the gate insulating plate by a physical vapor deposition method, and the semiconductor having a pattern is sequentially formed by a yellow light process and an etching process. Oxide layer.
  • the semiconductor oxide layer is a metal oxide layer.
  • the metal oxide layer is one or more of a ZnO layer, an In 2 O 3 layer, an IZO layer or an IGZO layer.
  • the semiconductor oxide layer is an IGZO layer.
  • the semiconductor oxide layer has a thickness of 400 to 1500 angstroms, and the thickness range includes any specific point value thereof, for example, 400 angstroms, 500 angstroms, 700 angstroms, 900 angstroms, 1000 angstroms, 1200 angstroms, or 1500 angstroms. .
  • Source Drain Layer-Specific Further, a physical vapor deposition method is employed in the semiconductor oxide The source and drain layers are deposited on the layer.
  • the source and drain layers on the semiconductor oxide layer first depositing a bottom layer of the source and drain layers, and then depositing a top layer of the source and drain layers to form the source and drain layers A composite layer having a two-layer structure.
  • the bottom layer of the composite layer is a ZnO (Al) layer
  • the top layer is a metal material.
  • the metal material of the top layer of the source and drain layers is a mixture of one or more of Al, Mo, and Nd.
  • the metal material is Al/Mo.
  • the source and drain layers have a bottom layer thickness of 300 to 1000 angstroms, and the thickness range includes any specific point value thereof, for example, 300 angstroms, 400 angstroms, 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, and 900 angstroms.
  • the source and drain layers have a top layer thickness of 1000 to 6000 angstroms, and the thickness range includes any specific point values thereof, such as 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms. , 4000 angstroms, 4500 angstroms, 5000 angstroms, 5,500 angstroms or 6,000 angstroms.
  • etch barrier layer Further, after depositing a composite layer forming the source and drain layers, a portion of the source and drain layers above the semiconductor oxide layer and other portions of the source and drain layers The process is performed by a yellow light process and an etch process, wherein a portion of the source and drain layers above the semiconductor oxide layer forms an etch stop layer after etching, and the structure of the etch stop layer is The structure of the bottom layer of the source drain layer.
  • the etch barrier layer is a ZnO (Al) layer.
  • the etch barrier layer has a thickness of 50 to 500 angstroms, and the thickness range includes any specific point value thereof, for example, 50 angstroms, 100 angstroms, 150 angstroms, 200 angstroms, 250 angstroms, 300 angstroms, and 350 angstroms. 400 angstroms, 450 angstroms or 500 angstroms.
  • the semiconductor oxide layer and the etch barrier layer are heated and activated in an oven to activate the semiconductor oxide layer into a semiconductor layer, the engraving
  • the etch barrier layer is oxidized to an insulating layer.
  • the activation temperature of the activation process is 250 to 450 ° C, and the temperature range includes any specific point value thereof, for example, 250 ° C, 300 ° C, 350 ° C, 400 ° C or 450 ° C;
  • the time of the activation process is 20 to 120 minutes, and the time range includes any specific point value thereof, such as 20 min, 40 min, 60 min, 80 min, 100 min or 120 min.
  • the passivation layer is deposited on the source and drain layers and the etch barrier layer by a physical vapor deposition method, and then sequentially obtained by a yellow light process and an etching process.
  • a passivation layer with a pattern is deposited on the source and drain layers and the etch barrier layer by a physical vapor deposition method, and then sequentially obtained by a yellow light process and an etching process.
  • the passivation layer is heated and activated, and then patterned.
  • the passivation layer is an SiOx layer or a composite layer of SiNx and SiOx.
  • the passivation layer is a composite layer of SiNx and SiOx.
  • the SiOx layer in the passivation layer is a bottom layer in contact with the etch stop layer.
  • the passivation layer has a thickness of 1500 to 4000 angstroms, and the thickness range includes any specific point value thereof, for example, 1500 angstroms, 1800 angstroms, 2000 angstroms, 2200 angstroms, 2500 angstroms. , 3000 angstroms, 3,300 angstroms, 3,500 angstroms, 3,800 angstroms, or 4,000 angstroms.
  • the transparent conductive layer is deposited on the passivation layer by a physical vapor deposition method, and then a transparent conductive layer having a pattern is sequentially formed by a yellow light process and an etching process.
  • the etched transparent conductive layer having a pattern is a pixel electrode.
  • the material of the transparent conductive layer is one or more of ITO, nano silver wire, IMO, ATO, FTO or ATO.
  • ITO refers to a doping system of In 2 O 3 :Sn
  • IMO refers to a doping system of In 2 O 3 :Mo
  • ATO refers to a doping system of SnO 2 :Sb
  • FTO refers to a doping of SnO 2 :F
  • ZAO refers to a doping system of ZnO:Al.
  • the material of the transparent conductive layer is ITO.
  • the transparent conductive layer has a thickness of 300 to 1000 angstroms, and the thickness range includes any specific point value thereof, for example, 300 angstroms, 400 angstroms, 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, and 900 angstroms. Ai or 1000 angstroms.
  • the present invention has the following beneficial effects:
  • the etch barrier layer is not separately deposited, but the ZnO (Al) is changed by performing a series of operations such as photolithography, etching, ion implantation, and heat activation on the source and drain layers using the composite layer structure.
  • the O content changes the conductivity of the etch barrier layer, thereby obtaining an etch barrier layer having a function of protecting the semiconductor oxide layer and having good insulation properties, that is, the etch barrier layer of the present invention is a source drain Part of the layer.
  • Such a structure can reduce the size of the thin film transistor as a whole by reducing the thickness of the etch barrier layer, so that the thin film transistor has more design space and the structure is optimized; on the other hand, by forming an etch having practical functions.
  • the barrier layer can effectively reduce the influence of water, oxygen and energy on the semiconductor oxide layer and protect the performance of the thin film transistor structure.
  • FIG. 1 is a schematic view showing the structure of a thin film transistor of Embodiment 1.
  • Figure 2 is a detailed structural view of the structure at A in Figure 1 (the passivation layer has been omitted).
  • Figure 3 is one of the steps of the preparation method of the second embodiment.
  • Figure 4 is one of the steps of the preparation method of the second embodiment.
  • Figure 5 is one of the steps of the preparation method of the second embodiment.
  • Figure 6 is one of the steps of the preparation method of the second embodiment.
  • Figure 7 is a detailed structural view of the structure at B in Figure 6.
  • Figure 8 is one of the steps of the preparation method of the second embodiment.
  • Figure 9 is a detailed structural view of the structure at C in Figure 8.
  • Figure 10 is one of the steps of the preparation method of the second embodiment.
  • Figure 11 is one of the steps of the preparation method of the second embodiment.
  • This embodiment provides a thin film transistor structure, as shown in FIG. 1, including a substrate 10, a gate electrode 20, a gate insulating layer 30, a semiconductor oxide layer 40, a source/drain layer 50, and a blunt layer disposed in order from bottom to top.
  • Layer 60 and transparent conductive layer 70 are transparent conductive layers.
  • the substrate 10 is a glass substrate
  • the gate electrode 20 is disposed on the substrate 10, and the length (the length in the left-right direction in FIG. 1) is smaller than the substrate length, and the material used for the gate electrode 20 is Al/Mo and the thickness is 3000 angstroms.
  • the gate insulating layer 30 is surrounded by the outside of the gate electrode 20 and is in contact with the side and top surfaces of the gate electrode 20, covering the substrate 10 and the gate electrode 20, which is a composite layer of SiNx and SiOx, and has a thickness of 3000 angstroms.
  • the semiconductor oxide layer 40 is disposed above the gate insulating layer 30, and its length (the length in the left-right direction in FIG. 1) is the same as the length of the top surface of the gate insulating layer, and is an IGZO layer having a thickness of 1000 ⁇ .
  • the source and drain layers 50 are surrounded by the outside of the semiconductor oxide layer 40, and are in contact with the side and top surfaces of the semiconductor oxide layer 40, respectively, over the gate insulating layer 30 and the semiconductor oxide layer 40.
  • the source and drain layer 50 is a composite layer. As shown in FIG. 2, the source and drain layers 50 include a top layer 51 and a bottom layer 52.
  • the bottom layer 52 is a ZnO (Al) layer having a thickness of 500 angstroms and the top layer 51 is an Al/Mo layer.
  • the Mo layer is located above the Al layer to a thickness of 3000 angstroms.
  • the source/drain layer 50 located above the semiconductor oxide layer 40 is recessed toward the inside thereof (ie, the downward direction in FIG.
  • the etch stop layer 80 is formed by etching the top layer 51 from the source and drain layer 50 located above the semiconductor oxide layer 40, leaving only the bottom layer 52, which is a ZnO (Al) layer, and the length (FIG. 1) The length in the left-right direction is smaller than the length of the semiconductor oxide layer, and the thickness thereof is 300 angstroms.
  • the source and drain layers 50 are etched to form the etch barrier layer 80, the source and drain layers 50 are formed with a window recessed toward the interior thereof, thereby causing source and drain on both sides of the etch barrier layer 80.
  • the pole layers respectively form a source and a drain.
  • the IGZO layer as the semiconductor oxide layer can be changed from a semiconductor oxide layer to a semiconductor layer after being heated, and the ZnO (Al) layer as an etch barrier can be heated and activated by increasing the oxygen content. It becomes an insulating layer with high resistance and strong insulation.
  • a passivation layer 60 overlies the source and drain layers 50 and the etch stop layer 80, which is a composite layer of SiNx and SiOx, having a thickness of 3000 angstroms.
  • the SiOx layer is located on the bottom layer of the passivation layer and is in contact with the etch barrier layer. Since the content of oxygen element in the SiOx layer is large, it contributes to the improvement of the insulation of the etch barrier layer.
  • the passivation layer 60 is further provided with a contact window 61 for matching the transparent conductive layer 70, the contact window 61 is recessed toward the inside of the passivation layer 60, and the thickness of the contact window is the thickness of the passivation layer, that is, the contact window is vertical
  • the straight direction runs through the passivation layer.
  • the transparent conductive layer 70 is used for electrically connecting the thin film transistor and the storage capacitor (not shown), and the end connected to the thin film transistor is substantially above the passivation layer, and the position is parallel to the semiconductor oxide layer.
  • the etch barrier and the gate are just staggered.
  • a convex portion 71 protrudes downward from the lower surface edge of the transparent conductive layer 70, and the convex portion 71 is just received in the contact window 61 of the passivation layer to realize the transparent conductive layer 70 and the source/drain layer 50. contact.
  • the transparent conductive layer 70 is an ITO layer having a thickness of 500 angstroms.
  • This embodiment provides a method for fabricating a thin film transistor structure.
  • a glass substrate 10 is first prepared, a gate electrode 20 is deposited on the substrate by a physical vapor deposition (PVD) method, and a patterned gate electrode 20 is sequentially formed by a yellow light process and an etching process.
  • the gate 20 is made of Al/Mo, has a thickness of 3000 angstroms, and has a length smaller than the length of the glass substrate 10.
  • a gate insulating plate 30 is then deposited on the etched gate 20 by a plasma enhanced chemical vapor deposition method.
  • the gate insulating plate 30 surrounds the outside of the gate electrode 20, is in contact with the side and top surfaces of the gate electrode 20, and covers the substrate 10 and the gate electrode 20, which is a composite layer of SiNx and SiOx, and has a thickness of 3000 angstroms.
  • a semiconductor oxide layer 40 is then deposited on the gate insulating plate 30 by a physical vapor deposition method, and a patterned semiconductor oxide layer 40 is sequentially formed by a yellow light process and an etching process.
  • the semiconductor oxide layer 40 is an IGZO layer having a thickness of 1000 ⁇ and a length equal to the length of the top surface of the gate insulating layer.
  • the source and drain layers 50 are then deposited on the etched semiconductor oxide layer 40 by physical vapor deposition, and the source and drain layers 50 are surrounded by the semiconductor oxide layer 40, respectively, and the semiconductor.
  • the side and top surfaces of the oxide layer 40 are in contact with the gate insulating layer 30 and the semiconductor oxide layer 40.
  • the underlayer 52 of the source and drain layers 50 is first deposited on the semiconductor oxide layer 40, and the top layer 51 of the source and drain layers 52 is deposited, so that the source and drain layers 50 are formed into a two-layer structure.
  • the bottom layer 52 is a ZnO (Al) layer having a thickness of 500 angstroms
  • the top layer 51 is an Al/Mo layer having a thickness of 3000 angstroms.
  • the portion of the source and drain layer 50 above the semiconductor oxide layer 40 and the other portions of the source and drain layer 40 are sequentially processed by a gray mask process and an etching process to make the semiconductor.
  • the source and drain layers above the oxide layer 40 are finally etched as an etch stop layer 80, and the other source and drain layer portions are etched into a patterned source and drain layer 40.
  • the top layer 51 of the source and drain layers is completely etched away, leaving only the underlayer 52, thereby forming an etch stop layer 80, which blocks the etch.
  • the layer is the same as the bottom layer of the source and drain layers, both of which are ZnO (Al) layers, and are etched
  • the barrier layer has a thickness of 300 angstroms and a length less than the length of the semiconductor oxide layer.
  • the source and drain layers 50 are etched to form the etch barrier layer 80, the source and drain layers 50 are formed into a window recessed toward the interior thereof, thereby causing the source and drain layers on both sides of the etch barrier layer 80.
  • the source and the drain are formed correspondingly.
  • oxygen ions are implanted into the etch barrier layer by an ion implantation method to increase the oxygen content in the ZnO (Al) layer.
  • the semiconductor oxide layer and the etch barrier layer are heated and activated in an oven to activate the semiconductor oxide layer into a semiconductor layer, and the etch barrier layer is oxidized to an insulating layer, wherein the heating temperature is 300 ° C, and the activation time It is activated for 60 minutes while introducing air or oxygen.
  • the ZnO (Al) thin film prepared by the non-passing oxygen has the best conductivity and the film also has a higher film.
  • a passivation layer 60 is deposited over the source and drain layers 40 and the etch stop layer 80 by a physical vapor deposition method, and the passivation layer 60 is activated at a high temperature.
  • a patterned passivation layer 60 is formed using a yellow light process and an etch process.
  • the passivation layer 60 is a composite layer of SiNx and SiOx and has a thickness of 3000 angstroms.
  • the SiOx layer is located on the bottom layer of the passivation layer 60 and is in contact with the etch barrier layer 80.
  • the reason why the SiOx layer is disposed on the bottom layer of the passivation layer in this embodiment is because the SiOx layer has a large oxygen content, and when the passivation layer is deposited, it is activated to further improve the ZnO (Al) junction with the SiOx layer.
  • the oxygen content in the layer further increases the insulation of the ZnO (Al) layer.
  • a transparent conductive layer 70 is deposited on the passivation layer 60 by a physical vapor deposition method, and a transparent conductive layer 70 having a pattern is sequentially formed by a yellow light process and an etching process.
  • a contact window 61 for matching the transparent conductive layer 70 is disposed on the passivation layer 60, and the contact window 61 is recessed toward the inside of the passivation layer 60, and the thickness of the contact window is the thickness of the passivation layer, that is, the contact window Wear on the passivation layer.
  • the transparent conductive layer 70 is used for electrically connecting the thin film transistor and the storage capacitor (not shown), and the end connected to the thin film transistor is substantially on the passivation layer, and is disposed at a position opposite to the semiconductor oxide layer, the etch barrier layer, and the gate electrode. Just waiting to be staggered.
  • a convex portion 71 protrudes downwardly from the lower surface edge of the transparent conductive layer 70, and the convex portion 71 is just received in the contact window 61 of the passivation layer to achieve contact between the transparent conductive layer 70 and the source and drain layers.
  • the transparent conductive layer 70 is an ITO layer having a thickness of 500 angstroms.

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Abstract

一种薄膜晶体管结构，包括由下至上依次设置的基板（10）、栅极（20）、栅极绝缘层（30）、半导体氧化物层（40）、源漏极层（50）、钝化层（60）和透明导电层（70），对应于半导体氧化物层上方的源漏极层处，通过刻蚀形成刻蚀阻挡层（80）。一种薄膜晶体管的制造方法，包括在基板上沉积并光刻栅极；在栅极上沉积栅极绝缘层；在栅极绝缘层上沉积并光刻半导体氧化物层；在半导体氧化物层上沉积并光刻源漏极层；在对应于半导体氧化物层上方的源漏极层处，刻蚀形成刻蚀阻挡层；在源漏极层和半导体氧化物层的上方沉积钝化层；在钝化层上沉积透明导电层。本方法未单独沉积刻蚀阻挡层，但通过刻蚀源漏极层形成具有实际功能的刻蚀阻挡层，优化薄膜晶体管结构的同时，保护半导体氧化物层。

Description

一种薄膜晶体管结构及其制备方法 技术领域
本发明涉及晶圆制造领域及显示技术领域，具体是一种薄膜晶体管结构及其制备方法。
背景技术
随着科学技术的快速发展，应用于手机、平板或电脑中的屏幕显示技术正不断地更新迭代，特别是自上世纪90年代以来，随着技术的突破及市场需求的急剧增长，使得以液晶显示(LCD)为代表的平板显示(FPD)技术迅速崛起。尤其是薄膜晶体管液晶平板显示器(TFT-LCD)，其具有性能优良、大规模生产特性好、自动化程度高、原材料成本低廉等诸多优点，因此成为平板显示器市场的主流产品。
薄膜晶体管液晶平板显示器是一类有源矩阵液晶显示设备，该类显示屏上的每个液晶像素点都是由集成在像素点后面的薄膜晶体管来驱动，薄膜晶体管(TFT)对于显示器的响应度及色彩真实度等具有重要影响，是该类显示器中的重要组成部分。
TFT(Thin Film Transistor)，即薄膜晶体管，主要有背沟道刻蚀结构TFT和背沟道保护结构TFT。背沟道刻蚀结构TFT主要包括由下至上依次设置的基板、栅极、栅极绝缘层、半导体层，以及位于半导体层和栅极绝缘层上方的源漏极层(包括漏极和源极)。其中，源漏极层是沉积在栅极绝缘层和半导体层上之后，在对应于半导体层的位置处，通过湿刻蚀制程得到的。由于湿刻蚀制程中需要使用强酸及其混合物，容易使背沟道处的半导体层遭到破坏。
目前的TFT元件中，使用较多的半导体层材料为a-IGZO薄膜，该材料具有载流子迁移率高、稳定性及均匀性佳等方面的优势，具有非常广泛地应用前景。但是有相关报道指出水、氧与光等介质与a-IGZO薄膜的接触将影响TFT元件的特性，因此更多技术人员采用背沟道保护结构TFT，在半导体层上设置保护层。背沟道保护结构TFT与背沟道刻蚀结构TFT的主要区别在于，半导体层上还设有一层刻蚀阻挡层，用于保护半导体层不因刻蚀制程而受到破坏。但是采用该 种结构的TFT时，需要增加一道工序来制作刻蚀阻挡层，影响产品的生产效率。此外，在半导体层上沉积刻蚀阻挡层的工艺仍会对半导体层材料的性能造成影响，并且由于该层的增加，使得TFT的尺寸增大，设计空间变小。
虽然现有技术中已开发有一些不同类型的薄膜晶体管结构，但是出于提高TFT结构性能、延长其使用寿命、扩展TFT矩阵设计空间、改良TFT结构的制备方法等因素的考虑，实有必要对现有技术进行改进，设计一种能够解决上述问题的新型薄膜晶体管结构并提供相应的制备方法。
发明内容
本发明的目的在于提供一种新型的薄膜晶体管结构及其制备方法，主要用于解决现有技术中设置刻蚀阻挡层保护半导体层时所产生的各种问题。
具体地，本发明包括两个方面的内容。
第一个方面，本发明提供一种薄膜晶体管结构，包括由下至上依次设置的基板、栅极、栅极绝缘层、半导体氧化物层、源漏极层、钝化层和透明导电层，在对应于所述半导体氧化物层上方的所述源漏极层处，通过刻蚀形成刻蚀阻挡层，所述半导体氧化物层和所述刻蚀阻挡层经过加热活化后分别成为半导体层和绝缘层。
【具体结构】进一步地，所述源漏极层朝向其内部凹陷形成窗口，所述刻蚀阻挡层容置在所述窗口中且与所述源漏极层连接，所述刻蚀阻挡层的厚度小于所述源漏极层，所述钝化层覆盖在所述刻蚀阻挡层和所述源漏极层上方。
可以理解的是，在本发明中，所述源漏极层是指用于形成源极和漏极两个电极的层结构，所述源漏极层向自身内部刻蚀形成内凹的窗口后，窗口两侧即分别为源极和漏极。
【基板】进一步地，所述基板为玻璃基板。
【栅极-材料】进一步地，所述栅极的材料为金属材料。
可选地，所述栅极为Al、Mo、Nd中的一种或几种。
优选地，所述栅极为Al/Mo。
【栅极-厚度】进一步地，所述栅极的厚度为2000～5500埃，该厚度范围包括了其中的任何具体点值，例如2000埃、2500埃、3000埃、3500埃、4000埃、 4500埃或者2500埃。
【栅极绝缘层-材料】进一步地，所述栅极绝缘层为SiOx层或者SiNx与SiOx的复合层。
优选地，所述栅极绝缘层为SiNx与SiOx的复合层。
【栅极绝缘层-厚度】进一步地，所述栅极绝缘层的厚度为1500～4000埃，该厚度范围包括了其中的任何具体点值，例如1500埃、1800埃、2000埃、2200埃、2500埃、3000埃、3300埃、3500埃、3800埃或者4000埃。
【半导体氧化物层-材料】进一步地，所述半导体氧化物层为金属氧化物层。
可选地，所述金属氧化物层为ZnO层、In2O3层、IZO层或IGZO层中的一种或几种。
优选地，所述半导体氧化物层为IGZO层。
【半导体氧化物层-厚度】进一步地，所述半导体氧化物层的厚度为400～1500埃，该厚度范围包括了其中的任何具体点值，例如400埃、500埃、700埃、900埃、1000埃、1200埃或者1500埃。
【源漏极层-复合层】进一步地，所述源漏极层为复合层，所述复合层的底层为ZnO(Al)层，顶层为金属材料。
可选地，所述源漏极层顶层的金属材料为Al、Mo、Nd中的一种或几种的混合物。
优选地，所述金属材料为Al/Mo。
【源漏极层-厚度】进一步地，所述源漏极层的底层厚度为300～1000埃，该厚度范围包括了其中的任何具体点值，例如300埃、400埃、500埃、600埃、700埃、800埃、900埃或者1000埃，所述源漏极层的顶层厚度为1000～6000埃，该厚度范围包括了其中的任何具体点值，例如1000埃、1500埃、2000埃、2500埃、3000埃、3500埃、4000埃、4500埃、5000埃、5500埃或者6000埃。
【刻蚀阻挡层-材料】进一步地，所述刻蚀阻挡层为ZnO(Al)层。
【刻蚀阻挡层-厚度】进一步地，所述刻蚀阻挡层的厚度为50～500埃，该厚度范围包括了其中的任何具体点值，例如50埃、100埃、150埃、200埃、250埃、300埃、350埃、400埃、450埃或者500埃。
【钝化层-材料】进一步地，所述钝化层为SiOx层或者SiNx与SiOx的复合层。
优选地，所述钝化层为SiNx与SiOx的复合层。
更优选地，所述钝化层中的SiOx层与所述刻蚀阻挡层、所述源漏极层相接触。
【钝化层-厚度】进一步地，所述钝化层的厚度为1500～4000埃，该厚度范围包括了其中的任何具体点值，例如1500埃、1800埃、2000埃、2200埃、2500埃、3000埃、3300埃、3500埃、3800埃或者4000埃。
【透明导电层-材料】进一步地，所述透明导电层的材料为ITO、纳米银线、IMO、ATO、FTO或ATO中的一种或几种。
其中，ITO是指In2O3:Sn的掺杂体系，IMO是指In2O3:Mo的掺杂体系，ATO是指SnO2:Sb的掺杂体系，FTO是指SnO2:F的掺杂体系，ZAO是指ZnO:Al的掺杂体系。
优选地，所述透明导电层的材料为ITO。
【透明导电层-厚度】进一步地，所述透明导电层的厚度为300～1000埃，该厚度范围包括了其中的任何具体点值，例如300埃、400埃、500埃、600埃、700埃、800埃、900埃或者1000埃。
第二个方面，本发明提供一种上述薄膜晶体管结构的制备方法，包括以下步骤：
在基板上沉积并光刻栅极；
在所述栅极上方沉积栅极绝缘板；
在所述栅极绝缘板上方沉积并光刻半导体氧化物层；
在所述半导体氧化物层上方沉积并光刻源漏极层；
在对应于所述半导体氧化物层上方的所述源漏极层处，刻蚀所述源漏极层，形成刻蚀阻挡层；
在所述源漏极层和所述半导体氧化物层的上方沉积钝化层；
在所述钝化层上方沉积透明导电层。
进一步地，所述基板为玻璃基板。
【栅极-具体】进一步地，采用物理气相沉积方法在基板上沉积所述栅极，再依次利用黄光工艺和刻蚀工艺制得具有图形的所述栅极。
进一步地，所述栅极为金属材料。
可选地，所述栅极为Al、Mo、Nd中的一种或几种。
优选地，所述栅极为Al/Mo。
进一步地，所述栅极的厚度为2000～5500埃，该厚度范围包括了其中的任何具体点值，例如2000埃、2500埃、3000埃、3500埃、4000埃、4500埃或者2500埃。
【栅极绝缘板-具体】进一步地，采用等离子增强化学气相沉积方法在已刻蚀好的所述栅极上沉积所述栅极绝缘板。
进一步地，所述栅极绝缘层为SiOx层或者SiNx与SiOx的复合层。
优选地，所述栅极绝缘层为SiNx与SiOx的复合层。
进一步地，所述栅极绝缘层的厚度为1500～4000埃，该厚度范围包括了其中的任何具体点值，例如1500埃、1800埃、2000埃、2200埃、2500埃、3000埃、3300埃、3500埃、3800埃或者4000埃。
【半导体氧化物层-具体】进一步地，采用物理气相沉积方法在所述栅极绝缘板上沉积所述半导体氧化物层，再依次利用黄光工艺和刻蚀工艺制得具有图形的所述半导体氧化物层。
进一步地，所述半导体氧化物层为金属氧化物层。
可选地，所述金属氧化物层为ZnO层、In2O3层、IZO层或IGZO层中的一种或几种。
优选地，所述半导体氧化物层为IGZO层。
进一步地，所述半导体氧化物层的厚度为400～1500埃，该厚度范围包括了其中的任何具体点值，例如400埃、500埃、700埃、900埃、1000埃、1200埃或者1500埃。
【源漏极层-具体】进一步地，采用物理气相沉积方法在所述半导体氧化物 层上沉积所述源漏极层。
进一步地，在所述半导体氧化物层上沉积所述源漏极层时，首先沉积所述源漏极层的底层，再沉积所述源漏极层的顶层，使所述源漏极层形成具有两层结构的复合层。
进一步地，所述复合层的底层为ZnO(Al)层，顶层为金属材料。
可选地，所述源漏极层顶层的金属材料为Al、Mo、Nd中的一种或几种的混合物。
优选地，所述金属材料为Al/Mo。
进一步地，所述源漏极层的底层厚度为300～1000埃，该厚度范围包括了其中的任何具体点值，例如300埃、400埃、500埃、600埃、700埃、800埃、900埃或者1000埃，所述源漏极层的顶层厚度为1000～6000埃，该厚度范围包括了其中的任何具体点值，例如1000埃、1500埃、2000埃、2500埃、3000埃、3500埃、4000埃、4500埃、5000埃、5500埃或者6000埃。
【形成刻蚀阻挡层】进一步地，沉积形成所述源漏极层的复合层后，针对所述源漏极层位于所述半导体氧化物层上方的部分和所述源漏极层的其他部分依次采用黄光工艺和刻蚀工艺进行处理，其中，所述源漏极层位于所述半导体氧化物层上方的部分在刻蚀后形成刻蚀阻挡层，所述刻蚀阻挡层的结构为所述源漏极层底层的结构。
【灰阶光罩】进一步地，在利用黄光工艺处理所述源漏极层时，选用灰阶光罩技术对所述源漏极层和所述刻蚀阻挡层进行图形化处理。
进一步地，所述刻蚀阻挡层为ZnO(Al)层。
进一步地，所述刻蚀阻挡层的厚度为50～500埃，该厚度范围包括了其中的任何具体点值，例如50埃、100埃、150埃、200埃、250埃、300埃、350埃、400埃、450埃或者500埃。
【离子注入】进一步地，形成所述刻蚀阻挡层后，利用离子注入方法增加所述刻蚀阻挡层中氧元素的含量。
【活化】进一步地，采用离子注入方法后，在烘箱中加热活化所述半导体氧化物层和所述刻蚀阻挡层，使所述半导体氧化物层活化为半导体层，所述刻 蚀阻挡层氧化为绝缘层。
【活化条件】进一步地，所述活化过程的加热温度为250～450℃，该温度范围包括了其中的任何具体点值，例如250℃、300℃、350℃、400℃或450℃；所述活化过程的时间为20～120min，该时间范围包括了其中的任何具体点值，例如20min、40min、60min、80min、100min或120min。
【钝化层-具体】进一步地，采用物理气相沉积方法在所述源漏极层和所述刻蚀阻挡层的上方沉积所述钝化层，再依次利用黄光工艺和刻蚀工艺制得具有图形的钝化层。
【钝化层-活化】进一步地，在沉积所述钝化层之后，先对所述钝化层进行加热活化，再进行图形化处理。
【钝化层-材料】进一步地，所述钝化层为SiOx层或者SiNx与SiOx的复合层。
优选地，所述钝化层为SiNx与SiOx的复合层。
更优选地，所述钝化层中的SiOx层为底层，与所述刻蚀阻挡层相接触。
【钝化层-厚度】进一步地，所述钝化层的厚度为1500～4000埃，该厚度范围包括了其中的任何具体点值，例如1500埃、1800埃、2000埃、2200埃、2500埃、3000埃、3300埃、3500埃、3800埃或者4000埃。
【透明导电层-具体】采用物理气相沉积方法在所述钝化层上沉积所述透明导电层，再依次利用黄光工艺和刻蚀工艺制得具有图形的透明导电层。
其中，已刻蚀的具有图形的透明导电层即像素电极。
进一步地，所述透明导电层的材料为ITO、纳米银线、IMO、ATO、FTO或ATO中的一种或几种。
其中，ITO是指In2O3:Sn的掺杂体系，IMO是指In2O3:Mo的掺杂体系，ATO是指SnO2:Sb的掺杂体系，FTO是指SnO2:F的掺杂体系，ZAO是指ZnO:Al的掺杂体系。
优选地，所述透明导电层的材料为ITO。
进一步地，所述透明导电层的厚度为300～1000埃，该厚度范围包括了其中的任何具体点值，例如300埃、400埃、500埃、600埃、700埃、800埃、900 埃或者1000埃。
与现有技术相比，本发明具有以下有益效果：
在本发明中，并未单独沉积刻蚀阻挡层，而是通过对采用复合层结构的源漏极层进行光刻、刻蚀、离子注入和加热活化等一系列操作，改变ZnO(Al)中O含量来改变刻蚀阻挡层的导电性，从而得到具有保护半导体氧化物层功能并且绝缘性良好的实际意义上的刻蚀阻挡层，也就是说，本发明的刻蚀阻挡层为源漏极层的一部分。这样的结构，一方面可以通过减少刻蚀阻挡层的厚度来减小薄膜晶体管整体的尺寸，使薄膜晶体管具有更多的设计空间，结构得以优化；另一方面，通过形成具有实际功能的刻蚀阻挡层，能够有效减少水、氧和能量对半导体氧化物层的影响，保护薄膜晶体管结构的性能。
附图说明
图1是实施例一薄膜晶体管结构的示意图。
图2是图1中A处结构的具体结构图(钝化层已略去)。
图3是实施例二制备方法的步骤之一。
图4是实施例二制备方法的步骤之一。
图5是实施例二制备方法的步骤之一。
图6是实施例二制备方法的步骤之一。
图7是图6中B处结构的具体结构图。
图8是实施例二制备方法的步骤之一。
图9是图8中C处结构的具体结构图。
图10是实施例二制备方法的步骤之一。
图11是实施例二制备方法的步骤之一。
具体实施方式
下面通过具体的实施例对本发明进行详细说明，应当理解的是，这些具体实施方式仅用来例举本发明，并非对本发明的实际保护范围构成任何形式的任何限定。
实施例一
本实施例提供一种薄膜晶体管结构，如图1所示，包括由下至上依次设置的的基板10、栅极20、栅极绝缘层30、半导体氧化物层40、源漏极层50、钝化层60和透明导电层70。
具体地，基板10为玻璃基板，栅极20设置在基板10上，且长度(图1中的左右方向的长度)小于基板长度，栅极20采用的材料为Al/Mo，厚度为3000埃。栅极绝缘层30包围在栅极20的外部，分别与栅极20的侧边和顶面接触，覆盖在基板10和栅极20上，其为SiNx与SiOx的复合层，厚度为3000埃。半导体氧化物层40设置在栅极绝缘层30的上方，其长度(图1中的左右方向的长度)与栅极绝缘层顶面的长度相同，其为IGZO层，厚度为1000埃。
源漏极层50包围在半导体氧化物层40的外部，分别与半导体氧化物层40的侧边和顶面接触，覆盖在栅极绝缘层30和半导体氧化物层40上。该源漏极层50为复合层，如图2所示，源漏极层50包括顶层51和底层52，其中底层52为ZnO(Al)层，厚度为500埃，顶层51为Al/Mo层，Mo层位于Al层的上方厚度为3000埃。位于半导体氧化物层40上方处的源漏极层50朝向自身内部(即图2中朝下的方向)凹陷形成一窗口，在该窗口中容置有刻蚀阻挡层80。该刻蚀阻挡层80由位于半导体氧化物层40上方处的源漏极层50刻蚀掉顶层51、仅剩底层52形成，该刻蚀阻挡层为ZnO(Al)层，且长度(图1中的左右方向的长度)小于半导体氧化物层的长度，其厚度为300埃。与此同时，由于源漏极层50刻蚀形成了刻蚀阻挡层80的同时，使源漏极层50形成朝向其自身内部凹陷的窗口，从而使得位于刻蚀阻挡层80两侧的源漏极层分别对应形成源极和漏极。值得注意的是，作为半导体氧化物层的IGZO层经过加热活化后，可由半导体氧化物层变为半导体层，作为刻蚀阻挡层的ZnO(Al)层通过增加氧含量、进而加热活化后，可成为电阻较高、绝缘性较强的绝缘层。
钝化层60覆盖在源漏极层50和刻蚀阻挡层80上，其为SiNx与SiOx的复合层，厚度为3000埃。其中，SiOx层位于钝化层的底层，可与刻蚀阻挡层接触。由于SiOx层中氧元素的含量较多，故而有助于提高刻蚀阻挡层的绝缘性。此外，钝化层60上还设有用于匹配透明导电层70的接触窗61，该接触窗61朝向钝化层60内部凹陷，且接触窗的厚度为钝化层的厚度，即该接触窗沿竖直方向贯穿于钝化层。透明导电层70用于电性连接薄膜晶体管和储电电容(图未示)，其与薄膜晶体管连接的一端大致位于钝化层上方，且位置与半导体氧化物层、刻 蚀阻挡层、栅极刚好错开。透明导电层70的下表面边缘处向下凸伸出一凸起部71，该凸起部71刚好容置在钝化层的接触窗61中，实现透明导电层70与源漏极层50的接触。透明导电层70为ITO层，厚度为500埃。
实施例二
本实施例提供一种薄膜晶体管结构的制备方法。
如图3所示，首先准备一块玻璃基板10，采用物理气相沉积(PVD)方法在基板上沉积栅极20，再依次利用黄光工艺和刻蚀工艺制得具有图形的栅极20。该栅极20采用的材料为Al/Mo，厚度为3000埃，长度则小于玻璃基板10的长度。
如图4所示，然后采用等离子增强化学气相沉积方法在已刻蚀好的栅极20上沉积栅极绝缘板30。该栅极绝缘板30包围在栅极20的外部，与栅极20的侧边和顶面接触，覆盖在基板10和栅极20上，其为SiNx与SiOx的复合层，厚度为3000埃。
如图5所示，然后采用物理气相沉积方法在栅极绝缘板30上沉积半导体氧化物层40，再依次利用黄光工艺和刻蚀工艺制得具有图形的半导体氧化物层40。该半导体氧化物层40为IGZO层，厚度为1000埃，长度与栅极绝缘层顶面的长度相同。
如图6所示，然后采用物理气相沉积方法在已刻蚀好的半导体氧化物层40上沉积源漏极层50，使源漏极层50包围在半导体氧化物层40的外部，分别与半导体氧化物层40的侧边和顶面接触，覆盖在栅极绝缘层30和半导体氧化物层40上。具体地，如图7所示，在半导体氧化物层40上首先沉积源漏极层50的底层52，再沉积源漏极层52的顶层51，使源漏极层50形成具有两层结构的复合层。其中，底层52为ZnO(Al)层，厚度为500埃，顶层51为Al/Mo层，厚度为3000埃。
如图8、图9所示，针对源漏极层50位于半导体氧化物层40上方的部分和源漏极层40的其他部分依次采用灰阶光罩工艺和刻蚀工艺进行处理，使得位于半导体氧化物层40上方的源漏极层最终刻蚀为刻蚀阻挡层80，其他源漏极层部分则刻蚀为具有图形的源漏极层40。具体地，在刻蚀位于半导体氧化物层40上方的源漏极层时，将源漏极层的顶层51全部刻蚀掉，仅剩余底层52，从而形成刻蚀阻挡层80，该刻蚀阻挡层与源漏极层底层相同，均为ZnO(Al)层，刻蚀阻 挡层的厚度为300埃，其长度小于半导体氧化物层的长度。另外，由于源漏极层50刻蚀形成了刻蚀阻挡层80的同时，使源漏极层50形成朝向其自身内部凹陷的窗口，从而使得位于刻蚀阻挡层80两侧的源漏极层分别对应形成源极和漏极。
在本实施例中，为了提高制得的薄膜晶体管结构的性能和使用寿命，需要对相关层结构进行改性处理。在刻蚀形成刻蚀阻挡层之后，利用离子注入方法向刻蚀阻挡层中注入氧离子以增加该ZnO(Al)层中的氧含量。然后，在烘箱中加热活化半导体氧化物层和刻蚀阻挡层，使所述半导体氧化物层活化为半导体层，所述刻蚀阻挡层氧化为绝缘层，其中，加热温度为300℃，活化时间为60min，同时通入空气或氧气进行活化。
可以理解的是，对于ZnO(Al)薄膜而言，其导电性会随着材料中氧含量的变化而变化，不通氧时制备的ZnO(Al)薄膜导电性最好，同时薄膜也具有较高的透过率(＞85％)，氧流量越大，电阻率随之越高。这是因为，当工作气体中掺入部分氧气，一方面氧与锌粒子反应的几率增加，结果ZnO(Al)薄膜内的氧缺位浓度降低而导致电阻率增加；另一方面，薄膜内的铝原子与氧反应生成Al2O3使其含量增加，薄膜中的替位Al3+减少而导致导电电子的浓度降低。另外，生成的Al2O3被隔离在晶界处，也会增加载流子的散射，使迁移率降低。由此可见，氧含量越多，会导致ZnO(Al)薄膜中的载流子浓度降低、电子迁移率降低，使得电阻率升高。本实施例中采用离子注入增加ZnO(Al)层中氧含量、以及通过高温活化的方式，恰是用于提高ZnO(Al)层中的氧含量，以使该层成为绝缘层。
如图10所示，在对刻蚀阻挡层进行活化后，采用物理气相沉积方法在源漏极层40和刻蚀阻挡层80的上方沉积钝化层60，高温活化钝化层60，再依次利用黄光工艺和刻蚀工艺制得具有图形的钝化层60。具体地，该钝化层60为SiNx与SiOx的复合层，厚度为3000埃。其中，SiOx层位于钝化层60的底层，可与刻蚀阻挡层80接触。本实施例之所以将SiOx层设于钝化层的底层，是因为SiOx层中氧含量较多，当沉积钝化层后对其进行活化，可进一步提高与SiOx层相接处的ZnO(Al)层中的氧含量，从而进一步提高ZnO(Al)层的绝缘性。
如图11所示，刻蚀好钝化层后，采用物理气相沉积方法在钝化层60上沉积透明导电层70，再依次利用黄光工艺和刻蚀工艺制得具有图形的透明导电层70。具体地，在钝化层60上设有用于匹配透明导电层70的接触窗61，该接触窗61朝向钝化层60内部凹陷，且接触窗的厚度为钝化层的厚度，即接触窗贯 穿于该钝化层。透明导电层70用于电性连接薄膜晶体管和储电电容(图未示)，其与薄膜晶体管连接的一端大致位于钝化层上，且位置与半导体氧化物层、刻蚀阻挡层、栅极等刚好错开。透明导电层70的下表面边缘处向下凸伸出一凸起部71，该凸起部71刚好容置在钝化层的接触窗61中，实现透明导电层70与源漏极层的接触。透明导电层70为ITO层，厚度为500埃。
本发明的上述实施例仅仅是为清楚地说明本发明所作的举例，而并非是对本发明的实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明权利要求的保护范围之内。

Claims (10)

  1. 一种薄膜晶体管结构，包括由下至上依次设置的基板、栅极、栅极绝缘层、半导体氧化物层、源漏极层、钝化层和透明导电层，其中：在对应于所述半导体氧化物层上方的所述源漏极层处，通过刻蚀形成刻蚀阻挡层，所述半导体氧化物层和所述刻蚀阻挡层经过加热活化后分别成为半导体层和绝缘层。
  2. 根据权利要求1所述的薄膜晶体管结构，其中：所述源漏极层朝向其内部凹陷形成窗口，所述刻蚀阻挡层容置在所述窗口中且与所述源漏极层连接，所述刻蚀阻挡层的厚度小于所述源漏极层，所述钝化层覆盖在所述刻蚀阻挡层和所述源漏极层上方。
  3. 根据权利要求2所述的薄膜晶体管结构，其中：所述源漏极层为复合层，所述复合层的底层为ZnO(Al)层，顶层为金属材料。
  4. 根据权利要求2所述的薄膜晶体管结构，其中：所述刻蚀阻挡层为ZnO(Al)层。
  5. 根据权利要求2所述的薄膜晶体管结构，其中：所述钝化层为SiOx层或者SiNx与SiOx的复合层。
  6. 一种根据权利要求1所述的薄膜晶体管结构的制备方法，其中，包括以下步骤：
    在基板上沉积并光刻栅极；
    在所述栅极上方沉积栅极绝缘板；
    在所述栅极绝缘板上方沉积并光刻半导体氧化物层；
    在所述半导体氧化物层上方沉积并光刻源漏极层；
    在对应于所述半导体氧化物层上方的所述源漏极层处，刻蚀所述源漏极层，形成刻蚀阻挡层；
    在所述源漏极层和所述半导体氧化物层的上方沉积钝化层；
    在所述钝化层上方沉积透明导电层。
  7. 根据权利要求6所述的制备方法，其中：在所述半导体氧化物层上沉积所述源漏极层时，首先沉积所述源漏极层的底层，再沉积所述源漏极层的顶层， 使所述源漏极层形成具有两层结构的复合层。
  8. 根据权利要求7所述的制备方法，其中：沉积形成所述源漏极层的复合层后，针对所述源漏极层位于所述半导体氧化物层上方的部分和所述源漏极层的其他部分依次采用黄光工艺和刻蚀工艺进行处理，其中，所述源漏极层位于所述半导体氧化物层上方的部分在刻蚀后形成刻蚀阻挡层，所述刻蚀阻挡层的结构为所述源漏极层底层的结构。
  9. 根据权利要求8所述的制备方法，其中：形成所述刻蚀阻挡层后，利用离子注入方法增加所述刻蚀阻挡层中氧元素的含量。
  10. 根据权利要求9所述的制备方法，其中：采用离子注入方法后，在烘箱中加热活化所述半导体氧化物层和所述刻蚀阻挡层，使所述半导体氧化物层活化为半导体层，所述刻蚀阻挡层氧化为绝缘层。
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