WO2014153853A1 - 薄膜晶体管及其制造方法、阵列基板和显示装置 - Google Patents

薄膜晶体管及其制造方法、阵列基板和显示装置 Download PDF

Info

Publication number
WO2014153853A1
WO2014153853A1 PCT/CN2013/077406 CN2013077406W WO2014153853A1 WO 2014153853 A1 WO2014153853 A1 WO 2014153853A1 CN 2013077406 W CN2013077406 W CN 2013077406W WO 2014153853 A1 WO2014153853 A1 WO 2014153853A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal oxide
layer
insulator layer
thin film
forming
Prior art date
Application number
PCT/CN2013/077406
Other languages
English (en)
French (fr)
Inventor
杜雷
Original Assignee
合肥京东方光电科技有限公司
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 合肥京东方光电科技有限公司, 京东方科技集团股份有限公司 filed Critical 合肥京东方光电科技有限公司
Priority to US14/355,058 priority Critical patent/US9437622B2/en
Publication of WO2014153853A1 publication Critical patent/WO2014153853A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • Embodiments of the present invention relate to a thin film transistor and a method of fabricating the same, an array substrate, and a display device. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the crystalline silicon thin film transistor has been developed to the present low temperature polysilicon thin film transistor, oxide thin film transistor, and the like.
  • oxide thin film transistor is superior to the amorphous silicon thin film transistor in terms of electron mobility, on-state current, and switching characteristics.
  • oxide thin film transistors because of the uniformity of oxides, there are advantages in the number of masks and manufacturing difficulties, and there is no difficulty in manufacturing a large-sized display, which is sufficient for requiring fast response and large current. Applications. Therefore, oxide thin film transistors are receiving increasing attention.
  • FIG. 1 is a schematic structural view of a prior art oxide thin film transistor including a substrate 1, a gate electrode 2, a gate insulating layer 3, a semiconductor layer 4, an etch barrier layer 5, and source and drain electrodes 7.
  • a substrate 1 a gate electrode 2, a gate insulating layer 3, a semiconductor layer 4, an etch barrier layer 5, and source and drain electrodes 7.
  • film formation, exposure, development, and the gate metal layer, the gate insulating layer, the metal oxide semiconductor layer, the etch barrier layer, and the data line metal layer are generally sequentially performed on the substrate 1.
  • Etching is performed to sequentially form the gate electrode 2, the gate insulating layer 3, the semiconductor layer 4, the etch barrier layer 5, and the source/drain electrodes 7.
  • the etch barrier layer 5 is generally a multilayer film structure composed of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), thus water repellency Poor, in the subsequent process of product manufacturing and during use, it is easily immersed in water vapor in the air, thereby damaging the semiconductor layer in the channel region under the etch barrier and causing product failure.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • SiON silicon oxynitride
  • One embodiment of the present invention provides a thin film transistor including a gate electrode and a gate insulating a layer, a semiconductor layer, an insulator layer, and a source/drain electrode, wherein the insulator layer is located above the semiconductor layer, covers a channel region of the source/drain electrode, and is composed of a metal oxide insulator.
  • Another embodiment of the present invention provides a method of fabricating a thin film transistor, comprising: forming a gate electrode on a substrate, and forming a gate insulating layer over the gate electrode; forming a semiconductor layer, and forming the semiconductor Forming a metal oxide insulator layer over the layer; and forming a source-drain electrode, wherein the metal oxide insulator layer covers a channel region of the source-drain electrode.
  • Another embodiment of the present invention provides an array substrate including the above thin film transistor. Another embodiment of the present invention provides a display device including the above array substrate.
  • FIG. 1 is a schematic cross-sectional view of a prior art thin film transistor
  • FIG. 2 is a schematic cross-sectional view showing an example of a thin film transistor according to an embodiment of the present invention
  • FIG. 3 is a schematic cross-sectional view showing another example of a thin film transistor according to an embodiment of the present invention
  • Flow chart of the method Flow chart of the method. detailed description
  • An embodiment of the present invention provides a thin film transistor in which an insulator layer composed of a metal oxide insulator is formed over a semiconductor layer, which is capable of reacting with water vapor, thereby preventing metal oxide semiconductors in a channel region from being subjected to damage.
  • Embodiments of the present invention also provide a method of fabricating the above thin film transistor and an array substrate and display device including the same.
  • a first embodiment of the present invention provides a thin film transistor.
  • the thin film transistor includes: a substrate 1, a gate electrode 2, a gate insulating layer 3, a semiconductor layer 4, an insulator layer 6, and a source/drain electrode 7, wherein
  • the gate electrode 2 is formed on the substrate 1, the gate insulating layer 3 is formed over the gate electrode 2, the semiconductor layer 4 is formed over the gate insulating layer 3, and the channel region covering the source and drain electrodes is formed over the semiconductor layer 4.
  • an insulator layer 6 composed of a metal oxide insulator, which is made of a metal oxide, so that it can react with water vapor immersed therein, thereby preventing the semiconductor layer 4 underneath from being damaged, in the semiconductor layer.
  • An active drain electrode 7 is also formed on top of 4.
  • the position of the insulator layer 6 on the semiconductor layer 4 can be flexibly set.
  • the insulator layer 6 is disposed at a corresponding position of the channel region of 7, that is, the insulator layer 6 and the source/drain electrodes 7 have no overlapping regions, and reference can be made again to FIG.
  • an entire insulator layer may be disposed over the semiconductor layer 4, in order to achieve ohmic contact between the semiconductor layer 4 and the source and drain electrodes 7, A via 8 electrically connecting the semiconductor layer 4 and the source and drain electrodes 7 may be provided at an overlapping region of the insulator layer 6 and the source/drain electrodes 7, as shown in FIG.
  • the insulator layer 6 and the semiconductor layer 4 may be made of the same metal oxide, and materials having different characteristics may be formed by controlling the percentage content of oxygen elements in the metal oxide, for example.
  • the percentage of oxygen in the metal oxide forming the insulator layer 6 is higher than the percentage of oxygen in the metal oxide forming the semiconductor layer 4, and the percentage of oxygen in the metal oxide is controlled to be 60% to 90%.
  • an insulator is formed and the insulator layer 6 is formed.
  • the insulator layer 6 is made of the same metal oxide as the semiconductor layer 4.
  • the metal oxide insulator reacts with water vapor, it can be converted into a semiconductor, which not only has the function of etching the barrier layer. When it is immersed in water vapor, it is converted into a semiconductor and functions as a semiconductor layer.
  • an insulator layer made of a metal oxide insulator is formed over the semiconductor layer. If water vapor in the air is immersed, the insulator layer composed of the metal oxide insulator first occurs with water vapor. The reaction is converted into a semiconductor to protect the metal oxide semiconductor of the channel region; at the same time, the metal oxide insulator can be used instead of the etch barrier layer, thereby saving the manufacture of the etch barrier layer and further the manufacturing process.
  • the second embodiment of the present invention further provides a method for manufacturing a thin film transistor. The process of the manufacturing method is as shown in FIG. 4, for example, mainly including:
  • a substrate 1 is provided, and a gate electrode 2 is formed on the substrate 1.
  • the substrate 1 may be a substrate made of an inorganic material such as a glass substrate or a quartz substrate, or may be a substrate made of an organic material.
  • a material for forming a gate electrode layer of the gate electrode 2 may be selected from the group consisting of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (A1), aluminum-niobium alloy (AlNd), titanium (Ti), and copper.
  • Mo molybdenum
  • MoNb molybdenum-niobium alloy
  • AlNd aluminum-niobium alloy
  • Ti titanium
  • copper copper
  • a single layer film or a multilayer composite film formed of one or more of (Cu ) for example, a single layer film or a multilayer composite film composed of Mo, A1 or an alloy containing Mo, A1, and having a film thickness of 100 nm ⁇ 500nm.
  • a gate insulating layer 3 is formed over the gate electrode 2.
  • the gate insulating layer 3 may be oxidized by silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), silicon oxynitride (SiON), aluminum.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • HfOx germanium oxide
  • SiON silicon oxynitride
  • AlOx aluminum
  • the metal oxide semiconductor film and the metal oxide insulator film may contain two elements of In (indium), Ga (gallium), Zn (word), Sn (tin), and A1 (aluminum). Or more elements and 0 (oxygen) elements, for example, IGZO (indium gallium oxide), IZO (indium oxide), InSnO (indium tin oxide), InGaSnO (indium gallium oxide), etc., of course, metal oxide insulator The percentage content of oxygen in the metal oxide semiconductor needs to be higher than the percentage content of oxygen in the metal oxide semiconductor.
  • the metal oxide semiconductor thin film and the metal oxide insulator thin film may be formed by deposition, spin coating, spray coating, or the like, but the embodiment of the invention is not limited thereto.
  • a magnetron sputtering film formation method may be employed without performing an annealing process to avoid subsequent annealing processes, which may affect the properties of the metal oxide.
  • the metal oxide semiconductor film and the metal oxide insulator film may be selected from the same metal oxide, and different metal oxides may be used, but embodiments of the present invention are not limited thereto.
  • the metal oxide insulator film and the metal oxide semiconductor film are made of the same metal oxide material, so that the desired metal oxide can be sequentially formed by using the same target by controlling the film formation environment. Semiconductor film and metal oxide insulator film.
  • a metal oxide film pre-formed with a metal oxide semiconductor layer may be previously deposited, and then a reaction gas mixed with oxygen (0 2 ) may be injected, by controlling the ratio of 0 2 in the reaction gas, A metal oxide semiconductor thin film and a metal oxide insulator thin film containing the same metal oxide are sequentially formed.
  • the metal oxide film of the semiconductor layer is described as an example, but the embodiment of the invention is not limited thereto.
  • the reaction gas forming the metal oxide semiconductor and the metal oxide insulator is generally a mixed gas containing 0 2 .
  • a metal oxide semiconductor film and a metal oxide insulator film containing the same metal oxide are sequentially formed; wherein, when the metal oxide semiconductor film is formed, the ratio of 0 2 in the reaction gas can be 10% ⁇ 40%;
  • the ratio of 0 2 in the reaction gas may be 60% to 90%, for example, when forming a metal oxide insulator film, the ratio of 0 2 in the reaction gas Can be 80% to 90%.
  • the specific film formation environment may vary with the variation of the ratio of 0 2 in the reaction gas.
  • the reaction gas for forming the metal oxide is a mixed gas of 0 2 (oxygen) and Ar (argon), and is not limited thereto.
  • it may be 0 2 ( a mixture of oxygen and N 2 (nitrogen).
  • a metal oxide semiconductor thin film and a metal oxide insulator thin film containing the same metal oxide can be sequentially formed by controlling the ratio of 0 2 in the reaction gas under different film forming environments.
  • the thickness of the metal oxide semiconductor thin film is 50nm ⁇ 100nm
  • a mixed gas of Ar and 0 2 0 2 ratio is from 10% to 40% film-forming temperature 25 ° C ⁇ 100 ° C
  • the pressure is between 0.5pa-lpa
  • the specific film formation environment can change with 0 2 / Ar flow changes.
  • the thickness of the metal oxide insulator film is 10nm 50nm
  • the deposition environment 02 remains ⁇ Ar mixed gas
  • the mixed gas of Ar and 0 2 0 2 ratio is from 60% to 90%
  • the film formation temperature It is between 25 °C and 100 °C
  • the pressure is between 4pa and 6pa.
  • the specific film-forming environment can be changed with the change of 0 2 /Ar flow rate.
  • a mixed gas of Ar and 0 2 0 2 ratio is 80% -90%.
  • the formation of the semiconductor layer 4 and the metal oxide insulator layer 6 may be separately formed by different patterning processes, or may be simultaneously formed by the same patterning process.
  • the patterning process may include some or all of the processes of masking, exposing, developing, photolithography, etching, etc. of the pattern.
  • forming a gate electrode on a substrate by using a patterning process includes: first depositing a gate electrode film on the substrate, then coating the photoresist, exposing and developing the photoresist by using a mask to form a photoresist pattern. Then, using the photoresist pattern as an etch mask, the corresponding gate electrode film is removed by etching or the like, and the remaining photoresist is removed, and finally a gate electrode pattern is formed on the substrate.
  • the process of forming the semiconductor layer 4 is the same as the process of forming the semiconductor layer in the method of fabricating the thin film transistor of the prior art. This will not be repeated here.
  • different metal oxide insulator layers may be formed as needed.
  • a metal oxide insulator film pre-formed with the metal oxide insulator layer 6 may be exposed, developed, and etched using a mask process to form a channel region at the pre-formed source and drain electrode.
  • the insulator layer at the corresponding location does not have an overlap region with the pre-formed source and drain electrodes.
  • a metal oxide insulator layer 6 may be disposed over the entire semiconductor layer 4, and the metal oxide insulator film pre-formed with the metal oxide insulator layer may be exposed by a mask process. And developing and etching to form an insulator layer having an overlap region with the pre-formed source and drain electrodes; the insulator layer and the pre-formed source and drain electrodes have overlapping regions, and the insulator layer may be subjected to a via process in the overlap region A via having electrically connected pre-formed source and drain electrodes and a semiconductor layer is formed through which the semiconductor layer and the pre-formed source and drain electrodes are brought into ohmic contact.
  • the semiconductor layer 4 and the metal oxide insulator layer 6 may be formed using a one-time patterning process.
  • the metal oxide insulator layer 6 when the metal oxide insulator layer 6 is provided over the entire semiconductor layer 4, and an insulator layer having an overlapping region with the pre-formed source/drain electrodes is formed, for example, it may be adopted in step S403.
  • the method of controlling the content of 0 2 in the reaction gas to form the metal oxide semiconductor thin film and the metal oxide insulator thin film, and when forming the semiconductor layer 4 and the metal oxide insulator layer 6, for example, may be formed by one patterning process, The process steps are reduced to reduce process costs.
  • the material of the metal thin film of the source and drain electrodes may be a single layer film or a multilayer composite film formed of one or more of Mo, MoNb, Al, AlNd, Ti, and Cu, for example, Mo. , A1 or a single layer film or a multilayer composite film composed of an alloy containing Mo and A1.
  • an insulator layer made of a metal oxide insulator is formed on a semiconductor layer.
  • the insulator layer composed of the metal oxide insulator is first and water.
  • the vapor reacts and is converted into a semiconductor, thereby preventing damage of the metal oxide semiconductor in the channel region; and in the embodiment of the invention, both the insulator layer and the semiconductor layer are composed of a metal oxide, so that a similar process can be used for engraving Etching, development, etc., eliminate the need to separately fabricate an etch barrier, thereby tubeizing the manufacturing process.
  • the third embodiment of the present invention further provides an array substrate, which comprises the thin film transistor provided by the first embodiment of the present invention, and other structures may be the same as the prior art, and details are not described herein again.
  • the fourth embodiment of the present invention further provides a display device.
  • the display device includes the array substrate provided in the third embodiment of the present invention.
  • Other structures may be the same as those in the prior art, and details are not described herein again.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管及其制作方法、阵列基板和显示装置，以避免沟道区域的半导体层发生损伤。该薄膜晶体管，包括栅电极（2）、栅极绝缘层（3）、半导体层（4）、绝缘体层（6）和源漏电极（7），其中绝缘体层（6）位于所述半导体层（4）上方，覆盖所述源漏电极（7）的沟道区域，由金属氧化物绝缘体构成。在该薄膜晶体管中，当空气中的水蒸气浸入时，该金属氧化物绝缘体构成的绝缘体层（6）会首先与水蒸气发生反应，从而能够防止沟道区域的金属氧化物半导体被损伤。

Description

薄膜晶体管及其制造方法、 阵列基板和显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管及其制造方法、 阵列基板和显示装 置。 背景技术
近年来， 薄膜晶体管液晶显示器（Thin Film Transistor Liquid Crystal Display, TFT-LCD )得到越来越广泛的应用， 同时用于驱动并控制像素的薄 膜晶体管的技术也随之得到发展， 已由原来的非晶硅薄膜晶体管发展到现在 的低温多晶硅薄膜晶体管、 氧化物薄膜晶体管等。
氧化物薄膜晶体管， 其电子迁移率、 开态电流、 开关特性等特性优于非 晶硅薄膜晶体管。此外， 对于氧化物薄膜晶体管， 由于氧化物的均匀性较好， 在掩模数量和制造难度上均有优势,在制造大尺寸的显示器方面也没有难度， 足以用于需要快速响应和较大电流的应用。 因此， 氧化物薄膜晶体管日益受 到重视。
如图 1所示为现有技术的氧化物薄膜晶体管的结构示意图， 包括基板 1、 栅电极 2、 栅极绝缘层 3、 半导体层 4、 刻蚀阻挡层 5和源漏电极 7。 在氧化 物薄膜晶体管的制造过程中， 一般在基板 1上依次进行栅极金属层、 栅极绝 缘层、 金属氧化物半导体层、 刻蚀阻挡层和数据线金属层的成膜、 曝光、 显 影和刻蚀， 以依次形成栅电极 2、 栅极绝缘层 3、 半导体层 4、 刻蚀阻挡层 5 和源漏电极 7。
刻蚀阻挡层 5—般是由硅的氧化物（SiOx ) 、 硅的氮化物（SiNx )和硅 的氮氧化物 （SiON ) 中的一种或多种组成的多层膜结构， 因此防水性不佳， 在产品制造的后续工艺中以及使用过程中，很容易受到空气中水蒸气的浸入， 从而使刻蚀阻挡层下方的沟道区域的半导体层受到损伤并造成产品的失效。 发明内容
本发明的一个实施例提供了一种薄膜晶体管， 其包括栅电极、 栅极绝缘 层、 半导体层、 绝缘体层和源漏电极， 其中， 所述绝缘体层位于所述半导体 层上方， 覆盖所述源漏电极的沟道区域， 并且由金属氧化物绝缘体构成。
本发明的另一个实施例提供了一种薄膜晶体管的制造方法， 其包括： 在 基板上形成栅电极， 并在所述栅电极之上形成栅极绝缘层； 形成半导体层， 并在所述半导体层之上形成金属氧化物绝缘体层； 以及形成源漏电极，其中， 所述金属氧化物绝缘体层覆盖所述源漏电极的沟道区域。
本发明的另一个实施例提供了一种阵列基板， 其包括上述薄膜晶体管。 本发明的另一个实施例提供了一种显示装置， 其包括上述阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术的薄膜晶体管的截面示意图；
图 2为本发明实施例提供的薄膜晶体的一个示例的截面示意图； 图 3为本发明实施例提供的薄膜晶体管的另一示例的截面示意图； 图 4为本发明实施例提供的薄膜晶体管的制造方法的流程图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明的实施例提供了一种薄膜晶体管， 其中， 在半导体层上方形成有 由金属氧化物绝缘体构成的绝缘体层， 其能够与水蒸气发生反应， 从而能够 防止沟道区域的金属氧化物半导体受到损伤。 本发明的实施例还提供了上述 薄膜晶体管的制造方法以及包括该薄膜晶体管的阵列基板和显示装置。
以下将结合附图对本发明实施例中的薄膜晶体管及其制造方法进行详细 说明， 以下实施例仅为示例， 并不引以为限。 本发明实施例一提供了一种薄膜晶体管， 如图 2所示， 该薄膜晶体管包 括： 基板 1、 栅电极 2、 栅极绝缘层 3、 半导体层 4、 绝缘体层 6和源漏电极 7, 其中， 栅电极 2形成在基板 1上， 栅极绝缘层 3形成在栅电极 2上方， 在 栅极绝缘层 3上方形成有半导体层 4, 在半导体层 4上方形成有覆盖源漏电 极的沟道区域并且由金属氧化物绝缘体构成的绝缘体层 6, 该绝缘体层 6由 于其由金属氧化物构成， 故其可以与浸入其中的水蒸气发生反应， 从而避免 其下方的半导体层 4受到损伤， 在半导体层 4之上还形成有源漏电极 7。
在本发明的实施例中， 绝缘体层 6位于半导体层 4上的位置可以灵活设 置。 在本发明的一些实施例中， 由于在使用过程中， 仅在源漏电极 7的沟道 区域处会有水蒸气浸入， 故为节省金属氧化物绝缘体材料的使用， 可仅在位 于源漏电极 7的沟道区域的对应位置处设置绝缘体层 6, 即绝缘体层 6和源 漏电极 7没有交叠区域， 可再次参考图 2。 在本发明的一些实施例中， 为了 筒化制造工艺， 降低刻蚀难度， 可在半导体层 4上方设置整层绝缘体层， 此 时为了使半导体层 4与源漏电极 7之间实现欧姆接触， 可在绝缘体层 6与源 漏电极 7的交叠区域处设置电性连接半导体层 4和源漏电极 7的过孔 8, 如 图 3所示。
在本发明的实施例中， 为了筒化工艺， 可使绝缘体层 6和半导体层 4采 用相同的金属氧化物， 并通过控制金属氧化物中氧元素的百分比含量而形成 具有不同特性的材料， 例如， 使形成绝缘体层 6的金属氧化物中氧元素的百 分比含量高于形成半导体层 4的金属氧化物中氧元素的百分比含量， 将金属 氧化物中氧元素的百分比含量控制在 60%~90%的范围内，形成绝缘体，进而 构成绝缘体层 6。在本发明的实施例中， 例如， 绝缘体层 6采用与半导体层 4 相同的金属氧化物， 当金属氧化物绝缘体与水蒸气发生反应后， 其可转化为 半导体， 不仅具有刻蚀阻挡层的功能， 并且在有水蒸气浸入时， 转化为半导 体而兼具半导体层的作用。
在本发明实施例提供的薄膜晶体管中， 在半导体层上方形成有由金属氧 化物绝缘体构成的绝缘体层， 若空气中的水蒸气浸入， 由金属氧化物绝缘体 构成的绝缘体层会首先与水蒸气发生反应， 并转化为半导体， 从而保护沟道 区域的金属氧化物半导体； 同时，可以用金属氧化物绝缘体代替刻蚀阻挡层， 从而节省刻蚀阻挡层的制造， 进而筒化制造工艺。 本发明实施例二还提供了一种薄膜晶体管的制造方法， 该制造方法的过 程如图 4所示， 例如， 主要包括：
S401: 提供一基板 1 , 并在基板 1上形成栅电极 2。
在 S401 中， 上述基板 1可以是玻璃基板、 石英基板等基于无机材料的 基板， 也可以是采用有机材料的基板。
在本发明的实施例中，形成栅电极 2的栅电极层的材料可选用钼（ Mo )、 钼铌合金 ( MoNb ) 、 铝（A1 ) 、 铝钕合金 ( AlNd ) 、 钛（ Ti )和铜 ( Cu ) 中的一种或多种形成的单层膜或多层复合膜， 例如， Mo、 A1或含 Mo、 A1 的合金组成的单层膜或多层复合膜， 且膜层厚度为 100nm~500nm。
S402: 在栅电极 2之上形成栅极绝缘层 3。
在本发明的实施例中， 栅极绝缘层 3可由硅的氧化物（SiOx ) 、 硅的氮 化物 （SiNx ) 、 铪的氧化物 （HfOx ) 、 硅的氮氧化物 （SiON ) 、 铝的氧化 物（AlOx )等中的一种或两种组成的单层膜或多层复合膜形成。
S403: 形成金属氧化物半导体薄膜和金属氧化物绝缘体薄膜。
在本发明的实施例中， 金属氧化物半导体薄膜和金属氧化物绝缘体薄膜 可以包含 In (铟） 、 Ga (镓） 、 Zn (辞） 、 Sn (锡）和 A1 (铝） 中的两种 元素或更多种元素以及 0 (氧）元素， 例如， IGZO (氧化铟镓辞）、 IZO (氧 化铟辞） 、 InSnO (氧化铟锡） 、 InGaSnO (氧化铟镓锡）等， 当然金属氧化 物绝缘体中氧元素的百分比含量需要高于金属氧化物半导体中氧元素的百分 比含量。
在本发明的实施例中， 可采用沉积、 旋涂和喷涂等方式形成金属氧化物 半导体薄膜和金属氧化物绝缘体薄膜，但是本发明的实施例不限于此。例如， 在本发明的实施例中， 可以采用磁控溅射成膜法， 无需进行退火工艺， 以避 免后续进行退火工艺， 对金属氧化物的性能造成影响。
在本发明的实施例中， 金属氧化物半导体薄膜和金属氧化物绝缘体薄膜 可选用相同的金属氧化物， 也可选用不同的金属氧化物， 但是本发明的实施 例不限于此。 例如， 在本发明的实施例中， 金属氧化物绝缘体薄膜和金属氧 化物半导体薄膜采用相同的金属氧化物材料， 这样可以通过控制成膜环境， 采用同种靶材依次形成所需的金属氧化物半导体薄膜和金属氧化物绝缘体薄 膜。 在本发明的实施例中， 可预先沉积一层预形成金属氧化物半导体层的金 属氧化物薄膜， 然后注入混有氧气（02 )的反应气体， 通过控制 02在反应气 体中的比例， 依次形成包含相同金属氧化物的金属氧化物半导体薄膜和金属 氧化物绝缘体薄膜。 物半导体层的金属氧化物薄膜为例进行说明，但是本发明的实施例不限于此。
在本发明的实施例中， 形成金属氧化物半导体和金属氧化物绝缘体的反 应气体一般为包含 02的混合气体。 通过控制 02在反应气体中的比例， 依次 形成包含相同金属氧化物的金属氧化物半导体薄膜和金属氧化物绝缘体薄 膜； 其中， 形成金属氧化物半导体薄膜时， 02在反应气体中的比例可以为 10%~40%； 形成金属氧化物绝缘体薄膜时， 02在反应气体中的比例可以为 60%~90%, 例如， 形成金属氧化物绝缘体层薄膜时， 02在反应气体中的比例 可以为 80%~90%。 当然，形成金属氧化物半导体和金属氧化物绝缘体时除控 制 02以外， 具体的成膜环境可随着 02在反应气体中的比例的变动而改变。 例如：形成金属氧化物半导体薄膜时，成膜温度为 Tl(例如: T1=25 °C~100°C ), 压力为 P1 (例如： Pl=0.5pa-lpa ) ； 形成金属氧化物绝缘体薄膜时， 成膜温 度为 T2 (例如: T2=25 °C ~100°C ) , 压力为 P2 (例如: P2=4pa-6pa ) 。
在本发明的实施例中以形成金属氧化物的反应气体是 02 (氧气）和 Ar (氩气） 的混合气体为例进行说明， 当然并不引以为限， 比如还可以是 02 (氧气）和 N2 (氮气） 的混合气体。
在本发明的实施例中，可通过控制 02在反应气体中的比例，在不同的成 膜环境下， 依次形成包含相同金属氧化物的金属氧化物半导体薄膜和金属氧 化物绝缘体薄膜。 例如， 金属氧化物半导体薄膜的厚度为 50nm~100nm, 成 膜环境为 02和 Ar 的混合气体， 在 02和 Ar 的混合气体中 02的比例为 10%-40%, 成膜温度为 25 °C~100°C , 压力在 0.5pa-lpa之间， 具体的成膜环 境可随着 02/Ar流量的变动而改变。
例如， 金属氧化物绝缘体薄膜的厚度为 10nm~50nm, 成膜环境仍为 02 和 Ar的混合气体， 在 02和 Ar的混合气体中 02的比例为 60%-90%, 成膜温 度为 25°C ~100°C , 压力在 4pa-6pa之间， 具体的成膜环境可随着 02/Ar流量 的变动而改变。 在本发明的实施例中，为形成防水性更好的金属氧化物绝缘体层，例如， 在 02和 Ar的混合气体中 02的比例为 80%-90%。
S404: 形成半导体层 4和金属氧化物绝缘体层 6。
在本发明的实施例中， 半导体层 4和金属氧化物绝缘体层 6的形成， 可 采用不同的构图工艺分别形成， 也可采用同一构图工艺同时形成。
在本发明的实施例中， 所述构图工艺可以包括制造图形的掩模、 曝光、 显影、 光刻， 刻蚀等部分或全部工艺过程。
举例来说， 采用构图工艺在基板上形成栅电极， 包括： 首先在基板上沉 积栅电极薄膜， 然后涂布光刻胶， 利用掩模板对光刻胶进行曝光和显影处理 来形成光刻胶图案， 接着利用该光刻胶图案作为蚀刻掩模， 通过刻蚀等工艺 去除相应的栅电极薄膜， 并且去除剩余的光刻胶， 最终在基板上形成栅电极 图形。
在本发明的实施例中， 当半导体层 4和绝缘体层 6采用不同的构图工艺 分别形成时， 形成半导体层 4的过程与现有技术的薄膜晶体管的制造方法中 半导体层的形成过程相同， 在此不再赘述。
在本发明的实施例中， 当半导体层 4和绝缘体层 6采用不同的构图工艺 分别形成时， 可根据需要形成不同的金属氧化物绝缘体层。
为了节省金属氧化物绝缘体材料的使用， 可采用掩模工艺， 对预形成金 属氧化物绝缘体层 6的金属氧化物绝缘体薄膜进行曝光、 显影和刻蚀， 形成 位于预形成源漏电极的沟道区域的对应位置处的绝缘体层， 即与预形成的源 漏电极不具有交叠区域。
为了能够筒化掩模工艺， 可以在半导体层 4的整个上方都设置金属氧化 物绝缘体层 6, 即可采用掩模工艺， 对预形成所述金属氧化物绝缘体层的金 属氧化物绝缘体薄膜进行曝光、 显影和刻蚀， 形成与预形成的源漏电极具有 交叠区域的绝缘体层； 该绝缘体层和预形成的源漏电极具有交叠区域， 可对 绝缘体层进行过孔工艺， 在交叠区域形成具有电性连接预形成的源漏电极以 及半导体层的过孔， 通过该过孔使半导体层和预形成的源漏电极实现欧姆接 触。
在本发明的实施例中， 半导体层 4和金属氧化物绝缘体层 6可采用一次 构图工艺形成。 在本发明的实施例中， 当半导体层 4的整个上方都设置金属氧化物绝缘 体层 6, 并且形成与预形成的源漏电极具有交叠区域的绝缘体层时， 例如， 可以采用步骤 S403中通过控制 02在反应气体中的含量来形成金属氧化物半 导体薄膜和金属氧化物绝缘体薄膜的方式， 并且在形成半导体层 4和金属氧 化物绝缘体层 6时， 例如， 可以采用一次构图工艺形成， 以筒化工艺步骤， 降低工艺成本。
S405: 沉积源漏电极的金属薄膜， 并进行图案化处理， 形成源漏电极 7。 在本发明的实施例中， 源漏电极的金属薄膜的材料可以是 Mo、 MoNb、 Al、 AlNd、 Ti和 Cu中的一种或多种形成的单层膜或多层复合膜，例如， Mo、 A1或含 Mo、 A1的合金组成的单层膜或多层复合膜。
本发明实施例提供的薄膜晶体管的制造方法， 在半导体层上形成有由金 属氧化物绝缘体构成的绝缘体层， 当空气中的水蒸气浸入时， 该金属氧化物 绝缘体构成的绝缘体层会首先与水蒸气发生反应， 并转化为半导体， 从而能 够防止沟道区域的金属氧化物半导体受到损伤； 并且本发明实施例中绝缘体 层和半导体层都是由金属氧化物构成， 因此可以采用相似的工艺进行刻蚀、 显影等， 无需单独制造刻蚀阻挡层， 从而筒化了制造工艺。
本发明实施例三还提供了一种阵列基板， 该阵列基板包含本发明实施例 一提供的薄膜晶体管， 其他结构可以与现有技术相同， 在此不再赘述。
本发明实施例四还提供了一种显示装置， 该显示装置包含本发明实施例 三提供的阵列基板， 其他结构可以与现有技术相同， 在此不再赘述。
以上实施例仅用以说明本发明的技术方案， 而非对其限制； 尽管参照前 述实施例对本发明进行了详细的说明， 本领域的普通技术人员应当理解： 其 依然可以对前述各实施例所记载的技术方案进行修改， 或者对其中部分技术 特征进行等同替换； 而这些修改或者替换， 并不使相应技术方案的本质脱离 本发明各实施例技术方案的精神和范围。

Claims

权利要求书
1、 一种薄膜晶体管， 包括栅电极、 栅极绝缘层、 半导体层、 绝缘体层和 源漏电极， 其中， 所述绝缘体层位于所述半导体层上方， 覆盖所述源漏电极 的沟道区域， 并且由金属氧化物绝缘体构成。
2、如权利要求 1所述的薄膜晶体管， 其中， 所述绝缘体层与所述源漏电 极不具有交叠区域。
3、如权利要求 1所述的薄膜晶体管， 其中， 所述绝缘体层与所述源漏电 极具有交叠区域， 且在所述交叠区域具有电性连接所述源漏电极以及所述半 导体层的过孔。
4、 如权利要求 1-3中任一项所述的薄膜晶体管， 其中， 所述绝缘体层包 含与所述半导体层相同的金属氧化物， 所述绝缘体层中氧元素在金属氧化物 中的百分比含量为 60%~90%。
5、 如权利要求 1-3中任一项所述的薄膜晶体管， 其中， 所述绝缘体层包 含与所述半导体层不同的金属氧化物。
6、 一种薄膜晶体管制造方法， 包括：
在基板上形成栅电极， 并在所述栅电极之上形成栅极绝缘层； 形成半导体层， 并在所述半导体层之上形成金属氧化物绝缘体层； 以及 形成源漏电极；
其中， 所述金属氧化物绝缘体层覆盖所述源漏电极的沟道区域。
7、 如权利要求 6所述的方法， 其中， 形成所述金属氧化物绝缘体层， 包 括：
对预形成所述金属氧化物绝缘体层的金属氧化物绝缘体薄膜进行曝光、 显影和刻蚀， 形成与预形成的源漏电极不具有交叠区域的金属氧化物绝缘体 层。
8、 如权利要求 6所述的方法， 其中， 形成所述金属氧化物绝缘体层， 包 括：
对预形成所述金属氧化物绝缘体层的金属氧化物绝缘体薄膜进行曝光、 显影和刻蚀， 形成与预形成的源漏电极具有交叠区域的绝缘体层； 以及
对所述绝缘体层进行过孔工艺， 形成在所述交叠区域具有电性连接所述 源漏电极以及所述半导体层的过孔的金属氧化物绝缘体层。
9、 如权利要求 6所述的方法， 其中， 形成半导体层， 并在所述半导体层 之上形成金属氧化物绝缘体层， 包括：
沉积预形成金属氧化物半导体层的金属氧化物薄膜；
注入混有氧气 02的反应气体；
控制 02在所述反应气体中的比例，依次形成包含相同金属氧化物的金属 氧化物半导体薄膜和金属氧化物绝缘体薄膜； 其中， 形成所述金属氧化物半 导体薄膜时， 02在反应气体中的比例为 10%~40%； 形成所述金属氧化物绝 缘体薄膜时， 02在反应气体中的比例为 60%~90%。
10、 如权利要求 9所述的方法， 其中， 通过对所述金属氧化物半导体薄 膜和所述金属氧化物绝缘体薄膜采用一次构图工艺而形成所述半导体层以及 位于所述半导体层之上的金属氧化物绝缘体层。
11、 如权利要求 9所述的方法， 其中， 形成所述金属氧化物绝缘体层薄 膜时， 02在反应气体中的比例为 80%~90%。
12、如权利要求 6-11中任一项所述的方法，其中，采用磁控溅射成膜法， 依次形成所述半导体层和所述金属氧化物绝缘体层。
13、 一种阵列基板， 包括权利要求 1-5中任一项所述的薄膜晶体管。
14、 一种显示装置， 包括权利要求 13所述的阵列基板。
PCT/CN2013/077406 2013-03-25 2013-06-18 薄膜晶体管及其制造方法、阵列基板和显示装置 WO2014153853A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/355,058 US9437622B2 (en) 2013-03-25 2013-06-18 Thin film transistor and method for manufacturing the same, array substrate and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310098005.8A CN103199114B (zh) 2013-03-25 2013-03-25 薄膜晶体管及其制作方法、阵列基板和显示装置
CN201310098005.8 2013-03-25

Publications (1)

Publication Number Publication Date
WO2014153853A1 true WO2014153853A1 (zh) 2014-10-02

Family

ID=48721559

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/077406 WO2014153853A1 (zh) 2013-03-25 2013-06-18 薄膜晶体管及其制造方法、阵列基板和显示装置

Country Status (3)

Country Link
US (1) US9437622B2 (zh)
CN (1) CN103199114B (zh)
WO (1) WO2014153853A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104091804B (zh) * 2014-06-16 2016-08-03 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN110047848B (zh) * 2019-04-02 2021-07-06 Tcl华星光电技术有限公司 一种阵列基板及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196371A (ja) * 2000-01-12 2001-07-19 Furontekku:Kk 銅配線基板及びその製造方法並びに液晶表示装置
US20070194386A1 (en) * 2006-02-17 2007-08-23 Samsung Electronics Co. Ltd. Methods of fabricating organic thin film transistors and organic thin film transistors fabricated using the same
CN101814529A (zh) * 2009-02-20 2010-08-25 株式会社半导体能源研究所 薄膜晶体管及其制造方法,以及半导体装置
CN101894760A (zh) * 2010-06-10 2010-11-24 友达光电股份有限公司 薄膜晶体管及其制造方法
CN203134811U (zh) * 2013-03-25 2013-08-14 合肥京东方光电科技有限公司 薄膜晶体管、阵列基板和显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010056541A (ja) * 2008-07-31 2010-03-11 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
CN102629054A (zh) * 2011-10-20 2012-08-08 京东方科技集团股份有限公司 一种tft阵列基板及其制造方法、显示器件
CN202443973U (zh) 2012-02-28 2012-09-19 北京京东方光电科技有限公司 氧化物半导体薄膜晶体管与显示装置
JP5838119B2 (ja) * 2012-04-24 2015-12-24 株式会社ジャパンディスプレイ 薄膜トランジスタ及びそれを用いた表示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196371A (ja) * 2000-01-12 2001-07-19 Furontekku:Kk 銅配線基板及びその製造方法並びに液晶表示装置
US20070194386A1 (en) * 2006-02-17 2007-08-23 Samsung Electronics Co. Ltd. Methods of fabricating organic thin film transistors and organic thin film transistors fabricated using the same
CN101814529A (zh) * 2009-02-20 2010-08-25 株式会社半导体能源研究所 薄膜晶体管及其制造方法,以及半导体装置
CN101894760A (zh) * 2010-06-10 2010-11-24 友达光电股份有限公司 薄膜晶体管及其制造方法
CN203134811U (zh) * 2013-03-25 2013-08-14 合肥京东方光电科技有限公司 薄膜晶体管、阵列基板和显示装置

Also Published As

Publication number Publication date
US9437622B2 (en) 2016-09-06
CN103199114A (zh) 2013-07-10
US20150279869A1 (en) 2015-10-01
CN103199114B (zh) 2016-11-16

Similar Documents

Publication Publication Date Title
US10615266B2 (en) Thin-film transistor, manufacturing method thereof, and array substrate
US10795478B2 (en) Array substrate and preparation method therefor, and display apparatus
JP6416128B2 (ja) 薄膜トランジスターの製作方法
WO2018196087A1 (zh) 一种阵列基板、显示装置及其制作方法
US9246007B2 (en) Oxide thin film transistor and method for manufacturing the same, array substrate, and display apparatus
WO2019010960A1 (zh) 阵列基板及其制备方法、显示面板、显示装置
US10236388B2 (en) Dual gate oxide thin-film transistor and manufacturing method for the same
US9842915B2 (en) Array substrate for liquid crystal display device and method of manufacturing the same
KR20120110040A (ko) 비정질 산화물 박막 트랜지스터, 그 형성방법 및 이를 포함한 디스플레이 패널
WO2018176784A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
WO2015165174A1 (zh) 一种薄膜晶体管及其制作方法、显示基板、显示装置
WO2017008345A1 (zh) 薄膜晶体管、薄膜晶体管的制造方法及显示装置
WO2015067054A1 (zh) 互补式薄膜晶体管及其制备方法、阵列基板和显示装置
WO2017219412A1 (zh) 顶栅型薄膜晶体管的制作方法
EP3001460B1 (en) Thin film transistor and preparation method therefor, display substrate, and display apparatus
WO2018196289A1 (zh) 薄膜晶体管及其制备方法
TW201715650A (zh) 薄膜電晶體及其製造方法
WO2019095408A1 (zh) 阵列基板及其制作方法、显示面板
WO2014153853A1 (zh) 薄膜晶体管及其制造方法、阵列基板和显示装置
US11289513B2 (en) Thin film transistor and method for fabricating the same, array substrate and display device
WO2015085605A1 (zh) 一种igzo电晶体结构及其制造方法
CN203134811U (zh) 薄膜晶体管、阵列基板和显示装置
US10692948B2 (en) Array substrate, manufacturing method thereof and display panel
WO2018045612A1 (zh) 氧化物薄膜晶体管的制备方法
CN209641659U (zh) 一种提升tft稳定性的基板结构

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14355058

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13880139

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13880139

Country of ref document: EP

Kind code of ref document: A1