WO2018045612A1 - 氧化物薄膜晶体管的制备方法 - Google Patents

氧化物薄膜晶体管的制备方法 Download PDF

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WO2018045612A1
WO2018045612A1 PCT/CN2016/101523 CN2016101523W WO2018045612A1 WO 2018045612 A1 WO2018045612 A1 WO 2018045612A1 CN 2016101523 W CN2016101523 W CN 2016101523W WO 2018045612 A1 WO2018045612 A1 WO 2018045612A1
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layer
thin film
film transistor
oxide thin
active layer
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French (fr)
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谢应涛
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武汉华星光电技术有限公司
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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to the field of semiconductor device manufacturing technologies, and in particular, to a method for fabricating an oxide thin film transistor, which is mainly used in an array substrate of a display device.
  • the flat panel display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the conventional flat panel display device mainly includes a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • Thin Film Transistors (TFTs) are an important part of flat panel display devices and can be formed on glass substrates or plastic substrates, and are commonly used as light-emitting devices and driving devices such as LCDs and OLEDs.
  • IGZO indium gallium zinc oxide
  • IGZO indium gallium zinc oxide
  • IGZO is an amorphous oxide containing indium, gallium and zinc, which has high mobility and carrier mobility of 20 to 30 times that of amorphous silicon.
  • Improve the charge and discharge rate of the TFT electrode to the pixel electrode, with high on-state current, low off-state current can be quickly switched, improve the response speed of the pixel, achieve faster refresh rate, and faster response also greatly improves the pixel scan of the pixel. The rate makes ultra-high resolution possible in the display panel.
  • an insulating dielectric layer is generally required to be deposited on the active layer of the indium gallium zinc oxide semiconductor, and the film forming process of the insulating dielectric layer has a large indium gallium zinc oxide semiconductor.
  • the effects such as the H atoms generated in the film formation process, increase the conductivity of the indium gallium zinc oxide semiconductor and ultimately affect the performance parameters of the thin film transistor, such as the threshold voltage.
  • the film forming process there may be process instability or unstable device parameters, which leads to a large difference in the performance parameters of the thin film transistor, and finally affects the uniformity of device formation in the array substrate. Therefore, how to reduce the difference in device performance due to different film forming processes and improve the repeatability of the film forming process are problems that those skilled in the art need to solve.
  • the present invention provides a method for preparing an oxide thin film transistor, which reduces the difference in device performance due to different film forming processes and improves the repeatability of the film forming process.
  • a method of fabricating an oxide thin film transistor comprising: providing a substrate and preparing an oxide semiconductor active layer on a substrate; depositing an insulating dielectric layer on the active layer; and forming a structural member after depositing the insulating dielectric layer Annealing is performed.
  • the annealing treatment environment is air, dry oxygen or wet oxygen atmosphere, the annealing temperature is 250-450 ° C, and the annealing time is 0.5-3 h.
  • the annealing process is performed by using a hot air annealing process or an infrared annealing process.
  • the oxide semiconductor is indium gallium zinc oxide.
  • the insulating dielectric layer comprises at least a silicon oxide film layer directly connected to the active layer.
  • the insulating dielectric layer further comprises a silicon nitride film layer on the silicon oxide film layer.
  • the material of the gate insulating layer is silicon oxide
  • step S25 includes:
  • step S25 further includes:
  • the process of annealing the formed structural member is increased, and the insulating medium is prepared.
  • the layer performance is improved by the difference in device performance caused by different film formation processes, which improves the repeatability of the film formation process.
  • FIG. 1 is a process flow diagram of a method of fabricating an oxide thin film transistor according to an embodiment of the present invention
  • FIGS. 2a-2e are flowcharts showing a method of fabricating an oxide thin film transistor according to Embodiment 1 of the present invention
  • 3a-3h are flowcharts showing a method of fabricating an oxide thin film transistor according to Embodiment 2 of the present invention.
  • This embodiment provides a method for preparing an oxide thin film transistor, as shown in the flow chart of FIG. 1, the method includes:
  • the structural member formed after depositing the insulating dielectric layer is annealed.
  • the environment for annealing treatment may be selected as air, dry oxygen or wet oxygen atmosphere, the annealing temperature may be selected between 250 and 450 ° C, and the annealing time may be selected to be 0.5 to 3 h.
  • an annealing treatment may be performed by applying a hot air annealing process or an infrared annealing process in an annealing furnace.
  • the oxide semiconductor is selected from indium gallium zinc oxide (IGZO).
  • the insulating dielectric layer is, for example, a passivation layer deposited on the active layer in a thin film transistor of a bottom gate structure, or a gate insulating layer deposited on the active layer in a thin film transistor of a top gate structure.
  • the insulating dielectric layer includes at least a silicon oxide film layer directly connected to the active layer.
  • the insulating dielectric layer further includes a silicon nitride (SiN x ) thin film layer deposited on the silicon oxide (SiO x ) thin film layer.
  • FIGS. 2a-2e show a flow chart of the preparation method of the present embodiment. Referring to Figures 2a-2e, the method includes the steps of:
  • a substrate 11 is provided and a gate electrode 12 is formed on the substrate 11.
  • the substrate 11 may be a glass substrate, and the material of the gate electrode 12 is a metal conductive material.
  • a metal conductive film is first deposited on the substrate 11 by a physical vapor deposition process (PVD), and then the metal conductive film is etched by a photomask process to form a patterned gate electrode 12.
  • PVD physical vapor deposition process
  • a gate insulating layer 13 is deposited on the substrate 11 having the gate electrode 12.
  • the material of the gate insulating layer 13 may be SiO x or SiN x , and the gate insulating layer 13 may be obtained by a chemical vapor deposition process (CVD).
  • an oxide semiconductor active layer 14 is formed on the gate insulating layer 13.
  • the oxide semiconductor is selected to be IGZO.
  • an IGZO thin film layer is first deposited on the gate insulating layer 13 by a physical vapor deposition process (PVD), and then the IGZO thin film layer is etched by a photomask process to form a patterned active layer 14.
  • PVD physical vapor deposition process
  • a source electrode 15 and a drain electrode 16 are formed on the gate insulating layer 13, and the source electrode 15 and the drain electrode 16 are electrically connected to the active layer 14, respectively.
  • the material of the source electrode 15 and the drain electrode 16 is a metal conductive material.
  • a metal conductive film is deposited on the gate insulating layer 13 by a physical vapor deposition process (PVD), and the metal conductive film covers the active layer 14; then the metal conductive film is etched by a photomask process to form a patterned source.
  • Electrode 15 and drain electrode 16 are spaced apart from each other and are electrically connected to the active layer 14, respectively.
  • a passivation layer 17 is deposited on the active layer 14, and the passivation layer 17 covers the source electrode 15 and the drain electrode 16.
  • the material of the passivation layer 17 is silicon oxide, and the passivation layer 17 can be obtained by a plasma enhanced chemical vapor deposition process (PECVD).
  • the structural member formed after depositing the passivation layer 17 (that is, the structural member formed after the step S15 is completed) is annealed. Specifically, the structural member was placed in an annealing furnace having an air atmosphere, and subjected to a hot air annealing process, and annealed at a temperature of 350 ° C for 1 hour to complete the preparation of the oxide thin film transistor.
  • an infrared annealing process may also be selected, and the environment for annealing may also be selected as a dry oxygen or wet oxygen atmosphere, and the annealing temperature may be selected at 250. Between -450 ° C, the annealing time can be selected to be 0.5 to 3 hours.
  • step S16 it is further required to sequentially prepare an organic flat layer and a pixel electrode on the passivation layer 17.
  • each mask process includes a mask, an exposure, a development, an etching, and a stripping process, respectively, wherein the etching process includes dry etching and wet etching.
  • the parameters of the reticle process may vary in each step, but in the field of display manufacturing, the reticle process is already a relatively mature process technology, and will not be described in detail herein.
  • Mobility refers to the mobility of the sample (thin film transistor)
  • Vth refers to the threshold voltage of the sample
  • SS refers to the Subthreshold Swing of the sample.
  • the samples 1, the sample 2, and the sample 3 in the first group of samples were prepared by referring to the process steps of the present example, but were not subjected to the de-processing (ie, the annealing process of step S16 was omitted).
  • the process parameters of depositing the passivation layer in the sample 1, the sample 2 and the sample 3 in step S15 are different, that is, in the film forming process of step S15, the remaining parameters such as the cavity pressure and the gas flow rate are consistent.
  • the power of the device was set to 1400 W to prepare Sample 1
  • the power of the device was set to 1000 W to prepare Sample 2
  • the power of the device was set to 600 W to prepare Sample 3.
  • the sample 4, the sample 5 and the sample 6 in the second group of samples were completely prepared according to the process steps of the present example (the annealing process of step S16 was added compared to the first group of samples).
  • the process parameters of the sample 4, the sample 5 and the sample 6 for depositing the passivation layer in step S15 are different, that is, when the film forming process of step S15 is performed, the remaining parameters such as the cavity pressure and the gas flow rate are consistent.
  • the power of the device was set to 1400 W to prepare Sample 4
  • the power of the device was set to 1000 W to prepare Sample 5
  • the power of the device was set to 600 W to prepare Sample 6.
  • the difference of the subthreshold swing is also small, which shows that after the process of increasing the decommissioning process, the difference in device performance caused by different film forming processes can be effectively reduced when the passivation layer is prepared, and the film forming process is improved. Repeatability.
  • FIGS. 3a-2h show a flow chart of the preparation method of the present embodiment. Referring to Figures 3a-2h, the method includes the steps of:
  • a substrate 21 is provided and a buffer layer 22 is prepared on the substrate 21.
  • the material of the buffer layer 22 may be SiO x , and the buffer layer 22 may be obtained by a chemical vapor deposition process (CVD).
  • the oxide semiconductor active layer 23 is formed on the buffer layer 22.
  • the oxide semiconductor is selected to be IGZO.
  • an IGZO thin film layer is first deposited on the buffer layer 22 by a physical vapor deposition process (PVD), and then the IGZO thin film layer is etched by a photomask process to form a patterned active layer 23.
  • PVD physical vapor deposition process
  • a gate insulating layer 24 is formed on the semiconductor active layer 23, and the material of the gate insulating layer 24 is silicon oxide.
  • the gate insulating layer 24 can be obtained by a chemical vapor deposition process (CVD).
  • the structural member formed after depositing the gate insulating layer 24 (that is, the structural member formed after the step S23 is completed) is annealed. Specifically, the structural member was placed in an annealing furnace having an air atmosphere, and annealed at a temperature of 350 ° C for 1 hour using a hot air annealing process.
  • an infrared annealing process may also be selected, and the environment for annealing may also be selected as a dry oxygen or wet oxygen atmosphere, and the annealing temperature may be selected at 250.
  • the annealing time can be selected to be 0.5 to 3 hours.
  • a gate electrode 25 is formed on the gate insulating layer 24 subjected to the annealing treatment.
  • the material of the gate electrode 25 is a metal conductive material.
  • a metal conductive film is first deposited on the gate insulating layer 24 by a physical vapor deposition process (PVD), and then the metal conductive film is etched by a photomask process to form a patterned gate electrode 25.
  • PVD physical vapor deposition process
  • the step specifically includes:
  • the layer 24 covers only the intermediate portion of the active layer 23, and the active layer 23 is exposed on both sides of the gate insulating layer 24.
  • an interlayer dielectric layer (ILD) 26 is formed on the gate electrode 25, and the interlayer dielectric layer 26 covers the buffer layer 22.
  • the material of the interlayer dielectric layer 26 may be SiO x or SiN x , and the interlayer dielectric layer 26 may be obtained by a chemical vapor deposition process (CVD).
  • via holes 26a, 26b connected to the active layer 23 are etched in the interlayer dielectric layer 26.
  • the via holes 26a, 26b are formed by a photomask process etching, the via holes 26a are communicated to the source connection portion 23a, and the via holes 26b are communicated to the drain connection portion 23b.
  • a source electrode 27 and a drain electrode 28 are prepared on the interlayer dielectric layer 26, and the source electrode 27 and the drain electrode 28 are electrically connected to the via hole 26a, 26b, respectively.
  • the source layer 23 completes the preparation of the oxide thin film transistor.
  • the material of the source electrode 27 and the drain electrode 28 is a metal conductive material.
  • a metal conductive film is first deposited on the interlayer dielectric layer 26 by a physical vapor deposition process (PVD); the metal conductive film is then etched by a photomask process to form a patterned source electrode 26 and drain electrode 27.
  • the source electrode 26 and the drain electrode 27 are spaced apart from each other, and the source electrode 26 is connected to the source connection portion 23a through a via hole 26a, and the drain electrode 27 is connected to the drain connection portion 23b through a via hole 26b.
  • the source connection portion 23a and the drain connection portion 23b are in the same layer and integrated structure as the active layer 23, and the source connection portion 23a and the drain connection portion 23b have good electrical conductivity, whereby When the source electrode 26 and the drain electrode 27 are connected to the active layer 23 through the source connection portion 23a and the drain connection portion 23b, respectively, the contact resistance between the source electrode 26 and the drain electrode 27 and the active layer 23 is reduced, and the contact resistance is improved. The performance of the device.
  • step S28 it is further required to sequentially prepare an organic flat layer and a pixel electrode on the interlayer dielectric layer 26.
  • each mask process includes a mask, an exposure, a development, an etching, and a stripping process, respectively, wherein the etching process includes dry etching and wet etching.
  • the parameters of the reticle process may vary in each step, but in the field of display manufacturing, the reticle process is already a relatively mature process technology, and will not be described in detail herein.
  • the process of annealing the formed structural member is increased, thereby reducing
  • the difference in device performance due to different film forming processes improves the repeatability of the film forming process.

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Abstract

提供了一种氧化物薄膜晶体管的制备方法，包括：提供一基底并在基底上制备形成氧化物半导体有源层；在所述有源层上沉积绝缘介质层；将沉积绝缘介质层后形成的结构件进行退火处理。本发明在氧化物半导体有源层上沉积完成绝缘介质层之后，即对所形成的结构件增加进行退火处理的工艺，降低了在制备绝缘介质层时因不同的成膜工艺所带来的器件性能差异，提高了成膜工艺的可重复性。

Description

氧化物薄膜晶体管的制备方法 技术领域
本发明涉及半导体器件制造技术领域,尤其涉及一种氧化物薄膜晶体管的制备方法，该氧化物薄膜晶体管主要应用于显示装置的阵列基板中。
背景技术
平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机电致发光显示装置(Organic Light Emitting Display，OLED)。薄膜晶体管(Thin Film Transistor，TFT)是平板显示装置的重要组成部分，可形成在玻璃基板或塑料基板上，通常作为开光装置和驱动装置用在诸如LCD、OLED。
在显示面板工业中，随着目前显示行业中大尺寸化，高解析度的需求越来越强烈，对有源层半导体器件充放电提出了更高的要求。IGZO(indium gallium zinc oxide，铟镓锌氧化物)是一种含有铟、镓和锌的非晶氧化物，其具有高迁移率，载流子迁移率是非晶硅的20～30倍，可以大大提高TFT对像素电极的充放电速率，具有高开态电流、低关态电流可以迅速开关，提高像素的响应速度，实现更快的刷新率，同时更快的响应也大大提高了像素的行扫描速率，使得超高分辨率在显示面板中成为可能。
在铟镓锌氧化物薄膜晶体管的制备工艺中，在铟镓锌氧化物半导体有源层上通常都需要沉积有绝缘介质层，绝缘介质层的成膜工艺对铟镓锌氧化物半导体具有较大的影响，例如成膜工艺中产生的H原子会提高铟镓锌氧化物半导体的导电性能，最终会影响薄膜晶体管的性能参数，例如阈值电压。成膜工艺中可能存在制程不稳定或设备参数不稳定，导致薄膜晶体管的性能参数出现较大的差异化，最终影响阵列基板中器件形成的均匀性。因此，如何降低因不同的成膜工艺所带来的器件性能差异、提高成膜工艺的可重复性是本领域技术人员需要解决的问题。
发明内容
有鉴于此，本发明提供了一种氧化物薄膜晶体管的制备方法，该方法降低因了不同的成膜工艺所带来的器件性能差异，提高了成膜工艺的可重复性。
为了实现上述目的，本发明采用了如下的技术方案：
一种氧化物薄膜晶体管的制备方法，包括：提供一基底并在基底上制备形成氧化物半导体有源层；在所述有源层上沉积绝缘介质层；将沉积绝缘介质层后形成的结构件进行退火处理。
其中，进行退火处理的环境为空气、干氧或湿氧气氛，退火温度为250～450℃，退火时间为0.5～3h。
其中，应用热风式退火工艺或红外退火工艺进行退火处理。
其中，所述氧化物半导体为铟镓锌氧化物。
其中，所述绝缘介质层至少包括直接连接在所述有源层上的氧化硅薄膜层。
其中，所述绝缘介质层还包括位于所述氧化硅薄膜层上的氮化硅薄膜层。
其中，该方法包括步骤：
S11、提供一基底并在基底上制备栅电极；
S12、在具有栅电极的基底上沉积栅极绝缘层；
S13、在所述栅极绝缘层上制备所述氧化物半导体有源层；
S14、在所述栅极绝缘层上制备源电极和漏电极，并且所述源电极和漏电极分别电连接到所述有源层；
S15、在所述有源层上沉积钝化层，并且所述钝化层覆盖所述源电极和漏电极，所述钝化层的材料为氧化硅；
S16、将沉积所述钝化层后形成的结构件进行退火处理。
其中，该方法包括步骤：
S21、提供一基底并在基底上制备缓冲层；
S22、在所述缓冲层上制备所述氧化物半导体有源层；
S23、在所述半导体有源层上制备栅极绝缘层，所述栅极绝缘层的材料为氧化硅；
S24、将沉积所述栅极绝缘层后形成的结构件进行退火处理；
S25、在进行退火处理的栅极绝缘层上制备栅电极；
S26、在所述栅电极上制备层间介质层，并且所述层间介质层覆盖所述缓冲层；
S27、在所述层间介质层中刻蚀出连通到所述有源层的过孔；
S28、在所述层间介质层上制备源电极和漏电极，所述源电极和漏电极分别通过所述过孔电连接到所述有源层。
其中，步骤S25包括：
S251、应用顶栅自对准工艺刻蚀形成栅电极，并相应刻蚀位于所述栅电极下方的栅极绝缘层，以使所述栅极绝缘层仅覆盖所述有源层的中间区域，所述栅极绝缘层的两侧裸露出所述有源层；所述源电极和漏电极分别连接于所述有源层裸露出于所述栅极绝缘层的部分。
其中，步骤S25还包括：
S252、应用离子注入工艺或等离子轰击工艺或金属氧化工艺，将裸露出的有源层转化为导体，在所述有源层的一端形成源极连接部，另一端形成漏极连接部，所述源极连接部用于连接所述源电极，所述漏极连接部用于连接所述漏电极。
本发明实施例中提供的氧化物薄膜晶体管的制备方法，在氧化物半导体有源层上沉积完成绝缘介质层之后，即对所形成的结构件增加进行退火处理的工艺，降低了在制备绝缘介质层时因不同的成膜工艺所带来的器件性能差异，提高了成膜工艺的可重复性。
附图说明
图1是本发明实施例提供的氧化物薄膜晶体管的制备方法的工艺流程图；
图2a-2e是本发明实施例1提供的氧化物薄膜晶体管的制备方法的流程图示；
图3a-3h是本发明实施例2提供的氧化物薄膜晶体管的制备方法的流程图示。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明的具体实施方式进行详细说明。这些优选实施方式的示例在附图中进行了例示。附图中所示和根据附图描述的本发明的实施方式仅仅是示例性的，并且本发明并不限于这些实施方式。
在此，还需要说明的是，为了避免因不必要的细节而模糊了本发明，在附图中仅仅示出了与根据本发明的方案密切相关的结构和/或处理步骤，而省略了与本发明关系不大的其他细节。
本实施例提供了一种氧化物薄膜晶体管的制备方法，如图1所示的流程图，该方法包括：
提供一基底并在基底上制备形成氧化物半导体有源层；
在所述有源层上沉积绝缘介质层；
将沉积绝缘介质层后形成的结构件进行退火处理。
在该方法中，进行退火处理的环境可以选择为空气、干氧或湿氧气氛，退火温度可以选择在250～450℃之间，退火时间可以选择为0.5～3h。
在该方法中，可以在退火炉中应用热风式退火工艺或红外退火工艺进行退火处理。
其中，所述氧化物半导体选择为铟镓锌氧化物(indium gallium zinc oxide，IGZO)。
其中，所述绝缘介质层例如是底栅结构的薄膜晶体管中在有源层上所沉积的钝化层，或者是顶栅结构的薄膜晶体管中在有源层上所沉积的栅极绝缘层。所述绝缘介质层至少包括直接连接在所述有源层上的氧化硅薄膜层。在另外的一些实施例中，所述绝缘介质层还包括沉积在所述氧化硅(SiOx)薄膜层上的氮化硅(SiNx)薄膜层。
实施例1
本实施例提供了一种底栅结构的氧化物薄膜晶体管的制备方法，图2a-2e示出了本实施例的制备方法的流程图示。参阅图2a-2e，该方法包括步骤：
S11、如图2a所示，提供一基底11并在基底11上制备栅电极12。具体地，所述基底11可以选用玻璃基底，所述栅电极12的材料为金属导电材料。首先通过物理气相沉积工艺(PVD)在基底11上沉积金属导电薄膜，然后通过光罩工艺将所述金属导电薄膜刻蚀形成图案化的栅电极12。
S12、如图2b所示，在具有栅电极12的基底11上沉积栅极绝缘层13。所述栅极绝缘层13的材料可以为SiOx或SiNx，所述栅极绝缘层13可以通过化学气相沉积工艺(CVD)制备获得。
S13、如图2c所示，在所述栅极绝缘层13上制备氧化物半导体有源层14。其中，所述氧化物半导体选择为IGZO。具体地，首先通过物理气相沉积工艺(PVD)在栅极绝缘层13上沉积IGZO薄膜层，然后通过光罩工艺将所述IGZO薄膜层刻蚀形成图案化的有源层14。
S14、如图2d所示，在所述栅极绝缘层13上制备源电极15和漏电极16，并且所述源电极15和漏电极16分别电连接到所述有源层14。所述源电极15和漏电极16的材料为金属导电材料。首先通过物理气相沉积工艺(PVD)在栅极绝缘层13上沉积金属导电薄膜，金属导电薄膜覆盖所述有源层14；然后通过光罩工艺将所述金属导电薄膜刻蚀形成图案化的源电极15和漏电极16。所述源电极15和漏电极16相互间隔，并且分别电连接到所述有源层14。
S15、如图2e所示，在所述有源层14上沉积钝化层(Passivation Layer)17，并且所述钝化层17覆盖所述源电极15和漏电极16。其中，所述钝化层17的材料为氧化硅，所述钝化层17可以通过等离子体增强化学气相沉积工艺(PECVD)制备获得。
S16、将沉积所述钝化层17后形成的结构件(即完成步骤S15后形成的结构件)进行退火处理。具体地，将该结构件放置在具有空气气氛的退火炉中，应用热风式退火工艺，以温度为350℃退火1小时，完成所述氧化物薄膜晶体管的制备。当然，在另外的一些实施例中，如前所述，在进行退火处理时，还可以选择红外退火工艺，进行退火处理的环境还可以选择为干氧或湿氧气氛，退火温度可以选择在250～450℃之间，退火时间可以选择为0.5～3小时。
进一步地，如果所述氧化物薄膜晶体管应用于显示装置的阵列基板中，则在完成步骤S16形成的结构之后，还需要在钝化层17上依次制备有机平坦层和像素电极。
以上的制备工艺中，每一次光罩工艺中又分别包括掩膜、曝光、显影、刻蚀和剥离等工艺，其中刻蚀工艺包括干法刻蚀和湿法刻蚀。在各个步骤中光罩工艺的参数可能有所不同，但是在显示器的制造领域，光罩工艺已经是现有的比较成熟的工艺技术，在此不再展开详细说明。
本实施例中具体制备两组样品进行对比，获得如下表1的数据，以说明本发明所取得的有益效果。
表1
Figure PCTCN2016101523-appb-000001
表1的数据中，Mobility是指样品(薄膜晶体管)的迁移率，Vth是指样品的阈值电压，SS是指样品的亚阈值摆幅(Subthreshold Swing)。
其中，第一组样品中的样品1、样品2和样品3参照本实施例的工艺步骤制备获得，但是不进行退工处理(即缺少了步骤S16的退火工艺)。其中，样品1、样品2和样品3在步骤S15沉积钝化层的工艺参数有所差异，即，在进行步骤S15的成膜工艺时，在腔体压力、气体流量等其余参数保持一致的情况下，将设备的功率设定为1400W制备获得样品1，将设备的功率设定为1000W制备获得样品2，将设备的功率设定为600W制备获得样品3。
其中，第二组样品中的样品4、样品5和样品6则完全按照本实施例的工艺步骤制备获得(相比于第一组样品增加了步骤S16的退火工艺)。其中，样品4、样品5和样品6在步骤S15沉积钝化层的工艺参数有所差异，即，在进行步骤S15的成膜工艺时，在腔体压力、气体流量等其余参数保持一致的情况下，将设备的功率设定为1400W制备获得样品4，将设备的功率设定为1000W制备获得样品5，将设备的功率设定为600W制备获得样品6。
从表1的数据中可以看出，在氧化物半导体有源层上沉积完成钝化层之后， 不进行退工处理的第一组样品中，各个样品的阈值电压Vth较大，并且样品之间的阈值电压的差值也比较大，样品之间的亚阈值摆幅差值也比较大，说明了钝化层的不同成膜工艺所带来的器件性能差异较大。而进行退工处理的第二组样品中，各个样品的阈值电压较为接近于0，并且样品之间的阈值电压的差值也比较小，各个样品的亚阈值摆幅也比较小，样品之间的亚阈值摆幅的差值也比较小，说明了在增加退工处理工艺之后，可以有效降低在制备钝化层时因不同的成膜工艺所带来的器件性能差异，提高了成膜工艺的可重复性。
实施例2
本实施例提供了一种顶栅结构的氧化物薄膜晶体管的制备方法，图3a-2h示出了本实施例的制备方法的流程图示。参阅图3a-2h，该方法包括步骤：
S21、如图3a所示，提供一基底21并在基底21上制备缓冲层(Buffer Layer)22。所述缓冲层22的材料可以为SiOx，所述缓冲层22可以通过化学气相沉积工艺(CVD)制备获得。
S22、如图3b所示，在所述缓冲层22上制备所述氧化物半导体有源层23。其中，所述氧化物半导体选择为IGZO。具体地，首先通过物理气相沉积工艺(PVD)在缓冲层22上沉积IGZO薄膜层，然后通过光罩工艺将所述IGZO薄膜层刻蚀形成图案化的有源层23。
S23、如图3c所示，在所述半导体有源层23上制备栅极绝缘层24，所述栅极绝缘层24的材料为氧化硅。所述栅极绝缘层24可以通过化学气相沉积工艺(CVD)制备获得。
S24、将沉积所述栅极绝缘层24后形成的结构件((即完成步骤S23后形成的结构件))进行退火处理。具体地，将该结构件放置在具有空气气氛的退火炉中，应用热风式退火工艺，以温度为350℃退火1小时。当然，在另外的一些实施例中，如前所述，在进行退火处理时，还可以选择红外退火工艺，进行退火处理的环境还可以选择为干氧或湿氧气氛，退火温度可以选择在250～450℃之间，退火时间可以选择为0.5～3小时。
S25、如图3d所示，在进行退火处理的栅极绝缘层24上制备栅电极25。其中，所述栅电极25的材料为金属导电材料。首先通过物理气相沉积工艺(PVD)在栅极绝缘层24上沉积金属导电薄膜，然后通过光罩工艺将所述金属导电薄膜刻蚀形成图案化的栅电极25。
在本实施例中，该步骤具体包括：
S251、参阅图3d，应用顶栅自对准工艺刻蚀所述金属导电薄膜形成栅电极25，并相应刻蚀位于所述栅电极25下方的栅极绝缘层24，以使所述栅极绝缘层24仅覆盖所述有源层23的中间区域，所述栅极绝缘层24的两侧裸露出所述有源层23。
S252、参阅图3e，应用离子注入工艺或等离子轰击工艺或金属氧化工艺，将裸露出的有源层23转化为导体，由此在所述有源层23的一端形成源极连接部23a，另一端形成漏极连接部23b。
S26、如图3f所示，在所述栅电极25上制备层间介质层(Inter Layer Dielectric，ILD)26，并且所述层间介质层26覆盖所述缓冲层22。所述层间介质层26的材料可以为SiOx或SiNx，所述层间介质层26可以通过化学气相沉积工艺(CVD)制备获得。
S27、如图3g所示，在所述层间介质层26中刻蚀出连通到所述有源层23的过孔26a、26b。具体地，采用光罩工艺刻蚀形成所述过孔26a、26b，过孔26a连通至所述源极连接部23a，过孔26b连通至所述漏极连接部23b。
S28、如图3h所示，在所述层间介质层26上制备源电极27和漏电极28，所述源电极27和漏电极28分别通过所述过孔26a、26b电连接到所述有源层23，完成所述氧化物薄膜晶体管的制备。其中，所述源电极27和漏电极28的材料为金属导电材料。首先通过物理气相沉积工艺(PVD)在层间介质层26上沉积金属导电薄膜；然后通过光罩工艺将所述金属导电薄膜刻蚀形成图案化的源电极26和漏电极27。所述源电极26和漏电极27相互间隔，所述源电极26通过过孔26a连接至所述源极连接部23a，所述漏电极27通过过孔26b连接至所述漏极连接部23b。如上结构中，源极连接部23a和漏极连接部23b与有源层23是同层且为一体的结构，并且源极连接部23a和漏极连接部23b具有良好的导电性能，由此，源电极26和漏电极27分别通过源极连接部23a和漏极连接部23b连接到有源层23时，减小了源电极26和漏电极27与有源层23之间的接触电阻，提高了器件的性能。
进一步地，如果所述氧化物薄膜晶体管应用于显示装置的阵列基板中，则在完成步骤S28形成的结构之后，还需要在层间介质层26上依次制备有机平坦层和像素电极。
以上的制备工艺中，每一次光罩工艺中又分别包括掩膜、曝光、显影、刻蚀和剥离等工艺，其中刻蚀工艺包括干法刻蚀和湿法刻蚀。在各个步骤中光罩工艺的参数可能有所不同，但是在显示器的制造领域，光罩工艺已经是现有的比较成熟的工艺技术，在此不再展开详细说明。
综上所述，本发明实施例中提供的氧化物薄膜晶体管的制备方法，在氧化物半导体有源层上沉积完成绝缘介质层之后，即对所形成的结构件增加进行退火处理的工艺，降低了在制备绝缘介质层时因不同的成膜工艺所带来的器件性能差异，提高了成膜工艺的可重复性。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (15)

  1. 一种氧化物薄膜晶体管的制备方法，其中，包括：
    提供一基底并在基底上制备形成氧化物半导体有源层；
    在所述有源层上沉积绝缘介质层；
    将沉积绝缘介质层后形成的结构件进行退火处理。
  2. 根据权利要求1所述的氧化物薄膜晶体管的制备方法，其中，进行退火处理的环境为空气、干氧或湿氧气氛，退火温度为250～450℃，退火时间为0.5～3h。
  3. 根据权利要求2所述的氧化物薄膜晶体管的制备方法，其中，应用热风式退火工艺或红外退火工艺进行退火处理。
  4. 根据权利要求1所述的氧化物薄膜晶体管的制备方法，其中，所述氧化物半导体为铟镓锌氧化物。
  5. 根据权利要求1所述的氧化物薄膜晶体管的制备方法，其中，所述绝缘介质层至少包括直接连接在所述有源层上的氧化硅薄膜层。
  6. 根据权利要求5所述的氧化物薄膜晶体管的制备方法，其中，所述绝缘介质层还包括位于所述氧化硅薄膜层上的氮化硅薄膜层。
  7. 根据权利要求1所述的氧化物薄膜晶体管的制备方法，其中，该方法包括步骤：
    S11、提供一基底并在基底上制备栅电极；
    S12、在具有栅电极的基底上沉积栅极绝缘层；
    S13、在所述栅极绝缘层上制备所述氧化物半导体有源层；
    S14、在所述栅极绝缘层上制备源电极和漏电极，并且所述源电极和漏电极分别电连接到所述有源层；
    S15、在所述有源层上沉积钝化层，并且所述钝化层覆盖所述源电极和漏电极，所述钝化层的材料为氧化硅；
    S16、将沉积所述钝化层后形成的结构件进行退火处理。
  8. 一种氧化物薄膜晶体管的制备方法，其中，包括步骤：
    S21、提供一基底并在基底上制备缓冲层；
    S22、在所述缓冲层上制备所述氧化物半导体有源层；
    S23、在所述半导体有源层上制备栅极绝缘层，所述栅极绝缘层的材料为氧化硅；
    S24、将沉积所述栅极绝缘层后形成的结构件进行退火处理；
    S25、在进行退火处理的栅极绝缘层上制备栅电极；
    S26、在所述栅电极上制备层间介质层，并且所述层间介质层覆盖所述缓冲层；
    S27、在所述层间介质层中刻蚀出连通到所述有源层的过孔；
    S28、在所述层间介质层上制备源电极和漏电极，所述源电极和漏电极分别通过所述过孔电连接到所述有源层。
  9. 根据权利要求8所述的氧化物薄膜晶体管的制备方法，其中，步骤S25包括：
    S251、应用顶栅自对准工艺刻蚀形成栅电极，并相应刻蚀位于所述栅电极下方的栅极绝缘层，以使所述栅极绝缘层仅覆盖所述有源层的中间区域，所述栅极绝缘层的两侧裸露出所述有源层；所述源电极和漏电极分别连接于所述有源层裸露出于所述栅极绝缘层的部分。
  10. 根据权利要求9所述的氧化物薄膜晶体管的制备方法，其中，步骤S25还包括：
    S252、应用离子注入工艺或等离子轰击工艺或金属氧化工艺，将裸露出的有源层转化为导体，在所述有源层的一端形成源极连接部，另一端形成漏极连接部，所述源极连接部用于连接所述源电极，所述漏极连接部用于连接所述漏电极。
  11. 根据权利要求8所述的氧化物薄膜晶体管的制备方法，其中，进行退火处理的环境为空气、干氧或湿氧气氛，退火温度为250～450℃，退火时间为0.5～3h。
  12. 根据权利要求11所述的氧化物薄膜晶体管的制备方法，其中，应用热风式退火工艺或红外退火工艺进行退火处理。
  13. 根据权利要求8所述的氧化物薄膜晶体管的制备方法，其中，所述氧化物半导体为铟镓锌氧化物。
  14. 根据权利要求8所述的氧化物薄膜晶体管的制备方法，其中，所述栅极绝缘层至少包括直接连接在所述有源层上的氧化硅薄膜层。
  15. 根据权利要求14所述的氧化物薄膜晶体管的制备方法，其中，所述栅极绝缘层还包括位于所述氧化硅薄膜层上的氮化硅薄膜层。
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