WO2023030108A1 - 金属氧化物薄膜晶体管及其制备方法、显示面板 - Google Patents

金属氧化物薄膜晶体管及其制备方法、显示面板 Download PDF

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WO2023030108A1
WO2023030108A1 PCT/CN2022/114382 CN2022114382W WO2023030108A1 WO 2023030108 A1 WO2023030108 A1 WO 2023030108A1 CN 2022114382 W CN2022114382 W CN 2022114382W WO 2023030108 A1 WO2023030108 A1 WO 2023030108A1
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metal oxide
layer
insulating layer
oxygen
thin film
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PCT/CN2022/114382
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English (en)
French (fr)
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林滨
王洋
邹振游
乐发垫
席文星
余雪
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京东方科技集团股份有限公司
福州京东方光电科技有限公司
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Priority to EP22863247.7A priority Critical patent/EP4369417A1/en
Publication of WO2023030108A1 publication Critical patent/WO2023030108A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Definitions

  • the present application relates to the field of display technology, in particular to a metal oxide thin film transistor, a manufacturing method thereof, and a display panel.
  • Indium gallium zinc oxide (IGZO) is widely used in the preparation of channel layers in thin film transistors due to its high mobility, good uniformity and good transparency.
  • the present application provides an oxide thin film transistor, its preparation method, and a display panel, and the technical scheme is as follows:
  • a metal oxide thin film transistor is provided, and the metal oxide thin film transistor includes:
  • a gate, a gate insulating layer, a metal oxide semiconductor layer, a source, a drain, and a first insulating layer are sequentially arranged on the substrate;
  • the first insulating layer is in contact with the metal oxide semiconductor
  • the first insulating layer is an inorganic insulating layer containing silicon and oxygen, and the atomic percentage of oxygen contained in the first insulating layer is greater than 50%;
  • the atomic percentage of oxygen contained in the metal oxide semiconductor layer is greater than 45%.
  • the thickness of the first insulating layer is less than 2000 angstroms.
  • the peak bond energy of the silicon-oxygen bond in the first insulating layer is greater than 1060 cm-1 and not more than 1080 cm-1.
  • the first insulating layer is formed by controlling the oxygen content in the deposition process to form a film layer mainly composed of silicon oxide. The difference does not exceed 5%.
  • the first insulating layer includes: an opposite first surface and a second surface; the first surface is a surface close to the metal oxide semiconductor layer, and the second surface is a surface away from the metal oxide semiconductor layer. the surface of the material semiconductor layer;
  • the distribution of oxygen atoms is: the closer to the second surface, the difference in the percentage of oxygen-containing atoms per two adjacent test positions The larger the , the closer the position to the first surface is to the smaller the difference in the atomic number percentage of oxygen content between two adjacent test positions.
  • the metal oxide thin film transistor further includes a second insulating film, the second insulating film is located on a side of the first insulating layer away from the metal oxide semiconductor layer, and the second insulating film includes
  • the silicon element also contains at least one of oxygen element and nitrogen element.
  • the densities of the first insulating layer at multiple test positions along the thickness direction are the same;
  • the density of the first insulating layer is smaller than the density of the second insulating film
  • the etching rate exceeds 25 angstroms/second and does not exceed 40 angstroms/second.
  • the etching rate ranges from 28 ⁇ /sec to 35 ⁇ /sec.
  • the second insulating film includes a silicon nitride film layer.
  • the second insulating film includes a silicon oxide film layer and a silicon nitride film layer sequentially located on the first insulating layer;
  • the atomic percentage of oxygen in the silicon oxide film layer in the second insulating film does not exceed the atomic percentage of oxygen in the silicon oxide film layer in the first insulating film, and the difference between the two is greater than 5% to 15%.
  • the second insulating film includes a silicon oxide film layer, a silicon oxynitride film layer and a silicon nitride film layer sequentially located on the first insulating layer;
  • the atomic percentage of oxygen in the silicon oxide film layer in the second insulating film does not exceed the atomic percentage of oxygen in the silicon oxide film layer in the first insulating film, and the difference between the two is greater than 5% to 15%.
  • the atomic number ratio of silicon to oxygen in the silicon oxide film layer is 33:67
  • the atomic number ratio of silicon to oxygen in the silicon oxynitride film layer is 36:52:12
  • the silicon nitride film layer The atomic number ratio of silicon and nitrogen in the layer is 51:49.
  • the ratio of the thickness of the first insulating layer to the thickness of the second insulating film ranges from 0.2 to 0.5.
  • the hydrogen-containing atomic number percentage in the silicon oxide film layer in the first insulating layer is less than 3%, and the silicon-hydrogen bond number percentage in the silicon oxide film layer in the first insulating layer is less than 7% .
  • the thickness of the source and the drain is greater than 3000 angstroms and less than 6000 angstroms, and the thickness of the first insulating layer is greater than 500 angstroms and not more than 1100 angstroms;
  • the slope angles of the source and the drain are both less than 60 degrees.
  • the metal oxide semiconductor layer includes opposite first surfaces and second surfaces, and the first surface is closer to the base substrate;
  • the part of the metal oxide semiconductor layer close to the first surface includes an amorphous or nanocrystalline metal oxide; the part of the metal oxide semiconductor layer close to the second surface includes a C-axis crystallized metal oxide. thing;
  • the amorphous or nanocrystalline metal oxide contains at least one of indium, gallium, zinc, tin and praseodymium;
  • the C-axis crystallized metal oxide includes at least one of indium, gallium, zinc, tin and praseodymium.
  • the amorphous or nanocrystalline metal oxide includes indium gallium zinc oxide, the atomic number ratio of indium gallium zinc oxide is 4:2:3, or the indium gallium zinc oxide
  • the atomic number ratio of indium gallium zinc in the compound is 1:1:1, or the atomic number ratio of indium gallium zinc in the indium gallium zinc oxide is 1:3:6;
  • the C-axis crystallized metal oxide includes indium gallium zinc oxide, the atomic number ratio of indium gallium zinc in the indium gallium zinc oxide is 4:2:3, or the indium gallium zinc atoms in the indium gallium zinc oxide The number ratio is 1:1:1, or the atomic number ratio of the InGaZn oxide is 1:3:6.
  • the carrier mobility of a portion of the metal oxide semiconductor layer close to the first surface ranges from 10 cm2/V ⁇ sec to 20 cm2/V ⁇ sec.
  • a method for preparing a metal oxide thin film transistor comprising:
  • the first insulating layer is in contact with the metal oxide semiconductor
  • the first insulating layer is an inorganic insulating layer containing silicon and oxygen, and the atomic percentage of oxygen contained in the first insulating layer is greater than 50%;
  • the atomic percentage of oxygen contained in the metal oxide semiconductor layer is greater than 45%.
  • forming the first insulating layer includes:
  • Dinitrogen oxide and silicon tetrahydrogen are introduced into the reaction chamber, and a first insulating layer is formed on the substrate by using chemical vapor deposition equipment.
  • the method also includes:
  • An oxygen supplement layer is formed on the side of the first insulating layer away from the base substrate, wherein the material of the oxygen supplement layer includes oxide, and the orthographic projection of the oxygen supplement layer on the base substrate is the same as Orthographic projections of the metal oxide semiconductor layer on the base substrate at least partially overlap, and oxygen atoms in the oxygen supplement layer can diffuse from the first insulating layer to the metal oxide semiconductor layer;
  • the oxygen supplement layer is removed.
  • the deposition rate of the first insulating layer is greater than 10 angstroms/second.
  • the deposition rate of the first insulating layer ranges from 14 ⁇ /sec to 16 ⁇ /sec.
  • a display panel in yet another aspect, includes: a base substrate, and a plurality of metal oxide thin film transistors as described in the above aspect disposed on the base substrate.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a metal oxide semiconductor layer, a drain electrode, and a first insulating layer provided in an embodiment of the present application;
  • Fig. 3 is a schematic diagram of the percentage curves of the content of each element in the first insulating layer, the metal oxide semiconductor layer and the gate insulating layer provided by the embodiment of the present application;
  • Fig. 4 is a schematic diagram of the relationship between the ratio of nitrous oxide and silicon tetrafluoride and the peak value of the silicon-oxygen bond provided by the embodiment of the present application;
  • Fig. 5 is a schematic diagram of a test of a first insulating layer formed on a large-size substrate provided by an embodiment of the present application;
  • Fig. 6 is a schematic diagram of a bond energy curve of a silicon-oxygen bond provided in an embodiment of the present application.
  • Fig. 7 is a partial schematic view of Fig. 6 in area A;
  • FIG. 8 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another metal oxide semiconductor layer, a drain electrode, and a first insulating layer provided in an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of another metal oxide semiconductor layer, a drain electrode, and a first insulating layer provided in an embodiment of the present application;
  • FIG. 11 is a schematic structural diagram of a gate insulating layer, a metal oxide semiconductor layer and a first insulating layer provided in an embodiment of the present application;
  • Fig. 12 is a schematic structural diagram of a gate insulating layer, a drain, a first insulating layer and a second insulating film provided by an embodiment of the present application;
  • FIG. 13 is a schematic structural view of a gate, a gate insulating layer, a first insulating layer, and a second insulating film provided by an embodiment of the present application;
  • FIG. 14 is a flow chart of a method for manufacturing a metal oxide thin film transistor provided in an embodiment of the present application.
  • FIG. 15 is a schematic diagram of the relationship between the temperature of a substrate and the wet etching rate according to an embodiment of the present application.
  • a thin film transistor includes: a gate, a gate insulating layer, a semiconductor layer, a source, a drain and a passivation layer stacked in sequence along a direction away from a substrate.
  • the balance of hydrogen (H) and oxygen (O) is controlled to control the characteristics of the oxide TFT (for example, the threshold voltage (Vth) drift of the oxide TFT needs to be small, the drain lower current, etc.) is very important.
  • Factors affecting the characteristics of the oxide TFT need to control not only the target material or process conditions for fabricating the metal oxide semiconductor layer, but also the target material or process conditions for the film layer in contact with the metal oxide semiconductor layer. Such as control gate insulating layer and passivation layer. The control of the film quality of these films is relatively important.
  • the insulating layers gate insulating layer and passivation layer
  • the deposition rate and film quality of the insulating layer there are certain requirements on the deposition rate and film quality of the insulating layer.
  • the metal oxide thin film transistor provided in the embodiment of the present application is used in a display area or an array substrate row driver (gate driver on array, GOA) circuit area.
  • GOA gate driver on array
  • the metal oxide thin film transistor provided by the embodiment of the present application can be applied to small-sized mobile devices (Mobile), notebook computers (notebook, NB), tablet computers (iPAD), small and medium-sized monitors (monitor, MNT), medium and large-sized TVs (television, TV) and medium and large size MNT and other products.
  • the metal oxide thin film transistor provided in the embodiment of the present application can be used in the display field or the chip field, and the display field can be a liquid crystal (liquid crystal display, LCD) display panel, an organic light-emitting diode OLED (organic light-emitting diode, OLED) display panel , quantum dot light emitting diodes (quantum dot light emitting diodes, QLED) display panels, micro light emitting diode display panels (micro light emitting diode, Micro LED) and sensing and other technical fields.
  • the oxide thin film transistor provided in the embodiment of the present application may be used as a TFT of a pixel switch, or may be used as a TFT in a circuit such as a GOA circuit and a pixel driving circuit.
  • the metal oxide thin film transistor provided by the embodiment of the present application is more effective in solving the product of the bottom gate back channel etch structure (back channel etch, BCE) structure, but it is not limited to the product of this structure, such as the top gate structure Products also apply.
  • BCE back channel etch
  • a bottom-gate BCE structure is taken as an example for illustration.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the metal oxide thin film transistor 10 in the display panel 01 may include: a gate (gate) 101 sequentially arranged on a base substrate (substrate) 20, a gate insulating layer (gate insulator, GI ) 102, a metal oxide semiconductor layer 103, a source 104, a drain 105 and a first insulating layer 106 as a passivation layer.
  • the source electrode 104 and the drain electrode 105 are located in the same layer and can be prepared by the same patterning process. Wherein, both the source electrode 104 and the drain electrode 105 are electrically connected to the metal oxide semiconductor layer 103 .
  • a gate insulating layer 102 , a metal oxide semiconductor layer 103 , a source 104 , and a first insulating layer 106 are sequentially stacked in a direction away from the gate 101 . Furthermore, a side of the first insulating layer 106 close to the gate 101 is formed on the source 104 and the drain 105 to contact the metal oxide semiconductor layer 103 between the source 104 and the drain 105 . Exemplarily, the region of the metal oxide semiconductor layer 101 below the source 104 and the drain 105 is used as the first region, and the region between the source 104 and the drain 105 is used as the second region. A side of the first insulating layer 106 close to the gate 101 is in contact with the second region of the metal oxide semiconductor layer 103 .
  • the first insulating layer 106 is a silicon oxide layer
  • the film layer is an inorganic insulating layer containing at least silicon (Si) and oxygen in the element composition test.
  • Si silicon
  • the first insulating layer 106 there is also a small amount of nitrogen (N) element in the first insulating layer 106, but the atomic number of the nitrogen element is very small, so the first insulating layer 106 can be referred to simply as Silicon oxide (SiO) film layer.
  • the proportion of atomic number, atomic number percentage, and atomic percentage mentioned in this application can all be understood as the unit of
  • the testing equipment can be a transmission electron microscope or the like.
  • it can be detected by using a secondary ion mass spectrometry (secondary ion mass spectroscopy, SIMS) analyzer.
  • SIMS secondary ion mass spectroscopy
  • the first insulating layer 106 is a first passivation layer (passivation layer, PVX), which is an oxygen-rich film layer, compared to the second insulating layer (second passivation layer PVX2) or the first insulating layer
  • the first insulating layer 106 close to the metal oxide semiconductor layer 103 is an oxygen-rich insulating layer.
  • the atomic percentage of oxygen contained in the first insulating layer 106 exceeds 50%, and an exemplary range is 50% to 75%.
  • the percentage of oxygen contained in the first insulating layer 106 may be 55%, 60%, 65% or 70%.
  • the atomic number percentage of oxygen contained in the metal oxide semiconductor layer 103 is greater than 45%.
  • the oxygen-containing atomic percentage greater than 45% can make the oxygen vacancies in the metal oxide semiconductor layer 103 not too many, and it is not easy to cause the negative bias of the characteristics of the metal oxide thin film transistor when the TFT device is working, which can effectively reduce the metal oxide semiconductor layer 103.
  • the negative bias of the characteristics of thin film transistors results in poor product sand point.
  • designing the oxygen content percentage of the first insulating layer 106 to be relatively large has at least the following advantages:
  • the first insulating layer 106 in contact with the metal oxide semiconductor layer 103 is an oxygen-rich insulating layer. Relatively speaking, the H content of this film layer is less, which has the following advantages:
  • the metal oxide semiconductor layer 103 is fabricated and before the first insulating layer is fabricated, the metal oxide semiconductor layer 103 is annealed, and then oxygen is supplemented to the metal oxide semiconductor layer 103 as an active layer.
  • the oxygen-rich first insulating layer 106 is beneficial to improve the efficiency and quality of injecting oxygen.
  • the role of the first insulating layer 106 may include: reducing surface defects of the metal oxide semiconductor layer 103 .
  • As a protective layer, H in the upper silicon nitride film layer is prevented from being injected into the metal oxide semiconductor layer 103 .
  • the metal oxide semiconductor layer 103 is annealed to remove H and unstable chemical bonds in the metal oxide semiconductor layer 103 .
  • an oxygen supplement layer is formed on the first insulating layer 106 to supplement oxygen to the metal oxide semiconductor layer 103 and reduce the conductorization of the metal oxide semiconductor layer 103. risk, adjust the semiconductor characteristics of the metal oxide semiconductor layer 103 .
  • the material of the oxygen supplement layer can be indium gallium zinc oxide (indium gallium zinc oxide, IGZO), and the oxygen supplement process is to carry out high-temperature annealing to the IGZO as the oxygen supplement layer, so that O passes through the first insulating layer 106 and then enters the metal oxide semiconductor layer 103 .
  • IGZO indium gallium zinc oxide
  • the embodiment of the present application provides a metal oxide thin film transistor. Since the oxygen content of the first insulating layer of the metal oxide thin film transistor is relatively high, the oxygen element in the first insulating layer can The metal oxide semiconductor layer can be diffused to achieve the function of supplementing oxygen to the metal oxide semiconductor layer, thereby improving the stability of the metal oxide thin film transistor. Moreover, the interface between the first insulating layer and the metal oxide semiconductor layer is matched, and surface defects of the metal oxide semiconductor layer can be reduced.
  • the atomic number percentage of oxygen contained in the metal oxide semiconductor layer is greater than 45%, so that the oxygen vacancies in the metal oxide semiconductor layer will not be too many, and it is not easy to cause a negative bias in the characteristics of the metal oxide thin film transistor when the device is working. It can effectively reduce the product sand point defect caused by the negative bias of the characteristics of the metal oxide thin film transistor.
  • Fig. 3 is a schematic diagram of the percentage curves of the content of each element in the first insulating layer, the metal oxide semiconductor layer and the gate insulating layer provided by the embodiment of the present application.
  • the atomic percentage of oxygen contained in the metal oxide semiconductor layer 103 may be greater than 50%.
  • the atomic percentage of oxygen contained greater than 50% can avoid the negative bias of the characteristics of the metal oxide thin film transistor during the operation of the device, thereby avoiding the product sand point defect caused by the negative bias of the characteristic of the metal oxide thin film transistor.
  • the gate insulating layer 102 may include a first sub-gate insulating layer and a second sub-gate insulating layer stacked in sequence along a direction away from the base substrate 20 (towards the metal oxide semiconductor layer).
  • the material of the first sub-gate insulating layer may be silicon nitride (SiNx), and the material of the second sub-gate insulating layer may be silicon oxide.
  • the thickness of the first insulating layer 106 is less than This thickness has the following advantages:
  • a second insulating layer such as SiN
  • the first insulating layer silicon oxide film layer
  • the via hole on the insulating layer needs an etchant, because the etching rate of SiN is greater than that of SiO, therefore, making SiO thinner can effectively increase the production capacity and reduce the production cost of the product.
  • the thickness of the first insulating layer 106 is less than Compared to existing technologies greater than The thickness of the thickness is beneficial to the oxygen that is directly injected into the metal oxide semiconductor layer 103 on the first insulating layer 106. When implanted into the lower surface layer and into the metal oxide semiconductor layer 103, the oxygen implantation efficiency and quality are relatively poor.
  • the thickness of the first insulating layer 106 is less than It is possible to avoid cracks at the position of the source electrode 104 or the drain electrode. If the thickness of the first insulating layer 106 is high-temperature annealed, due to the thickness of the first insulating layer 106 is thicker and the internal stress is greater, cracks will appear in the area overlapping the source electrode 104 or the drain electrode 105 In particular, cracks are likely to occur on the sidewalls of the thicker source electrode 104 or drain electrode 105 . Since the crack may expose the source electrode 104 or the drain electrode 105 , the appearance of the crack may directly cause the source electrode 104 or the drain electrode 105 to be oxidized or even corroded.
  • the H element in the film layer above the source electrode 104 or the drain electrode may enter the surface of the metal oxide semiconductor layer 103 in contact with the source electrode 104 or the drain electrode 105 through the source electrode 104 or the drain electrode 105, resulting in metal oxidation.
  • the characteristics of thin film transistors deteriorate, and in severe cases, sand spots will appear on the display panel.
  • the first insulating layer 106 is a relatively thin film layer rich in oxygen, which not only ensures better oxygen injection effect and quality, but also effectively improves productivity and avoids defective cracks in the first insulating layer 106 .
  • the bond energy peak range of the silicon-oxygen bond can be 1060 cm- 1 to 1080cm-1.
  • the bond energy peak of the silicon-oxygen bond may range from 1063 cm ⁇ 1 to 1067 cm ⁇ 1 .
  • cm-1 is used to represent the number of waves contained in 1 cm.
  • the bond energy peak value of the silicon-oxygen bond is used to represent the bond energy value at which the absorbance (absorbance) is maximum.
  • the bond energy of the silicon-oxygen bond (Si—O) in the above embodiment is relatively large, which fully demonstrates that the first insulating layer is a film layer rich in Si—O.
  • the first insulating layer 106 may be formed on the base substrate 20 by using chemical vapor deposition equipment.
  • the gas used to prepare the first insulating layer 106 may include N 2 O (nitrogen oxide) and SiH 4 (silicon tetrahydrogen). The N 2 O and SiH 4 are reacted and deposited to form silicon oxide, that is, the first insulating layer 106 may be a single-layer silicon oxide film.
  • each film layer of the metal oxide thin film transistor 10 can be prepared in a reaction chamber.
  • N 2 O and SiH 4 may be introduced into the reaction chamber.
  • the bond energy peak value of the silicon-oxygen bond in the prepared first insulating layer 106 in the infrared absorption spectrometer test can reach 1060 cm In the range of -1 to 1080cm-1, an oxygen-enriched film layer can be realized.
  • the bond energy peak value of Si—O reaches above 1060 cm ⁇ 1 , which means that the oxygen content in the film layer (the first insulating layer 106 ) is higher than the conventional practice.
  • the oxygen-rich first insulating layer 106 when implementing the oxygen-rich first insulating layer 106 , it is necessary to control the passing amount of SiH 4 or H. That is to say, when oxygen is abundant, H is relatively less, or the ratio of the content ratio of O and H is larger, and the proportion of H content is smaller.
  • the atomic percentage of hydrogen in the silicon oxide film layer in the first insulating layer 106 is less than 3%. Moreover, the number percentage of silicon-hydrogen bonds (Si—H) in the silicon oxide film layer in the first insulating layer 106 is less than 7%. Wherein, the percentage of the number of silicon-hydrogen bonds in the silicon oxide film layer may refer to the ratio of the number of silicon-hydrogen bonds to the sum of the number of silicon-hydrogen bonds and the number of silicon-oxygen bonds.
  • the hydrogen content in the silicon oxide film layer in the first insulating layer 106 is less, it can avoid the hydrogen element in the first insulating layer 106 from moving toward the first insulating layer 106 close to the metal oxide semiconductor layer. Diffusion in the direction of 103 ensures that the characteristics of the metal oxide thin film transistor will not be negatively biased.
  • FIG. 5 is a schematic diagram of a test of a first insulating layer formed on a large-size substrate provided by an embodiment of the present application.
  • Fig. 5 is used for representing and can be used for testing the first insulating layer that forms on the large-scale base substrate in the central (center) region and the edge (edge) region of this large-scale base substrate.
  • the first insulating layer formed on the large-sized base substrate has bond energy peak values of silicon-oxygen bonds in the central region and the edge region of the large-sized base substrate.
  • the hydrogen atomic percentage of the first insulating layer 106 in the center (center) region of the large-sized substrate is 2.9%, and the first insulating layer 106 is in the large-sized substrate.
  • the atomic percentage of hydrogen in the center region was 4.1%.
  • the bond energy peak value of the silicon-oxygen bond in the central region of the first insulating layer formed on the large-size substrate is 1060 cm-1.
  • the peak bond energy of the silicon-oxygen bond in the edge region of the first insulating layer formed on the large-size base substrate is 1053 cm-1.
  • the bond energy peak value of the silicon-oxygen bond and the hydrogen atomic percentage that the bond energy peak value of the silicon-oxygen bond in the central region is greater than the bond energy peak value of the silicon-oxygen bond in the edge region, and the hydrogen atomic percentage in the central region
  • the atomic percentage of hydrogen is less than that of the peripheral region (the atomic percentage of hydrogen in the central region is less than 3%, and the atomic percentage of hydrogen in the peripheral region is greater than 3%). It can be seen from this that, when the first insulating layer is formed on a large-sized substrate, the film quality of the first insulating layer located in the central region is better than that of the first insulating layer located in the edge region.
  • the above-mentioned first insulating layer 106 in different regions of the present application is formed through one process, and the content of Si in different regions is consistent, and the difference lies in the relative content of H and O. If the content of H is more, the problem of sand spots will be serious. If the content of O is more, that is, the content of H is less, the problem of sand spots will be effectively improved.
  • the first insulating layer 106 can be prepared in a reaction chamber.
  • the first insulating layer 106 is a film layer mainly composed of silicon oxide formed by controlling the oxygen content introduced into the reaction chamber during the deposition process.
  • the atomic number percentages of oxygen in multiple test positions are consistent in theory, but there is a certain difference in the actual test, but the difference is not more than ⁇ 3%, the maximum The difference between the numerical value and the minimum numerical value shall not exceed 5%.
  • the percentage of atomic number of oxygen contained in each test position in the thickness direction of the first insulating layer 106 is basically maintained within the range of numerical fluctuations (ie, the maximum difference is not more than 5%). As shown in Figure 3, it is a wavy line microscopically, and close to a straight line macroscopically.
  • the first insulating layer 106 may include a first surface and a second surface opposite to each other.
  • the first surface is a surface close to the metal oxide semiconductor layer 103
  • the second surface is a surface far away from the metal oxide semiconductor layer 103 .
  • the distribution of oxygen atoms is: the closer to the second surface, the greater the difference in the percentage of oxygen-containing atoms in two adjacent test positions, and the closer to the second surface. The smaller the difference in the atomic number percentages of oxygen contained in every two adjacent test positions at the position of the first surface.
  • the test position may be the position of the first insulating layer 106 in the thickness direction.
  • the two adjacent test positions may be adjacent positions of the first insulating layer 106 in the thickness direction.
  • the oxygen-containing atomic number percentage curve of each test position in the thickness direction of the first insulating layer 106 can be a continuous curve, so the test positions of the first insulating layer 106 in the thickness direction can also be continuous. the test location.
  • the outer sidewall of the first insulating layer 106 may be tested directly after the formation of the first insulating layer 106 .
  • the sidewall of the cut first insulating layer 106 may be tested. This embodiment of the present application does not limit it.
  • FIG. 8 is a schematic structural diagram of another display panel provided by an embodiment of the present application. It can be seen with reference to FIG. 8 that the metal oxide thin film transistor 10 may further include: a second insulating film 107 .
  • the second insulating film 107 may be located on a side of the first insulating layer 106 away from the metal oxide semiconductor layer 103 .
  • the second insulating film 107 may include silicon element, and the second insulating film 107 may further include at least one of oxygen element and nitrogen (N) element.
  • the second insulating film 107 can function as a barrier.
  • the second insulating film 107 can block impurities from the outside, such as hydrogen or oxygen elements entering key film layers through the second insulating film 107 .
  • the key film layer may be a film layer located on the side of the second insulating film 107 close to the gate 101, for example, the key film layer includes the first insulating layer 106, the source electrode 104, the drain electrode 105 and the metal oxide semiconductor layer 103 .
  • the first insulating layer 106 is a single layer of silicon oxide film.
  • the single-layer silicon oxide film layer can be a film layer with the same film quality (referred to as film quality) prepared under the same process conditions.
  • the second insulating film 107 may only include a silicon oxide film layer, or may only include a silicon nitride film layer, or may include a silicon oxide film layer and a silicon oxide film layer stacked on one side of the first insulating layer 106 in sequence.
  • the silicon nitride film layer may further alternatively include a silicon oxide film layer, a silicon oxynitride film layer and a silicon nitride film layer stacked on one side of the first insulating layer 106 in sequence.
  • the first insulating layer 106 and the second insulating film 107 there may be an organic resin (resin) between the first insulating layer 106 and the second insulating film 107 .
  • the second insulating film 107 only includes a silicon nitride film layer, the first insulating layer 106 and the second insulating film 107 can be distinguished based on the material of the film layer. Moreover, the second insulating film 107 can discharge the H element in the silicon nitride film layer during the high temperature annealing process.
  • the first insulating layer 106 is a single-layer silicon oxide film layer. Silicon film layer.
  • the metal oxide thin film transistor has higher requirements on the characteristics
  • the first insulating film 106 (the first insulating layer 106 is a single-layer silicon oxide film layer, and the silicon oxide film layer is called the first The silicon oxide film layer) may be provided with a second silicon oxide film layer having a different film quality from the first silicon oxide film layer.
  • the side of the second silicon oxide film layer away from the first insulating layer 106 has a silicon nitride film layer.
  • the second silicon oxide film layer and the silicon nitride film layer may both belong to the second insulating film 107 .
  • the film quality difference between the first silicon oxide film layer and the second silicon oxide film layer can be used to represent at least one of the following differences: the atomic percentage of oxygen in the first silicon oxide film layer, and The difference of the oxygen-containing atomic percentage in the second silicon oxide film layer is larger; The difference of the deposition rate when forming the first silicon oxide film layer and the deposition rate when forming the second silicon oxide film layer is larger; The density of the second silicon oxide film layer is quite different from that of the second silicon oxide film layer.
  • the atomic percentage of oxygen in the silicon oxide film layer in the second insulating film 107 does not exceed the atomic percentage of oxygen in the silicon oxide film layer in the first insulating layer 106. Moreover, the difference between the two is greater than 5% to 15%, for example, 10%.
  • the thickness of the silicon oxide film layer in the second insulating film 107 may be greater than the thickness of the first insulating layer 106, for example, the thickness of the silicon oxide film layer in the second insulating film 107 is The thickness of the silicon nitride film layer in the second insulating film 107 can be
  • the metal oxide semiconductor layer 103 is supplemented with oxygen through the oxygen supply layer, the second silicon oxide film layer
  • the function is to improve the interface between the silicon nitride film layer and the first silicon oxide film layer, and prevent the hydrogen element in the silicon nitride film layer from entering the second metal oxide semiconductor layer 103 that does not overlap with the source electrode 104 or the drain electrode 105.
  • the second silicon oxide film layer in the second insulating film 107 is a transition film layer, which is mainly used to improve the interface and prevent hydrogen or water vapor from entering the key film layer of the metal oxide thin film transistor.
  • the second insulating film 107 can expel the H element in the silicon nitride film layer included in it during the high-temperature annealing process, and supplement the O element in the first insulating layer 106 into the metal oxide semiconductor layer 103 .
  • the second insulating film 107 may include a silicon oxide film layer, a silicon nitride oxide film layer and a silicon nitride film layer stacked on one side of the first insulating layer 106 .
  • the function of the silicon oxide film layer in the second insulating film 107 may be the same as that of the second silicon oxide film layer in the previous implementation manner.
  • the second insulating film 107 can expel the hydrogen elements in the silicon oxynitride and silicon nitride film layers included in it during the high-temperature annealing process, and replenish the oxygen elements in the first insulating layer 106 to the metal oxide semiconductor layer. 103 in.
  • the thickness of the silicon oxide film layer in the second insulating film 107 may be greater than the thickness of the first insulating layer 106, for example, the thickness of the silicon oxide film layer in the second insulating film 107 is The thickness of the silicon oxynitride film layer in the second insulating film 107 can be The thickness of the silicon nitride film layer in the second insulating film 107 can be
  • the first insulating layer 106 and the second insulating film 107 are also called passivation layer (passivation layer, PVX), that is, the first insulating layer 106 is called the first passivation layer, and the second insulating film 107 is called the second passivation layer.
  • passivation layer PVX
  • Second passivation layer Second passivation layer.
  • the thickness range of the first passivation layer 106 in the related art is to Within a certain range, the first passivation layer 106 can prevent external hydrogen elements from entering key film layers.
  • the thickness of the first passivation layer 106 in the embodiment of the present application is less than Its function is to supplement oxygen for the metal oxide semiconductor layer 103 and reduce surface defects of the metal oxide semiconductor layer 103 .
  • the main film layer that prevents outside hydrogen elements from entering the key film layer is the second passivation layer 107 .
  • the structure of the second passivation layer 107 can be as described in the above embodiments. That is to say, the first passivation layer 106 (single-layer silicon oxide film layer with a thickness less than 2000 angstroms) in the embodiment of the present application is not equivalent to the first passivation layer (thickness ranging from 3000 angstroms to 5000 angstroms) in the prior art. silicon oxide film in the angstrom range).
  • the first insulating layer 106 is a single-layer silicon oxide film
  • the first insulating layer 106 is a film with the same film quality (referred to as film quality) prepared under the same process conditions.
  • film quality film quality
  • the densities of the first insulating layer 106 at multiple test positions along the thickness direction of the first insulating layer 106 are the same.
  • the density of the first insulating layer 106 at multiple test positions along the thickness direction of the first insulating layer 106 is the same may refer to: the first insulating layer 106 at multiple test positions along the thickness direction of the first insulating layer 106
  • the densities of the test locations are exactly the same.
  • the densities of the first insulating layer 106 at multiple test positions along the thickness direction of the first insulating layer 106 are within a certain error range.
  • the density deviation of the first insulating layer 106 at multiple test positions along the thickness direction of the first insulating layer 106 does not exceed 5%.
  • the density of every two adjacent test positions closer to the first surface, and the density of every two adjacent test positions closer to the second surface are the same as There may be a certain difference in density between the first surface and the second surface of the first insulating layer 106 .
  • the density of every two adjacent test positions closer to the first surface, and the density of every two adjacent test positions closer to the second surface are the same as those of the first insulating layer 106.
  • the error range of the density of the area between the first surface and the second surface is 0% to 5%.
  • the insulating layer 106 is a single film layer.
  • the density of the first insulating layer 106 is smaller than that of the second insulating film 107 .
  • the density of the first insulating layer 106 is small, so the first insulating layer 106 is relatively looser than the second insulating film 107 . It is thus easier to supplement the metal oxide semiconductor layer 103 with oxygen after forming the first insulating layer 106 and before forming the second insulating film 107 .
  • the oxygen in the metal oxide semiconductor layer 103 is easy to overflow and be trapped in the first insulating layer 106 and is not easy to pass through the second insulating layer 106.
  • the film 107 is released to the outside. This is beneficial for the first insulating layer 106 to supply oxygen to the metal oxide semiconductor layer 103 again, avoiding poor performance of the metal oxide thin film transistor caused by excessive hydrogen concentration in the metal oxide semiconductor layer 103 and its surroundings.
  • the density of the film layer can be negatively correlated with the deposition rate of the film layer. That is, the greater the deposition rate of the film, the smaller the density of the film; the lower the deposition rate of the film, the greater the density of the film.
  • the deposition rate of the first insulating layer 106 may be greater than that of the second insulating film 107 so that the density of the first insulating layer 106 is smaller than that of the second insulating film 107 .
  • the deposition rate of the first insulating layer 106 is about.
  • the deposition rate of the first insulating layer 106 is no more than
  • the deposition rate of the silicon oxide film layer of the second insulating film 107 can be greater than the deposition rate of the first insulating layer 106, for example can be to
  • the deposition of the silicon oxide film layer of the second insulating film 107 can be made The rate is greater than the deposition rate of the first insulating layer 106 .
  • the density of the first insulating layer 106 is smaller than that of the second insulating film 107 means that the density of the first insulating layer 106 is smaller than that of the silicon nitride film layer of the second insulating film 107 .
  • an annealing treatment may be performed.
  • the annealing treatment also causes the metal oxide semiconductor layer 103 to lose some oxygen atoms. Therefore, with reference to FIG. 10 , in order to ensure sufficient oxygen concentration in the metal oxide semiconductor layer 103 after the metal oxide thin film transistor is manufactured and avoid its conductorization, it is necessary to effectively carry out the metal oxide semiconductor layer 103 after the first insulating layer 106 is formed. Oxygenation.
  • an oxygen supplement layer is formed on the side of the first insulating layer 106 away from the gate 101 (the oxygen supplement layer needs to be removed after the oxygen supplement is completed, the oxygen supplement
  • the material of the layer may be indium gallium zinc oxide).
  • the process of supplementing oxygen is that the oxygen element in the supplementing oxygen layer diffuses to the metal oxide semiconductor layer 103 through the first insulating layer 106 .
  • the oxygen element needs to diffuse to the metal oxide semiconductor layer 10 through the first insulating layer 106 , so the first insulating layer 106 needs to be designed to be relatively loose (ie less dense).
  • the deposition rate of the first insulating layer 106 is designed to be larger (for example, greater than ), so as to prepare a relatively loose first insulating layer 106, so that the oxygen element in the oxygen-supplementing layer can diffuse to the metal oxide semiconductor layer 103 through the loose first insulating layer 106, so as to reduce the The number of oxygen vacancies increases, improving the stability of the metal oxide thin film transistor 10 .
  • the density (that is, the degree of porosity) of the first insulating layer 106 can be characterized by an etching rate when the first insulating layer 106 is etched with a hydrogen fluoride (HF) solution.
  • HF hydrogen fluoride
  • the etching rate when using HF solution to etch the first insulating layer 106 exceeds (angstrom/s) and not exceeding
  • the range of the etching rate when using HF solution to etch the first insulating layer 106 can be to In the range.
  • the etching rate during HF solution etching is greater than It can be considered that the film layer is relatively loose, but in the embodiment of the present application, the etching rate when using HF solution to etch the first insulating layer 106 reaches It can be explained that the density of the first insulating layer 106 is small.
  • the oxygen replenishing layer formed on the side of the first insulating layer 106 away from the gate 101 to replenish oxygen to the metal oxide semiconductor layer 103 .
  • the ratio of the thickness of the first insulating layer 106 to the thickness of the second insulating film 107 ranges from 0.2 to 0.5.
  • the thickness of the first insulating layer 106 (single-layer silicon oxide layer) is 1000 angstroms.
  • the second insulating film 107 includes a silicon oxide film layer and a silicon nitride film layer stacked on the first insulating layer 106 in this order.
  • the thickness of the silicon oxide film layer in the second insulating film 107 is 3000 Angstroms
  • the thickness of the silicon nitride film layer is That is, the thickness of the second insulating film 107 is 4000 angstroms.
  • the thickness of the first insulating layer 106 is relatively thin.
  • the thickness of the first insulating layer 106 is relatively thin (for example, the thickness is less than ), it may cause the metal oxide semiconductor layer 103 to be easily conductive, and the performance of the metal oxide thin film transistor 10 is poor. If the thickness of the first insulating layer 106 is thicker (for example, greater than ), then referring to FIG. 11 , since the film layer pressure of the first insulating layer 106 is relatively high, it is easy to cause cracks in the first insulating layer 106 .
  • the crack may expose the source electrode 104 or the drain electrode 105, the appearance of the crack may cause the etching solution to flow to the metal oxide semiconductor layer 103 through the crack, and the metal oxide semiconductor layer 103 is etched, It leads to the deterioration of the characteristics of metal oxide thin film transistors, and in severe cases, it will cause sand spots on the display panel.
  • the white dotted line on the left side is the boundary line between the source electrode 104 or the drain electrode 105 and the metal oxide semiconductor layer 103
  • the white dotted line on the right side is the boundary line between the first insulating layer 106 and the metal oxide semiconductor layer 103.
  • the boundary line of the oxide semiconductor layer 103 is the boundary line between the first insulating layer 106 and the metal oxide semiconductor layer 103.
  • the thickness range of the first insulating layer 106 in the metal oxide thin film transistor 10 provided in the embodiment of the present application is to On the one hand, it can prevent the metal oxide semiconductor layer 103 from being easily conductorized and ensure the performance of the metal oxide thin film transistor 10 ;
  • the thickness of the first insulating layer 106 is greater than and not exceeding
  • first via hole in the first insulating layer 106 and the second insulating film 107, and the first via hole may be used to expose the drain electrode 105, so that the second insulating film 107 is further away from the gate 101.
  • the pixel unit formed on the side is electrically connected to the drain 105 through the first via hole.
  • the gate insulating layer 102, the first insulating layer 106 and the second insulating film 107 may have a second via hole, and the second via hole may be used to expose the gate 101, so that the second insulating film 107 A common electrode formed on a side away from the gate 101 is electrically connected to the gate 101 through the second via hole.
  • the meaning used to indicate the silicon oxide film layer in the second insulating film, or the silicon nitride oxide film layer in the second insulating film is: the second insulating film 107 includes silicon oxide film layer In the case of a film layer and a silicon nitride film layer, the layer can be a silicon nitride film layer of the second insulating film; the second insulating film 107 includes a silicon oxide film layer, a silicon nitride oxide film layer, and a silicon nitride film layer In the case of a layer, the layer may be a silicon oxynitride film layer and a silicon nitride film layer of the second insulating film.
  • the lowermost white dotted line is used to indicate the boundary line between the gate 101 and the gate insulating layer 102
  • the middle white dotted line is used to indicate the gate insulating layer 102 and the first insulating layer 106.
  • the uppermost white dotted line is used to indicate the boundary line between the silicon oxide film layer of the second insulating film 107 and the silicon nitride film layer or silicon oxynitride film layer of the second insulating film 107 .
  • the slope angle of the first via hole in the silicon oxide film layer in the first insulating layer 106 and the silicon oxide film layer in the second insulating film 107 may range from 40 degrees to 60 degrees.
  • the slope angle of the first via hole in the silicon nitride film layer in the second insulating film 107 may range from 60 degrees to 70 degrees.
  • the slope angle of the first via hole in the silicon oxide film layer in the first insulating layer 106 and the silicon oxide film layer in the second insulating film 107 is the same as that of the first via hole in the silicon nitride film layer in the second insulating film.
  • the slope angles of the vias are approximately equal.
  • the slope angle of the first via hole in the silicon oxide film layer in the first insulating layer 106 and the silicon oxide film layer in the second insulating film 107 may refer to: the silicon oxide film layer in the first insulating layer 106 and the second via hole The included angle between the sidewall and the bottom surface of the first via hole in the silicon oxide film layer in the second insulating film 107 .
  • the slope angle of the first via hole in the silicon nitride film layer in the second insulating film 107 may refer to the angle between the sidewall and the bottom surface of the first via hole in the silicon nitride film layer in the second insulating film 107 .
  • the slope angle of the second via hole of the gate insulating layer 102 may be greater than 80 degrees.
  • the slope angle of the second via hole in the silicon oxide film layer in the first insulating layer 106 and the silicon oxide film layer in the second insulating film 107 may range from 40 degrees to 60 degrees.
  • the slope angle of the second via hole in the silicon nitride film layer in the second insulating film 107 may be greater than 80 degrees.
  • the slope angle of the second via hole in the gate insulating layer 102 may refer to the angle between the sidewall and the bottom surface of the second via hole in the gate insulating layer 102 .
  • the slope angle of the second via hole in the silicon oxide film layer in the first insulating layer 106 and the silicon oxide film layer in the second insulating film 107 may refer to: the silicon oxide film layer in the first insulating layer 106 and the second insulating film layer The included angle between the sidewall and the bottom surface of the second via hole in the silicon oxide film layer in the film 107 .
  • the slope angle of the second via hole in the silicon nitride film layer in the second insulating film 107 may refer to the angle between the sidewall and the bottom surface of the second via hole in the silicon nitride film layer in the second insulating film 107 .
  • the thickness of the source electrode 104 and the drain electrode 105 may be greater than and less than Moreover, the slope angles of the source electrode 104 and the drain electrode 105 are both smaller than 60° (degrees). Designing the slope angle of the source electrode 104 and the slope angle of the drain electrode 105 to be small can prevent the first insulating layer 106 formed on the side of the source electrode 104 and the drain electrode 105 away from the base substrate 20 from forming on the source electrode 104. Cracks appear on the slope and the slope of the drain 105 to ensure the yield of the metal oxide thin film transistor 10 .
  • the slope angle of the source 104 may refer to the angle between the sidewall of the source 104 and the side of the source 104 close to the gate 101 .
  • the slope angle of the drain 105 may refer to the angle between the sidewall of the drain 105 and the side of the drain 105 close to the gate 101 .
  • the metal oxide semiconductor layer 103 may include a first surface and a second surface opposite to each other, and the first surface is closer to the base substrate 20 than the second surface.
  • the portion of the metal oxide semiconductor layer 103 close to the first surface includes amorphous or nanocrystalline metal oxide.
  • a portion of the metal oxide semiconductor layer 103 close to the second surface includes a C-axis crystallized metal oxide.
  • the amorphous or nanocrystalline metal oxide contains at least one of indium, gallium, zinc, tin and praseodymium.
  • the C-axis crystallized metal oxide contains at least one of indium, gallium, zinc, tin and praseodymium.
  • the amorphous or nanocrystalline metal oxide comprises indium gallium zinc oxide.
  • the indium gallium zinc atomic number ratio of the indium gallium zinc oxide is 4:2:3, or the indium gallium zinc atomic number ratio of the indium gallium zinc oxide is 1:1:1, or the indium gallium zinc oxide
  • the atomic number ratio of gallium to zinc is 1:3:6.
  • the atomic number ratio of amorphous or nanocrystalline InGaZn oxide InGaZn refers to the number of indium atoms: the number of gallium atoms: the number of zinc atoms.
  • the atomic number ratio of indium gallium zinc oxide is 4:2:3, so the amorphous or nanocrystalline indium gallium zinc oxide can be amorphous or nanocrystalline In4Ga2Zn3Ox.
  • the metal oxide of the C-axis crystal includes indium gallium zinc oxide.
  • the indium gallium zinc atomic number ratio of the indium gallium zinc oxide is 4:2:3, or the indium gallium zinc atomic number ratio of the indium gallium zinc oxide is 1:1:1, or the indium gallium zinc oxide
  • the atomic number ratio of gallium to zinc is 1:3:6.
  • the C-axis crystalline indium gallium zinc oxide indium gallium zinc atomic number ratio refers to the number of indium atoms: the number of gallium atoms: the number of zinc atoms.
  • the c-axis crystalline indium gallium zinc oxide may be c-axis crystalline In4Ga2Zn3Ox.
  • the process of forming the metal oxide semiconductor layer 103 in the metal oxide thin film transistor 10 shown in FIG. An amorphous or nanocrystalline metal oxide is formed on the side of the gate 101 , and then a C-axis crystallized metal oxide is formed on the side of the amorphous or nanocrystalline metal oxide away from the gate 101 by using a magnetron sputtering device.
  • the thickness of the amorphous or nanocrystalline metal oxide ranges from to The thickness range of C-axis crystallized metal oxides is to
  • the carrier mobility of the portion of the metal oxide semiconductor layer 103 close to the first surface ranges from 10 cm 2 /V ⁇ S (square centimeter/volt ⁇ second) to 20cm 2 /V ⁇ S.
  • the carrier mobility of an amorphous or nanocrystalline metal oxide may be 15 cm 2 /V ⁇ S. Since the carrier mobility of the amorphous or nanocrystalline metal oxide is relatively large, the conductivity of the metal oxide thin film transistor is relatively good.
  • the embodiment of the present application provides a metal oxide thin film transistor. Since the oxygen content of the first insulating layer of the metal oxide thin film transistor is relatively high, the oxygen element in the first insulating layer can The metal oxide semiconductor layer can be diffused to achieve the function of supplementing oxygen to the metal oxide semiconductor layer, thereby improving the stability of the metal oxide thin film transistor. In addition, the interface between the first insulating layer and the metal oxide semiconductor layer is matched, and surface defects of the metal oxide semiconductor layer can be reduced.
  • the atomic number percentage of oxygen contained in the metal oxide semiconductor layer is greater than 45%, so that the oxygen vacancies in the metal oxide semiconductor layer will not be too many, and it is not easy to cause a negative bias in the characteristics of the metal oxide thin film transistor when the device is working. It can effectively reduce the product sand point defect caused by the negative bias of the characteristics of the metal oxide thin film transistor.
  • the embodiment of the present application provides a method for manufacturing a metal oxide thin film transistor, which can be used to prepare the metal oxide thin film transistor 10 shown in FIG. 1 .
  • the method may include: forming a gate 101 , a gate insulating layer 102 , a metal oxide semiconductor layer 103 , a source 104 , a drain 105 , and a first insulating layer 106 on the substrate 20 .
  • the source electrode 104 and the drain electrode 105 can be prepared by the same patterning process, that is, the source electrode 104 and the drain electrode 105 can be located in the same layer.
  • a gate insulating layer 102 , a metal oxide semiconductor layer 103 , a source 104 , and a first insulating layer 106 are sequentially stacked along a direction away from the gate 101 . Moreover, a side of the first insulating layer 106 close to the gate 101 is at least partially in contact with the metal oxide semiconductor layer 103 .
  • the orthographic projection of the metal oxide semiconductor layer 103 on the base substrate 20 includes a first region that at least partially overlaps the source electrode 104 and the drain electrode 105, and a first region that does not overlap the source electrode 104 and the drain electrode 105. Second area.
  • the region of the metal oxide semiconductor layer 101 below the source electrode 104 and the drain electrode 105 serves as the first region
  • the region located between the source electrode 104 and the drain electrode 105 serves as the second region.
  • a side of the first insulating layer 106 close to the gate 101 is in contact with a portion of the metal oxide semiconductor layer 103 located in the second region.
  • the first insulating layer 106 is an inorganic insulating layer containing at least silicon and oxygen. In the actual test of the first insulating layer 106, there is a small amount of nitrogen element in the first insulating layer 106, but the atomic number of the nitrogen element is very small, so the first insulating layer 106 can be simply referred to as a silicon oxide film. layer.
  • the atomic percentage of oxygen contained in the first insulating layer 106 is greater than 50%.
  • the atomic percentage of oxygen contained in the first insulating layer 106 ranges from 50% to 75%.
  • the percentage of oxygen contained in the first insulating layer 106 may be 55%, 60%, 65% or 70%. That is, the oxygen content in the first insulating layer 106 is relatively high, and the first insulating layer 106 is an oxygen-enriched film layer.
  • the atomic number percentage of oxygen contained in the metal oxide semiconductor layer 103 is greater than 45%.
  • the oxygen atomic percentage of the metal oxide semiconductor layer 103 greater than 45% is the actual test data, and the oxygen atomic percentage greater than 45 can make the oxygen vacancies in the metal oxide semiconductor layer 103 not too many, It is not easy to cause the negative bias of the characteristics of the metal oxide thin film transistor when the device is working, which can effectively reduce the sand point defect of the product caused by the negative bias of the characteristic of the metal oxide thin film transistor.
  • the oxygen content percentage of the first insulating layer 106 is designed to be larger, so that the oxygen element in the first insulating layer 106 can diffuse to the metal oxide semiconductor layer 103, so as to supplement the oxygen to the metal oxide semiconductor layer 103.
  • an oxygen supplement layer is formed on the first insulating layer 106 to supplement oxygen to the metal oxide semiconductor layer 103), thereby improving the metal Stability of Oxide Thin Film Transistors.
  • the material of the oxygen supplement layer may be IGZO.
  • the first insulating layer 106 is located on one side of the metal oxide semiconductor layer 103, the first insulating layer 106 is close to the side of the metal oxide semiconductor layer 103, and can be connected with the side of the metal oxide semiconductor layer 103 close to the first insulating layer 106.
  • One-side matching ie, interface matching
  • the function of the first insulating layer 106 may include: supplementing oxygen to the metal oxide semiconductor layer 103 and reducing surface defects of the metal oxide semiconductor layer 103 .
  • the embodiment of the present application provides a method for manufacturing a metal oxide thin film transistor. Since the oxygen content of the first insulating layer of the metal oxide thin film transistor prepared by this method is relatively high, the first insulating layer of the metal oxide thin film transistor can be made Oxygen element in an insulating layer can diffuse to the metal oxide semiconductor layer, so as to supplement oxygen to the metal oxide semiconductor layer, thereby improving the stability of the metal oxide thin film transistor. Moreover, the interface between the first insulating layer and the metal oxide semiconductor layer is matched, and surface defects of the metal oxide semiconductor layer can be reduced.
  • the atomic number percentage of oxygen contained in the metal oxide semiconductor layer is greater than 45%, so that the oxygen vacancies in the metal oxide semiconductor layer will not be too many, and it is not easy to cause a negative bias in the characteristics of the metal oxide thin film transistor when the device is working. It can effectively reduce the product sand point defect caused by the negative bias of the characteristics of the metal oxide thin film transistor.
  • FIG. 14 is a flow chart of a method for manufacturing a metal oxide thin film transistor provided in an embodiment of the present application. This method can be used for the metal oxide thin film transistor provided in the above embodiments, for example, to prepare the metal oxide thin film transistor shown in FIG. 1 . Referring to Figure 14, the method may include:
  • Step 301 forming a gate on a base substrate.
  • a base substrate 20 may be obtained first, a gate thin film is formed on one side of the base substrate 20 , and then the gate thin film is patterned to obtain the gate 101 .
  • the base substrate 20 may be a glass substrate.
  • Step 302 forming a gate insulating layer on a side of the gate away from the substrate.
  • a gate insulating layer 102 may be formed on the side of the gate 101 away from the base substrate 20, so that the gate 101 and the subsequently formed source 104 and drain 105 insulation.
  • the gate insulating layer 102 may include a first sub-gate insulating layer 102 and a second sub-gate insulating layer 102 sequentially stacked along a direction away from the base substrate 20 .
  • the material of the first sub-gate insulating layer 102 may be silicon nitride, and the material of the second sub-gate insulating layer 102 may be silicon oxide.
  • Step 303 forming a metal oxide semiconductor thin film on the side of the gate insulating layer away from the base substrate.
  • a metal oxide semiconductor thin film may be formed on a side of the gate insulating layer 102 away from the base substrate 20 , and the metal oxide semiconductor thin film may cover the base substrate 20 in its entirety.
  • a magnetron sputtering device may be used to form the first thin film on the side of the gate insulating layer 102 away from the base substrate 20 .
  • the first thin film can be prepared by using materials with high mobility.
  • a magnetron sputtering device is used to form a second thin film on the side of the first thin film away from the base substrate 20 .
  • the first thin film and the second thin film may be collectively referred to as a metal oxide semiconductor thin film.
  • the first thin film may be an amorphous or nanocrystalline metal oxide
  • the second thin film may be a C-axis crystallized metal oxide.
  • the amorphous or nanocrystalline metal oxide contains at least one of indium, gallium, zinc, tin and praseodymium.
  • the C-axis crystallized metal oxide contains at least one of indium, gallium, zinc, tin and praseodymium.
  • the amorphous or nanocrystalline metal oxide comprises indium gallium zinc oxide.
  • the indium gallium zinc atomic number ratio of the indium gallium zinc oxide is 4:2:3, or the indium gallium zinc atomic number ratio of the indium gallium zinc oxide is 1:1:1, or the indium gallium zinc oxide
  • the atomic number ratio of gallium to zinc is 1:3:6.
  • the atomic number ratio of amorphous or nanocrystalline InGaZn oxide InGaZn refers to the number of indium atoms: the number of gallium atoms: the number of zinc atoms.
  • the atomic number ratio of indium gallium zinc oxide is 4:2:3, so the amorphous or nanocrystalline indium gallium zinc oxide can be amorphous or nanocrystalline In4Ga2Zn3Ox.
  • the metal oxide of the C-axis crystal includes indium gallium zinc oxide.
  • the indium gallium zinc atomic number ratio of the indium gallium zinc oxide is 4:2:3, or the indium gallium zinc atomic number ratio of the indium gallium zinc oxide is 1:1:1, or the indium gallium zinc oxide
  • the atomic number ratio of gallium to zinc is 1:3:6.
  • the C-axis crystalline indium gallium zinc oxide indium gallium zinc atomic number ratio refers to the number of indium atoms: the number of gallium atoms: the number of zinc atoms.
  • the c-axis crystalline indium gallium zinc oxide may be c-axis crystalline In4Ga2Zn3Ox.
  • the thickness range of the first film is to The thickness of the second film ranges from to
  • Step 304 patterning the metal oxide semiconductor thin film to obtain a metal oxide semiconductor layer.
  • the metal oxide semiconductor thin film may be patterned by a photolithography process to obtain the metal oxide semiconductor layer 103 .
  • the orthographic projection of the metal oxide semiconductor layer 103 on the base substrate 20 is at least partially overlapped with the orthographic projection of the gate 101 on the base substrate 20 .
  • the photolithography process may include processes such as photoresist (photoresist, PR) coating, exposure, development, etching, and photoresist stripping.
  • the photolithography process may also be referred to as a mask plate process.
  • the metal oxide semiconductor thin film in step 303 includes a first thin film and a second thin film. Therefore, the step of patterning the metal oxide semiconductor thin film may refer to patterning the first thin film and the second thin film.
  • performing patterning treatment on the first thin film can obtain the amorphous or nanocrystalline metal oxide near the first surface in the metal oxide semiconductor layer 103
  • performing patterning treatment on the second thin film can obtain the metal oxide semiconductor layer 103 C-axis crystallized metal oxides near the second surface.
  • the first surface and the second surface are opposite sides of the metal oxide semiconductor layer 103 , and the first surface is closer to the base substrate 20 than the second surface.
  • the carrier mobility of the amorphous or nanocrystalline metal oxide close to the first surface in the metal oxide semiconductor layer 103 is relatively high.
  • the carrier mobility of the amorphous or nanocrystalline metal oxide near the first surface in the metal oxide semiconductor layer 103 ranges from 10 cm 2 /V ⁇ S to 20 cm 2 /V ⁇ S.
  • the carrier mobility is 15 cm 2 /V ⁇ S.
  • Step 305 forming source and drain thin films on the side of the metal oxide semiconductor layer away from the base substrate.
  • a source-drain thin film may be formed on the side of the metal oxide semiconductor layer 103 away from the base substrate 20 .
  • the material of the source-drain film may be a metal material, and the source-drain film may cover the base substrate 20 in its entirety.
  • Step 306 patterning the source and drain thin films to obtain the source and drain.
  • the source and drain films may be patterned by a photolithography process to obtain the source 104 and the drain 105 .
  • an etchant may be used to perform wet etching on the source-drain film to obtain the source electrode 104 and the drain electrode 105 .
  • the source electrode 104 and the drain electrode 105 are prepared by the same patterning process.
  • the orthographic projection of the source electrode 104 on the base substrate 20 overlaps with the orthographic projection of the metal oxide semiconductor layer 103 on the base substrate 20 .
  • the orthographic projection of the drain electrode 105 on the base substrate 20 overlaps with the orthographic projection of the metal oxide semiconductor layer 103 on the base substrate 20 .
  • the thickness of the prepared source electrode 104 and drain electrode 105 can be greater than and less than
  • the sidewall of the source 104 close to the drain 105 and the sidewall of the drain 105 close to the source 104 may be a curved line or a broken line.
  • the included angles between different regions of the sidewall of the source 104 close to the drain 105 and the side of the source 104 close to or away from the first insulating layer 106 are different, and the sidewall of the drain 105 close to the source 104 The included angles between different regions of the drain electrode 105 and the side of the drain electrode 105 that is close to or away from the first insulating layer 106 are different.
  • the slope angles of the prepared source electrode 104 and the drain electrode 105 are both smaller than 60°. Designing the slope angle of the source electrode 104 and the slope angle of the drain electrode 105 to be small can prevent the first insulating layer 106 formed on the side of the source electrode 104 and the drain electrode 105 away from the gate electrode 101 from climbing on the source electrode 104. Cracks appear on the slope and on the slope of the drain 105 to ensure the yield of the metal oxide thin film transistor 10 .
  • Step 307 using chemical vapor deposition equipment to form a first insulating layer on the side of the source away from the substrate.
  • each film layer of the metal oxide thin film transistor can be prepared in a reaction chamber.
  • N 2 O and SiH 4 may be introduced into the reaction chamber.
  • the ratio of the N 2 O content to the SiH 4 content may be greater than 78.
  • the ratio of the N 2 O content to the SiH 4 content may be 80.
  • the bond energy peak value of the silicon-oxygen bond in the prepared first insulating layer 106 in the infrared absorption spectrometer test can reach 1060 cm -1 to 1080cm-1 range.
  • the bond energy peak value of Si-O reaches more than 1060 cm-1, indicating that the oxygen content in the film layer (first insulating layer 106) is relatively high, and impurities (such as hydrogen, etc.) in the first insulating layer 106 can be avoided.
  • high content leads to unstable characteristics of metal oxide thin film transistors.
  • the deposition rate of the first insulating layer 106 during preparation may be greater than Exemplarily, the deposition rate of the first insulating layer 106 during preparation does not exceed
  • the formed first insulating layer 106 can be relatively loose (less dense), which is convenient for the subsequent formation of the first insulating layer 106 away from the gate 101.
  • the oxygen supply layer on one side supplies oxygen to the metal oxide semiconductor layer 103 .
  • the deposition rate of the first insulating layer 106 is related to the deposition power of the chemical vapor deposition equipment, the deposition pressure, and the temperature in the reaction chamber when the first insulating layer 106 is prepared.
  • first insulating layers 106 can be formed in the reaction chamber at different temperatures first, using 1% HF solution Each formed first insulating layer 106 is wet-etched, and the density of the first insulating layer 106 is characterized by wet etch rate (WER). Wherein, the first insulating layer 106 with a higher wet etching rate is looser, and the first insulating layer 106 with a lower wet etching rate is denser.
  • WER wet etch rate
  • the wet etching rate of the first insulating layer 106 formed when the temperature of the reaction chamber is 230° C. by 1% HF solution is faster. That is, the first insulating layer 106 formed when the temperature of the reaction chamber is 230° C. is relatively loose.
  • the temperature of the reaction chamber ranges from 100°C to 300°C, further from 200°C to 250°C, for example, 230°C.
  • the thickness of the first insulating layer 106 is relatively thin (for example, less than ), it may cause the metal oxide semiconductor layer 103 to be easily conductive, and the performance of the metal oxide thin film transistor is poor. If the thickness of the first insulating layer 106 is thicker (for example, greater than ), because the internal stress of the first insulating layer 106 is relatively large, it is easy to cause cracks in the area where the first insulating layer 106 overlaps with the source electrode 104 or the drain electrode 105 . Since the crack may expose the source electrode 104 or the drain electrode 105 , the appearance of the crack may directly cause the source electrode 104 or the drain electrode 105 to be oxidized or even corroded.
  • the hydrogen element in the film layer above the source electrode 104 or the drain electrode may enter the surface of the metal oxide semiconductor layer 103 in contact with the source electrode 104 or the drain electrode 105 through the source electrode 104 or the drain electrode 105, resulting in metal oxidation.
  • the characteristics of thin film transistors deteriorate, and in severe cases, sand spots will appear on the display panel.
  • the thickness range of the first insulating layer 106 prepared in the embodiment of the present application is to On the one hand, it can prevent the metal oxide semiconductor layer 103 from being easily conductorized and ensure the performance of the metal oxide thin film transistor; on the other hand, it can avoid cracks in the first insulating layer 106 and ensure the yield rate of the metal oxide thin film transistor. Moreover, the thickness of the first insulating layer 106 is small (greater than ), so the production capacity of the first insulating layer 106 is higher, the cost is reduced, and the mass production is improved. For example, the thickness of the first insulating layer 106 is greater than and not exceeding
  • Step 308 forming an oxygen supplement layer on the side of the first insulating layer away from the base substrate.
  • an oxygen supplement layer is formed on the side of the first insulating layer 106 away from the gate 101 .
  • the oxygen supplement layer is made of indium gallium zinc oxide, and the orthographic projection of the oxygen supplement layer on the base substrate 20 at least partially overlaps the orthographic projection of the metal oxide semiconductor layer 103 on the base substrate 20 .
  • the oxygen element in the oxygen-supplementing layer can be diffused to the metal oxide semiconductor layer 103 through the loose first insulating layer 106, so as to The number of oxygen vacancies in the metal oxide semiconductor layer 103 is reduced to improve the stability of the metal oxide thin film transistor.
  • Step 309 removing the oxygen supplement layer.
  • the oxygen supplement layer may be removed so as to form the second insulating film 107 subsequently.
  • Step 310 forming a second insulating film on the side of the first insulating layer away from the base substrate.
  • chemical vapor deposition equipment may be used to form the second insulating film 107 on the side of the first insulating layer 106 away from the gate. Furthermore, the preparation conditions for preparing the second insulating film 107 are different from those for preparing the first insulating layer 106 .
  • the second insulating film 107 as an example comprising a silicon oxide film layer and a silicon nitride film layer stacked in sequence on the first insulating layer.
  • the film quality of the silicon oxide film layer of the first insulating layer 106 is different from that of the silicon oxide film layer of the second insulating film 107 .
  • the atomic percentage of oxygen contained in the silicon oxide film layer of the first insulating layer 106 is quite different from the atomic percentage of oxygen contained in the silicon oxide film layer of the second insulating film 107; the silicon oxide film forming the first insulating layer 106
  • the difference between the deposition rate of the film layer and the deposition rate of the silicon oxide film layer of the second insulating film 107 is large; The density of the layers varies greatly.
  • the function of the silicon oxide film layer of the second insulating film 107 is to improve the interface between the silicon nitride film layer of the second insulating film 107 and the silicon oxide film layer of the first insulating layer 106, and prevent hydrogen in the silicon nitride film layer from The element enters into the metal oxide semiconductor layer 103 between the source electrode 104 or the drain electrode 105 or into an interface in contact with the metal oxide semiconductor layer 103 in the source electrode 104 or the drain electrode 105 . That is to say, the silicon oxide film layer in the second insulating film 107 mainly serves as a key film layer for improving the interface and preventing hydrogen elements from entering the metal oxide thin film transistor.
  • the key film layer may be a film layer located on the side of the second insulating film 107 close to the gate 101, for example, the key film layer includes the first insulating layer 106, the source electrode 104, the drain electrode 105 and the metal oxide semiconductor layer 103 .
  • the second insulating film 107 can expel the hydrogen element in the silicon nitride film layer included in it during the high temperature annealing process, and replenish the oxygen element in the first insulating layer 106 into the metal oxide semiconductor layer 103 .
  • the embodiment of the present application provides a method for manufacturing a metal oxide thin film transistor. Since the oxygen content of the first insulating layer of the metal oxide thin film transistor prepared by this method is relatively high, the first insulating layer of the metal oxide thin film transistor can be made Oxygen atoms in an insulating layer can diffuse to the metal oxide semiconductor layer, so as to supplement oxygen to the metal oxide semiconductor layer, thereby improving the stability of the metal oxide thin film transistor. Moreover, the interface between the first insulating layer and the metal oxide semiconductor layer is matched, and surface defects of the metal oxide semiconductor layer can be reduced.
  • the atomic number percentage of oxygen contained in the metal oxide semiconductor layer is greater than 45%, so that the oxygen vacancies in the metal oxide semiconductor layer will not be too many, and it is not easy to cause a negative bias in the characteristics of the metal oxide thin film transistor when the device is working. It can effectively reduce the product sand point defect caused by the negative bias of the characteristics of the metal oxide thin film transistor.
  • the embodiment of the present application also provides a display panel.
  • the display panel 01 may include: a base substrate 20, and a plurality of metal oxide thin films provided on the base substrate 20 as provided in the above-mentioned embodiments Transistor 10 (FIG. 1 shows a metal oxide thin film transistor 10).
  • the metal oxide thin film transistor may be the metal oxide thin film transistor 10 shown in FIG. 1 or FIG. 8 .
  • the display panel may further include: a pixel unit located on a side of the second insulating film 107 of the metal oxide thin film transistor 10 away from the base substrate 20 .
  • the pixel unit may at least include a pixel electrode, and the material of the pixel electrode may be indium tin oxide (ITO).
  • the embodiment of the present application also provides a display device.
  • the display device may include a power supply component and the display panel as provided in the above embodiments.
  • the power supply component is used to supply power to the display panel.
  • the display device may be a liquid crystal display device, an organic light-emitting diode (organic light-emitting diode, OLED) display device (such as an active-matrix organic light-emitting diode (AMOLED)), Electronic paper, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame or navigator, etc. Any product or component with display function and fingerprint recognition function.
  • OLED organic light-emitting diode
  • AMOLED active-matrix organic light-emitting diode

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Abstract

本申请公开了一种金属氧化物薄膜晶体管及其制备方法、显示面板，涉及显示技术领域。由于该金属氧化物薄膜晶体管的第一绝缘层的含氧量较高，因此可以使得该第一绝缘层中的氧元素可以向金属氧化物半导体层扩散，以达到对金属氧化物半导体层进行补氧的作用，进而提高金属氧化物薄膜晶体管的稳定性。并且，该第一绝缘层与金属氧化物半导体层的界面匹配，能够降低金属氧化物半导体层的表面缺陷。同时，金属氧化物半导体层的含氧原子数量百分比大于45％，可以使金属氧化物半导体层内的氧空位不会太多，不容易在器件工作时引起金属氧化物薄膜晶体管的特性负偏，可有效降低金属氧化物薄膜晶体管的特性负偏导致的产品沙点不良。

Description

金属氧化物薄膜晶体管及其制备方法、显示面板
本公开要求于2021年8月31日提交的申请号为202111016209.3、发明名称为“金属氧化物薄膜晶体管及其制备方法、显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本申请涉及显示技术领域，特别涉及一种金属氧化物薄膜晶体管及其制备方法、显示面板。
背景技术
铟镓锌氧化物(indium gallium zinc oxide，IGZO)由于其迁移率高，均一性好以及透明性好等优点，被广泛应用于制备薄膜晶体管中的沟道层。
发明内容
本申请提供了一种氧化物薄膜晶体管及其制备方法、显示面板，所述技术方案如下：
一方面，提供了一种金属氧化物薄膜晶体管，所述金属氧化物薄膜晶体管包括：
依次设置在衬底基板上的栅极，栅极绝缘层，金属氧化物半导体层，源极，漏极，第一绝缘层；
其中，所述第一绝缘层与所述金属氧化物半导体接触；
所述第一绝缘层为包含硅元素和氧元素的无机绝缘层，所述第一绝缘层的含氧原子数量百分比大于50％；
所述金属氧化物半导体层的含氧原子数量百分比大于45％。
可选的，所述第一绝缘层的厚度小于2000埃。
可选的，所述第一绝缘层中的硅氧键的键能峰值大于1060cm-1且不超过1080cm-1。
可选的，所述第一绝缘层是通过控制沉积工艺中的氧气含量形成主要成分为氧化硅的膜层，在第一绝缘层的厚度方向上，多个测试位置的含氧原子数量 百分比的差值不超过5％。
可选的，所述第一绝缘层包括：相对的第一表面和第二表面；所述第一表面为靠近所述金属氧化物半导体层的表面，所述第二表面为远离所述金属氧化物半导体层的表面；
从所述第二表面到所述第一表面测试的多个测试位置中，氧原子的分布情况为：越靠近第二表面的位置每相邻两个测试位置的含氧原子数量百分比的差值越大，越靠近第一表面的位置每相邻两个测试位置的含氧原子数量百分比的差值越小。
可选的，所述金属氧化物薄膜晶体管还包括第二绝缘膜，所述第二绝缘膜位于所述第一绝缘层远离所述金属氧化物半导体层的一侧，所述第二绝缘膜包含硅元素，还包含氧元素和氮元素中的至少之一。
可选的，所述第一绝缘层在沿所述厚度方向上的多个测试位置的致密度相同；
所述第一绝缘层的致密度小于所述第二绝缘膜的致密度；
采用氟化氢溶液刻蚀所述第一绝缘层时，刻蚀速率超过25埃/秒且不超过40埃/秒。
可选的，采用氟化氢溶液刻蚀所述第一绝缘层时，刻蚀速率的范围为在28埃/秒至35埃/秒的范围内。
可选的，所述第二绝缘膜包括氮化硅膜层。
可选的，所述第二绝缘膜包括依次位于所述第一绝缘层上的氧化硅膜层和氮化硅膜层；
所述第二绝缘膜中的氧化硅膜层中的氧原子百分比不超过所述第一绝缘层中的氧化硅膜层中的氧原子百分比，二者的差值大于5％至15％。
可选的，所述第二绝缘膜包括依次位于所述第一绝缘层上的氧化硅膜层，氮氧化硅膜层和氮化硅膜层；
所述第二绝缘膜中的氧化硅膜层中的氧原子百分比不超过所述第一绝缘层中的氧化硅膜层中的氧原子百分比，二者的差值大于5％至15％。
可选的，所述氧化硅膜层中的硅氧原子数比为33：67，所述氮氧化硅膜层中的硅氧氮原子数比为36：52：12，所述氮化硅膜层中的硅氮原子数比为51：49。
可选的，所述第一绝缘层的厚度和第二绝缘膜的厚度的比值范围为0.2至0.5。
可选的，所述第一绝缘层中的氧化硅膜层中的含氢原子数量百分比小于3％，且所述第一绝缘层中的氧化硅膜层中的硅氢键数量百分比小于7％。
可选的，所述源极和所述漏极的厚度大于3000埃且小于6000埃，所述第一绝缘层的厚度大于500埃且不超过1100埃；
其中，所述源极和所述漏极的坡度角均小于60度。
可选的，所述金属氧化物半导体层包括相对的第一表面和第二表面，所述第一表面更靠近所述衬底基板；
所述金属氧化物半导体层中靠近所述第一表面的部分包括非晶或纳米晶的金属氧化物；所述金属氧化物半导体层中靠近所述第二表面的部分包括C轴结晶的金属氧化物；
所述非晶或纳米晶的金属氧化物包含铟元素、镓元素、锌元素、锡以及镨元素中的至少之一；
所述C轴结晶的金属氧化物包含铟元素、镓元素、锌元素、锡元素以及镨元素中的至少之一。
可选的，所述非晶或纳米晶的金属氧化物包含铟镓锌氧化物，所述铟镓锌氧化物的铟镓锌原子数比为4：2：3，或者所述铟镓锌氧化物的铟镓锌原子数比为1：1：1，又或者所述铟镓锌氧化物的铟镓锌原子数比为1：3：6；
所述C轴结晶的金属氧化物包含铟镓锌氧化物，所述铟镓锌氧化物的铟镓锌原子数比为4：2：3，或者所述铟镓锌氧化物的铟镓锌原子数比为1：1：1，又或者所述铟镓锌氧化物的铟镓锌原子数比为1：3：6。
可选的，所述金属氧化物半导体层中靠近所述第一表面的部分的载流子迁移率的范围为10平方厘米/伏·秒至20平方厘米/伏·秒。
另一方面，提供了一种金属氧化物薄膜晶体管的制备方法，所述方法包括：
在衬底基板上形成栅极，栅极绝缘层，金属氧化物半导体层，源极，漏极，第一绝缘层；
其中，所述第一绝缘层与所述金属氧化物半导体接触；
所述第一绝缘层为包含硅元素和氧元素的无机绝缘层，所述第一绝缘层的含氧原子数量百分比大于50％；
所述金属氧化物半导体层的含氧原子数量百分比大于45％。
可选的，形成所述第一绝缘层，包括：
向反应腔室内通入氧化二氮和四氢化硅，并采用化学气相沉积设备在所述衬底基板上形成第一绝缘层。
可选的，所述方法还包括：
在所述第一绝缘层远离所述衬底基板的一侧形成补氧层，其中，所述补氧层的材料包括氧化物，所述补氧层在所述衬底基板上的正投影与所述金属氧化物半导体层在所述衬底基板上的正投影至少部分交叠，所述补氧层中的氧原子能够从所述第一绝缘层扩散至所述金属氧化物半导体层；
去除所述补氧层。
可选的，所述第一绝缘层的沉积速率大于10埃/秒。
可选的，所述第一绝缘层的沉积速率的范围为14埃/秒至16埃/秒。
又一方面，提供了一种显示面板，所述显示面板包括：衬底基板，以及设置在所述衬底基板上的多个如上述方面所述的金属氧化物薄膜晶体管。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种显示面板的结构示意图；
图2是本申请实施例提供的一种金属氧化物半导体层，漏极以及第一绝缘层的结构示意图；
图3是本申请实施例提供的第一绝缘层，金属氧化物半导体层以及栅极绝缘层中各个元素含量的百分比曲线示意图；
图4是本申请实施例提供的一种氧化二氮和四氟化硅的比值，与硅氧键峰值的关系示意图；
图5是本申请实施例提供的一种大尺寸衬底基板上形成的第一绝缘层的测试示意图；
图6是本申请实施例提供的一种硅氧键的键能的曲线示意图；
图7是图6在A区域的局部示意图；
图8是本申请实施例提供的另一种显示面板的结构示意图；
图9是本申请实施例提供的另一种金属氧化物半导体层，漏极以及第一绝缘层的结构示意图；
图10是本申请实施例提供的又一种金属氧化物半导体层，漏极以及第一绝缘层的结构示意图；
图11是本申请实施例提供的一种栅极绝缘层，金属氧化物半导体层以及第一绝缘层的结构示意图；
图12是本申请实施例提供的一种栅极绝缘层，漏极，第一绝缘层以及第二绝缘膜的结构示意图；
图13是本申请实施例提供的一种栅极，栅极绝缘层，第一绝缘层以及第二绝缘膜的结构示意图；
图14是本申请实施例提供的一种金属氧化物薄膜晶体管的制备方法的流程图；
图15是本申请实施例提供的一种衬底基板的温度与湿法腐蚀率的关系示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
相关技术中，薄膜晶体管包括：沿远离衬底基板的方向依次层叠的栅极，栅极绝缘层，半导体层，源极，漏极以及钝化层。
但是，相关技术中的半导体层的含氧百分比较小，薄膜晶体管的稳定性较差。
氧化物薄膜晶体管(thin film transistor，TFT)中，控制氢(H)和氧(O)的平衡以控制氧化物TFT的特性(比如需使得氧化物TFT的阈值电压(Vth)漂移较小，漏电流较低等)非常重要。影响氧化物TFT的特性的因素除了需要控制制作金属氧化物半导体层的靶材或工艺条件，还要控制与该金属氧化物半导体层接触的膜层的靶材或工艺条件。例如控制栅极绝缘层和钝化层。这些膜 层的膜层质量的控制相对重要。
除了要使得氧化物TFT的特性满足要求，还要考虑量产的产能以及量产对特性的影响，提高良率。比如，需保证与氧化物TFT的金属氧化物半导体层接触的绝缘层(栅极绝缘层和钝化层)不会在退火过程中开裂。并且，对该绝缘层的沉积速率和膜质也有一定要求。
上述部分和全部的技术问题通过本申请下述的有限的实施例可以优化。
本申请实施例提供的金属氧化物薄膜晶体管用于显示区域或阵列基板行驱动(gate driver on array，GOA)电路的区域。
本申请实施例提供的金属氧化物薄膜晶体管可应用于小尺寸移动设备(Mobile)、笔记本电脑(notebook，NB)，平板电脑(iPAD)，中小尺寸的监视器(monitor，MNT)，中大尺寸的电视机(television，TV)以及中大尺寸的MNT等产品。
本申请实施例提供的金属氧化物薄膜晶体管可以用于显示领域或芯片领域，显示领域可以是液晶(liquid crystal display，LCD)显示面板，有机发光二极管OLED(organic light-emitting diode，OLED)显示面板，量子点发光二极管(quantum dot light emitting diodes，QLED)显示面板，微型发光二极管显示面板(micro light emitting diode，Micro LED)以及传感等技术领域中。其中，本申请实施例提供的氧化物薄膜晶体管可以作为像素开关的TFT，或者可以作为GOA电路以及像素驱动电路等电路中的TFT。
本申请实施例提供的金属氧化物薄膜晶体管在解决底栅背沟道蚀刻型结构(back channel etch，BCE)结构的产品效果更为明显，但是也不限于该结构的产品，比如顶栅结构的产品也适用。本申请实施例以底栅BCE结构为例进行说明。
图1是本申请实施例提供的一种显示面板的结构示意图。参考图1可以看出，该显示面板01中的金属氧化物薄膜晶体管10可以包括：依次设置在衬底基板(substrate)20上的栅极(gate)101，栅极绝缘层(gate insulator，GI)102，金属氧化物半导体层103，源极(source)104，漏极(drain)105以及作为钝化层的第一绝缘层106。
参考图1，源极104和漏极105位于同层，可以采用同一次构图工艺制备得 到。其中，源极104和漏极105均与金属氧化物半导体层103电连接。
参考图1，栅极绝缘层102，金属氧化物半导体层103，源极104，以及第一绝缘层106沿远离栅极101的方向依次层叠。并且，第一绝缘层106靠近栅极101的一侧形成在源极104和漏极105上与源极104和漏极105之间的金属氧化物半导体层103接触。示例的，金属氧化物半导体层101中位于源极104和漏极105下方的区域作为第一区域，位于源极104和漏极105之间的区域作为第二区域。第一绝缘层106靠近栅极101的一侧与金属氧化物半导体层103的第二区域接触。
其中，第一绝缘层106为氧化硅层，在元素成分测试时膜层为至少含有硅(Si)元素和氧元素的无机绝缘层。该第一绝缘层106在实际测试中，该第一绝缘层106中还具有少量的氮(N)元素，但是氮元素的原子数占比非常少，因此可以将该第一绝缘层106简称为氧化硅(SiO)膜层。
本申请所述的原子数占比、原子数量百分比、原子百分率，均可以理解为单位为
Figure PCTCN2022114382-appb-000001
测试设备可以为透射电子显微镜等类似的设备。比如可以采用二次离子质谱(secondary ion mass spectroscopy，SIMS)分析仪进行检测得到。
可选的，第一绝缘层106为第一钝化层(passiv ation layer，PVX)，为富氧膜层，相比第二绝缘层(第二钝化层PVX2)或第一绝缘层之上的绝缘层，该靠近金属氧化物半导体层103的第一绝缘层106为富氧绝缘层。
第一绝缘层106的含氧原子数量百分比超过50％，示例性的范围为50％至75％。示例的，第一绝缘层106的含氧百分比可以为55％，60％，65％或者70％等。
在本申请实施例中，金属氧化物半导体层103的含氧原子数量百分比大于45％。该含氧原子数量百分比大于45％可以使金属氧化物半导体层103内的氧空位不会太多，不容易在TFT器件工作时引起金属氧化物薄膜晶体管的特性负偏，可有效降低金属氧化物薄膜晶体管的特性负偏导致的产品沙点不良。
参考图2，由于金属氧化物半导体层103的迁移率较大，金属氧化物薄膜晶体管中金属氧化物半导体层103的氧空位相对较多，金属氧化物薄膜晶体管的特性控制难度较大。因此将第一绝缘层106的含氧百分比设计的较大，至少有如下优势：
与金属氧化物半导体层103接触的第一绝缘层106为富氧的绝缘层，相对 而言该膜层的H含量较少，有如下优势：
(1)有利于降低金属氧化物半导体层103中进入H，避免作为有源层的金属氧化物半导体层103被导体化。
(2)有利于降低源极104和漏极105表面的氧化层与H结合形成水，腐蚀源极和漏极。
(3)金属氧化物半导体层103制作完成后且在第一绝缘层制作之前，对金属氧化物半导体层103退火，之后再对作为有源层的金属氧化物半导体层103补氧。在补充氧的过程中，富氧的第一绝缘层106有利于提高注入氧气的效率和质量。
(4)第一绝缘层106的作用可以包括：降低金属氧化物半导体层103的表面缺陷。作为保护层避免上层的氮化硅膜层中的H注入到金属氧化物半导体层103。
需要说明的是，在形成该第一绝缘层106之前，对金属氧化物半导体层103退火去除金属氧化物半导体层103中的H以及不稳定的化学键。形成该第一绝缘层106之后且形成第二绝缘膜107之前在第一绝缘层106上形成补氧层，以对金属氧化物半导体层103进行补氧，降低金属氧化物半导体层103被导体化风险，调节金属氧化物半导体层103的半导体特性。其中，补氧层的材料可以为铟镓锌氧化物(indium gallium zinc oxide，IGZO)，补氧工艺为对作为补氧层的IGZO进行高温退火，使得O通过第一绝缘层106再进入到金属氧化物半导体层103。
综上所述，本申请实施例提供了一种金属氧化物薄膜晶体管，由于该金属氧化物薄膜晶体管的第一绝缘层的含氧量较高，因此可以使得该第一绝缘层中的氧元素可以向金属氧化物半导体层扩散，以达到对金属氧化物半导体层进行补氧的作用，进而提高金属氧化物薄膜晶体管的稳定性。并且，该第一绝缘层与金属氧化物半导体层的界面匹配，能够降低金属氧化物半导体层的表面缺陷。同时，金属氧化物半导体层的含氧原子数量百分比大于45％，可以使金属氧化物半导体层内的氧空位不会太多，不容易在器件工作时引起金属氧化物薄膜晶体管的特性负偏，可有效降低金属氧化物薄膜晶体管的特性负偏导致的产品沙点不良。
图3为本申请实施例提供的第一绝缘层，金属氧化物半导体层以及栅极绝 缘层中各个元素含量的百分比曲线示意图。参考图3，金属氧化物半导体层103的含氧原子百分比可以大于50％。
其中，该含氧原子数量百分比大于50％可以避免在器件工作时引起金属氧化物薄膜晶体管的特性负偏，从而避免金属氧化物薄膜晶体管的特性负偏导致的产品沙点不良。
可选的，栅极绝缘层102可以包括沿远离衬底基板20的方向(朝向金属氧化物半导体层)依次层叠的第一子栅极绝缘层和第二子栅极绝缘层。该第一子栅极绝缘层的材料可以为氮化硅(SiNx)，第二子栅极绝缘层的材料可以为氧化硅。
在本申请实施例中，第一绝缘层106的厚度小于
Figure PCTCN2022114382-appb-000002
该厚度有如下优势：
(1)因第一绝缘层(氧化硅膜层)106上还制作有第二绝缘层(如SiN)，在形成第一绝缘层和第二绝缘层之后需要形成像素电极并通过第一绝缘层和第二绝缘层上的过孔与漏极连接。绝缘层上的过孔需要刻蚀液，因SiN的刻蚀速率大于所述SiO的刻蚀速率，因此，SiO做薄可以有效提高产能，降低产品的制作成本。
(2)第一绝缘层106的厚度小于
Figure PCTCN2022114382-appb-000003
相比现有技术大于
Figure PCTCN2022114382-appb-000004
的厚度，对于通过在第一绝缘层106上直接注入金属氧化物半导体层103的氧是有利的，若该膜层较厚，从该第一绝缘层106的上面表层的补氧层(IGZO)注入到下面表层并进入金属氧化物半导体层103，氧的注入效率和质量相对较差。
(3)第一绝缘层106的厚度小于
Figure PCTCN2022114382-appb-000005
可以避免搭在源极104或漏极的位置产生裂纹。若厚度较厚对第一绝缘层106进行高温退火时，第一绝缘层106因厚度较厚，内应力较大而导致与源极104或漏极105交叠的区域出现裂纹
Figure PCTCN2022114382-appb-000006
尤其是在厚度较厚的源极104或漏极105的侧壁容易发生裂纹。由于该裂纹可能会露出源极104或漏极105，因此该裂纹的出现可能会直接导致源极104或漏极105被氧化，甚至会被腐蚀。并且，位于源极104或漏极上方的膜层中的H元素可能会通过源极104或漏极105进入与源极104或漏极105接触的金属氧化物半导体层103的表面，导致金属氧化物薄膜晶体管的特性恶化，严重时会导致显示面板出现沙点。
上述实施例中，第一绝缘层106为富有氧气的较薄的膜层，不仅保证较好 的氧气注入效果和质量，还有效提高产能，并避免第一绝缘层106的裂纹不良。
在本申请实施例中，采用红外吸收光谱仪(fourier transform infrared spectroscopy，FTIR)测试第一绝缘层106中的硅氧键(Si-O)时，硅氧键的键能峰值的范围可以为1060cm-1至1080cm-1。例如，采用红外吸收光谱仪测试第一绝缘层106中的硅氧键(Si-O)时，硅氧键的键能峰值的范围可以为1063cm-1至1067cm-1。其中，cm-1用于表示1厘米中所含波的个数。硅氧键的键能峰值用于表示在吸光度(absorbance)最大时的键能值。
上述实施例的硅氧键(Si-O)的键能相对较大，充分说明该第一绝缘层为富含有Si-O的膜层。
在本申请实施例中，第一绝缘层106可以采用化学气相沉积设备形成在衬底基板20上。并且，制备第一绝缘层106的气体可以包括N 2O(氧化二氮)和SiH4(四氢化硅)。该N 2O和SiH 4发生反应沉积形成氧化硅，即第一绝缘层106可以为单层的氧化硅膜层。
需要说明的是，该金属氧化物薄膜晶体管10的各个膜层均可以在反应腔室内制备。在形成第一绝缘层106时，可以向反应腔室内通入N 2O和SiH 4。
参考图4，通过将N 2O的含量和SiH 4的含量的比值设计的较大，可以使得制备得到的第一绝缘层106中的硅氧键在红外吸收光谱仪测试中的键能峰值达到1060cm-1至1080cm-1范围内，实现富氧膜层。通常情况下，Si-O的键能峰值达到1060cm-1以上的，表示膜层(第一绝缘层106)中的含氧量比常规的做法更高。
可选的，在实现富氧的第一绝缘层106时需要控制SiH 4或H的通过量。也就是说氧气富足时H是相对较少的，或者说O和H的含量比的比值较大，H含量占比更小。
该第一绝缘层106中的氧化硅膜层中的含氢原子数量百分比小于3％。并且，该第一绝缘层106中的氧化硅膜层中的硅氢键(Si-H)数量百分比小于7％。其中，氧化硅膜层中的硅氢键数量百分比可以是指：硅氢键的数量，与硅氢键的数量和硅氧键的数量之和的比值。
由此，由于第一绝缘层106中的氧化硅膜层中的含氢量较少，因此可以避免第一绝缘层106中的氢元素过多的向第一绝缘层106靠近金属氧化物半导体层103的方向扩散，确保金属氧化物薄膜晶体管的特性不会负偏。
本申请实施例在制备显示面板时，可以在一个大尺寸衬底基板上制备，并通过切割得到多个显示面板。图5是本申请实施例提供的一种大尺寸衬底基板上形成的第一绝缘层的测试示意图。图5用于表示可以用于测试大尺寸衬底基板上形成的第一绝缘层在该大尺寸衬底基板的中心(center)区域和边缘(edge)区域的含氢原子百分比，以及可以测试大尺寸衬底基板上形成的第一绝缘层在该大尺寸衬底基板的中心区域和边缘区域的硅氧键的键能峰值。
参考下述表1可以看出，第一绝缘层106在该大尺寸衬底基板的中心(center)区域的含氢原子百分比为2.9％，且第一绝缘层106在该大尺寸衬底基板的中心(center)区域的含氢原子百分比为4.1％。
表1
测试位置 硅氧键的键能峰值 含氢原子百分比(H％)
中心区域 1060 2.9％
边缘区域 1053 4.1％
另外，参考上述表1和图6可以看出，大尺寸衬底基板上形成的第一绝缘层在该大尺寸衬底基板的中心区域的硅氧键的键能峰值为1060cm-1。大尺寸衬底基板上形成的第一绝缘层在该大尺寸衬底基板的边缘区域的硅氧键的键能峰值为1053cm-1。
通过硅氧键的键能峰值以及含氢原子百分比的测试结果可以看出，中心区域的硅氧键的键能峰值大于边缘区域的硅氧键的键能峰值，且中心区域的含氢原子百分比小于边缘区域的含氢原子百分比(中心区域的含氢原子百分比小于3％，边缘区域的含氢原子百分比大于3％)。由此可以看出，在大尺寸衬底基板上形成的第一绝缘层时，位于中心区域的第一绝缘层的膜质相对于边缘区域的第一绝缘层的膜质好。也即是，在制备时大尺寸衬底基板的尺寸越小，越能得到高质量的第一绝缘层。由此，可以在保证产能的前提下，采用较小尺寸的衬底基板来一次制备较少数量的显示面板。
上述本申请不同区域的第一绝缘层106是通过一次工艺形成的，不同区域中Si的含量一致，差异在于H和O的相对含量。若H的含量较多，则沙点问题严重，若O的含量较多也就是H含量较少，则沙点问题得到有效改善。
在本申请实施例中，第一绝缘层106可以在反应腔室内制备得到。并且，该第一绝缘层106是通过控制沉积工艺中向反应腔室内通入的氧气含量形成主 要成分为氧化硅的膜层。其中，在第一绝缘层106的厚度方向上，多个测试位置的含氧原子数量百分比在理论上是一致的，但是在实际测试中具有一定差，但是的差值不超过±3％，最大数值和最小数值的差值不超过5％。
也即是，该第一绝缘层106的厚度方向上的各个测试位置的含氧原子数量百分比基本保持在数值波动范围(即最大的差值不超过5％)内。如附图3，微观上呈波浪线，宏观上接近直线。
在本申请实施例中，第一绝缘层106可以包括相对的第一表面和第二表面。其中，第一表面为靠近金属氧化物半导体层103的表面，第二表面为远离金属氧化物半导体层103的表面。从第二表面到第一表面的多个测试位置中，氧原子的分布情况为：越靠近第二表面的位置每相邻两个测试位置的含氧原子数量百分比的差值越大，越靠近第一表面的位置每相邻两个测试位置的含氧原子数量百分比的差值越小。
体现在图3上可以看出，第一绝缘层106的厚度方向上的各个测试位置的含氧原子数量百分比曲线中，越远离金属氧化物半导体层103的曲线(图3中106范围内越靠左的曲线)波动幅度越大，越靠近金属氧化物半导体层103的曲线(图3中106范围内越靠右的曲线)波动幅度越小。
其中，测试位置可以为第一绝缘层106在厚度方向的位置。相邻两个测试位置可以为第一绝缘层106在厚度方向上的相邻的位置。从图3可以看出，第一绝缘层106的厚度方向上的各个测试位置的含氧原子数量百分比曲线可以为连续的曲线，因此第一绝缘层106在厚度方向上的测试位置也可以为连续的测试位置。
并且，测试第一绝缘层106在厚度方向上的各个测试位置的含氧原子数量时，可以直接在形成第一绝缘层106之后，对该第一绝缘层106的外侧壁进行测试。当然，也可以沿第一绝缘层106的厚度方向切割第一绝缘层106之后，对切割得到的第一绝缘层106的侧壁进行测试。本申请实施例对此不做限定。
图8是本申请实施例提供的另一种显示面板的结构示意图。参考图8可以看出，金属氧化物薄膜晶体管10还可以包括：第二绝缘膜107。该第二绝缘膜107可以位于第一绝缘层106远离金属氧化物半导体层103的一侧。其中，该第二绝缘膜107可以包含硅元素，且该第二绝缘膜107还可以包括氧元素和氮(N)元素中的至少之一。
由于第二绝缘膜107位于第一绝缘层106远离栅极101的一侧，因此该第二绝缘膜107可以起到阻隔作用。例如该第二绝缘膜107可以阻隔外界的杂质，氢元素或氧元素等通过第二绝缘膜107进入关键膜层。其中，该关键膜层可以为位于第二绝缘膜107靠近栅极101的一侧的膜层，例如关键膜层包括第一绝缘层106，源极104，漏极105以及金属氧化物半导体层103。
可选的，第一绝缘层106为单层的氧化硅膜层。该单层的氧化硅膜层可以是采用相同工艺条件制备出的膜层质量(简称膜质)相同的膜层。
在一些实施方式中，第二绝缘膜107可以仅包括氧化硅膜层，或者可以仅包括氮化硅膜层，又或者可以包括依次层叠在第一绝缘层106的一侧的氧化硅膜层和氮化硅膜层，再或者可以包括依次层叠在第一绝缘层106的一侧的氧化硅膜层，氮氧化硅膜层以及氮化硅膜层。
在一些中小尺寸的实施例中，第一绝缘层106和第二绝缘膜107之间还可以具有有机树脂(resin)。作为一种可选的实现方式，若第二绝缘膜107仅包括氮化硅膜层，则第一绝缘层106和第二绝缘膜107可以基于膜层的材料进行区分。并且，第二绝缘膜107可以在高温退火过程中将氮化硅膜层中的H元素排出。
示例的，若金属氧化物薄膜晶体管的特性可以满足基本要求，则为了提高产能降低成本，可以直接在第一绝缘层106(该第一绝缘层106为单层的氧化硅膜层)上形成氮化硅膜层。
作为另一种可选的实现方式，金属氧化物薄膜晶体管的特性要求较高，第一绝缘膜106(第一绝缘层106为单层的氧化硅膜层，该氧化硅膜层称为第一氧化硅膜层)上可以设置与第一氧化硅膜层的膜质具有差异的第二氧化硅膜层。并且，该第二氧化硅膜层远离第一绝缘层106的一侧具有氮化硅膜层。其中，第二氧化硅膜层和氮化硅膜层可以同属于第二绝缘膜107。
需要说明的是，第一氧化硅膜层和第二氧化硅膜层的膜质具有差异可以用于表示下述差异中的至少一种：第一氧化硅膜层中的含氧原子百分比，与第二氧化硅膜层中的含氧原子百分比的差异较大；形成第一氧化硅膜层时的沉积速率与形成第二氧化硅膜层时的沉积速率的差异较大；第一氧化硅膜层的致密度与第二氧化硅膜层的致密度的差异较大。
示例的，第二绝缘膜107中的氧化硅膜层中的氧原子百分比不超过第一绝 缘层106中氧化硅膜层中的氧原子百分比。并且，二者的差值大于5％至15％，例如为10％。
可选的，第二绝缘膜107中的氧化硅膜层的厚度可以大于第一绝缘层106的厚度，例如第二绝缘膜107中的氧化硅膜层的厚度为
Figure PCTCN2022114382-appb-000007
第二绝缘膜107中的氮化硅膜层的厚度可以为
Figure PCTCN2022114382-appb-000008
若在形成第一绝缘层106(第一氧化硅膜层)之后且在形成第二氧化硅膜层之前，通过补氧层对金属氧化物半导体层103进行补氧，则第二氧化硅膜层的作用是改善氮化硅膜层和第一氧化硅膜层的界面，防止氮化硅膜层中的氢元素进入与源极104或漏极105均不重叠的金属氧化物半导体层103的第二区域，或者进入与源极104或漏极105中和金属氧化物半导体层103接触的界面。也即是，第二绝缘膜107中的第二氧化硅膜层为过渡膜层，主要起到改善界面并防止氢元素或水汽进入金属氧化物薄膜晶体管的关键膜层。
并且，第二绝缘膜107可以在高温退火过程中将其包括的氮化硅膜层中的H元素排出，并将第一绝缘层106中的O元素补到金属氧化物半导体层103中。
作为又一种可选的实现方式，第二绝缘膜107可以包括层叠在第一绝缘层106的一侧的氧化硅膜层，氮氧化硅膜层以及氮化硅膜层。
在该实现方式中，第二绝缘膜107中的氧化硅膜层的作用可以与上一种实现方式中第二氧化硅膜层的作用相同。并且，第二绝缘膜107可以在高温退火过程中将其包括的氮氧化硅以及氮化硅膜层中的氢元素排出，并将第一绝缘层106中的氧元素补到金属氧化物半导体层103中。
其中，第二绝缘膜107的氧化硅膜层中的硅氧原子数比为33：67，即Si：O＝33：67。第二绝缘膜107的氮氧化硅膜层中的硅氧氮原子数比为36：52：12，即Si：O：N＝36：52：12。第二绝缘膜107的氮化硅膜层中的硅氮原子数比为51：49，即Si：N＝51：49。
可选的，第二绝缘膜107中的氧化硅膜层的厚度可以大于第一绝缘层106的厚度，例如第二绝缘膜107中的氧化硅膜层的厚度为
Figure PCTCN2022114382-appb-000009
第二绝缘膜107中的氮氧化硅膜层的厚度可以为
Figure PCTCN2022114382-appb-000010
第二绝缘膜107中的氮化硅膜层的厚度可以为
Figure PCTCN2022114382-appb-000011
在本领域，第一绝缘层106和第二绝缘膜107也称为钝化层(passivation layer，PVX)，即第一绝缘层106称为第一钝化层，第二绝缘膜107称为第二 钝化层。
在本领域中，一般情况下，相关技术中的第一钝化层106的厚度范围在
Figure PCTCN2022114382-appb-000012
至
Figure PCTCN2022114382-appb-000013
范围内，该第一钝化层106能够防止外界的氢元素进入关键膜层。但是本申请实施例中的第一钝化层106的厚度小于
Figure PCTCN2022114382-appb-000014
其作用是便于为金属氧化物半导体层103进行补氧以及降低金属氧化物半导体层103的表面缺陷。
并且，本申请实施例中防止外界的氢元素进入关键膜层的主要膜层是第二钝化层107。该第二钝化层107的结构可以如上述实施例所描述的结构。也即是，本申请实施例中的第一钝化层106(单层的氧化硅膜层，厚度小于2000埃)不相当于现有技术的第一钝化层(厚度范围在3000埃至5000埃范围内的氧化硅膜层)。
在本申请实施例中，由于第一绝缘层106为单层的氧化硅膜层，因此该第一绝缘层106是采用相同工艺条件制备出的膜层质量(简称膜质)相同的膜层。由此，第一绝缘层106在沿第一绝缘层106的厚度方向上的多个测试位置的致密度相同。其中，第一绝缘层106在沿第一绝缘层106的厚度方向上的多个测试位置的致密度相同可以是指：第一绝缘层106在沿第一绝缘层106的厚度方向上的多个测试位置的致密度完全相同。或者是指：第一绝缘层106在沿第一绝缘层106的厚度方向上的多个测试位置的致密度在一定的误差范围内。例如，第一绝缘层106在沿第一绝缘层106的厚度方向上的多个测试位置的致密度偏差不超过5％。
可选的，该第一绝缘层106中，越靠近第一表面的位置每相邻两个测试位置的致密度，以及越靠近第二表面的位置每相邻两个测试位置的致密度，与第一绝缘层106的第一表面和第二表面之间的区域的致密度会存在一定的差异。例如，第一绝缘层106中越靠近第一表面的位置每相邻两个测试位置的致密度，以及越靠近第二表面的位置每相邻两个测试位置的致密度，与第一绝缘层106的第一表面和第二表面之间的区域的致密度的误差范围为0％至5％。
需要说明的是，在第一绝缘层106的厚度方向上，多个测试位置的含氧原子百分比的差值不超过5％，以及多个测试位置的致密度相同均可以用于说明该第一绝缘层106为单层膜层。
在本申请实施例中，第一绝缘层106的致密度小于第二绝缘膜107的致密 度。第一绝缘层106的致密度小，因此第一绝缘层106相对而言比第二绝缘膜107疏松。由此在形成第一绝缘层106之后且在形成第二绝缘膜107之前为金属氧化物半导体层103补充氧气更为容易。同时，在形成第二绝缘膜107之后的高温退火过程中，因第二绝缘膜107致密，金属氧化物半导体层103中的氧气容易溢出并陷于第一绝缘层106内而不容易通过第二绝缘膜107释放到外部。这有利于第一绝缘层层106再次为金属氧化物半导体层103补氧，避免金属氧化物半导体层103以及其周边的氢元素的浓度过大而导致的金属氧化物薄膜晶体管的特性较差。
其中，膜层的致密度可以与膜层的沉积速率负相关。也即是，膜层的沉积速率越大，膜层的致密度越小；膜层的沉积速率越小，膜层的致密度越大。由此，第一绝缘层106的沉积速率可以大于第二绝缘膜107的沉积速率，以使得第一绝缘层106的致密度小于第二绝缘膜107的致密度。
可选的，第一绝缘层106的沉积速率为
Figure PCTCN2022114382-appb-000015
左右。示例的，第一绝缘层106的沉积速率为不超过
Figure PCTCN2022114382-appb-000016
第二绝缘膜107的氧化硅膜层的沉积速率可以大于第一绝缘层106的沉积速率，例如可以为
Figure PCTCN2022114382-appb-000017
至
Figure PCTCN2022114382-appb-000018
由于第二绝缘膜107的氧化硅膜层的厚度相对于第一绝缘层106的厚度厚，因此为了提高第二绝缘膜107的制备效率，可以使得第二绝缘膜107的氧化硅膜层的沉积速率大于第一绝缘层106的沉积速率。
需要说明的是，第一绝缘层106的致密度小于第二绝缘膜107的致密度用于表示：第一绝缘层106的致密度小于第二绝缘膜107的氮化硅膜层的致密度。
参考图9，形成金属氧化物半导体层103后需要排出氢元素，例如可以进行退火处理。该退火处理同时会导致金属氧化物半导体层103损失一部分氧原子。因此参考图10，为了保证金属氧化物薄膜晶体管制作完成后金属氧化物半导体层103中足够的氧浓度，避免其导体化，需要在形成第一绝缘层106后对金属氧化物半导体层103进行有效补氧。在形成第一绝缘层106之后且在形成第二绝缘膜107之前，在第一绝缘层106远离栅极101的一侧形成补氧层(补氧层在补氧完成之后需去除，该补氧层的材料可以为铟镓锌氧化物)。
该补氧的过程为补氧层中的氧元素通过第一绝缘层106扩散至金属氧化物半导体层103。其中，氧元素需要通过第一绝缘层106扩散至金属氧化物半导体层10，则需要将第一绝缘层106设计的较为疏松(即致密度较小)。由此在本 申请实施例中，将第一绝缘层106的沉积速率设计的较大(例如大于
Figure PCTCN2022114382-appb-000019
)，以便制备得到较为疏松的第一绝缘层106，进而使得补氧层中的氧元素能够通过疏松的第一绝缘层106扩散至金属氧化物半导体层103，以减少金属氧化物半导体层103中的氧空位的数量，提高金属氧化物薄膜晶体管10的稳定性。
其中，为了便于示出对金属氧化物薄膜晶体管10的金属氧化物半导体层103的补氧过程，图2，图9以及图10仅示出了金属氧化物半导体层103，漏极105以及第一绝缘层106。
在本申请实施例中，第一绝缘层106的致密度(即疏松程度)可以采用氟化氢(HF)溶液对第一绝缘层106进行刻蚀时的刻蚀速率来表征。其中，刻蚀速率越快表明第一绝缘层106的致密度越小(即第一绝缘层106越疏松)；刻蚀速率越慢表明第一绝缘层106的致密度越大(即第一绝缘层106越致密)。
可选的，本申请实施例中，采用HF溶液刻蚀第一绝缘层106时的刻蚀速率超过
Figure PCTCN2022114382-appb-000020
(埃/秒)且不超过
Figure PCTCN2022114382-appb-000021
示例的，采用HF溶液刻蚀第一绝缘层106时的刻蚀速率的范围可以为在
Figure PCTCN2022114382-appb-000022
至
Figure PCTCN2022114382-appb-000023
的范围内。
通常情况下，HF溶液刻蚀时的刻蚀速率大于
Figure PCTCN2022114382-appb-000024
即可认为膜层较为疏松，而本申请实施例中，采用HF溶液刻蚀第一绝缘层106时的刻蚀速率达到
Figure PCTCN2022114382-appb-000025
可以说明该第一绝缘层106的致密度较小。
通过设计较为疏松的第一绝缘层106，可以便于形成在第一绝缘层106远离栅极101的一侧的补氧层对金属氧化物半导体层103进行补氧。
可选的，第一绝缘层106的厚度和第二绝缘膜107的厚度的比值范围为0.2至0.5。示例的，第一绝缘层106(单层的氧化硅层)的厚度为1000埃。第二绝缘膜107包括依次层叠在第一绝缘层106上的氧化硅膜层和氮化硅膜层。其中，第二绝缘膜107中的氧化硅膜层的厚度为3000埃，氮化硅膜层的厚度为
Figure PCTCN2022114382-appb-000026
即第二绝缘膜107的厚度为4000埃。第一绝缘层106的厚度和第二绝缘膜107的厚度的比值为1000/4000＝0.25。
由于第一绝缘层106的厚度和第二绝缘膜107的厚度的比值较小，因此可以进一步说明该第一绝缘层106的厚度较薄。
在本申请实施例中，若第一绝缘层106的厚度较薄(例如厚度小于
Figure PCTCN2022114382-appb-000027
)，则可能会导致金属氧化物半导体层103易被导体化，金属氧化物薄膜晶体管10的性能较差。若第一绝缘层106的厚度较厚(例如大于
Figure PCTCN2022114382-appb-000028
)，则参考图11， 由于第一绝缘层106的膜层压力较大，容易导致第一绝缘层106出现裂纹。由于该裂纹可能会露出源极104或漏极105，因此该裂纹的出现可能会导致刻蚀液通过该裂纹流至金属氧化物半导体层103，对该金属氧化物半导体层103进行了刻蚀，导致金属氧化物薄膜晶体管的特性恶化，严重时会导致显示面板出现沙点。其中，图11所示的两条白色虚线中，左侧的白色虚线为源极104或漏极105与金属氧化物半导体层103的分界线，右侧的白色虚线为第一绝缘层106与金属氧化物半导体层103的分界线。
由此，本申请实施例提供的金属氧化物薄膜晶体管10中的第一绝缘层106的厚度范围为
Figure PCTCN2022114382-appb-000029
至
Figure PCTCN2022114382-appb-000030
一方面可以避免金属氧化物半导体层103易被导体化，保证金属氧化物薄膜晶体管10的性能，另一方面可以避免第一绝缘层106出现裂纹，保证金属氧化物薄膜晶体管10的良率。示例的，第一绝缘层106的厚度大于
Figure PCTCN2022114382-appb-000031
且不超过
Figure PCTCN2022114382-appb-000032
参考图12，第一绝缘层106和第二绝缘膜107中可以具有第一过孔，该第一过孔可以用于露出漏极105，以便后续在第二绝缘膜107远离栅极101的一侧形成的像素单元通过该第一过孔与漏极105电连接。
参考图13，栅极绝缘层102，第一绝缘层106和第二绝缘膜107中可以具有第二过孔，该第二过孔可以用于露出栅极101，以便后续在第二绝缘膜107远离栅极101的一侧形成的公共(common)电极通过该第二过孔与栅极101电连接。
其中，图12和图13中，用于表示第二绝缘膜中的氧化硅膜层，或者还包括第二绝缘膜中的氮氧化硅膜层的含义是：在第二绝缘膜107包括氧化硅膜层和氮化硅膜层的情况下，该层可以为第二绝缘膜的氮化硅膜层；在第二绝缘膜107包括氧化硅膜层，氮氧化硅膜层，以及氮化硅膜层的情况下，该层可以为第二绝缘膜的氮氧化硅膜层和氮化硅膜层。图13所示的三条白色虚线中，最下侧的白色虚线用于表示栅极101和栅极绝缘层102的分界线，中间的白色虚线用于表示栅极绝缘层102和第一绝缘层106的分界线，最上侧的白色虚线用于表示第二绝缘膜107的氧化硅膜层和第二绝缘膜107的氮化硅膜层或氮氧化硅膜层的分界线。
在本申请实施例中，第一绝缘层106中的氧化硅膜层和第二绝缘膜107中的氧化硅膜层中第一过孔的坡度角的范围可以为40度至60度。第二绝缘膜107 中氮化硅膜层中第一过孔的坡度角的范围可以为60度至70度。参考图12，第一绝缘层106中的氧化硅膜层和第二绝缘膜107中的氧化硅膜层中第一过孔的坡度角，与第二绝缘膜中氮化硅膜层中第一过孔的坡度角大致相等。
其中，第一绝缘层106中的氧化硅膜层和第二绝缘膜107中的氧化硅膜层中第一过孔的坡度角可以是指：第一绝缘层106中的氧化硅膜层和第二绝缘膜107中的氧化硅膜层中第一过孔的侧壁与底面之间的夹角。第二绝缘膜107中氮化硅膜层中第一过孔的坡度角可以是指：第二绝缘膜107中氮化硅膜层中第一过孔的侧壁与底面之间的夹角。
另外，栅极绝缘层102的第二过孔的坡度角可以大于80度。第一绝缘层106中的氧化硅膜层和第二绝缘膜107中的氧化硅膜层中第二过孔的坡度角的范围可以为40度至60度。第二绝缘膜107中氮化硅膜层中第二过孔的坡度角的范围可以大于80度。
其中，栅极绝缘层102的第二过孔的坡度角可以是指：栅极绝缘层102的第二过孔的侧壁与底面之间的夹角。第一绝缘层106中的氧化硅膜层和第二绝缘膜107中的氧化硅膜层中第二过孔的坡度角可以是指：第一绝缘层106中的氧化硅膜层和第二绝缘膜107中的氧化硅膜层中第二过孔的侧壁与底面之间的夹角。第二绝缘膜107中氮化硅膜层中第二过孔的坡度角可以是指：第二绝缘膜107中氮化硅膜层中第二过孔的侧壁与底面之间的夹角。
在本申请实施例中，源极104和漏极105的厚度可以大于
Figure PCTCN2022114382-appb-000033
且小于
Figure PCTCN2022114382-appb-000034
并且，源极104和漏极105的坡度角均小于60°(度)。将源极104的坡度角以及漏极105的坡度角设计的均较小，可以避免形成在源极104和漏极105远离衬底基板20的一侧的第一绝缘层106在源极104的爬坡处以及在漏极105的爬坡处出现裂纹，保证金属氧化物薄膜晶体管10的良率。
其中，源极104的坡度角可以是指：源极104的侧壁与源极104靠近栅极101的一面之间的夹角。漏极105的坡度角可以是指：漏极105的侧壁与漏极105靠近栅极101的一面之间的夹角。
在本申请实施例中，金属氧化物半导体层103可以包括相对的第一表面和第二表面，该第一表面相对于第二表面更靠近衬底基板20。其中，该金属氧化物半导体层103中靠近第一表面的部分包括非晶或纳米晶的金属氧化物。该金属氧化物半导体层103中靠近第二表面的部分包括C轴结晶的金属氧化物。
该非晶或纳米晶的金属氧化物包含铟元素、镓元素、锌元素、锡以及镨元素中的至少之一。该C轴结晶的金属氧化物包含铟元素、镓元素、锌元素、锡元素以及镨元素中的至少之一。
可选的，非晶或纳米晶的金属氧化物包含铟镓锌氧化物。该铟镓锌氧化物的铟镓锌原子数比为4：2：3，或者该铟镓锌氧化物的铟镓锌原子数比为1：1：1，又或者铟镓锌氧化物的铟镓锌原子数比为1：3：6。其中，非晶或纳米晶铟镓锌氧化物铟镓锌原子数比是指铟原子数：镓原子数：锌原子数。例如，铟镓锌氧化物的铟镓锌原子数比为4：2：3，则该非晶或纳米晶铟镓锌氧化物可以为非晶或纳米晶In4Ga2Zn3Ox。
另外，C轴结晶的金属氧化物包含铟镓锌氧化物。该铟镓锌氧化物的铟镓锌原子数比为4：2：3，或者该铟镓锌氧化物的铟镓锌原子数比为1：1：1，又或者铟镓锌氧化物的铟镓锌原子数比为1：3：6。其中，C轴结晶铟镓锌氧化物铟镓锌原子数比是指铟原子数：镓原子数：锌原子数。例如，铟镓锌氧化物的铟镓锌原子数比为4：2：3，则该C轴结晶铟镓锌氧化物可以为C轴结晶In4Ga2Zn3Ox。
在本申请实施例中，对于形成图1所示的金属氧化物薄膜晶体管10中的金属氧化物半导体层103的过程包括：采用磁控溅射设备在栅极绝缘层102远离栅极101的一侧形成非晶或纳米晶的金属氧化物，之后再采用磁控溅射设备在非晶或纳米晶的金属氧化物远离栅极101的一侧形成C轴结晶的金属氧化物。
可选的，非晶或纳米晶的金属氧化物的厚度范围为
Figure PCTCN2022114382-appb-000035
至
Figure PCTCN2022114382-appb-000036
C轴结晶的金属氧化物的厚度范围为
Figure PCTCN2022114382-appb-000037
至
Figure PCTCN2022114382-appb-000038
另外，金属氧化物半导体层103中靠近第一表面的部分(即非晶或纳米晶的金属氧化物)的载流子迁移率的范围为10cm 2/V·S(平方厘米/伏·秒)至20cm 2/V·S。例如非晶或纳米晶的金属氧化物的载流子迁移率可以为15cm 2/V·S。由于非晶或纳米晶的金属氧化物的载流子迁移率较大，因此该金属氧化物薄膜晶体管的导电性较好。
综上所述，本申请实施例提供了一种金属氧化物薄膜晶体管，由于该金属氧化物薄膜晶体管的第一绝缘层的含氧量较高，因此可以使得该第一绝缘层中的氧元素可以向金属氧化物半导体层扩散，以达到对金属氧化物半导体层进行补氧的作用，进而提高金属氧化物薄膜晶体管的稳定性。并且，该第一绝缘层 与金属氧化物半导体层的界面匹配，能够降低金属氧化物半导体层的表面缺陷。同时，金属氧化物半导体层的含氧原子数量百分比大于45％，可以使金属氧化物半导体层内的氧空位不会太多，不容易在器件工作时引起金属氧化物薄膜晶体管的特性负偏，可有效降低金属氧化物薄膜晶体管的特性负偏导致的产品沙点不良。
本申请实施例提供的一种金属氧化物薄膜晶体管的制备方法，该方法可以用于制备图1所示的金属氧化物薄膜晶体管10。该方法可以包括：在衬底基板20上形成栅极101，栅极绝缘层102，金属氧化物半导体层103，源极104，漏极105，以及第一绝缘层106。其中，源极104和漏极105可以采用同一次构图工艺制备得到，即源极104和漏极105可以位于同层。
参考图1，制备得到的金属氧化物薄膜晶体管10中，栅极绝缘层102，金属氧化物半导体层103，源极104，以及第一绝缘层106沿远离栅极101的方向依次层叠。并且，第一绝缘层106靠近栅极101的一侧与金属氧化物半导体层103至少部分接触。示例的，金属氧化物半导体层103在衬底基板20上的正投影包括与源极104和漏极105的至少部分重叠的第一区域，以及与源极104和漏极105均不重叠的第二区域。也即是，金属氧化物半导体层101中位于源极104和漏极105下方的区域作为第一区域，位于源极104和漏极105之间的区域作为第二区域。第一绝缘层106靠近栅极101的一侧与金属氧化物半导体层103位于第二区域的部分接触。
其中，第一绝缘层106为至少含有硅元素和氧元素的无机绝缘层。该第一绝缘层106在实际测试中，该第一绝缘层106中还具有少量的氮元素，但是氮元素的原子数占比非常少，因此可以将该第一绝缘层106简称为氧化硅膜层。
该第一绝缘层106的含氧原子数量百分比大于50％。可选的，第一绝缘层106的含氧原子数量百分比的范围为50％至75％。示例的，第一绝缘层106的含氧百分比可以为55％，60％，65％或者70％等。也即是，该第一绝缘层106中的含氧量较高，该第一绝缘层106为富氧膜层。
在本申请实施例中，金属氧化物半导体层103的含氧原子数量百分比大于45％。其中，该金属氧化物半导体层103的含氧原子数量百分比大于45％为实际测试的数据，该含氧原子数量百分比大于45％可以使金属氧化物半导体层103 内的氧空位不会太多，不容易在器件工作时引起金属氧化物薄膜晶体管的特性负偏，可有效降低金属氧化物薄膜晶体管的特性负偏导致的产品沙点不良。
参考图2，由于金属氧化物半导体层103的迁移率较大，因此可能会导致金属氧化物薄膜晶体管中金属氧化物半导体层103的氧空位相对较多，金属氧化物薄膜晶体管的特性控制难度较大。因此将第一绝缘层106的含氧百分比设计的较大，可以使得该第一绝缘层106中的氧元素可以向金属氧化物半导体层103扩散，以达到对金属氧化物半导体层103进行补氧的作用(例如在形成该第一绝缘层106之后且至形成第二绝缘膜107之前在第一绝缘层106上形成补氧层，以对金属氧化物半导体层103进行补氧)，进而提高金属氧化物薄膜晶体管的稳定性。其中，补氧层的材料可以为IGZO。
另外，该第一绝缘层106位于金属氧化物半导体层103的一侧，该第一绝缘层106靠近金属氧化物半导体层103的一面，可以与金属氧化物半导体层103靠近第一绝缘层106的一面匹配(即界面匹配)，能够降低金属氧化物半导体层103的表面缺陷。
由此可知，该第一绝缘层106的作用可以包括：对金属氧化物半导体层103进行补氧，以及降低金属氧化物半导体层103的表面缺陷。
综上所述，本申请实施例提供了一种金属氧化物薄膜晶体管的制备方法，由于该方法制备得到的金属氧化物薄膜晶体管的第一绝缘层的含氧量较高，因此可以使得该第一绝缘层中的氧元素可以向金属氧化物半导体层扩散，以达到对金属氧化物半导体层进行补氧的作用，进而提高金属氧化物薄膜晶体管的稳定性。并且，该第一绝缘层与金属氧化物半导体层的界面匹配，能够降低金属氧化物半导体层的表面缺陷。同时，金属氧化物半导体层的含氧原子数量百分比大于45％，可以使金属氧化物半导体层内的氧空位不会太多，不容易在器件工作时引起金属氧化物薄膜晶体管的特性负偏，可有效降低金属氧化物薄膜晶体管的特性负偏导致的产品沙点不良。
图14是本申请实施例提供的一种金属氧化物薄膜晶体管的制备方法的流程图。该方法可以上述实施例所提供的金属氧化物薄膜晶体管，例如用于制备图1所示的金属氧化物薄膜晶体管。参考图14，该方法可以包括：
步骤301、在衬底基板上形成栅极。
在本申请实施例中，可以先获取一衬底基板20，并在衬底基板20的一侧形成栅极薄膜，之后对该栅极薄膜进行图案化处理，从而得到栅极101。其中，该衬底基板20可以为玻璃基板。
步骤302、在栅极远离衬底基板的一侧形成栅极绝缘层。
在本申请实施例中，在形成栅极101之后，可以在该栅极101远离衬底基板20的一侧形成栅极绝缘层102，以使得栅极101与后续形成的源极104和漏极105绝缘。
可选的，栅极绝缘层102可以包括沿远离衬底基板20的方向依次层叠的第一子栅极绝缘层102和第二子栅极绝缘层102。该第一子栅极绝缘层102的材料可以为氮化硅，第二子栅极绝缘层102的材料可以为氧化硅。
步骤303、在栅极绝缘层远离衬底基板的一侧形成金属氧化物半导体薄膜。
在形成栅极绝缘层102之后，可以在该栅极绝缘层102远离衬底基板20的一侧形成金属氧化物半导体薄膜，并且，该金属氧化物半导体薄膜可以整层覆盖该衬底基板20。
可选的，可以采用磁控溅射设备在栅极绝缘层102远离衬底基板20的一侧形成第一薄膜。该第一薄膜可以采用迁移率较高的材料进行制备。之后，再采用磁控溅射设备在第一薄膜远离衬底基板20的一侧形成第二薄膜。其中，第一薄膜和第二薄膜可以统称为金属氧化物半导体薄膜。
其中，该第一薄膜可以为非晶或纳米晶的金属氧化物，该第二薄膜可以为C轴结晶的金属氧化物。该非晶或纳米晶的金属氧化物包含铟元素、镓元素、锌元素、锡以及镨元素中的至少之一。该C轴结晶的金属氧化物包含铟元素、镓元素、锌元素、锡元素以及镨元素中的至少之一。
可选的，非晶或纳米晶的金属氧化物包含铟镓锌氧化物。该铟镓锌氧化物的铟镓锌原子数比为4：2：3，或者该铟镓锌氧化物的铟镓锌原子数比为1：1：1，又或者铟镓锌氧化物的铟镓锌原子数比为1：3：6。其中，非晶或纳米晶铟镓锌氧化物铟镓锌原子数比是指铟原子数：镓原子数：锌原子数。例如，铟镓锌氧化物的铟镓锌原子数比为4：2：3，则该非晶或纳米晶铟镓锌氧化物可以为非晶或纳米晶In4Ga2Zn3Ox。
另外，C轴结晶的金属氧化物包含铟镓锌氧化物。该铟镓锌氧化物的铟镓锌原子数比为4：2：3，或者该铟镓锌氧化物的铟镓锌原子数比为1：1：1，又或 者铟镓锌氧化物的铟镓锌原子数比为1：3：6。其中，C轴结晶铟镓锌氧化物铟镓锌原子数比是指铟原子数：镓原子数：锌原子数。例如，铟镓锌氧化物的铟镓锌原子数比为4：2：3，则该C轴结晶铟镓锌氧化物可以为C轴结晶In4Ga2Zn3Ox。
可选的，第一薄膜的厚度范围为
Figure PCTCN2022114382-appb-000039
至
Figure PCTCN2022114382-appb-000040
第二薄膜的厚度范围为
Figure PCTCN2022114382-appb-000041
至
Figure PCTCN2022114382-appb-000042
步骤304、对金属氧化物半导体薄膜进行图案化处理，得到金属氧化物半导体层。
在本申请实施例中，在形成金属氧化物半导体薄膜之后，可以采用光刻工艺该金属氧化物半导体薄膜进行图案化处理，得到金属氧化物半导体层103。其中，该金属氧化物半导体层103在衬底基板20上的正投影与栅极101在衬底基板20上的正投影至少部分重叠。该光刻工艺可以包括：光刻胶(photoresist，PR)涂覆、曝光、显影、刻蚀和光刻胶剥离等工艺。该光刻工艺也可以称为掩膜板工艺。
可选的，上述步骤303中的金属氧化物半导体薄膜包括第一薄膜和第二薄膜。由此该步骤对金属氧化物半导体薄膜进行图案化处理的可以是指对第一薄膜和第二薄膜进行图案化处理。其中，对第一薄膜进行图案化处理可以得到金属氧化物半导体层103中靠近第一表面的非晶或纳米晶的金属氧化物，对第二薄膜进行图案化处理可以得到金属氧化物半导体层103中靠近第二表面的C轴结晶的金属氧化物。其中，第一表面和第二表面为金属氧化物半导体层103相对的两面，且第一表面相对于第二表面更靠近衬底基板20。
其中，该金属氧化物半导体层103中靠近第一表面的非晶或纳米晶的金属氧化物的载流子迁移率较高。可选的，金属氧化物半导体层103中靠近第一表面的非晶或纳米晶的金属氧化物的载流子迁移率的范围为10cm 2/V·S至20cm 2/V·S。例如载流子迁移率为15cm 2/V·S。
步骤305、在金属氧化物半导体层远离衬底基板的一侧形成源漏极薄膜。
在本申请实施例中，在制备得到金属氧化物半导体层103之后，可以在该金属氧化物半导体层103远离衬底基板20的一侧形成源漏极薄膜。其中，该源漏极薄膜的材料可以为金属材料，且源漏极薄膜可以整层覆盖该衬底基板20。
步骤306、对源漏极薄膜进行图案化处理，得到源极和漏极。
在本申请实施例中，在形成源漏极薄膜之后，可以采用光刻工艺对源漏极薄膜进行图案化处理，得到源极104和漏极105。其中，在刻蚀源漏极薄膜时，可以采用刻蚀剂对源漏极薄膜进行湿法刻蚀，得到源极104和漏极105。在该实现方式中，源极104和漏极105是采用同一次构图工艺制备得到的。
该源极104在衬底基板20上的正投影与金属氧化物半导体层103在衬底基板20上的正投影存在交叠区域。该漏极105在衬底基板20上的正投影与金属氧化物半导体层103在衬底基板20上的正投影存在交叠区域。
并且，制备得到的源极104和漏极105的厚度可以大于
Figure PCTCN2022114382-appb-000043
且小于
Figure PCTCN2022114382-appb-000044
另外，源极104靠近漏极105的侧壁，以及漏极105靠近源极104的侧壁可以为曲线或折线。由此，源极104靠近漏极105的侧壁中的不同区域与源极104靠近或远离第一绝缘层106的一面之间的夹角不同，且漏极105靠近源极104的侧壁中的不同区域与漏极105靠近或远离第一绝缘层106的一面之间的夹角不同。
其中，制备得到的源极104和漏极105的坡度角均小于60°。将源极104的坡度角以及漏极105的坡度角设计的均较小，可以避免形成在源极104和漏极105远离栅极101的一侧的第一绝缘层106在源极104的爬坡处以及在漏极105的爬坡处出现裂纹，保证金属氧化物薄膜晶体管10的良率。
步骤307、采用化学气相沉积设备在源极远离衬底基板的一侧形成第一绝缘层。
在本申请实施例中，该金属氧化物薄膜晶体管的各个膜层可以在反应腔室内制备。在形成第一绝缘层106时，可以向反应腔室内通入N 2O和SiH 4。可选的，N 2O的含量和SiH 4的含量的比值可以大于78。示例的，N 2O的含量和SiH 4的含量的比值可以为80。
参考图4，通过将N 2O的含量和SiH 4的含量的比值设计的较大，可以使得制备得到的第一绝缘层106中的硅氧键在红外吸收光谱仪测试中的键能峰值达到1060cm-1至1080cm-1范围内。通常情况下，Si-O的键能峰值达到1060cm-1以上的，表示膜层(第一绝缘层106)中的含氧量较高，可避免第一绝缘层106中的杂质(例如氢等)含量较高导致金属氧化物薄膜晶体管的特性不稳定。
在本申请实施例中，第一绝缘层106在制备时的沉积速率可以大于
Figure PCTCN2022114382-appb-000045
示例的，第一绝缘层106在制备时的沉积速率不超过
Figure PCTCN2022114382-appb-000046
通过将第一绝缘层106在制备时的沉积速率设置的较大，可以使得形成的第一绝缘层106较为疏松(致密度较小)，便于后续形成在第一绝缘层106远离栅极101的一侧的补氧层对金属氧化物半导体层103进行补氧。
在本申请实施例中，第一绝缘层106的沉积速率与在制备该第一绝缘层106时化学气相沉积设备的沉积功率，沉积压力，以及反应腔室内的温度相关。
另外，为了检测反应腔室不同温度下形成的第一绝缘层106的致密度(即疏松程度)，可以先在不同温度的反应腔室形成不同的第一绝缘层106，采用1％的HF溶液对形成的各个第一绝缘层106进行湿法刻蚀，并采用湿法腐蚀率(wet etch rate，WER)表征第一绝缘层106的致密度。其中，湿法腐蚀率越大的第一绝缘层106越疏松，湿法腐蚀率越小的第一绝缘层106越致密。
参考图15，1％的HF溶液对反应腔室的温度在230℃时形成的第一绝缘层106的湿法腐蚀率为
Figure PCTCN2022114382-appb-000047
相对于反应腔室在其他温度下时形成的第一绝缘层106的湿法腐蚀率快。也即是，反应腔室的温度在230℃时形成的第一绝缘层106较疏松。由此，可以使得形成第一绝缘层106时，反应腔室的温度范围为100℃至300℃，进一步为200℃至250℃，例如为230℃。
在本申请实施例中，若第一绝缘层106的厚度较薄(例如小于
Figure PCTCN2022114382-appb-000048
)，则可能会导致金属氧化物半导体层103易被导体化，金属氧化物薄膜晶体管的性能较差。若第一绝缘层106的厚度较厚(例如大于
Figure PCTCN2022114382-appb-000049
)，则由于第一绝缘层106的膜层内应力较大，容易导致第一绝缘层106与源极104或漏极105交叠的区域出现裂纹。由于该裂纹可能会露出源极104或漏极105，因此该裂纹的出现可能会直接导致源极104或漏极105被氧化，甚至会被腐蚀。并且，位于源极104或漏极上方的膜层中的氢元素可能会通过源极104或漏极105进入与源极104或漏极105接触的金属氧化物半导体层103的表面，导致金属氧化物薄膜晶体管的特性恶化，严重时会导致显示面板出现沙点。
由此，本申请实施例制备得到的第一绝缘层106的厚度范围为
Figure PCTCN2022114382-appb-000050
至
Figure PCTCN2022114382-appb-000051
一方面可以避免金属氧化物半导体层103易被导体化，保证金属氧化物薄膜晶体管的性能，另一方面可以避免第一绝缘层106出现裂纹，保证金属氧化物薄膜晶体管的良率。并且，第一绝缘层106的厚度较小(大于
Figure PCTCN2022114382-appb-000052
)，因此第一绝缘层106的产能较高，降低成本，提高量产性。示例的，第一绝缘层106的厚度大于
Figure PCTCN2022114382-appb-000053
且不超过
Figure PCTCN2022114382-appb-000054
步骤308、在第一绝缘层远离衬底基板的一侧形成补氧层。
在本申请实施例中，参考图2，由于金属氧化物半导体层103的迁移率较大，因此可能会导致金属氧化物半导体层103的氧空位相对较多，金属氧化物薄膜晶体管的特性控制难度较大。参考图9，形成金属氧化物半导体层103后需要排出氢元素，例如可以进行退火处理。该退火处理同时会导致金属氧化物半导体层103损失一部分氧原子。由此，参考图10，为了保证金属氧化物薄膜晶体管制制作完成后金属氧化物半导体层103中足够的氧浓度，避免其导体化，需要在形成第一绝缘层106后对金属氧化物半导体层103进行有效补氧。在形成第一绝缘层106之后且在形成第二绝缘膜107之前，在第一绝缘层106远离栅极101的一侧形成补氧层。其中，补氧层的材料为铟镓锌氧化物，补氧层在衬底基板20上的正投影与金属氧化物半导体层103在衬底基板20上的正投影至少部分交叠。
由于上述步骤307制备得到的第一绝缘层106较为疏松(致密度较小)，进而可以使得补氧层中的氧元素能够通过疏松的第一绝缘层106扩散至金属氧化物半导体层103，以减少金属氧化物半导体层103中的氧空位的数量，提高金属氧化物薄膜晶体管的稳定性。
步骤309、去除补氧层。
在本申请实施例中，在补氧层对金属氧化物半导体层103补氧完成后，可以将该补氧层去除，以便后续形成第二绝缘膜107。
步骤310、在第一绝缘层远离衬底基板的一侧形成第二绝缘膜。
在本申请实施例中，可以采用化学气相沉积设备在第一绝缘层106远离栅极的一侧形成第二绝缘膜107。并且，制备该第二绝缘膜107时的制备制备条件与制备第一绝缘层106时的制备条件不同。
以第二绝缘膜107包括位于第一绝缘层上依次层叠的氧化硅膜层和氮化硅膜层为例。第一绝缘层106的氧化硅膜层和第二绝缘膜107的氧化硅膜层的膜质具有差异。例如，第一绝缘层106的氧化硅膜层中的含氧原子百分比，与第二绝缘膜107的氧化硅膜层中的含氧原子百分比的差异较大；形成第一绝缘层106的氧化硅膜层时的沉积速率与形成第二绝缘膜107的氧化硅膜层时的沉积速率的差异较大；第一绝缘层106的氧化硅膜层的致密度与第二绝缘膜107的氧化硅膜层的致密度的差异较大。
其中，第二绝缘膜107的氧化硅膜层的作用是改善第二绝缘膜107的氮化硅膜层和第一绝缘层106的氧化硅膜层的界面，防止氮化硅膜层中的氢元素进入源极104或漏极105之间的金属氧化物半导体层103或者进入与源极104或漏极105中与金属氧化物半导体层103接触的界面。也即是，第二绝缘膜107中的氧化硅膜层主要起到改善界面并防止氢元素进入金属氧化物薄膜晶体管的关键膜层。其中，该关键膜层可以为位于第二绝缘膜107靠近栅极101的一侧的膜层，例如关键膜层包括第一绝缘层106，源极104，漏极105以及金属氧化物半导体层103。
并且，第二绝缘膜107可以在高温退火过程中将其包括的氮化硅膜层中的氢元素排出，并将第一绝缘层106中的氧元素补到金属氧化物半导体层103中。
综上所述，本申请实施例提供了一种金属氧化物薄膜晶体管的制备方法，由于该方法制备得到的金属氧化物薄膜晶体管的第一绝缘层的含氧量较高，因此可以使得该第一绝缘层中的氧原子可以向金属氧化物半导体层扩散，以达到对金属氧化物半导体层进行补氧的作用，进而提高金属氧化物薄膜晶体管的稳定性。并且，该第一绝缘层与金属氧化物半导体层的界面匹配，能够降低金属氧化物半导体层的表面缺陷。同时，金属氧化物半导体层的含氧原子数量百分比大于45％，可以使金属氧化物半导体层内的氧空位不会太多，不容易在器件工作时引起金属氧化物薄膜晶体管的特性负偏，可有效降低金属氧化物薄膜晶体管的特性负偏导致的产品沙点不良。
本申请实施例还提供了一种显示面板，参考图1，该显示面板01可以包括：衬底基板20，以及设置在该衬底基板20的多个如上述实施例所提供的金属氧化物薄膜晶体管10(图1示出了一个金属氧化物薄膜晶体管10)。其中，该金属氧化物薄膜晶体管可以为图1或图8所示的金属氧化物薄膜晶管10。
可选的，该显示面板还可以包括：位于金属氧化物薄膜晶体管10的第二绝缘膜107远离衬底基板20的一侧的像素单元。其中，像素单元可以至少包括像素电极，该像素电极的材料可以为氧化铟锡(indium tin oxide，ITO)。
本申请实施例还提供了一种显示装置。该显示装置可以包括供电组件以及如上述实施例所提供的显示面板。该供电组件用于为显示面板供电。
可选的，该显示装置可以为液晶显示装置、有机发光二极管(organic light-emitting diode，OLED)显示装置(例如为有源矩阵有机发光二极管(active-matrix organic light-emitting diode，AMOLED))、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能以及指纹识别功能的产品或部件。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (24)

  1. 一种金属氧化物薄膜晶体管，其特征在于，包括：
    依次设置在衬底基板上的栅极，栅极绝缘层，金属氧化物半导体层，源极，漏极，第一绝缘层；
    其中，所述第一绝缘层与所述金属氧化物半导体层接触；
    所述第一绝缘层为包含硅元素和氧元素的无机绝缘层，所述第一绝缘层的含氧原子数量百分比大于50％；
    所述金属氧化物半导体层的含氧原子数量百分比大于45％。
  2. 根据权利要求1所述的金属氧化物薄膜晶体管，其特征在于，所述第一绝缘层的厚度小于2000埃。
  3. 根据权利要求1或2所述的金属氧化物薄膜晶体管，其特征在于，所述第一绝缘层中的硅氧键的键能峰值大于1060cm-1且不超过1080cm-1。
  4. 根据权利要求1至3任一所述的金属氧化物薄膜晶体管，其特征在于，所述第一绝缘层是通过控制沉积工艺中的氧气含量形成主要成分为氧化硅的膜层，在第一绝缘层的厚度方向上，多个测试位置的含氧原子数量百分比的差值不超过5％。
  5. 根据权利要求1至4任一所述的金属氧化物薄膜晶体管，其特征在于，所述第一绝缘层包括：相对的第一表面和第二表面；所述第一表面为靠近所述金属氧化物半导体层的表面，所述第二表面为远离所述金属氧化物半导体层的表面；
    从所述第二表面到所述第一表面测试的多个测试位置中，氧原子的分布情况为：越靠近第二表面的位置每相邻两个测试位置的含氧原子数量百分比的差值越大，越靠近第一表面的位置每相邻两个测试位置的含氧原子数量百分比的差值越小。
  6. 根据权利要求1至5任一所述的金属氧化物薄膜晶体管，其特征在于，所 述金属氧化物薄膜晶体管还包括第二绝缘膜，所述第二绝缘膜位于所述第一绝缘层远离所述金属氧化物半导体层的一侧，所述第二绝缘膜包含硅元素，还包含氧元素和氮元素中的至少之一。
  7. 根据权利要求6所述的金属氧化物薄膜晶体管，其特征在于，
    所述第一绝缘层在沿所述厚度方向上的多个测试位置的致密度相同；
    所述第一绝缘层的致密度小于所述第二绝缘膜的致密度；
    采用氟化氢溶液刻蚀所述第一绝缘层时，刻蚀速率超过25埃/秒且不超过40埃/秒。
  8. 根据权利要求7所述的金属氧化物薄膜晶体管，其特征在于，采用氟化氢溶液刻蚀所述第一绝缘层时，刻蚀速率的范围为在28埃/秒至35埃/秒的范围内。
  9. 根据权利要求6至8任一所述的金属氧化物薄膜晶体管，其特征在于，所述第二绝缘膜包括氮化硅膜层。
  10. 根据权利要求6至8任一所述的金属氧化物薄膜晶体管，其特征在于，所述第二绝缘膜包括依次位于所述第一绝缘层上的氧化硅膜层和氮化硅膜层；
    所述第二绝缘膜中的氧化硅膜层中的氧原子百分比不超过所述第一绝缘层中的氧化硅膜层中的氧原子百分比，二者的差值大于5％至15％。
  11. 根据权利要求6至8任一所述的金属氧化物薄膜晶体管，其特征在于，所述第二绝缘膜包括依次位于所述第一绝缘层上的氧化硅膜层，氮氧化硅膜层和氮化硅膜层；
    所述第二绝缘膜中的氧化硅膜层中的氧原子百分比不超过所述第一绝缘层中的氧化硅膜层中的氧原子百分比，二者的差值大于5％至15％。
  12. 根据权利要求11所述的金属氧化物薄膜晶体管，其特征在于，所述氧化硅膜层中的硅氧原子数比为33：67，所述氮氧化硅膜层中的硅氧氮原子数比为36：52：12，所述氮化硅膜层中的硅氮原子数比为51：49。
  13. 根据权利要求6至12任一所述的金属氧化物薄膜晶体管，其特征在于，所述第一绝缘层的厚度和第二绝缘膜的厚度的比值范围为0.2至0.5。
  14. 根据权利要求1至13任一所述的金属氧化物薄膜晶体管，其特征在于，所述第一绝缘层中的氧化硅膜层中的含氢原子数量百分比小于3％，且所述第一绝缘层中的氧化硅膜层中的硅氢键数量百分比小于7％。
  15. 根据权利要求1至14任一所述的金属氧化物薄膜晶体管，其特征在于，所述源极和所述漏极的厚度大于3000埃且小于6000埃，所述第一绝缘层的厚度大于500埃且不超过1100埃；
    其中，所述源极和所述漏极的坡度角均小于60度。
  16. 根据权利要求1至15任一所述的金属氧化物薄膜晶体管，其特征在于，所述金属氧化物半导体层包括相对的第一表面和第二表面，所述第一表面更靠近所述衬底基板；
    所述金属氧化物半导体层中靠近所述第一表面的部分包括非晶或纳米晶的金属氧化物；所述金属氧化物半导体层中靠近所述第二表面的部分包括C轴结晶的金属氧化物；
    所述非晶或纳米晶的金属氧化物包含铟元素、镓元素、锌元素、锡以及镨元素中的至少之一；
    所述C轴结晶的金属氧化物包含铟元素、镓元素、锌元素、锡元素以及镨元素中的至少之一。
  17. 根据权利要求16所述的金属氧化物薄膜晶体管，其特征在于，所述非晶或纳米晶的金属氧化物包含铟镓锌氧化物，所述铟镓锌氧化物的铟镓锌原子数比为4：2：3，或者所述铟镓锌氧化物的铟镓锌原子数比为1：1：1，又或者所述铟镓锌氧化物的铟镓锌原子数比为1：3：6；
    所述C轴结晶的金属氧化物包含铟镓锌氧化物，所述铟镓锌氧化物的铟镓锌原子数比为4：2：3，或者所述铟镓锌氧化物的铟镓锌原子数比为1：1：1，又或者所述铟镓锌氧化物的铟镓锌原子数比为1：3：6。
  18. 根据权利要求16或17所述的金属氧化物薄膜晶体管，其特征在于，所述金属氧化物半导体层中靠近所述第一表面的部分的载流子迁移率的范围为10平方厘米/伏·秒至20平方厘米/伏·秒。
  19. 一种金属氧化物薄膜晶体管的制备方法，其特征在于，所述方法包括：
    在衬底基板上形成栅极，栅极绝缘层，金属氧化物半导体层，源极，漏极，第一绝缘层；
    其中，所述第一绝缘层与所述金属氧化物半导体接触；
    所述第一绝缘层为包含硅元素和氧元素的无机绝缘层，所述第一绝缘层的含氧原子数量百分比大于50％；
    所述金属氧化物半导体层的含氧原子数量百分比大于45％。
  20. 根据权利要求19所述的方法，其特征在于，形成所述第一绝缘层，包括：
    向反应腔室内通入氧化二氮和四氢化硅，并采用化学气相沉积设备在所述衬底基板上形成第一绝缘层。
  21. 根据权利要求19或20所述的方法，其特征在于，所述方法还包括：
    在所述第一绝缘层远离所述衬底基板的一侧形成补氧层，其中，所述补氧层的材料包括氧化物，所述补氧层在所述衬底基板上的正投影与所述金属氧化物半导体层在所述衬底基板上的正投影至少部分交叠，所述补氧层中的氧原子能够从所述第一绝缘层扩散至所述金属氧化物半导体层；
    去除所述补氧层。
  22. 根据权利要求19至21任一所述的金属氧化物薄膜晶体管，其特征在于，所述第一绝缘层的沉积速率大于10埃/秒。
  23. 根据权利要求19所述的金属氧化物薄膜晶体管，其特征在于，所述第一绝缘层的沉积速率的范围为14埃/秒至16埃/秒。
  24. 一种显示面板，其特征在于，所述显示面板包括：衬底基板，以及设置在所述衬底基板上的多个如权利要求1至16任一所述的金属氧化物薄膜晶体管。
PCT/CN2022/114382 2021-08-31 2022-08-24 金属氧化物薄膜晶体管及其制备方法、显示面板 WO2023030108A1 (zh)

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