WO2019119584A1 - 阵列基板及其制造方法 - Google Patents

阵列基板及其制造方法 Download PDF

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Publication number
WO2019119584A1
WO2019119584A1 PCT/CN2018/072735 CN2018072735W WO2019119584A1 WO 2019119584 A1 WO2019119584 A1 WO 2019119584A1 CN 2018072735 W CN2018072735 W CN 2018072735W WO 2019119584 A1 WO2019119584 A1 WO 2019119584A1
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layer
gate
drain
substrate
material layer
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PCT/CN2018/072735
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English (en)
French (fr)
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白思航
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武汉华星光电半导体显示技术有限公司
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Priority to US15/979,335 priority Critical patent/US10651257B2/en
Publication of WO2019119584A1 publication Critical patent/WO2019119584A1/zh
Priority to US16/824,323 priority patent/US10727289B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a method of fabricating the same.
  • LTPS TFTs low temperature polysilicon thin film transistors
  • Conventional low-temperature polysilicon thin film transistors mostly use a top gate structure.
  • the surface of the active layer formed by deposition is not flat, which is liable to cause flatness of a structure such as a gate deposited on the active layer.
  • the degree is poor, and thus the resistance distribution of the interface between the active layer and the gate is uneven, which leads to unstable overall performance.
  • the present invention provides an array substrate and a method of fabricating the same.
  • a method of manufacturing an array substrate comprising the steps of:
  • a via hole is formed on the source/drain layer to form a source and a drain.
  • the via hole is disposed corresponding to the active layer, and the source and the drain are electrically connected to the active layer.
  • the gate layer includes a first gate and a second gate spaced apart from the first gate, the first gate is disposed corresponding to the active layer, and the second gate is The drain is electrically connected.
  • the polysilicon material layer, the etch barrier material layer and the gate insulating material layer are etched to form an active layer, an etch barrier layer and a gate insulating layer, the gate insulating layer Covering the gate layer and the substrate, the active layer is formed on the gate layer, and the etch barrier layer covers the active layer, further comprising:
  • the gate insulating material layer is etched such that the second gate is exposed away from a top surface of the substrate to enable the second gate to be in contact with the drain.
  • the active layer includes a channel region, a first non-channel region, and a second non-channel region, the channel region being connected to the first non-channel region and the second non-channel Between the regions, the channel region is disposed corresponding to the through hole, and the active layer is located at the first non-channel region and an end surface remote from the channel region is electrically connected to the source, The active layer is electrically connected to the drain at an end surface of the second non-channel region and away from the channel region.
  • depositing an etch barrier material layer on the polysilicon material layer comprises the following steps:
  • the etch barrier material layer comprising a first etch stop material layer and a second etch connected to the first etch stop material layer
  • the first etch barrier material layer is disposed corresponding to the active layer, and the first etch barrier material layer has a thickness greater than a thickness of the second etch barrier material layer.
  • the thickness of the first etch barrier material layer is the same as the thickness of the pre-etched etch barrier material layer.
  • the via is formed on the source and drain layers to form a source and a drain, the via is disposed corresponding to the active layer, and the source and the drain are electrically connected to the active layer
  • the manufacturing method further includes the step of forming an organic light-emitting layer on the source and the drain.
  • an organic light-emitting layer on the source and the drain includes the following steps:
  • a pixel defining layer is formed on the passivation layer, the pixel defining layer covers the anode, and the organic light emitting layer includes the passivation layer, the anode, and the pixel defining layer.
  • forming the gate layer on the substrate comprises the following steps:
  • the gate layer is formed on the buffer layer, and the substrate, the barrier layer, and the buffer layer are sequentially laminated to form the substrate.
  • An array substrate comprising a substrate, a gate layer, a gate insulating layer, an active layer made of a polysilicon material, an etch barrier layer, a source and a drain, wherein the gate layer is disposed on the substrate
  • the gate insulating layer covers the gate layer and the substrate, the active layer is disposed on the gate insulating layer, and the etch barrier layer covers the active layer, the source And the drain is disposed on the etch barrier layer, and the source and the drain are electrically connected to the active layer.
  • the array substrate provided by the present invention and the manufacturing method thereof are characterized in that the array substrate is a bottom gate structure, which reduces the surface unevenness caused by the active layer made of a polysilicon material in the top gate structure in the prior art.
  • the uneven interface resistance improves the stability of the electrical performance of the overall structure.
  • the filling of the source line and the drain line may be prevented from being unevenly filled, the contact is poor, and the like, and the filling process may be avoided.
  • the bubbles cause incomplete filling, which is more advantageous for the source and the drain to contact the active layer.
  • FIG. 1 is a schematic diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a flowchart of a method of manufacturing an array substrate according to an embodiment of the present invention
  • Figure 3 is a schematic view of a first primary structure
  • Figure 4 is a schematic view of a second primary structure
  • Figure 5 is a schematic view of a third primary structure
  • Figure 6 is a schematic view of a fourth primary structure
  • Figure 7 is a schematic view of a sixth primary structure
  • Figure 8 is a schematic view of a seventh primary structure
  • Figure 9 is a schematic view of an eighth primary structure
  • Figure 10 is a schematic illustration of a fourth sub-primary structure.
  • an embodiment of the present invention provides an array substrate 100 .
  • the array substrate 100 is applied to a display panel.
  • the array substrate 100 includes a substrate 11, a gate layer 13, a gate insulating layer 15, an active layer 17 made of a polysilicon material, an etch barrier layer 19, a source 21, and a drain 23.
  • the gate layer 13 is disposed on the substrate 11, the gate insulating layer 15 covers the gate layer 13 and the substrate 11, the active layer 17 is disposed on the gate insulating layer 15, and the etch barrier layer 19 covers the active layer 17, the source 21 and the drain 23 are provided on the etch barrier layer 19.
  • the source 21 and the drain 23 are electrically connected to the active layer 17
  • the substrate 11 is a flexible substrate.
  • the array substrate 100 is a flexible display panel.
  • the gate layer 13 is formed on the substrate 11.
  • the gate layer 13 includes a first gate 131 and a second gate 133 spaced apart from the first gate 131.
  • the first gate 131 and the second gate 133 are made of metal Mo
  • the second gate 135 is disposed corresponding to the terminal region (PAD) of the array substrate 100.
  • the first gate 131 and the second gate 133 may be made of other metals, such as a metal such as Al, Ti, Cu, Cr, or a single layer structure of an alloy such as AlNd or MoNb, or Al/ A laminate made of a metal such as Mo, Ti/Al/Ti or the like is formed.
  • the second gate 133 is in contact with the drain 23 away from the top surface of the substrate 11.
  • the gate insulating layer 15 covers the gate layer 13. In this embodiment, the thickness of the gate insulating layer 15 is about It will be appreciated, the gate insulating layer 15 may be formed of SiNx, SiO 2 material may also be a single layer laminated SiNx / SiO 2, SiNx / Al 2 O 3 is formed of an insulating material.
  • the active layer 17 is formed on the gate insulating layer 17.
  • the active layer 17 includes a channel region 171, a first non-channel region 173, and a second non-channel region 175.
  • the channel region 171 is connected to the first non-channel. Between the region 173 and the second non-channel region 175.
  • the channel region 171 is disposed corresponding to the first gate 131.
  • the active layer 17 is formed by channel doping through a polysilicon material.
  • the active layer 17 is located in the first non-channel region 173 and is electrically connected to the source 21 of the end surface away from the channel region 171 .
  • the active layer 17 is located at the end surface and the drain of the second non-channel region 175 and away from the channel region 171 .
  • the pole 23 is electrically connected.
  • the etch barrier layer 19 covers the channel region 171, the first non-channel region 173, and the second non-channel region 175.
  • the etch stop layer 19 is used to prevent the etching liquid or the etching gas from affecting the active layer 17 of the lower layer during the process of fabricating the array substrate 100.
  • the source 21 and the drain 23 are formed by depositing a source/drain material layer (not shown) on the etch barrier layer 19 and forming a via hole 25.
  • the array substrate 100 further includes an organic light emitting layer 40 that is further formed on the source 21 and the drain 23 .
  • the organic light emitting layer 40 includes a passivation layer 41, an anode 43, a pixel defining layer 45, and a spacer 47.
  • the passivation layer 41 covers the source 21 and the drain 23, and the anode 43 is formed on the passivation layer 41 and connected to the drain 23.
  • the pixel defining layer 43 is formed on the passivation layer 41, and the spacer 47 is formed on the pixel defining layer 43.
  • the substrate 11 includes a substrate 111, a barrier layer 113, and a buffer layer 115.
  • the barrier layer 113 is formed on the substrate 111
  • the buffer layer 115 is formed on the barrier layer 113.
  • the substrate 111, the barrier layer 113, and the buffer layer 115 are sequentially stacked to form the substrate 11.
  • the substrate 111 is made of a material such as polyimide (PI) and/or polyethylene terephthalate (PET). It will be appreciated that the substrate 111 may also be made of a hard material such as glass.
  • the present invention also provides a method for fabricating an array substrate, which includes the following steps:
  • Step 201 referring to FIG. 3, a gate layer 13 is formed on the substrate 11.
  • the structure formed in step 201 is the first primary structure 201.
  • a predetermined pattern of the gate layer 13 is formed on the substrate 11 by a photomask (not shown).
  • Step 202 referring to FIG. 4, a gate insulating material layer 32 is formed on the gate layer 13, and the gate insulating material layer 32 covers the gate layer 13 and the substrate 11.
  • the structure formed in step 202 is the second primary structure 202.
  • Step 203 referring to FIG. 5, a polysilicon material layer 34 is formed on the gate insulating material layer 32.
  • the structure formed in step 203 is the third primary structure 203.
  • Step 204 referring to FIG. 6, a etch stop material layer 36 is deposited over the polysilicon material layer 34.
  • the structure formed in step 204 is the fourth primary structure 204.
  • Step 205 channel doping the polysilicon material layer 34.
  • the structure formed in step 205 is a fifth primary structure (not shown).
  • Step 206 referring to FIG. 7, etching the polysilicon material layer 34, the etch barrier material layer 36, and the gate insulating material layer 32, thereby forming an active layer 17, an etch barrier layer 19, and a gate insulating layer 15, the gate A gate insulating layer 15 covering the gate layer 13 and the substrate 11 is formed on the gate layer 13 , and the etch barrier layer 19 covers the active layer 17 .
  • the structure formed in step 206 is the sixth primary structure 206.
  • Step 207 referring to FIG. 8, a source/drain layer 38 is formed on the active layer 17 and the gate insulating layer 15.
  • the active layer 17 is electrically connected to the source and drain layers 20.
  • the structure formed in step 207 is the seventh primary structure 207.
  • Step 208 referring to FIG. 9, a via hole 25 is formed on the source/drain layer 38, thereby forming a source electrode 21 and a drain electrode 23.
  • the via hole 25 is disposed corresponding to the active layer 17, and the source electrode 21 and the drain electrode 23 are both provided. It is electrically connected to the active layer 17.
  • the structure formed in step 208 is the eighth primary structure 208.
  • the gate layer 13 includes a first gate 131 and a second gate 133 spaced apart from the first gate 131.
  • the first gate 131 is disposed corresponding to the active layer 17.
  • the second gate 135 is disposed corresponding to a terminal region (not shown) of the array substrate 100.
  • step 206 the polysilicon material layer 34, the etch barrier material layer 36 and the gate insulating material layer 32 are etched, thereby forming the active layer 17, the etch stop layer 19 overlying the active layer 17, and the gate insulation.
  • the step of the layer 15 includes the steps of: etching the gate insulating material layer 32 such that the second gate electrode 133 is exposed away from the top surface of the substrate 11 to enable the second gate electrode 133 to The drain 23 is in contact.
  • the active layer 17 includes a channel region 171, a first non-channel region 173, and a second non-channel region 175.
  • the channel region 171 is connected between the first non-channel region 173 and the second non-channel region 175.
  • the channel region 171 is disposed corresponding to the position of the first gate 131.
  • the second gate 133 is disposed adjacent to the second non-channel region 175.
  • the through hole 25 is provided corresponding to the channel region 171.
  • step 206 since the etching stopper layer 19 is provided, the region where the first gate electrode 131 and the second gate electrode 133 are disposed is avoided during etching, thereby avoiding etching of the liquid or etching gas to the gate layer 13. influences.
  • the polysilicon material layer 16 of the non-active layer region 103, the etch barrier layer 19, and the gate insulating layer 15 located in the non-active layer region 103 are etched away by the entire surface etching until the second gate 133 is away from The top surface of the substrate 11 is exposed.
  • a via hole 25 is formed by etching a source drain layer 20 through a mask, thereby forming a source 21 and a drain 23.
  • the drain 23 is in contact with the second gate 133.
  • the active layer 17 of the first non-channel region 173 is electrically connected to the source 21 away from the end surface of the channel region 171, and the active layer 17 of the second non-channel region 175 is away from the end surface of the channel region 171 and the drain 23 Electrical connection.
  • the method specifically includes:
  • Step 2041 referring to FIG. 10, a pre-etched etch stop material layer 360 is deposited over the polysilicon material layer 34.
  • the structure formed in step 2041 is the fourth sub-primary structure 2041.
  • Step 2042 referring again to FIG. 6, etching the pre-etched etch stop material layer 360 to form an etch stop material layer 36, the etch stop material layer 36 including the first etch stop material layer 361 and the first etch stop material layer 361 is connected to the second etch barrier material layer 363.
  • the first etch barrier material layer 361 is disposed corresponding to the active layer 17.
  • the first etch barrier material layer 361 is disposed corresponding to the first gate 131.
  • the thickness of the material layer 361 is greater than the thickness of the second etch stop material layer 363.
  • the thickness of the pre-etched etch stop material layer 360 formed in step 2041 is about
  • the thickness of the first etch stop material layer 361 is the same as the thickness of the pre-etch etch stop material layer 360 formed in step 2041. In other words, the thickness of the first etch stop material layer 361 remains pre-cut.
  • the original thickness of the etch stop material layer 360, the thickness of the second etch stop material layer 363 is about The subsequent etching process is prevented from affecting the underlying material, thereby affecting the performance of the array substrate 100.
  • the barrier material layer 36 is etched by a mask to form a first etch barrier material layer 361 and a second etch barrier material layer 363 connected to the first etch barrier material layer 361.
  • the filling of the source line and the drain line may avoid uneven filling and poor contact, which is more advantageous for the source 21 and the drain. 23 contact with the active layer 17.
  • the manufacturing method further includes a step 209: forming an organic light emitting layer 40 on the source 21 and the drain 23, the organic light emitting layer 40 including a passivation layer 41 and an anode 43. And pixel definition layer 45.
  • the method specifically includes the following steps:
  • a passivation layer 41 is deposited on the source 21 and the drain 23.
  • a passivation layer 41 is formed on the source 21 and the drain 23 by a photomask, and a via hole 411 is formed in the passivation layer 41.
  • Step 2092 an anode 45 is formed on the passivation layer 41, and the anode 43 is connected to the drain 23.
  • an anode 45 is formed on the passivation layer 41 through a photomask, and the anode 45 is connected to the drain 23 through the via hole 411.
  • Step 2093 forming a pixel defining layer 45 on the passivation layer 41, the pixel defining layer 45 covering the anode 43.
  • a spacer 47 is formed on the pixel defining layer 45.
  • the spacer 47 is used to support the thickness of the case.
  • a pixel defining layer 45 and a spacer 47 are formed on the passivation layer 41 by a photomask.
  • step 201 that is, the step of forming the gate layer 13 on the substrate 11, the following steps are specifically included:
  • Step 2012 forming a buffer layer 115 on the barrier layer 113;
  • step 2013, the gate layer 13 is formed on the buffer layer 115, and the substrate 111, the barrier layer 113, and the buffer layer 115 are sequentially laminated to form the substrate 11.
  • step 2013, the gate layer 13 is formed on the buffer layer 115 by a photomask.
  • the array substrate 100 and the manufacturing method thereof are provided.
  • the array substrate 100 is a bottom gate structure, which reduces the interface resistance caused by surface unevenness caused by grain boundaries in polysilicon in the top gate structure in the prior art.
  • the phenomenon of unevenness improves the stability of the electrical properties of the thin film transistor.
  • the filling of the source line and the drain line may be prevented from being unevenly filled, the contact is poor, and the like, and the filling process may be avoided.
  • the bubbles cause incomplete filling, which is more advantageous for the contact of the source 21 and the drain 23 with the active layer 17.

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Abstract

一种阵列基板及其制造方法，制造方法包括以下步骤：在基底(11)上形成栅极层(13)(201)；在栅极层(13)上形成栅极绝缘材料层(32)(202)；在栅极绝缘材料层(32)上形成多晶硅材料层(34)(203)；在多晶硅材料层(34)上沉积形成刻蚀阻挡材料层(36)(204)；对多晶硅材料层(34)进行沟道掺杂(205)；形成有源层(17)、刻蚀阻挡层(19)及栅极绝缘层(15)；在有源层(17)及栅极绝缘层(15)上形成源漏极层(38)，有源层(17)与源漏极层(38)电性连接(207)；及在源漏极层(38)上形成通孔(25)，进而形成源极(21)及漏极(23)，通孔(25)对应有源层(17)设置，源极(21)及漏极(23)均与有源层(17)电性连接(208)。由于阵列基板(100)为底栅结构，减小了顶栅结构中由于有源层引起的表面不平整带来的界面电阻不均的现象，提高了阵列基板(100)的电学性能的稳定性。

Description

阵列基板及其制造方法
本发明要求2017年12月18日递交的发明名称为“阵列基板及其制造方法”的申请号2017113612368的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示技术领域，特别涉及一种阵列基板及其制造方法。
背景技术
目前，低温多晶硅薄膜晶体管(LTPS TFT)以其高电子迁移率和稳定性受到较大的关注。传统的低温多晶硅薄膜晶体管多采用顶栅极(Top Gate)结构，然而，沉积形成的有源层的表面不平整，易造成后续沉积于所述有源层的栅极(Gate)等结构的平坦度较差，进而易导致所述有源层与所述栅极之间界面的电阻分布不均，进而导致整体性能不稳定。
发明内容
为了解决前述问题，本发明提供一种阵列基板及其制造方法。
一种阵列基板的制造方法，其包括以下步骤：
在基底上形成栅极层；
在所述栅极层上形成栅极绝缘材料层，所述栅极绝缘材料层覆盖所述栅极层及所述基底；
在所述栅极绝缘材料层上形成多晶硅材料层；
在所述多晶硅材料层上沉积形成刻蚀阻挡材料层；
对所述多晶硅材料层进行沟道掺杂；
蚀刻所述多晶硅材料层、所述刻蚀阻挡材料层及所述栅极绝缘材料层，进而形成有源层、刻蚀阻挡层及栅极绝缘层，所述栅极绝缘层覆盖所述栅极层及 所述基底，所述有源层形成于所述栅极层上，所述刻蚀阻挡层覆盖所述有源层；
在所述有源层及所述栅极绝缘层上形成源漏极层，所述有源层与所述源漏极层电性连接；及
在所述源漏极层上形成通孔，进而形成源极及漏极，所述通孔对应有源层设置，所述源极及所述漏极均与有源层电性连接。
进一步地，所述栅极层包括第一栅极及与所述第一栅极间隔设置的第二栅极，所述第一栅极对应所述有源层设置，所述第二栅极与所述漏极电性连接。
进一步地，所述蚀刻所述多晶硅材料层、所述刻蚀阻挡材料层及所述栅极绝缘材料层，进而形成有源层、刻蚀阻挡层及栅极绝缘层，所述栅极绝缘层覆盖所述栅极层及所述基底，所述有源层形成于所述栅极层上，所述刻蚀阻挡层覆盖所述有源层，还包括：
蚀刻所述栅极绝缘材料层，使得所述第二栅极远离所述基底的顶面露出，以使所述第二栅极能够与所述漏极接触。
进一步地，所述有源层包括沟道区域、第一非沟道区域及第二非沟道区域，所述沟道区域连接于第一所述非沟道区域及所述第二非沟道区域之间，所述沟道区域对应所述通孔设置，所述有源层位于所述第一非沟道区域且远离所述沟道区域的端面与所述源极电性连接，所述有源层位于所述第二非沟道区域且远离所述沟道区域的端面与所述漏极电性连接。
进一步地，所述在所述多晶硅材料层上沉积形成刻蚀阻挡材料层，包括以下步骤：
在所述多晶硅材料层上沉积形成预制刻蚀阻挡材料层；
蚀刻所述预制刻蚀阻挡材料层进而形成所述刻蚀阻挡材料层，所述刻蚀阻挡材料层包括第一刻蚀阻挡材料层及与所述第一刻蚀阻挡材料层连接的第二刻蚀阻挡材料层，所述第一刻蚀阻挡材料层对应所述有源层设置，所述第一刻蚀阻挡材料层的厚度大于所述第二刻蚀阻挡材料层的厚度。
进一步地，所述第一刻蚀阻挡材料层的厚度与所述预制刻蚀阻挡材料层的厚度相同。
进一步地，所述在所述源漏极层上形成通孔，进而形成源极及漏极，所述通孔对应有源层设置，所述源极及所述漏极均与有源层电性连接后，所述制造 方法还包括步骤：在所述源极及所述漏极上形成有机发光层。
进一步地，所述在所述源极及所述漏极上形成有机发光层，具体包括以下步骤：
在所述源极及所述漏极上沉积形成钝化层；
在所述钝化层上形成阳极，所述阳极与所述漏极连接；
在所述钝化层上形成像素定义层，所述像素定义层覆盖所述阳极，所述有机发光层包括所述钝化层、所述阳极及所述像素定义层。
进一步地，所述在基底上形成栅极层，包括以下步骤：
在衬底上形成阻挡层；
在所述阻挡层上形成缓冲层；
在所述缓冲层上形成所述栅极层，所述衬底、所述阻挡层及所述缓冲层依次层叠形成所述基底。
一种阵列基板，其包括基底、栅极层、栅极绝缘层、由多晶硅材料制成的有源层、刻蚀阻挡层、源极及漏极，所述栅极层设于所述基底上，所述栅极绝缘层覆盖所述栅极层及所述基底，所述有源层设于所述栅极绝缘层上，所述刻蚀阻挡层覆盖所述有源层，所述源极及所述漏极设于所述刻蚀阻挡层上，所述源极与所述漏极均与所述有源层电性连接。
本发明提供的阵列基板及其制造方法，由于所述阵列基板为底栅结构，其减小了现有技术中顶栅结构中，由多晶硅材料制成的有源层引起的表面不平整带来的界面电阻不均的现象，提高了整体结构的电学性能的稳定性。此外，由于不采用传统的挖孔填充源极及漏极的做法，避免填充所述源极线及所述漏极线时可能存在填充不均，接触不良等现象，更能避免填充过程中由于气泡造成填充不完全的现象，更有利于所述源极及所述漏极与所述有源层的接触。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的阵列基板的示意图；
图2是本发明实施例提供的阵列基板的制造方法的流程图；
图3是第一初级结构的示意图；
图4是第二初级结构的示意图；
图5是第三初级结构的示意图；
图6是第四初级结构的示意图；
图7是第六初级结构的示意图；
图8是第七初级结构的示意图；
图9是第八初级结构的示意图；
图10是第四子初级结构的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，本发明实施例提供一种阵列基板100。阵列基板100应用于显示面板。阵列基板100包括基底11、栅极层13、栅极绝缘层15、由多晶硅材料制成的有源层17、刻蚀阻挡层19、源极21及漏极23。栅极层13设于基底11上，栅极绝缘层15覆盖栅极层13及基底11，有源层17设于栅极绝缘层15上，刻蚀阻挡层19覆盖有源层17，源极21及漏极23设于刻蚀阻挡层19上。源极21与漏极23均与有源层17电性连接
本实施方式中，基底11为柔性基底。所述阵列基板100为柔性显示面板。
栅极层13形成于基底11上，栅极层13包括第一栅极131及与第一栅极131间隔设置的第二栅极133。本实施方式中，第一栅极131及第二栅极133由金属Mo制成，所述第二栅极135对应阵列基板100的端子区(PAD)设置。在其它实施例中，第一栅极131及第二栅极133可以由其它金属制成，例如Al、Ti、Cu、Cr等金属或者AlNd、MoNb等合金的单层结构，也可以用Al/Mo、Ti/Al/Ti等金属制成的叠层形成。第二栅极133远离衬底11的顶面与漏极23 接触。
栅极绝缘层15覆盖栅极层13。本实施方式中，栅极绝缘层15的厚度约为
Figure PCTCN2018072735-appb-000001
可以理解，栅极绝缘层15可以由SiNx、SiO 2等单层材料构成也可用SiNx/SiO 2、SiNx/Al 2O 3等绝缘物质的叠层形成。
有源层17形成于栅极绝缘层17上，有源层17包括沟道区域171、第一非沟道区域173及第二非沟道区域175，沟道区域171连接于第一非沟道区域173及第二非沟道区域175之间。沟道区域171对应第一栅极131设置。本实施方式中，有源层17经多晶硅材料通过沟道掺杂形成。有源层17位于第一非沟道区域173且远离沟道区域171的端面与源极21电性连接，有源层17位于第二非沟道区域175且远离沟道区域171的端面与漏极23电性连接。
刻蚀阻挡层19覆盖沟道区域171、第一非沟道区域173及第二非沟道区域175。刻蚀阻挡层19用于在制造所述阵列基板100的过程中，避免刻蚀液体或刻蚀气体在对下层的有源层17造成影响。
本实施方式中，源极21与漏极23通过于刻蚀阻挡层19上沉积源漏极材料层(图未示)并形成通孔25形成。
进一步地，阵列基板100还包括还形成于源极21及漏极23上的有机发光层40。有机发光层40包括钝化层41、阳极43、像素定义层45及间隙物47，钝化层41覆盖源极21与漏极23，阳极43形成于钝化层41上并与漏极23连接，像素定义层43形成于钝化层41，间隙物47形成于像素定义层43上。
进一步地，所述基底11包括衬底111、阻挡层113及缓冲层115。阻挡层113形成于衬底111上，缓冲层115形成于阻挡层113上。衬底111、阻挡层113及缓冲层115依次呈层叠设置形成基底11。衬底111由聚酰亚胺(PI)及/或聚对苯二甲酸乙二醇酯(PET)等材料制成。可以理解，衬底111也可以由硬质材料制成，例如玻璃。
请参阅图2，本发明还提供一种阵列基板的制造方法，其包括以下步骤：
步骤201，请参阅图3，在基底11上形成栅极层13。设在步骤201中形成的结构为第一初级结构201。
本实施方式中，通过一道光罩(图未示)于基底11上形成预设图案的栅极层13。
步骤202，请参阅图4，在栅极层13上形成栅极绝缘材料层32，栅极绝缘材料层32覆盖栅极层13及基底11。设在步骤202中形成的结构为第二初级结构202。
步骤203，请参阅图5，在栅极绝缘材料层32上形成多晶硅材料层34。设在步骤203中形成的结构为第三初级结构203。
步骤204，请参阅图6，在多晶硅材料层34上沉积形成刻蚀阻挡材料层36。设在步骤204中形成的结构为第四初级结构204。
步骤205，对多晶硅材料层34进行沟道掺杂。设在步骤205中形成的结构为第五初级结构(图未示)。
步骤206，请参阅图7，蚀刻多晶硅材料层34、刻蚀阻挡材料层36及栅极绝缘材料层32，进而形成有源层17、刻蚀阻挡层19及栅极绝缘层15，所述栅极绝缘层15覆盖所述栅极层13及所述基底11，所述有源层17形成于所述栅极层13上，所述刻蚀阻挡层19覆盖所述有源层17。设在步骤206中形成的结构为第六初级结构206。
步骤207，请参阅图8，在有源层17及栅极绝缘层15上形成源漏极层38，有源层17与源漏极层20电性连接。设在步骤207中形成的结构为第七初级结构207。
步骤208，请参阅图9，在源漏极层38上形成通孔25，进而形成源极21及漏极23，所述通孔25对应有源层17设置，源极21及漏极23均与有源层17电性连接。设在步骤208中形成的结构为第八初级结构208。
进一步地，栅极层13包括第一栅极131及与第一栅极131间隔设置的第二栅极133。第一栅极131对应有源层17设置。第二栅极135对应阵列基板100的端子区(图未示)设置。
在步骤206中，即蚀刻多晶硅材料层34、刻蚀阻挡材料层36及栅极绝缘材料层32，进而形成有源层17、覆盖于有源层17上的刻蚀阻挡层19及栅极绝缘层15的步骤中，具体包括以下步骤：蚀刻所述栅极绝缘材料层32，使得所述第二栅极133远离所述基底11的顶面露出，以使所述第二栅极133能够与所述漏极23接触。
进一步地，有源层17包括沟道区域171、第一非沟道区域173及第二非 沟道区域175。沟道区域171连接于第一非沟道区域173及第二非沟道区域175之间。沟道区域171对应第一栅极131的位置设置。第二栅极133邻近第二非沟道区域175设置。通孔25对应沟道区域171设置。
在步骤206中，由于设有蚀刻阻挡层19，进而在蚀刻时避开了设有第一栅极131及第二栅极133的区域，避免刻蚀液体或刻蚀气体对栅极层13的影响。另外，通过整面蚀刻的方式，蚀刻除去非有源层区域103的多晶硅材料层16、刻蚀阻挡层19及位于非有源层区域103的栅极绝缘层15，直至第二栅极133远离基底11的顶面露出。
在步骤208中，通过一道光罩蚀刻源漏极层20形成通孔25，进而形成源极21及漏极23。漏极23与第二栅极133接触连接。第一非沟道区域173的有源层17远离沟道区域171的端面与源极21电性连接，第二非沟道区域175的有源层17远离沟道区域171的端面与漏极23电性连接。
进一步地，在步骤204中，即所述在多晶硅材料层34上沉积形成刻蚀阻挡材料层36的步骤中，具体包括：
步骤2041，请参阅图10，在多晶硅材料层34上沉积形成预制刻蚀阻挡材料层360。设在步骤2041中形成的结构为第四子初级结构2041。
步骤2042，请再次参阅图6，蚀刻预制刻蚀阻挡材料层360进而形成刻蚀阻挡材料层36，刻蚀阻挡材料层36包括第一刻蚀阻挡材料层361及与第一刻蚀阻挡材料层361连接的第二刻蚀阻挡材料层363，第一刻蚀阻挡材料层361对应所述有源层17设置，第一刻蚀阻挡材料层361对应第一栅极131设置，第一刻蚀阻挡材料层361的厚度大于第二刻蚀阻挡材料层363的厚度。
在本实施方式中，在步骤2041中所形成的预制刻蚀阻挡材料层360的厚度约为
Figure PCTCN2018072735-appb-000002
在步骤2042中，第一刻蚀阻挡材料层361的厚度与步骤2041中所形成的预制刻蚀阻挡材料层360的厚度相同，换句话说，第一刻蚀阻挡材料层361的厚度保留预制刻蚀阻挡材料层360的原有厚度，所述第二刻蚀阻挡材料层363的厚度约为
Figure PCTCN2018072735-appb-000003
避免后续刻蚀制程对下层材料造成影响，进而影响阵列基板100的性能。
在步骤2042中，通过一道光罩蚀刻刻蚀阻挡材料层36进而形成第一刻蚀阻挡材料层361及与第一刻蚀阻挡材料层361连接的第二刻蚀阻挡材料层 363。
由于不采用传统的挖孔填充源极及漏极的做法，避免填充所述源极线及所述漏极线时可能存在填充不均，接触不良等现象，更有利于源极21及漏极23和有源层17的接触。
进一步地，请再次参阅图1，在步骤208后，所述制造方法还包括步骤209：在源极21及漏极23上形成有机发光层40，有机发光层40包括钝化层41、阳极43及像素定义层45。
在步骤209中，即所述在源极21及漏极23上形成有机发光层40的步骤中，具体包括以下步骤：
步骤2091，在源极21及漏极23上沉积形成钝化层41。
进一步地，在步骤2091中，通过一道光罩在源极21及漏极23上沉积形成钝化层41，所述钝化层41上形成过孔411。
步骤2092，在所述钝化层41上形成阳极45，阳极43与漏极23连接。
进一步地，在步骤2092中，通过一道光罩在所述钝化层41上形成阳极45，所述阳极45通过所述过孔411与漏极23连接。
步骤2093，在所述钝化层41上形成像素定义层45，所述像素定义层45覆盖所述阳极43。
进一步地，在步骤2093，在所述像素定义层45上形成间隙物47。所述间隙物47用于支撑盒厚。通过一道光罩在所述钝化层41上形成像素定义层45及间隙物47。
进一步地，在步骤201中，即所述在基底11上形成栅极层13的步骤中，具体包括以下步骤：
步骤2011，在衬底111上形成阻挡层113；
步骤2012，在所述阻挡层113上形成缓冲层115；
步骤2013，在所述缓冲层115上形成所述栅极层13，所述衬底111、所述阻挡层113及所述缓冲层115依次层叠形成所述基底11。
在步骤2013中，通过一道光罩在所述缓冲层115上形成所述栅极层13。
本发明提供的阵列基板100及其制造方法，由于所述阵列基板100为底栅结构，其减小了现有技术中顶栅结构中由于多晶硅中晶界引起的表面不平整带 来的界面电阻不均的现象，提高了薄膜晶体管的电学性能的稳定性。此外，由于不采用传统的挖孔填充源极及漏极的做法，避免填充所述源极线及所述漏极线时可能存在填充不均，接触不良等现象，更能避免填充过程中由于气泡造成填充不完全的现象，更有利于源极21及漏极23和有源层17的接触。
可以理解，以上所揭露的仅为本发明的较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (15)

  1. 一种阵列基板的制造方法，其包括以下步骤：
    在基底上形成栅极层；
    在所述栅极层上形成栅极绝缘材料层，所述栅极绝缘材料层覆盖所述栅极层及所述基底；
    在所述栅极绝缘材料层上形成多晶硅材料层；
    在所述多晶硅材料层上沉积形成刻蚀阻挡材料层；
    对所述多晶硅材料层进行沟道掺杂；
    蚀刻所述多晶硅材料层、所述刻蚀阻挡材料层及所述栅极绝缘材料层，进而形成有源层、刻蚀阻挡层及栅极绝缘层，所述栅极绝缘层覆盖所述栅极层及所述基底，所述有源层形成于所述栅极层上，所述刻蚀阻挡层覆盖所述有源层；
    在所述有源层及所述栅极绝缘层上形成源漏极层，所述有源层与所述源漏极层电性连接；及
    在所述源漏极层上形成通孔，进而形成源极及漏极，所述通孔对应有源层设置，所述源极及所述漏极均与有源层电性连接。
  2. 如权利要求1所述的制造方法，其中，所述栅极层包括第一栅极及与所述第一栅极间隔设置的第二栅极，所述第一栅极对应所述有源层设置，所述第二栅极与所述漏极电性连接。
  3. 如权利要求2所述的制造方法，其中，所述蚀刻所述多晶硅材料层、所述刻蚀阻挡材料层及所述栅极绝缘材料层，进而形成有源层、刻蚀阻挡层及栅极绝缘层，所述栅极绝缘层覆盖所述栅极层及所述基底，所述有源层形成于所述栅极层上，所述刻蚀阻挡层覆盖所述有源层，还包括：
    蚀刻所述栅极绝缘材料层，使得所述第二栅极远离所述基底的顶面露出，以使所述第二栅极能够与所述漏极接触。
  4. 如权利要求1所述的制造方法，其中，所述在所述多晶硅材料层上沉积形成刻蚀阻挡材料层，包括以下步骤：
    在所述多晶硅材料层上沉积形成预制刻蚀阻挡材料层；
    蚀刻所述预制刻蚀阻挡材料层形成所述刻蚀阻挡材料层，所述刻蚀阻挡材料层包括第一刻蚀阻挡材料层及与所述第一刻蚀阻挡材料层连接的第二刻蚀 阻挡材料层，所述第一刻蚀阻挡材料层对应所述有源层设置，所述第一刻蚀阻挡材料层的厚度大于所述第二刻蚀阻挡材料层的厚度。
  5. 如权利要求4所述的制造方法，其中，所述第一刻蚀阻挡材料层的厚度与所述预制刻蚀阻挡材料层的厚度相同。
  6. 如权利要求1所述的制造方法，其中，所述在所述源漏极层上形成通孔，进而形成源极及漏极，所述通孔对应有源层设置，所述源极及所述漏极均与有源层电性连接后，所述制造方法还包括步骤：在所述源极及所述漏极上形成有机发光层。
  7. 如权利要求6所述的制造方法，其中，所述在所述源极及所述漏极上形成有机发光层，具体包括以下步骤：
    在所述源极及所述漏极上沉积形成钝化层；
    在所述钝化层上形成阳极，所述阳极与所述漏极连接；
    在所述钝化层上形成像素定义层，所述像素定义层覆盖所述阳极，所述有机发光层包括所述钝化层、所述阳极及所述像素定义层。
  8. 如权利要求1所述的制造方法，其中，所述在基底上形成栅极层，包括以下步骤：
    在衬底上形成阻挡层；
    在所述阻挡层上形成缓冲层；
    在所述缓冲层上形成所述栅极层，所述衬底、所述阻挡层及所述缓冲层依次层叠形成所述基底。
  9. 一种阵列基板，其中，所述阵列基板包括基底、栅极层、栅极绝缘层、由多晶硅材料制成的有源层、刻蚀阻挡层、源极及漏极，所述栅极层设于所述基底上，所述栅极绝缘层覆盖所述栅极层及所述基底，所述有源层设于所述栅极绝缘层上，所述刻蚀阻挡层覆盖所述有源层，所述源极及所述漏极设于所述刻蚀阻挡层上，所述源极与所述漏极均与所述有源层电性连接。
  10. 如权利要求9所述的阵列基板，其中，所述有源层包括沟道区域、第一非沟道区域及第二非沟道区域，所述沟道区域连接于第一所述非沟道区域及所述第二非沟道区域之间，所述沟道区域对应所述通孔设置，所述有源层位于所述第一非沟道区域且远离所述沟道区域的端面与所述源极电性连接，所述有源层 位于所述第二非沟道区域且远离所述沟道区域的端面与所述漏极电性连接。
  11. 如权利要求9所述的阵列基板，其中，所述栅极层包括第一栅极及与所述第一栅极间隔设置的第二栅极，所述第一栅极对应所述有源层设置，所述第二栅极与所述漏极电性连接。
  12. 如权利要求11所述的阵列基板，其中，所述第二栅极远离所述基底的顶面与所述漏极接触。
  13. 如权利要求9所述的阵列基板，其中，所述阵列基板还包括还形成于所述源极及所述漏极上的有机发光层。
  14. 如权利要求9所述的阵列基板，其中，所述基底包括衬底、阻挡层及缓冲层，所述阻挡层形成于所述衬底上，所述缓冲层形成于所述阻挡层上。
  15. 如权利要求14所述的阵列基板，其中，所述衬底由柔性材料制成。
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