WO2018014248A1 - 薄膜晶体管制造方法、tft阵列基板及柔性显示屏 - Google Patents

薄膜晶体管制造方法、tft阵列基板及柔性显示屏 Download PDF

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WO2018014248A1
WO2018014248A1 PCT/CN2016/090638 CN2016090638W WO2018014248A1 WO 2018014248 A1 WO2018014248 A1 WO 2018014248A1 CN 2016090638 W CN2016090638 W CN 2016090638W WO 2018014248 A1 WO2018014248 A1 WO 2018014248A1
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layer
gate
insulating layer
gate insulating
flexible substrate
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PCT/CN2016/090638
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English (en)
French (fr)
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赵继刚
袁泽
余晓军
魏鹏
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深圳市柔宇科技有限公司
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Priority to CN201680015887.9A priority Critical patent/CN107454979B/zh
Priority to PCT/CN2016/090638 priority patent/WO2018014248A1/zh
Publication of WO2018014248A1 publication Critical patent/WO2018014248A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Definitions

  • the present invention relates to the field of manufacturing thin film transistors, and more particularly to a method for fabricating a thin film transistor, a TFT array substrate, and a flexible display.
  • TFT thin-film transistors
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • the gate insulating layer is usually made of an inorganic material, such as SiNx or SiOx. Chemical vapor deposition is formed.
  • the insulating material is usually made of an inorganic material, the mechanical properties and properties of the gate insulating layer are easily broken and cracked under stress, thereby affecting the underlying layer substrate and other layer structures.
  • Embodiments of the present invention provide a method for fabricating a thin film transistor and an array substrate for solving the technical problem that a climbing structure having a height difference of a gate insulating layer is crushed to affect other layer structures when subjected to stress.
  • the invention provides a method for manufacturing a thin film transistor, the method comprising:
  • planarization layer Forming a gate insulating layer, an active layer, and a planarization layer on the gate and the flexible substrate, wherein the planarization is formed on the gate insulating layer and on both sides of the active layer, wherein The planarization layer and the gate insulating layer have the same thickness relative to the surface of the flexible substrate;
  • the TFT array substrate of the present application includes a flexible substrate, a gate electrode stacked on the surface of the flexible substrate, a gate insulating layer covering the gate electrode, an active layer stacked on the gate insulating layer, and a flat layer, a source, and a drain on a surface of the flexible substrate and on opposite sides of the gate insulating layer, the flat layer is connected to the gate insulating layer, and the source and the drain are both formed in the On the active layer and the planar layer; the source and the drain are spaced apart from each other.
  • the flexible display screen of the present application includes the array substrate, and a display module such as an organic light emitting film layer, an encapsulating layer, a touch substrate, and an optical film substrate. .
  • a flat layer is formed on both sides of the gate insulating layer to improve the flatness of the source and the drain, and to reduce the degree of stress of the gate insulating layer.
  • FIG. 1 is a view showing a step of manufacturing a thin film transistor according to a first embodiment of the present invention.
  • FIG. 2 to 8 are schematic cross-sectional views showing respective manufacturing flows of the method of manufacturing the thin film transistor shown in Fig. 1.
  • FIG. 9 is a schematic structural view of a thin film transistor according to the present invention.
  • Fig. 10 is a view showing the steps of a method of manufacturing a thin film transistor of a second embodiment of the present invention.
  • 11 to 14 are schematic cross-sectional views showing a manufacturing process different from the first embodiment of the thin film transistor manufacturing method of the second embodiment.
  • the invention provides a thin film transistor, a TFT array substrate and a flexible display screen, which can be used in a liquid crystal display or an organic display.
  • the flexible display screen according to the embodiment of the present invention is used for, but not limited to, a mobile phone, a tablet computer, a palmtop computer, a personal digital assistant (PDA), or an e-reader.
  • PDA personal digital assistant
  • the invention provides a method for manufacturing a thin film transistor, the method comprising:
  • planarization layer Forming a gate insulating layer, an active layer, and a planarization layer on the gate and the flexible substrate, wherein the planarization is formed on the gate insulating layer and on both sides of the active layer, wherein The planarization layer and the gate insulating layer have the same thickness relative to the surface of the flexible substrate;
  • a metal layer is deposited on the active layer and the planarization layer, and the metal layer is patterned to form a source and a drain.
  • Step S1 A glass substrate 30 is provided, and a flexible substrate 10 is laid on the surface of the glass substrate 30.
  • the flexible substrate 10 includes the substrate itself (the material may be an organic polymer) and a barrier layer or a buffer layer on the substrate.
  • the flexible substrate 10 in this embodiment may be made of polyimide or polyethylene naphthalate.
  • the flexible substrate 10 and the glass substrate 30 are of a separable structure.
  • step S2 a gate electrode 12 is formed on the surface of the flexible substrate 10.
  • the gate is coated with a metal material on the surface of the flexible substrate 10 and formed by a patterning process.
  • Step S3 forming a gate insulating layer active layer and a planarization layer on the gate electrode and the flexible substrate.
  • the planarization is formed on the gate insulating layer and on both sides of the active layer, wherein a surface of the planarization layer facing away from the flexible substrate is flat with a surface of the gate insulating layer facing away from the flexible substrate Qi.
  • an insulating layer 101 covering the gate electrode 12 and a semiconductor layer 102 stacked on the insulating layer 101 are formed on the surface of the gate electrode 12 and the flexible substrate 10; wherein the insulating layer of the embodiment
  • the 101 is made of an inorganic material, so it is a non-planar structure. Patterning the insulating layer 101 and the semiconductor layer 102 such that the insulating layer 101 forms the gate insulating layer 14, forming the semiconductor layer 102 to form the active layer 16, and exposing the location of the flexible substrate A first surface and a second surface (not labeled) on opposite sides of the gate insulating layer.
  • step S3 specifically includes: step S31, forming a photomask on the semiconductor layer 101;
  • Step S32 patterning the photomask to remove both sides of the photomask to form a residual photomask, the remaining photomask covering the gate and exposing the semiconductor layer at positions on both sides of the gate;
  • Step S33 patterning the exposed semiconductor layer portion and the insulating layer covered by the semiconductor layer to form the gate insulating layer 14 and the active layer 16;
  • step S34 the remaining photomask is removed.
  • the portion of the semiconductor layer that is patterned to be exposed and the insulating layer that is covered by the semiconductor layer are formed by using the same mask, etching, development, and the like to form the gate insulating layer 14 and the active layer 16 at a time, and the active layer 16 Located above the gate insulating layer 14 and projected onto the gate insulating layer 14.
  • the gate insulating layer 14 and the active layer 16 are simultaneously formed, which saves a mask process.
  • the material of the semiconductor layer is one or more of indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (InZnO) or zinc tin oxide (ZnSnO); or low temperature polysilicon material or Polysilicon material.
  • the gate insulating layer 14 is formed using one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiNxOy) or a mixture thereof.
  • Step S3 forming a gate insulating layer, an active layer, and a planarization layer on the gate and the flexible substrate further includes:
  • the organic layer is patterned to form a planarization layer, and the active layer is exposed.
  • an organic layer is formed on the first surface, the second surface, and the gate insulating layer 14 of the flexible substrate 10 on opposite sides of the gate insulating layer 14 , and then removed by patterning.
  • the organic layer of a surface and a second surface portion constitutes the planarization layer 18.
  • the planarization layer 18 is located on opposite sides of the gate insulating layer 14 and is in contact with the gate insulating layer 14 to stabilize the gate insulating layer 14 and improve the gate insulating layer 14 to be bent. The intensity of time.
  • Step S4 depositing a metal layer on the active layer and the planarization layer, and patterning the metal layer to form a source and a drain.
  • a metal layer 103 is formed on the active layer 16 and the planarization layer 18 .
  • the metal layer 103 is patterned to be formed on both sides of the active layer 16 .
  • the active layer 16 and the planarization layer 18 carry connected and spaced source and drain electrodes 19 and 20 .
  • the patterned metal layer is formed to be disposed on both sides of the active layer, and the spaced apart source and drain contacts with the active layer and the planar layer include: a photoresist layer is disposed on the layer (not shown);
  • the remaining photoresist layer is peeled off to form a source 19 and a drain 20 separated by a gap 21.
  • the material of the metal layer 103 is selected from one of copper, tungsten, chromium, aluminum, molybdenum, niobium and combinations thereof.
  • the photoresist layer is finally removed.
  • step S5 removing the glass substrate 30.
  • the glass substrate 30 serves as a support for the flexible substrate 10 so that the flexible substrate 10 has the most sufficient load-bearing strength to form other layer structures of the thin film transistor on the flexible substrate 11.
  • the thin film transistor manufacturing method includes:
  • step S11 a glass substrate 30 is provided, and a flexible substrate 10 is laid on the surface of the glass substrate 30.
  • step S12 a gate electrode 11 is formed on the surface of the flexible substrate 10.
  • Step S13 forming an organic layer on the gate electrode and the flexible substrate; patterning the organic layer to form the planarization layer, exposing the gate electrode and a third surface of the flexible substrate, the third The surface is located between the two sides of the gate and the planarization layer.
  • an organic layer 105 is formed on the surface of the flexible substrate 10 , and the organic layer 105 is formed by a patterning process to be spaced apart from the gate 12 and located on opposite sides of the gate 12 .
  • Layer 18 Exposing the gate and the third surface of the flexible substrate, the third surface being located between the two sides of the gate and the planarization layer.
  • step S14 sequentially forming an insulating layer and a semiconductor layer on the third surface of the flexible substrate and the gate;
  • the remaining photomask is removed.
  • An insulating layer 101 and a semiconductor layer 102 laminated on the insulating layer 10 are formed on the gate electrode 12 and the third surface and the planarization layer 18, and the insulating layer 101 is formed by the same patterning process.
  • the gate insulating layer 14 of the gate electrode 12 is covered such that the semiconductor layer 102 forms the active layer 16 on the gate insulating layer 14.
  • step S15 forming a metal layer 103 on the active layer 16 and the planarization layer 18, patterning the metal layer 103 to form the active layer 16 on both sides, by the active
  • the layer 16 and the planarization layer 18 carry connected and spaced source and drain electrodes 19, 20.
  • Step S16 removing the glass substrate 30.
  • the thin film transistor of the present invention adopts a flat layer of organic material formed on opposite sides of the gate insulating layer 14.
  • the source 19 and the drain 20 are formed on the planarization layer 18 and the active layer 16, and the source 19 is enhanced.
  • the stability of the drain 20 is prevented from being affected by the fragile gate insulating layer 14.
  • FIG. 9 it can be understood as a partial structural diagram of a TFT array substrate.
  • the present invention provides a TFT array substrate including a flexible substrate 10 , a gate electrode 12 stacked on the surface of the flexible substrate 10 , and a gate 12 covering the gate electrode 12 .
  • a gate insulating layer 14 an active layer 16 stacked on the gate insulating layer 14 , a planarization layer 18 and a source disposed on opposite sides of the gate insulating layer 14 on the surface of the flexible substrate 10 19.
  • a drain 20; a channel 21 is disposed between the source 19 and the drain 20.
  • the channel 21 is projected onto the gate 12.
  • the source 19 and the drain 20 are both formed on the active layer 16 and the planarization layer 18 . Specifically, the source 19 and the drain 20 are respectively connected to the active layer 16 and are located on the planarization layer 18 on both sides of the active layer 16 .
  • the gate insulating layer 14 forms the surface of the flexible substrate 10 and the gate electrode 12 and covers the gate electrode 12.
  • the active layer 16 is on the gate insulating layer 14 and parallel to the surface of the flexible substrate 10, the active layer 16 is projected on the gate insulating layer 14, and the active layer 16 is The orthographic projection is larger than the gate 12.
  • the planarization layer 18 is formed on the surface of the flexible substrate 10 and is connected to the three-level insulating layer on opposite sides of the gate insulating layer 14. The height of the planarization layer 18 is equal to or lower than the height of the gate insulating layer 14.
  • the active layer 16 has a height greater than or equal to the planarization layer 18.
  • the source 19 is partially on the active layer 16 and the other part is on the planarization layer 18; the drain 20 is partially on the active layer 16 and the source 19 passes through the channel 21 Another portion is located on the planarization layer 18. Specifically, another portion of the source 19 is formed on the planarization layer 18 on one side of the active layer 16; and another portion of the drain 20 is formed on the other side of the active layer 16 18, the planarization layer 18 is highly equivalent to the active layer 16, and the source 19 and the drain 20 are respectively connected to the active layer 16 and located at The planarization layer 18 on both sides of the active layer 16 improves the flatness of the source 19 and the drain 20, reduces the degree of bending of the source 19 and the drain 20, and enhances the source 19 and the drain 20. Stability.
  • the invention also provides a flexible display screen (not shown), which comprises the TFT array substrate, the organic light emitting film layer, the encapsulation layer and the display module formed by stacking the touch film optical film layer lamps. .

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Abstract

一种薄膜晶体管制造方法及TFT阵列基板，TFT阵列基板包括柔性基板(10)、叠设于柔性基板(10)表面的栅极(12)、覆盖所述栅极(12)的栅极绝缘层(14)、叠设于所述栅极绝缘层(14)上的有源层(16)、设于柔性基板(10)表面的且位于所述栅极绝缘层(14)相对两侧的平坦层(18)、源极(19)及漏极(20)，所述平坦层(18)与所述栅极绝缘层(14)连接，所述源极(19)与漏极(20)均形成于所述有源层(16)及所述平坦层(18)上；所述源极(19)与漏极(20)之间间隔设置。还提供一种柔性显示屏。

Description

薄膜晶体管制造方法、TFT阵列基板及柔性显示屏 技术领域
本发明涉及薄膜晶体管的制造领域，尤其涉及一种薄膜晶体管制造方法、TFT阵列基板及柔性显示屏。
背景技术
目前薄膜晶体管(Thin-film transistors，TFT)阵列基板被广泛应用于不同类型的显示装置中，如柔性显示屏、LCD或OLED显示屏。薄膜晶体管中高质量的栅极绝缘层是实现TFT阵列基板的好的电学稳定性、较小的泄露电流等重要参数的关键，因此栅极绝缘层通常选择无机材料制成，比如使用SiNx或者SiOx通过化学气相沉淀形成。当TFT阵列基板在应用于柔性显示屏，随着柔性基板的弯曲，其上的TFT膜层结构会对应地受到拉应力与压应力，结构中如有多层膜的搭接，如源漏极、栅极绝缘层等存在高度差，造成的爬坡结构，则应力情况更为复杂，常出现较大的局部应力。由于构成栅极绝缘层通常采用无机材料，其力学性质与性能导致在承受应力的情况下，容易破碎而产生开裂现象，因此影响阵列基板底层及其它层结构。
发明内容
本发明实施例提供一种薄膜晶体管制造方法及阵列基板，用以解决栅极绝缘层存在高度差的爬坡结构在受到应力时产生破碎影响其它层结构的技术问题。
本发明提供一种薄膜晶体管制造方法，所述方法包括：
在柔性基板上形成栅极；
在所述栅极及所述柔性基板上形成栅极绝缘层、有源层和平坦化层，其中所述平坦化形成于所述栅极绝缘层、和有源层两侧，其中，所述平坦化层与所述栅极绝缘层相对柔性基板表面的厚度相同；以及
在所述有源层及平坦化层上沉积金属层，图案化所述金属层以形成源极及 漏极。
本申请所述的TFT阵列基板包括柔性基板、叠设于柔性基板表面的栅极、覆盖所述栅极的栅极绝缘层、叠设于所述栅极绝缘层上的有源层、设于柔性基板表面的且位于所述栅极绝缘层相对两侧的平坦层、源极及漏极，所述平坦层与所述栅极绝缘层连接，所述源极与漏极均形成于所述有源层及所述平坦层上；所述源极与漏极之间间隔设置。
本申请所述的柔性显示屏包括所述的阵列基板，以及有机发光膜层、封装层、触控基板、光学膜基板等显示模组。。
本发明所述的薄膜晶体管在制造过程中，在栅极绝缘层两侧形成平坦层以提高源极与漏极平整度，减小栅极绝缘层受应力程度。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明第一实施例提供的薄膜晶体管制步骤图。
图2至图8是图1所示的薄膜晶体管制造方法的各个制造流程的截面示意图。
图9是本发明所述的薄膜晶体管结构示意图。
图10是本发明第二实施例的薄膜晶体管制造方法步骤图。
图11-图14是第二实施例的薄膜晶体管制造方法的不同于第一实施例的制造流程的截面示意图。
具体实施方式
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述。
本发明提供了薄膜晶体管、TFT阵列基板及柔性显示屏，所述薄膜晶体管可以用于液晶显示屏或者有机显示屏中。本发明实施例涉及的柔性显示屏用于但不限于手机、平板电脑、掌上电脑、个人数字助理(Personal Digital Assistant，PDA)或电子阅读器等，本发明实施例对此不作具体限定。
本发明提供一种薄膜晶体管制造方法，所述方法包括：
在柔性基板上形成栅极；
在所述栅极及所述柔性基板上形成栅极绝缘层、有源层和平坦化层，其中所述平坦化形成于所述栅极绝缘层、和有源层两侧，其中，所述平坦化层与所述栅极绝缘层相对柔性基板表面的厚度相同；以及
在所述有源层及平坦化层上沉积金属层，图案化所述金属层以形成源极及漏极。
具体实施例详细步骤结合参阅图1及图2-7进行说明：
步骤S1：提供一玻璃基板30，并在所述玻璃基板30表面铺设柔性基板10。所述柔性基板10包括基板本身(材料可为有机聚合物)以及基板上的阻隔层或缓冲层。本实施例中所述柔性基板10可以为聚酰亚胺或者聚萘二甲酸乙二醇酯制成。所述柔性基板10与玻璃基板30为可分离式结构。
如图3，步骤S2：在所述柔性基板10的表面上形成栅极12。所述栅极为金属材料涂于柔性基板10的表面上再通过图案化工艺形成。
步骤S3：在所述栅极及所述柔性基板上形成栅极绝缘层有源层和平坦化层。其中所述平坦化形成于所述栅极绝缘层、和有源层两侧，其中，所述平坦化层背向所述柔性基板的表面与所述栅极绝缘层背向柔性基板的表面平齐。
具体为如图4，在所述栅极12及所述柔性基板10表面形成覆盖所述栅极12的绝缘层101及层叠于绝缘层101上的半导体层102；其中，本实施例的绝缘层101采用无机材料制成，所以为非平坦化结构。图案化所述绝缘层101和半导体层102，使所述绝缘层101形成所述栅极绝缘层14，使所述半导体层102形成所述有源层16，并且露出所述柔性基板的位于所述栅极绝缘层相对两侧的第一表面和第二表面(图未标)。
具体一并参阅图5，步骤S3具体包括：步骤S31，在所述半导体层101上形成一光掩模；
步骤S32，图案化所述光掩模，去除光掩模两侧部分，形成剩余光掩模，所述剩余光掩模覆盖所述栅极并露出所述栅极两侧位置的半导体层；
步骤S33，图案化露出的半导体层部分及被所述半导体层遮盖的绝缘层，以形成所述的栅极绝缘层14及有源层16；
步骤S34，去除剩余光掩模。本步骤中图案化露出的半导体层部分及被所述半导体层遮盖的绝缘层，使用同一道光罩、蚀刻、显影等构图方式一次形成栅极绝缘层14及有源层16，并且有源层16位于栅极绝缘层14上方并正投影于栅极绝缘层14。与现有技术相比，同时形成栅极绝缘层14及有源层16，节省了一道光罩工艺。其中，所述半导体层的材料为氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟锌(InZnO)或氧化锌锡(ZnSnO)中的一种或多种；或者为低温多晶硅材料或者多晶硅材料。所述栅极绝缘层14采用氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的一种制成或者多种混合形成。
步骤S3在所述栅极及所述柔性基板上形成栅极绝缘层、有源层和平坦化层”还包括：
在所述柔性基板的第一表面、第二表面及有源层上形成有机层；
图案化所述有机层形成平坦化层，并露出所述有源层。
具体参阅图6，在所述栅极绝缘层14相对两侧的所述柔性基板10第一表面、第二表面及所述栅极绝缘层14上涂布形成有机层，再通过图案化去除第一表面、第二表面部分所述有机层构成所述平坦化层18。所述平坦化层18位于所述栅极绝缘层14相对两侧并与所述栅极绝缘层14接触，以稳固所述栅极绝缘层14，提高所述栅极绝缘层14受到弯折外时的强度。
步骤S4：在所述有源层及平坦化层上沉积金属层，图案化所述金属层以形成源极及漏极。
具体的参阅图7，在所述有源层16及平坦化层18上形成金属层103，参阅图8，图案化所述金属层103以形成设置在所述有源层16两侧，由所述有源层16及所述平坦化层18承载连接的且间隔设置的源极19及漏极20。
其中，所述图案化所述金属层以形成设置在所述有源层两侧，与所述有源层及所述平坦层接触的且间隔设置的源极及漏极包括：在所述金属层上设置光阻层(图未示)；
图案化所述光阻层，以移除覆盖所述有源层中部的部分光阻层以及覆盖在平坦层远离栅极绝缘层的部分的光阻层，保留覆盖平坦层邻近所述栅极绝缘层的部分的光阻层以及覆盖所述有源层邻近所述平坦层的部分的光阻层；
移除未覆盖有所述光阻层的所述金属层；以及
剥离剩余的光阻层，形成通过间隙21分隔的源极19及漏极20。其中，金属层103材质选自铜、钨、铬、铝、钼、钽及其组合的其中之一。最后移除所述光阻层。
参阅图9，步骤S5：去除所述玻璃基板30。所述玻璃基板30作为柔性基板10的支撑体使柔性基板10具有最够的承载强度，以便在柔性基板11上形成薄膜晶体管的其它层结构。
参阅图10，本发明第二实施例中，与第一实施例不同之处在于平坦化层18的形成步骤的顺序。所述薄膜晶体管制造方法包括：
参阅图2，步骤S11：提供一玻璃基板30，并在所述玻璃基板30表面铺设柔性基板10。
参阅图3，步骤S12：在所述柔性基板10的表面上形成栅极11。
步骤S13：在所述栅极及所述柔性基板上形成有机层；图案化所述有机层形成所述平坦化层，露出所述栅极及所述柔性基板的第三表面，所述第三表面位于所述栅极两侧与所述平坦化层之间位置。
具体的参阅图11与图12，在所述柔性基板10的表面形成有机层105，通过图案化工艺使有机层105形成与所述栅极12间隔且位于所述栅极12相对两侧的平坦化层18。露出所述栅极及所述柔性基板的第三表面，所述第三表面位于所述栅极两侧与所述平坦化层之间位置。
参阅图13，步骤S14：在所述柔性基板的第三表面及所述栅极上依次沉积形成绝缘层和半导体层；
在所述半导体层上形成一光掩模；
图案化所述光掩模，去除光掩模两侧部分，形成剩余光掩模，所述剩余光掩模覆盖所述栅极并露出位于所述第三表面上的半导体层；
图案化露出的半导体层部分及被所述半导体层遮盖的绝缘层，以形成所述的栅极绝缘层及有源层；其中所述栅极绝缘层及有源层位于所述栅极两侧与所述平坦化层之间位置；以及
去除剩余光掩模。
在所述栅极12及所述第三表面、平坦化层18上形成绝缘层101及层叠于绝缘层10上的半导体层102，通过同一道图案化工艺使所述绝缘层101形成 覆盖所述栅极12的栅极绝缘层14，使半导体层102形成位于栅极绝缘层14上的有源层16。
参阅图14，步骤S15：在所述有源层16及平坦化层18上形成金属层103，图案化所述金属层103以形成设置在所述有源层16两侧、由所述有源层16及所述平坦化层18承载连接的且间隔设置的源极19及漏极20。
步骤S16：去除所述玻璃基板30。
本发明所述的薄膜晶体管采用在栅极绝缘层14相对两侧形成有机材料的平坦层，源极19及漏极20形成于平坦化层18及有源层16上，增强了源极19及漏极20的稳固性，防止被易破碎的栅极绝缘层14影响。
请参阅图9，可以理解为TFT阵列基板的部分结构示意图，本发明提供一种TFT阵列基板，其包括柔性基板10、叠设于柔性基板10表面的栅极12、覆盖所述栅极12的栅极绝缘层14、叠设于所述栅极绝缘层14上的有源层16、设于柔性基板10表面的且位于所述栅极绝缘层14相对两侧的平坦化层18、源极19、漏极20；所述源极19与漏极20之间设有沟道21。所述沟道21正投影于所述栅极12。所述源极19与漏极20均形成于所述有源层16及所述平坦化层18上。具体为，所述源极19与漏极20分别与有源层16的连接且位于所述有源层16两侧的所述平坦化层18上。
具体的，栅极绝缘层14形成柔性基板10的表面及栅极12上并覆盖所述栅极12。于所述有源层16位于所述栅极绝缘层14上并平行于所述柔性基板10的表面，所述有源层16正投影于所述栅极绝缘层14上，且有源层16的正投影大于所述栅极12。所述平坦化层18形成于所述柔性基板10的表面并位于所述栅极绝缘层14相对两侧与三级绝缘层连接。所述平坦化层18的高度与所述栅极绝缘层14高度相当或者低于栅极绝缘层14高度。所述有源层16高度大于等于所述平坦化层18。所述源极19部分位于所述有源层16上，另一部分位于所述平坦化层18上；所述漏极20部分位于有源层16上与所述源极19通过所述沟道21间隔，另一部分位于所述平坦化层18上。具体为所述源极19另一部分形成于所述有源层16一侧的所述平坦化层18上；漏极20另一部分形成于所述有源层16另一侧的所述平坦化层18上，平坦化层18与所述有源层16高度相当，所述源极19与漏极20分别与有源层16的连接且位于所 述有源层16两侧的所述平坦化层18上，提高源极19与漏极20平整度，减少源极19及漏极20结构的弯曲程度，增强了源极19及漏极20的稳固性。
本发明还提供一种柔性显示屏(图未示)，所述柔性显示屏包括以上所述的TFT阵列基板、有机发光膜层、封装层、触控基板光学膜层灯层叠形成的显示模组。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (12)

  1. 一种薄膜晶体管制造方法，其特征在于，所述方法包括：
    在柔性基板上形成栅极；
    在所述栅极及所述柔性基板上形成栅极绝缘层、有源层和平坦化层，其中所述平坦化形成于所述栅极绝缘层和有源层两侧；以及
    在所述有源层及平坦化层上沉积金属层，图案化所述金属层以形成源极及漏极。
  2. 如权利要求1所述的薄膜晶体管制造方法，其特征在于，所述在所述栅极及所述柔性基板上形成栅极绝缘层、有源层和平坦化层的步骤包括：
    在所述栅极及所述柔性基板上形成覆盖所述栅极的绝缘层和层叠于所述绝缘层上的半导体层；
    图案化所述绝缘层和半导体层，使所述绝缘层形成所述栅极绝缘层，使所述半导体层形成所述有源层，并且露出所述柔性基板的位于所述栅极绝缘层相对两侧的第一表面和第二表面。
  3. 如权利要求2所述的薄膜晶体管制造方法，其特征在于，所述在所述栅极及所述柔性基板上形成栅极绝缘层、有源层和平坦化层的步骤包括：
    在所述柔性基板的第一表面、第二表面及有源层上形成有机层；
    图案化所述有机层形成平坦化层，并露出所述有源层。
  4. 如权利要求2所述的薄膜晶体管制造方法，其特征在于，步骤图案化所述绝缘层和半导体层，使所述绝缘层形成所述栅极绝缘层，使所述半导体层形成所述有源层包括：
    在所述半导体层上形成一光掩模；
    图案化所述光掩模，去除光掩模两侧部分，形成剩余光掩模，所述剩余光掩模覆盖所述栅极并露出所述栅极两侧位置的半导体层；
    图案化露出的半导体层部分及被所述半导体层遮盖的绝缘层，以形成所述的栅极绝缘层及有源层；以及
    去除剩余光掩模。
  5. 如权利要求1所述的薄膜晶体管制造方法，其特征在于，所述在所述 栅极及所述柔性基板上形成栅极绝缘层、有源层和平坦化层的步骤包括：
    在所述栅极及所述柔性基板上形成有机层；
    图案化所述有机层形成所述平坦化层，露出所述栅极及所述柔性基板的第三表面，所述第三表面位于所述栅极两侧与所述平坦化层之间位置。
  6. 如权利要求5所述的薄膜晶体管制造方法，其特征在于，所述在所述栅极及所述柔性基板上形成栅极绝缘层、有源层和平坦化层的步骤的包括：在所述柔性基板的第三表面及所述栅极上依次沉积形成绝缘层和半导体层；
    在所述半导体层上形成一光掩模；
    图案化所述光掩模，去除光掩模两侧部分，形成剩余光掩模，所述剩余光掩模覆盖所述栅极并露出位于所述第三表面上的半导体层；
    图案化露出的半导体层部分及被所述半导体层遮盖的绝缘层，以形成所述的栅极绝缘层及有源层；其中所述栅极绝缘层及有源层位于所述栅极两侧与所述平坦化层之间位置；以及
    去除剩余光掩模。
  7. 如权利要求1所述的薄膜晶体管制造方法，其特征在于，所述平坦化层背向所述柔性基板的表面与所述栅极绝缘层背向柔性基板的表面平齐。
  8. 如权利要求1或5所述的薄膜晶体管制造方法，其特征在于，在所述有源层及平坦层上形成金属层，图案化所述金属层以形成设置在所述有源层两侧，与所述有源层及所述平坦层接触的且间隔设置的源极及漏极的步骤包括：
    在所述金属层上设置光阻层；
    图案化所述光阻层，以移除覆盖所述有源层中部的部分光阻层以及覆盖在平坦层远离栅极绝缘层的部分的光阻层，保留覆盖平坦层邻近所述栅极绝缘层的部分的光阻层以及覆盖所述有源层邻近所述平坦层的部分的光阻层；
    移除未覆盖有所述光阻层的所述金属层；以及
    剥离剩余的光阻层。
  9. 如权利要求1所述的薄膜晶体管制造方法，其特征在于，所述栅极绝缘层包括氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的任意一种或多种。
  10. 一种TFT阵列基板，其特征在于，所述阵列基板包括柔性基板、叠设于柔性基板表面的栅极、覆盖所述栅极的栅极绝缘层、叠设于所述栅极绝缘层 上的有源层、设于柔性基板表面的且位于所述栅极绝缘层相对两侧的平坦层、源极及漏极，所述平坦层与所述栅极绝缘层连接，所述源极与漏极均形成于所述有源层及所述平坦层上；所述源极与漏极之间间隔设置。
  11. 如权利要求10所述的TFT阵列基板，其特征在于，所述栅极绝缘层与所述平坦层远离所述柔性基板表面平齐。
  12. 一种柔性显示屏，其特征在于，所述柔性显示屏包括权利要求10-11任一项所述的阵列基板。
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