WO2019216161A9 - Module semi-conducteur de puissance, son procédé de production et convertisseur de puissance électrique - Google Patents

Module semi-conducteur de puissance, son procédé de production et convertisseur de puissance électrique Download PDF

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Publication number
WO2019216161A9
WO2019216161A9 PCT/JP2019/016768 JP2019016768W WO2019216161A9 WO 2019216161 A9 WO2019216161 A9 WO 2019216161A9 JP 2019016768 W JP2019016768 W JP 2019016768W WO 2019216161 A9 WO2019216161 A9 WO 2019216161A9
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WIPO (PCT)
Prior art keywords
lead terminal
power semiconductor
conductive adhesive
adhesive portion
semiconductor module
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PCT/JP2019/016768
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English (en)
Japanese (ja)
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WO2019216161A1 (fr
Inventor
悠矢 清水
創一 坂元
真紀 長谷川
Original Assignee
三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to DE112019002333.0T priority Critical patent/DE112019002333T5/de
Priority to JP2020518228A priority patent/JP6952889B2/ja
Priority to CN201980029908.6A priority patent/CN112074954B/zh
Publication of WO2019216161A1 publication Critical patent/WO2019216161A1/fr
Publication of WO2019216161A9 publication Critical patent/WO2019216161A9/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49589—Capacitor integral with or on the leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Definitions

  • the present invention relates to a power semiconductor module, a manufacturing method thereof, and a power conversion device.
  • Patent Document 1 describes a lead frame, a power chip arranged on the lead frame, and an IC arranged on the lead frame and driving the power chip in the transfer mold package.
  • a semiconductor device including a chip and a bootstrap capacitor connected to an IC chip is disclosed. The bootstrap capacitor is bonded onto the lead frame via an insulating adhesive.
  • An object of the present invention is to provide a power semiconductor module having high reliability.
  • An object of the present invention is to provide a power conversion device having high reliability.
  • the power semiconductor module of the first aspect of the present invention includes a plurality of lead terminals, a chip capacitor, and an electronic element.
  • the plurality of lead terminals include a first lead terminal and a second lead terminal that is separated from the first lead terminal.
  • the chip capacitor includes a first electrode and a second electrode.
  • the electronic element is a first conductive adhesive portion and is bonded to one of a plurality of lead terminals.
  • the first conductive adhesive portion contains the conductive filler at the first content.
  • the first electrode and the second electrode of the chip capacitor are bonded to the first lead terminal and the second lead terminal by a second conductive adhesive portion, respectively.
  • the second conductive adhesive portion contains the conductive filler at a second content higher than the first content.
  • the power semiconductor module of the second aspect of the present invention includes a plurality of lead terminals, a chip capacitor, and an electronic element.
  • the plurality of lead terminals include a first lead terminal and a second lead terminal that is separated from the first lead terminal.
  • the chip capacitor includes a first electrode and a second electrode.
  • the electronic element is a first conductive adhesive portion and is bonded to one of a plurality of lead terminals.
  • the first conductive adhesive portion contains the first conductive filler.
  • the first electrode and the second electrode of the chip capacitor are bonded to the first lead terminal and the second lead terminal by a second conductive adhesive portion, respectively.
  • the second conductive adhesive portion contains a second conductive filler.
  • the second conductive adhesive portion has a lower electrical resistivity than the first conductive adhesive portion.
  • the method for manufacturing a power semiconductor module of the present invention includes joining a power semiconductor chip to at least one of a plurality of lead terminals.
  • the plurality of lead terminals include a first lead terminal and a second lead terminal that is separated from the first lead terminal.
  • the method for manufacturing a power semiconductor module of the present invention includes joining an electronic device to one of a plurality of lead terminals at a first conductive adhesive portion.
  • the first conductive adhesive portion contains the conductive filler at the first content.
  • the method for manufacturing a power semiconductor module of the present invention includes supplying a conductive adhesive to a plurality of first locations of a first lead terminal and a plurality of second locations of a second lead terminal.
  • the first electrode of the chip capacitor is placed on the conductive adhesive on the plurality of first locations, and the second electrode of the chip capacitor is placed on the plurality of second locations. It is provided to be placed on a conductive adhesive.
  • Chip capacitors are of a different type from electronic elements.
  • the conductive adhesive is cured to join the first electrode and the second electrode of the chip capacitor to the first lead terminal and the second lead terminal, respectively. It is provided to form the conductive adhesive portion of 2.
  • the second conductive adhesive portion contains the conductive filler at a second content higher than the first content.
  • the method for manufacturing a power semiconductor module of the present invention includes sealing a power semiconductor chip, a chip capacitor, and an electronic element with a sealing member.
  • the power conversion device of the present invention has the power semiconductor module of the present invention, and outputs a main conversion circuit that converts and outputs the input power and a control signal that controls the main conversion circuit to the main conversion circuit. It is equipped with a control circuit.
  • the second content of the conductive filler in the second conductive adhesive portion is determined by the first conductive adhesive portion. It is higher than the first content of the conductive filler.
  • the second conductive adhesive portion has a lower electrical resistivity than the first conductive adhesive portion. Therefore, it is possible to increase the margin between the electric resistance of the second conductive adhesive portion and the permissible electric resistance generally required for the joint portion of the chip capacitor. Further, even if the stress applied to the second conductive adhesive introduces at least one of partial peeling and cracking into the second conductive adhesive, the electrical resistance of the second conductive adhesive increases. Can be made smaller. The reliability of the electrical connection of the second conductive adhesive can be improved.
  • the power semiconductor module according to the first and second aspects of the present invention has high reliability. According to the method for manufacturing a power semiconductor module of the present invention, a power semiconductor module having high reliability can be manufactured.
  • the power conversion device of the present invention includes a main conversion circuit having the power semiconductor module of the present invention. According to the power converter of the present invention, it has high reliability.
  • FIG. 5 is a schematic partially enlarged plan view of a region II shown in FIG. 1 of the power semiconductor module according to the first embodiment. It is a schematic partial enlarged cross-sectional view of the power semiconductor module which concerns on Embodiment 1 in the cross-sectional line III-III shown in FIG. It is a figure which shows the circuit of the electronic element included in the power semiconductor module which concerns on Embodiment 1.
  • FIG. It is the schematic sectional drawing of the semiconductor device which concerns on Embodiment 1.
  • FIG. It is a figure which shows the flowchart of the manufacturing method of the power semiconductor module which concerns on Embodiment 1.
  • FIG. It is a figure which shows the flowchart of the manufacturing method of the power semiconductor module which concerns on Embodiment 1.
  • FIG. It is a schematic plan view which shows one step of the manufacturing method of the power semiconductor module which concerns on Embodiment 1.
  • FIG. It is a schematic partial enlarged sectional view in sectional line IX-IX of the process shown in FIG. 8 in the manufacturing method of the power semiconductor module of Embodiment 1.
  • FIG. It is a schematic partial enlarged plan view of one step of the manufacturing method of the power semiconductor module which concerns on Embodiment 1.
  • FIG. 5 is a schematic partially enlarged cross-sectional view taken along the cross-sectional line XIII-XIII of the process shown in FIG. 12 in the method for manufacturing a power semiconductor module according to the first embodiment. It is a schematic partial enlarged plan view of one step of the manufacturing method of the power semiconductor module which concerns on the modification of Embodiment 1.
  • FIG. It is a figure which shows the flowchart of the manufacturing method of the semiconductor device which concerns on Embodiment 1.
  • FIG. It is the schematic sectional drawing of the power semiconductor module which concerns on Embodiment 2.
  • FIG. It is the schematic sectional drawing of the semiconductor device which concerns on Embodiment 2.
  • FIG. It is the schematic sectional drawing of the power semiconductor module which concerns on Embodiment 3.
  • FIG. It is a block diagram which shows the structure of the power conversion system which concerns on Embodiment 4.
  • the power semiconductor module 1 of the first embodiment will be described with reference to FIGS. 1 to 4.
  • the power semiconductor module 1 mainly includes a plurality of lead terminals, a power semiconductor chip 20, a chip capacitor 27, an electronic element 25, and a sealing member 40.
  • the power semiconductor module 1 may further include a control semiconductor chip 23.
  • the plurality of lead terminals further include a first lead terminal 11, a second lead terminal 12, a third lead terminal 13, a fourth lead terminal 14, and a fifth lead terminal 15.
  • the first lead terminal 11, the second lead terminal 12, the third lead terminal 13, the fourth lead terminal 14, and the fifth lead terminal 15 are separated from each other.
  • the plurality of lead terminals may include a plurality of pads (for example, a first pad 11a, a second pad 12a, a third pad 14a, and a fourth pad 15a).
  • the first lead terminal 11 may include a first pad 11a, which is a wide portion of the first lead terminal 11.
  • the second lead terminal 12 may include a second pad 12a, which is a wide portion of the second lead terminal 12.
  • the fourth lead terminal 14 may include a third pad 14a, which is a wide portion of the fourth lead terminal 14.
  • the fifth lead terminal 15 may include a fourth pad 15a, which is a wide portion of the fifth lead terminal 15.
  • the fifth lead terminal 15 includes a stepped portion 15b between the fourth pad 15a and the third protruding portion 15c.
  • the stepped portion 15b includes a first end portion connected to the fourth pad 15a and a second end portion opposite to the first end portion. The second end is above the first end.
  • At least a part of the plurality of lead terminals includes a plurality of protrusions protruding from the sealing member 40.
  • the plurality of protrusions are bent.
  • the first lead terminal 11 includes a first protruding portion 11c that protrudes from the sealing member 40.
  • the first protruding portion 11c includes a first protruding portion 11d extending horizontally from the first pad 11a and a second protruding portion 11e extending upward from the first protruding portion 11d.
  • the second lead terminal 12 includes a second protruding portion 12c that protrudes from the sealing member 40.
  • the second protruding portion 12c includes a third protruding portion 12d extending horizontally from the second pad 12a and a fourth protruding portion 12e extending upward from the third protruding portion 12d.
  • the fifth lead terminal 15 includes a third protruding portion 15c that protrudes from the sealing member 40.
  • the third protruding portion 15c includes a fifth protruding portion 15d extending horizontally from the second end portion of the stepped portion 15b, and a sixth protruding portion 15e extending upward from the fifth protruding portion 15d.
  • electronic components power semiconductor chip 20, control semiconductor chip 23, chip capacitor 27, electronic element 25
  • DIP dual in-line package
  • the plurality of lead terminals are formed of a conductive material such as copper.
  • a part of the plurality of lead terminals may be covered with a plating portion 17 such as a silver plating portion.
  • the plated portion 17 may be formed of a material that is less likely to be oxidized than the material that constitutes the plurality of lead terminals.
  • a material that is less likely to be oxidized than a material that constitutes a plurality of lead terminals is a noble metal material such as silver.
  • the plated portion 17 may be formed on the innermost portion of the first lead terminal 11.
  • a plated portion 17 may be formed on the innermost portion of the second lead terminal 12.
  • the plating portion 17 may be formed on a part of the fourth pad 15a of the fifth lead terminal 15.
  • the first lead terminal 11 may include a first through hole 16a.
  • the first through hole 16a is formed outside the chip capacitor 27 (on the side of the first protruding portion 11c).
  • the first through hole 16a may be formed inside the chip capacitor 27 (opposite the first protrusion 11c), or may be formed outside and inside the chip capacitor 27.
  • the second lead terminal 12 may include a second through hole 16b.
  • the second through hole 16b is formed outside the chip capacitor 27 (on the side of the second protruding portion 12c).
  • the second through hole 16b may be formed inside the chip capacitor 27 (opposite the second protrusion 12c), or may be formed outside and inside the chip capacitor 27. Good.
  • the power semiconductor chip 20 may be, for example, a reverse conduction IGBT (RC-IGBT), an insulated gate bipolar transistor (IGBT) including a freewheel diode (FWD), a metal oxide semiconductor field effect transistor (MOSFET), or a diode. Good.
  • the power semiconductor chip 20 has, for example, a rated current of 1 A or more and a rated voltage of 100 V or more.
  • the power semiconductor chip 20 may be made of a semiconductor material such as silicon (Si), silicon carbide (SiC) or gallium nitride (GaN).
  • the power semiconductor module 1 may include one power semiconductor chip 20 or may include a plurality of power semiconductor chips 20. In the present embodiment, the power semiconductor module 1 includes a power semiconductor chip 20 for high voltage and a power semiconductor chip 20 for low voltage. The high-voltage power semiconductor chip 20 is joined to the fourth pad 15a of the fifth lead terminal 15.
  • the power semiconductor chip 20 is bonded to at least one of a plurality of lead terminals (fifth lead terminal 15). At least one of the plurality of lead terminals (fifth lead terminal 15) to which the power semiconductor chip 20 is bonded is a first lead terminal 11, a second lead terminal 12, a third lead terminal 13, and a fourth. It is different from the lead terminal 14 of.
  • the power semiconductor chip 20 is bonded to the fourth pad 15a (particularly, the plating portion 17) of the fifth lead terminal 15 at the solder bonding portion 30.
  • the solder joint portion 30 can efficiently transfer the heat generated by the power semiconductor chip 20 to the fifth lead terminal 15.
  • the power semiconductor chip 20 is electrically connected to a plurality of lead terminals (particularly, the plating portion 17) via a conductive wire 29.
  • the control semiconductor chip 23 is configured to control the power semiconductor chip 20.
  • the control semiconductor chip 23 constitutes a part of a control circuit that controls the power semiconductor chip 20.
  • the control semiconductor chip 23 may be configured to control the gate voltage of the power semiconductor chip 20.
  • the control semiconductor chip 23 may be configured to detect a current flowing through the power semiconductor chip 20.
  • the power semiconductor module 1 is an intelligent power module (IPM) incorporating a power semiconductor chip 20 and a control semiconductor chip 23 configured to control the power semiconductor chip 20.
  • the control semiconductor chip 23 is electrically connected to the power semiconductor chip 20 via the conductive wire 29.
  • the control semiconductor chip 23 is electrically connected to the first lead terminal 11 and the second lead terminal 12 via the conductive wire 29.
  • the power semiconductor module 1 may include one control semiconductor chip 23, or may include a plurality of control semiconductor chips 23.
  • the power semiconductor module 1 controls a high-voltage control semiconductor chip 23 configured to control a high-voltage power semiconductor chip 20 and a low-voltage power semiconductor chip 20. It includes a control semiconductor chip 23 for low voltage, which is configured.
  • the control semiconductor chip 23 is joined to at least one of a plurality of lead terminals (fourth lead terminal 14). At least one of the plurality of lead terminals (fourth lead terminal 14) to which the control semiconductor chip 23 is bonded is a first lead terminal 11, a second lead terminal 12, a third lead terminal 13, and a third lead terminal 13. It is different from the lead terminal 15 of 5.
  • the control semiconductor chip 23 is bonded to the third pad 14a of the fourth lead terminal 14 at the conductive bonding portion 33.
  • the conductive joint portion 33 may be, for example, a solder joint portion or a first conductive adhesive portion 35 described later.
  • the electronic element 25 is an electronic component of a different type from the chip capacitor 27.
  • the electronic element 25 constitutes a part of a control circuit that controls the power semiconductor chip 20.
  • the electronic element 25 may be a passive electronic component.
  • the passive electronic component is, for example, a diode 25a such as a chip diode or a resistor 25b such as a chip resistor.
  • the diode 25a which is an example of a passive electronic component, has, for example, a rated current of less than 1A and a rated voltage of less than 100V.
  • the electronic element 25 is a rectifying semiconductor chip.
  • the rectifying semiconductor chip contains a resistor 25b in addition to the diode 25a.
  • the semiconductor chip for rectification incorporating the resistor 25b and the chip capacitor 27 may form a bootstrap circuit.
  • the electronic element 25 may be a bootstrap diode (BSD).
  • the bootstrap circuit is a circuit that produces a gate drive power supply on the P side using only the gate drive power supply on the N side.
  • the bootstrap circuit is composed of a rectifying semiconductor chip and a capacitor in the circuit of the gate drive unit.
  • the bootstrap circuit is different from the snubber circuit arranged on the output side (drain-source, collector-emitter) of the switching element (for example, the power semiconductor chip 20).
  • the electronic element 25 may be electrically connected to the control semiconductor chip 23 via the conductive wire 29 and the first lead terminal 11.
  • the electronic element 25 may be electrically connected to the third lead terminal 13 (particularly, the plating portion 17) via the conductive wire 29.
  • the electronic element 25 is a first conductive adhesive portion 35 and is joined to one of a plurality of lead terminals. Specifically, the electronic element 25 is bonded to the first lead terminal 11 at the first conductive adhesive portion 35.
  • the first conductive adhesive portion 35 contains the first conductive filler at the first content.
  • the first conductive adhesive portion 35 includes a first resin and a first conductive filler dispersed in the first resin.
  • the first conductive filler may be composed of, for example, one or more conductive materials selected from the group consisting of silver, nickel and copper. In the present specification, the conductive filler also includes conductive particles.
  • the first resin may be, for example, an epoxy resin.
  • the chip capacitor 27 may be, for example, a surface mount type multilayer ceramic capacitor.
  • the chip capacitor 27 constitutes a part of a control circuit that controls the power semiconductor chip 20.
  • the chip capacitor 27 may be a bootstrap capacitor (BSC) that forms part of the bootstrap circuit.
  • BSC bootstrap capacitor
  • the capacity of the chip capacitor 27 is appropriately determined according to the power consumption of the control semiconductor chip 23, the gate capacity of the power semiconductor chip 20, and the charging time and discharging time of the chip capacitor 27.
  • the chip capacitor 27 includes a first electrode 28a and a second electrode 28b.
  • the chip capacitor 27 is the tallest.
  • the first electrode 28a and the second electrode 28b of the chip capacitor 27 are joined to the first lead terminal 11 and the second lead terminal 12 by the second conductive adhesive portion 37, respectively.
  • the second conductive adhesive portion 37 contains a second resin and a second conductive filler dispersed in the second resin.
  • the second conductive filler may be composed of, for example, one or more conductive materials selected from the group consisting of silver, nickel and copper. In the present embodiment, even if the second conductive filler contained in the second conductive adhesive portion 37 is made of the same material as the first conductive filler contained in the first conductive adhesive portion 35. Alternatively, it may be composed of a material different from that of the first conductive filler.
  • the second resin may be, for example, an epoxy resin. The second resin may be made of the same material as the first resin, or may be made of a different material.
  • the second conductive adhesive portion 37 has a lower electrical resistivity than the first conductive adhesive portion 35.
  • the second conductive adhesive portion 37 has a second content that is higher than the first content.
  • the first content may be 65% by weight or less, or 60% by weight or less.
  • the second content may be, for example, 75% by weight or more, or 80% by weight or more.
  • the first content is the ratio of the weight of the first conductive filler to the weight of the first conductive adhesive portion 35 expressed in units of weight%.
  • the second content is the ratio of the weight of the conductive filler contained in the second conductive adhesive portion 37 to the weight of the second conductive adhesive portion 37 expressed in units of weight%. It is a thing.
  • the difference between the second content and the first content may be 10% by weight or more, 15% by weight or more, or 20% by weight or more. Since the content of the first conductive filler in the first conductive adhesive portion 35 is relatively low, the cost of the first conductive adhesive portion 35 can be reduced.
  • the power semiconductor chip 20 and the like generate heat during use of the power semiconductor module 1. Therefore, the thermal stress caused by the difference between the coefficient of thermal expansion of the first lead terminal 11 and the coefficient of thermal expansion of the second lead terminal 12 and the coefficient of thermal expansion of the chip capacitor 27 is the second conductive adhesive portion. It is applied to 37. Further, mechanical stress may be applied to the second conductive adhesive portion 37 during the use of the power semiconductor module 1 or in the manufacturing process of the power semiconductor module 1.
  • the first lead terminal 11 and the second lead terminal 12 have dimensional variations at the time of manufacturing the lead frame 10 (see FIG. 8), or the first lead terminal 11 and the second lead terminal 12 have different dimensions.
  • the chip capacitor 27 is joined to the first lead terminal 11 and the second lead terminal 12 with a height difference between the first lead terminal 11 and the second lead terminal 12. There is. As shown in FIG. 13, when the lead frame 10 to which the electronic components (power semiconductor chip 20, control semiconductor chip 23, chip capacitor 27, electronic element 25) are bonded is clamped by the mold 45, the first lead terminal is obtained.
  • the heights of the 11 and the second lead terminal 12 are aligned, and mechanical stress may be applied to the second conductive adhesive portion 37. These thermal and mechanical stresses introduce at least one of the partial peels and cracks in the second conductive bond 37 and increase the electrical resistance in the second conductive bond 37.
  • the second conductive adhesive portion 37 has a lower electrical resistivity than the first conductive adhesive portion 35.
  • the second conductive filler is made of the same material as the first conductive filler, the second content of the conductive filler in the second conductive adhesive portion 37 is the first conductive. It is higher than the first content of the conductive filler in the adhesive portion 35. Therefore, it is possible to increase the margin between the second electric resistance of the second conductive adhesive portion 37 and the permissible electric resistance generally required for the joint portion of the chip capacitor 27. Further, even if at least one of partial peeling and cracking is introduced into the second conductive adhesive portion 37, the increase in electrical resistance of the second conductive adhesive portion 37 can be reduced. In this way, the reliability of the electrical connection of the second conductive adhesive portion 37 can be improved.
  • the first content rate and the second content rate are obtained by the following methods.
  • the sealing member 40, the electronic element 25, and the lead terminals (first lead terminal 11, second lead terminal 12) are removed from the power semiconductor module 1, and the conductive adhesive portion (first conductive adhesive portion 35) is removed.
  • the second conductive adhesive portion 37) is taken out. Weigh the conductive adhesive.
  • the conductive adhesive portion is heat-treated at a temperature lower than the melting point of the conductive filler (first conductive filler, second conductive filler). For example, when the conductive filler is made of silver having a melting point of 962 ° C., the conductive adhesive portion may be heat-treated at 800 ° C.
  • the resin contained in the conductive adhesive portion is volatilized to extract the conductive filler contained in the conductive adhesive portion. Weigh the extracted conductive filler. Calculate the ratio of the weight of the conductive filler to the weight of the conductive adhesive portion. In this way, the first content rate and the second content rate are obtained.
  • the electrical resistivity of the first conductive adhesive portion 35 and the electrical resistivity of the second conductive adhesive portion 37 can be obtained by the following methods.
  • the sealing member 40, the electronic element 25, and the lead terminals (first lead terminal 11, second lead terminal 12) are removed from the power semiconductor module 1, and the conductive adhesive portion (first conductive adhesive portion 35) is removed.
  • the second conductive adhesive portion 37) is taken out.
  • the resistance of the conductive adhesive portion is measured by the four-terminal method. Measure the joint area and thickness of the conductive adhesive part. Multiply the electrical resistance by the joint area and divide by the thickness. In this way, the electrical resistivity of the first conductive adhesive portion 35 and the electrical resistivity of the second conductive adhesive portion 37 can be obtained.
  • the electrical resistivity of the first conductive adhesive portion 35 and the electrical resistivity of the second conductive adhesive portion 37 can also be obtained by another method.
  • a part of the power semiconductor module 1 is cut out from the power semiconductor module 1.
  • a part of the power semiconductor module 1 includes a conductive adhesive portion (first conductive adhesive portion 35, second conductive adhesive portion 37) and a lead terminal (first lead terminal 11, second lead terminal 12). ), And at least a part of electronic components (power semiconductor chip 20, control semiconductor chip 23, chip capacitor 27, electronic element 25).
  • the electric resistance of the conductive adhesive portion is calculated by subtracting the electric resistance of a part of the lead terminal and at least a part of the electronic component from the electric resistance of a part of the power semiconductor module 1. Measure the joint area and thickness of the conductive adhesive part. Multiply the electrical resistance by the joint area and divide by the thickness. In this way, the electrical resistivity of the first conductive adhesive portion 35 and the electrical resistivity of the second conductive adhesive portion 37 can be obtained.
  • the first conductive adhesive portion 35 may further contain insulating particles made of an insulating inorganic material.
  • the insulating particles are composed of, for example, one or more inorganic materials selected from the group consisting of silica, alumina and aluminum nitride.
  • the addition of the insulating particles to the first conductive adhesive portion 35 brings about the following first action and second action.
  • the first action is for the insulating particles to reduce the volume of the energizable region of the first conductive adhesive portion 35 and increase the electrical resistance of the first conductive adhesive portion 35.
  • the second action is that the insulating particles increase the content of the first conductive filler in the energizable region of the first conductive adhesive portion 35, increasing the contact between the first conductive fillers. For the sake of the like, the electric resistance of the first conductive adhesive portion 35 is reduced.
  • the insulating particles are added to the first conductive adhesive portion 35 so that the second action becomes larger than the first action. Therefore, the insulating particles reduce the electrical resistance of the first conductive adhesive portion 35. Even if the first content of the first conductive filler in the first conductive adhesive portion 35 is relatively low, the insulating particles provide the reliability of the electrical connection of the first conductive adhesive portion 35. Can be improved.
  • the first conductive adhesive portion 35 may contain 3% by weight or more of the silica particles, or 6% by weight or more of the silica particles.
  • the first conductive adhesive portion 35 may contain, for example, 18% by weight or less of silica particles, or 12% by weight or less. The higher the content of the conductive filler, the smaller the degree of the second action.
  • the insulating particles may be selectively added to the first conductive adhesive portion 35 without being added to the second conductive adhesive portion 37.
  • the insulating particles increase the elastic modulus of the first conductive adhesive portion 35 and decrease the coefficient of linear expansion of the first conductive adhesive portion 35. Therefore, the warp of the first lead terminal 11 is reduced. The height difference between the first lead terminal 11 and the second lead terminal 12 is reduced. Peeling and cracking introduced into the second conductive adhesive portion 37 are reduced. The reliability of the electrical connection of the second conductive adhesive portion 37 can be improved.
  • the first surface 11s of the first lead terminal 11 facing the first electrode 28a may be made of copper or tin.
  • the second surface 12s of the second lead terminal 12 facing the second electrode 28b may be made of copper or tin.
  • the first surface 11s of the first lead terminal 11 and the second surface 12s of the second lead terminal 12 may be exposed from the plating portion 17 made of a material that is not easily oxidized.
  • the first surface 11s of the first lead terminal 11 and the second surface 12s of the second lead terminal 12 are more easily oxidized than the plated portion 17.
  • the second conductive adhesive portion 37 has a relatively low electrical resistance.
  • the first surface 11s is interposed via the second conductive adhesive portion 37.
  • a resistive and reliable electrical connection can be obtained.
  • the first electrode 28a and the second electrode 28b of the chip capacitor 27 may be made of gold, silver, palladium or nickel, or may be made of copper or tin.
  • the surface of the first electrode 28a and the surface of the second electrode 28b do not have to be formed of a material that is not easily oxidized, such as silver.
  • the surface of the first electrode 28a and the surface of the second electrode 28b are more easily oxidized than the plated portion 17.
  • the second conductive adhesive portion 37 has a relatively low electrical resistance. Therefore, even if the first electrode 28a and the second electrode 28b are made of copper or tin, between the first lead terminal 11 and the chip capacitor 27 via the first conductive adhesive portion 35. Obtain a low resistance and reliable electrical connection and a low resistance and reliable electrical connection between the second lead terminal 12 and the chip capacitor 27 via the second conductive adhesive portion 37. be able to.
  • the electronic element 25 and the chip capacitor 27 may be joined to the first lead terminal 11. Therefore, the first distance between the electronic element 25 and the chip capacitor 27 is narrowed.
  • the wiring resistance between the electronic element 25 and the chip capacitor 27 can be reduced.
  • the first distance between the electronic element 25 and the chip capacitor 27 can be made narrower than the second distance between the chip capacitor 27 and the power semiconductor chip 20.
  • the adverse effects of electromagnetic noise and heat generated from the power semiconductor chip 20 on the chip capacitor 27 are suppressed.
  • the operation of an electric circuit (for example, a bootstrap circuit) including an electronic element 25 (for example, a rectifying semiconductor chip incorporating a diode 25a and a resistor 25b) and a chip capacitor 27 is stabilized.
  • the sealing member 40 seals a part of a plurality of lead terminals, a power semiconductor chip 20, a control semiconductor chip 23, a chip capacitor 27, an electronic element 25, and a conductive wire 29.
  • the sealing member 40 has electrical insulation.
  • the sealing member 40 may be made of a mold resin.
  • the sealing member 40 may be composed of, for example, an epoxy resin, a polyimide resin, a polyamide resin, a polyamide-imide resin, a fluorine-based resin, an isocyanate-based resin, a silicone resin, or a resin material selected from the group consisting of combinations thereof. ..
  • the first protruding portion 11c protrudes from the portion 41a of the sealing member 40.
  • the shortest distance d between the portion 41a of the sealing member 40 and the chip capacitor 27 may be 5 times or less the thickness of the first lead terminal 11.
  • the thickness of the first lead terminal 11 may be, for example, 0.2 mm or more.
  • the thickness of the first lead terminal 11 may be, for example, 2.0 mm or less.
  • the second protruding portion 12c protrudes from the portion 41b of the sealing member 40.
  • the shortest distance d between the portion 41b of the sealing member 40 and the chip capacitor 27 may be 5 times or less the thickness t of the second lead terminal 12.
  • the thickness t of the second lead terminal 12 may be, for example, 0.2 mm or more.
  • the thickness t of the second lead terminal 12 may be, for example, 2.0 mm or less.
  • the mold is used in the step of sealing the electronic components (power semiconductor chip 20, control semiconductor chip 23, chip capacitor 27, electronic element 25) with the sealing member 40 (see FIGS. 6, 12, and 13).
  • the length of the first lead terminal 11 extending into the cavity 45a of the mold 45 and the length of the second lead terminal 12 extending into the cavity 45a of the mold 45 are reduced.
  • the amount of deflection of the plate member is proportional to the cube of the length of the plate member extending from the fixed end, and the cube of the thickness of the plate member. Is inversely proportional to.
  • the length of the first lead terminal 11 extending in the cavity 45a of the mold 45 is reduced, the amount of bending of the first lead terminal 11 is reduced. Since the length of the second lead terminal 12 extending in the cavity 45a of the mold 45 is reduced, the amount of bending of the second lead terminal 12 is reduced. The height difference between the first lead terminal 11 and the second lead terminal 12 is reduced. The introduction of partial peeling and cracks into the second conductive adhesive portion 37 can be suppressed, and the reliability of the electrical connection of the second conductive adhesive portion 37 can be improved.
  • the first through hole 16a of the first lead terminal 11 and the second through hole 16b of the second lead terminal 12 are filled with the sealing member 40. Therefore, due to the difference between the coefficient of thermal expansion of the sealing member 40 and the coefficient of thermal expansion of the first lead terminal 11 and the second lead terminal 12, the first lead terminal 11 and the second lead terminal Even if the 12 is deformed, the first lead terminal 11 and the second lead terminal 12 are deformed into substantially the same shape starting from the first through hole 16a and the second through hole 16b. Therefore, the introduction of partial peeling and cracks into the second conductive adhesive portion 37 can be suppressed, and the reliability of the electrical connection of the second conductive adhesive portion 37 can be improved.
  • the sealing member 40 filled in the first through hole 16a and the second through hole 16b Through the sealing member 40 filled in the first through hole 16a and the second through hole 16b, the sealing member 40 on the upper side of the first lead terminal 11 and the second lead terminal 12 and the first lead.
  • the terminal 11 and the sealing member 40 on the lower side of the second lead terminal 12 are integrated.
  • the sealing member 40 filled in the first through hole 16a and the second through hole 16b functions as an anchor against the force of pulling out the first lead terminal 11 and the second lead terminal 12 from the sealing member 40. To do. Therefore, the first lead terminal 11 and the second lead terminal 12 are prevented from being pulled out from the sealing member 40, and the shear stress is suppressed from being applied to the second conductive adhesive portion 37.
  • the introduction of partial peeling and cracks into the second conductive adhesive portion 37 can be suppressed, and the reliability of the electrical connection of the second conductive adhesive portion 37 can be improved.
  • the semiconductor device 2 of the present embodiment will be described with reference to FIG.
  • the semiconductor device 2 includes a power semiconductor module 1 and a wiring board 51 including a plurality of wirings (for example, wirings 54 and 55) and a plurality of through holes (for example, through holes 52 and 53).
  • the wiring board 51 has a first main surface 51a and a second main surface 51b on the opposite side of the first main surface 51a.
  • the first main surface 51a faces electronic components (power semiconductor chip 20, control semiconductor chip 23, chip capacitor 27, electronic element 25).
  • the plurality of through holes extend from the first main surface 51a to the second main surface 51b.
  • the plurality of wirings are formed on the second main surface 51b.
  • the plurality of lead terminals are inserted into the plurality of through holes of the wiring board 51.
  • the protruding portions of the plurality of lead terminals are joined to the plurality of wirings at solder joints (for example, solder joints 57 and 58).
  • solder joints for example, solder joints 57 and 58.
  • the second protruding portion 11e (see FIG. 1) of the first lead terminal 11 is inserted into a through hole (not shown) of the wiring board 51.
  • the second protruding portion 11e of the first lead terminal 11 is joined to the wiring (not shown) at a solder joint portion (not shown).
  • the fourth protruding portion 12e of the second lead terminal 12 is inserted into the through hole 52.
  • the fourth protruding portion 12e of the second lead terminal 12 is joined to the wiring 54 by the solder joint portion 57.
  • the sixth protruding portion 15e of the fifth lead terminal 15 is inserted into the through hole 53.
  • the sixth protruding portion 15e of the fifth lead terminal 15 is joined to the wiring 55 at the solder joint portion 58.
  • the manufacturing method of the power semiconductor module 1 of the first embodiment will be described with reference to FIGS. 6 to 10 and 12 to 14.
  • the lead frame 10 includes a frame portion 10a and a plurality of lead terminals.
  • the plurality of lead terminals include a first lead terminal 11, a second lead terminal 12, a third lead terminal 13, a fourth lead terminal 14, and a fifth lead terminal 15.
  • the plurality of lead terminals extend from the frame portion 10a toward the inside of the opening 10b of the frame portion 10a.
  • the lead frame 10 may further include a terminal connection portion 18.
  • the terminal connection portion 18 connects the plurality of lead terminals to each other in the opening 10b of the frame, and also connects the plurality of lead terminals to the frame portion 10a.
  • the terminal connection portion 18 suppresses bending of the plurality of lead terminals in the opening 10b of the frame portion 10a.
  • the electronic components power semiconductor chip 20, control semiconductor chip 23, chip capacitor 27, electronic element 25
  • the power semiconductor chip 20 is joined to the fifth lead terminal 15 which is one of a plurality of lead terminals at the solder joint portion 30 (S1a).
  • the control semiconductor chip 23 is bonded to the fourth lead terminal 14, which is one of the plurality of lead terminals, at the conductive bonding portion 33 (S1b).
  • the conductive joint portion 33 may be a solder joint portion or a first conductive adhesive portion 35.
  • An electronic element 25 such as a rectifying semiconductor chip is joined to a first lead terminal 11 which is one of a plurality of lead terminals by a first conductive adhesive portion 35 (S1c).
  • the first electrode 28a and the second electrode 28b of the chip capacitor 27 are connected to the first lead terminal 11 and the second lead terminal 12 included in the plurality of lead terminals by the second conductive adhesive portion 37.
  • Each is joined (S1d).
  • the conductive adhesive 37a is applied to the first surface 11s and the second surface 11s of the first lead terminal 11 by a screen printing method or a dispenser method such as an inkjet method. It is supplied on the second surface 12s of the lead terminal 12 (S1e).
  • the conductive adhesive 37a contains a second resin and a second conductive filler dispersed in the second resin.
  • the conductive adhesive 37a is spread by the chip capacitor 27.
  • the conductive adhesive 37a is cured, and the first electrode 28a and the second electrode 28b of the chip capacitor 27 are joined to the first lead terminal 11 and the second lead terminal 12, respectively.
  • Part 37 is formed (S1g).
  • the second conductive adhesive portion 37 (conductive adhesive 37a) contains the conductive filler at a second content higher than that of the first content.
  • the second conductive adhesive portion 37 may extend to the first edge portion 11p of the first lead terminal 11 and the second edge portion 12p of the second lead terminal 12. ..
  • the second conductive adhesive portion 37 does not protrude from the first edge portion 11p of the first lead terminal 11 and the second edge portion 12p of the second lead terminal 12.
  • the first edge portion 11p of the first lead terminal 11 and the second edge portion 12p of the second lead terminal 12 are opposed to each other, and the first surface 11s and the first surface 11s of the first lead terminal 11 and the first lead terminal 11 are opposed to each other. It is below the chip capacitor 27 in a plan view of the second surface 12s of the lead terminal 12 of 2.
  • the second conductive adhesive portion 37 on the first region 11r and the second region 12r is joined to the main body portion of the chip capacitor 27 excluding the first electrode 28a and the second electrode 28b.
  • the first region 11r is located between the first electrode 28a and the first edge portion 11p of the first lead terminal 11 in the first surface 11s of the first lead terminal 11 facing the chip capacitor 27. It is an area.
  • the second region 12r is located between the second electrode 28b and the second edge portion 12p of the second lead terminal 12 in the second surface 12s of the second lead terminal 12 facing the chip capacitor 27. It is an area.
  • the first region 11r and the second region 12r are below the main body of the chip capacitor 27.
  • step S1e as shown in FIG. 10, the conductive adhesive 37a is applied to a plurality of first portions of the first surface 11s of the first lead terminal 11 and the second surface 12s of the second lead terminal 12. It may be supplied to a plurality of second locations of the above.
  • step S1f the first electrode 28a of the chip capacitor 27 is placed on the conductive adhesives 37a on the plurality of first locations, and the second electrode 28b of the chip capacitor 27 is placed on the plurality of second locations. It may be placed on the conductive adhesive 37a of the above. The chip capacitor 27 spreads the conductive adhesive 37a.
  • the chip capacitor 27 pushes the conductive adhesive 37a.
  • the conductive adhesive 37a is prevented from protruding from the first edge portion 11p and the second edge portion 12p.
  • the second conductive adhesive portion 37 is prevented from protruding from the first edge portion 11p and the second edge portion 12p. It is possible to more reliably prevent the insulation reliability of the power semiconductor module 1 from being lowered.
  • the second conductive adhesive portion 37 protrudes from the first edge portion 11p or the second edge portion 12p.
  • the minimum distance G between the second conductive adhesive portion 37 on the first lead terminal 11 and the second conductive adhesive portion 37 on the second lead terminal 12 becomes too short, and the power semiconductor module Insulation reliability is reduced.
  • the conductive wire 29 is bonded to the power semiconductor chip 20, the first lead terminal 11, the second lead terminal 12, the plurality of lead terminals including the third lead terminal 13, the control semiconductor chip 23, and the electronic element 25. Will be done.
  • the conductive wire 29 is bonded using a wire bonder.
  • the method of manufacturing the power semiconductor module 1 is to seal electronic components (power semiconductor chip 20, control semiconductor chip 23, chip capacitor 27, electronic element 25) with a sealing member 40. It is provided with sealing (S2). Specifically, the lead frame 10 to which the electronic components (power semiconductor chip 20, control semiconductor chip 23, chip capacitor 27, electronic element 25) are bonded is set in the mold 45. The sealing resin is injected into the cavity 45a of the mold 45 by using a transfer molding method or a compression molding method. The electronic components (power semiconductor chip 20, control semiconductor chip 23, chip capacitor 27, electronic element 25) are sealed by the sealing member 40.
  • the frame portion 10a, the terminal connecting portion 18, and the protruding portions of the plurality of lead terminals are exposed from the sealing member 40. There is.
  • the shortest distance between the mold 45 portion 46a on which the first lead terminal 11 protrudes and the chip capacitor 27 may be 5 times or less the thickness of the first lead terminal 11.
  • the shortest distance d between the portion 46b of the mold 45 on which the second lead terminal 12 protrudes and the chip capacitor 27 may be 5 times or less the thickness t of the second lead terminal 12.
  • the length of the first lead terminal 11 extending in the cavity 45a of the mold 45 is reduced, the amount of bending of the first lead terminal 11 is reduced. Since the length of the second lead terminal 12 extending in the cavity 45a of the mold 45 is reduced, the amount of bending of the second lead terminal 12 is reduced. The introduction of partial peeling and cracks into the second conductive adhesive portion 37 can be suppressed, and the reliability of the electrical connection of the second conductive adhesive portion 37 can be improved.
  • the manufacturing method of the power semiconductor module 1 includes processing the lead frame 10 (S3). Specifically, the frame portion 10a and the terminal connection portion 18 are removed. Part of the plurality of protrusions of the plurality of lead terminals (for example, a part of the plurality of protrusions of the third lead terminal 13 and the fourth lead terminal 14) may be further removed. A part of the plurality of protrusions (for example, the first protrusion 11c, the second protrusion 12c, and the third protrusion 15c) of the plurality of lead terminals is bent. In this way, the power semiconductor module 1 shown in FIGS. 1 to 3 is obtained.
  • the second conductive adhesive portion 37 is 80% or more 100% of the first region 11r of the first lead terminal 11 below the chip capacitor 27. % Or less, and 80% or more and 100% or less of the second region 12r of the second lead terminal 12 below the chip capacitor 27.
  • 80% or more and 100% or less of the first region 11r is 80% of the area of the first region 11r in the plan view of the first surface 11s of the first lead terminal 11 facing the chip capacitor 27. It means more than 100% or less.
  • 80% or more and 100% or less of the second region 12r of the second lead terminal 12 is the area of the second region 12r in the plan view of the second surface 12s of the second lead terminal 12 facing the chip capacitor 27. It means 80% or more and 100% or less.
  • the second conductive adhesive portion 37 is 90% or more and 100% or less of the first region 11r of the first lead terminal 11 below the chip capacitor 27, and the second lead terminal 12 below the chip capacitor 27. 90% or more and 100% or less of the second region 12r may be covered.
  • the second conductive adhesive portion 37 includes all of the first region 11r of the first lead terminal 11 below the chip capacitor 27 and the second region 12r of the second lead terminal 12 below the chip capacitor 27. You may cover all of.
  • the second conductive adhesive portion 37 on the first region 11r and the second region 12r is joined to the main body portion of the chip capacitor 27 excluding the first electrode 28a and the second electrode 28b.
  • the second conductive adhesive portion 37 does not protrude from the first edge portion 11p and the second edge portion 12p.
  • Thermal stress due to the difference between the coefficient of thermal expansion of the second conductive adhesive portion 37 and the coefficient of thermal expansion of the sealing member 40 is applied to the second conductive adhesive portion 37.
  • This thermal stress is generated when the sealing member 40 is cooled, for example, in the step of molding the sealing resin to form the sealing member 40.
  • the second conductive adhesive portion 37 on the first region 11r and the second region 12r is joined to the main body portion of the chip capacitor 27 excluding the first electrode 28a and the second electrode 28b, and is a sealing member. Not in contact with 40. Therefore, the second conductive adhesive portion 37 on the first region 11r and the second region 12r increases the volume of the second conductive adhesive portion 37 without increasing the thermal stress. In this way, the thermal stress per unit volume of the second conductive adhesive portion 37 is reduced. The generation of cracks in the second conductive adhesive portion 37 is suppressed. The reliability of the electrical connection of the second conductive adhesive portion 37 can be improved.
  • the second conductive adhesive portion 37 which does not protrude from the portion 12p, uses the conductive adhesive 37a with the plurality of first portions of the first surface 11s of the first lead terminal 11. It can be easily formed by supplying it to a plurality of second portions on the second surface 12s of the second lead terminal 12.
  • the manufacturing method of the semiconductor device 2 of the present embodiment will be described with reference to FIG.
  • the manufacturing method of the semiconductor device 2 includes preparing the power semiconductor module 1 (S11).
  • the power semiconductor module 1 is prepared by the method of manufacturing the power semiconductor module 1 of the present embodiment.
  • the manufacturing method of the semiconductor device 2 further includes mounting the power semiconductor module 1 on the wiring board 51 (S12). Specifically, a plurality of penetrating portions of the wiring board 51 (for example, a fourth protruding portion 12e of the second lead terminal 12 and a sixth protruding portion 15e of the fifth lead terminal 15) of the plurality of lead terminals. It is inserted into a hole (for example, through holes 52, 53).
  • a hole for example, through holes 52, 53.
  • electronic components power semiconductor chip 20, control semiconductor chip 23, chip capacitor 27, electronic element 25
  • DIP dual in-line package
  • the protruding portions of the plurality of lead terminals (for example, the fourth protruding portion 12e of the second lead terminal 12 and the sixth protruding portion 15e of the fifth lead terminal 15) are attached to the wiring board 51. Solder joints to a plurality of wires (for example, wires 54 and 55). In this way, the semiconductor device 2 shown in FIG. 5 is obtained.
  • the power semiconductor module 1 of the present embodiment includes a plurality of lead terminals, a power semiconductor chip 20, a chip capacitor 27, an electronic element 25 of a type different from that of the chip capacitor 27, and a sealing member 40.
  • the plurality of lead terminals include a first lead terminal 11 and a second lead terminal 12 that is separated from the first lead terminal 11.
  • the chip capacitor 27 includes a first electrode 28a and a second electrode 28b.
  • the sealing member 40 seals the power semiconductor chip 20, the chip capacitor 27, and the electronic element 25.
  • the power semiconductor chip 20 is bonded to at least one of a plurality of lead terminals (for example, a fifth lead terminal 15).
  • the electronic element 25 is joined to one of a plurality of lead terminals (for example, the first lead terminal 11) by the first conductive adhesive portion 35.
  • the first conductive adhesive portion 35 contains a conductive filler at a first content rate.
  • the first electrode 28a and the second electrode 28b of the chip capacitor 27 are joined to the first lead terminal 11 and the second lead terminal 12 by the second conductive adhesive portion 37, respectively.
  • the second conductive adhesive portion 37 contains the conductive filler at a second content higher than that of the first content.
  • the power semiconductor module 1 of the present embodiment includes a plurality of lead terminals, a power semiconductor chip 20, a chip capacitor 27, an electronic element 25 of a type different from that of the chip capacitor 27, and a sealing member 40.
  • the plurality of lead terminals include a first lead terminal 11 and a second lead terminal 12 that is separated from the first lead terminal 11.
  • the chip capacitor 27 includes a first electrode 28a and a second electrode 28b.
  • the sealing member 40 seals the power semiconductor chip 20, the chip capacitor 27, and the electronic element 25.
  • the power semiconductor chip 20 is bonded to at least one of a plurality of lead terminals (for example, a fifth lead terminal 15).
  • the electronic element 25 is joined to one of a plurality of lead terminals (for example, the first lead terminal 11) by the first conductive adhesive portion 35.
  • the first conductive adhesive portion 35 contains the first conductive filler.
  • the first electrode 28a and the second electrode 28b of the chip capacitor 27 are joined to the first lead terminal 11 and the second lead terminal 12 by the second conductive adhesive portion 37, respectively.
  • the second conductive adhesive portion 37 contains a second conductive filler.
  • the second conductive adhesive portion has a lower electrical resistivity than the first conductive adhesive portion.
  • the second conductive adhesive portion 37 has a lower electrical resistivity than the first conductive adhesive portion 35.
  • the second conductive filler is made of the same material as the first conductive filler, the second content of the conductive filler in the second conductive adhesive portion 37 is the first conductive adhesive portion. It is higher than the first content of the conductive filler in 35. Therefore, it is possible to increase the margin between the electric resistance of the second conductive adhesive portion 37 and the allowable electric resistance generally required for the joint portion of the chip capacitor 27. Further, even if at least one of partial peeling and cracking is introduced into the second conductive adhesive portion 37 by the stress applied to the second conductive adhesive portion 37, the electricity of the second conductive adhesive portion 37 is increased. The resistance increment can be reduced. The reliability of the electrical connection of the second conductive adhesive portion 37 can be improved.
  • the power semiconductor module 1 of the present embodiment has high reliability.
  • the first conductive adhesion is performed.
  • the cost of the unit 35 is reduced. According to the power semiconductor module 1 of the present embodiment, the cost of the power semiconductor module 1 can be reduced.
  • the tallest chip capacitor 27 among the electronic components (power semiconductor chip 20, control semiconductor chip 23, chip capacitor 27, electronic element 25) bonded to a plurality of lead terminals does not use the conductive wire 29. It is joined to the first lead terminal 11 and the second lead terminal 12 by the second conductive adhesive portion 37. Therefore, the height of the power semiconductor module 1 can be reduced. According to the power semiconductor module 1 of the present embodiment, the power semiconductor module 1 can be miniaturized.
  • the second conductive adhesive portion 37 is 80% or more and 100% or less of the first region 11r of the first lead terminal 11 below the chip capacitor 27, and the chip capacitor. It covers 80% or more and 100% or less of the second region 12r of the second lead terminal 12 below 27.
  • the first region 11r is located between the first electrode 28a and the first edge portion 11p of the first lead terminal 11 in the first surface 11s of the first lead terminal 11 facing the chip capacitor 27. It is an area.
  • the second region 12r is located between the second electrode 28b and the second edge portion 12p of the second lead terminal 12 in the second surface 12s of the second lead terminal 12 facing the chip capacitor 27. It is an area.
  • the first edge portion 11p and the second edge portion 12p are opposed to each other, and a plan view of the first surface 11s of the first lead terminal 11 and the second surface 12s of the second lead terminal 12 Is below the chip capacitor 27.
  • the second conductive adhesive portion 37 on the first region 11r and the second region 12r is joined to the main body portion of the chip capacitor 27 excluding the first electrode 28a and the second electrode 28b.
  • the second conductive adhesive portion 37 does not protrude from the first edge portion 11p and the second edge portion 12p.
  • the thermal stress per unit volume of the second conductive adhesive portion 37 due to the difference between the coefficient of thermal expansion of the second conductive adhesive portion 37 and the coefficient of thermal expansion of the sealing member 40 is reduced.
  • the generation of cracks in the second conductive adhesive portion 37 is suppressed. It can be prevented that the insulation reliability of the power semiconductor module 1 is lowered.
  • the reliability of the electrical connection of the second conductive adhesive portion 37 can be improved.
  • the method for manufacturing a power semiconductor module according to the present embodiment includes joining the power semiconductor chip 20 to at least one of a plurality of lead terminals (S1a).
  • the plurality of lead terminals include a first lead terminal 11 and a second lead terminal 12 that is separated from the first lead terminal 11.
  • the method for manufacturing a power semiconductor module according to the present embodiment includes joining the electronic element 25 to one of a plurality of lead terminals (S1c) at the first conductive adhesive portion 35.
  • the first conductive adhesive portion 35 contains a conductive filler at a first content rate.
  • the conductive adhesive 37a is supplied to a plurality of first locations of the first lead terminal 11 and a plurality of second locations of the second lead terminal 12 ( It is provided with S1e).
  • the first electrode 28a of the chip capacitor 27 is placed on the conductive adhesive 37a on the plurality of first locations, and the second electrode 28b of the chip capacitor 27 is placed on the conductive adhesive 37a. It comprises placing it on the conductive adhesive 37a on a plurality of second places (S1f).
  • the type of the chip capacitor 27 is different from that of the electronic element 25.
  • the conductive adhesive 37a is cured, and the first electrode 28a and the second electrode 28b of the chip capacitor 27 are connected to the first lead terminal 11 and the second lead.
  • a second conductive adhesive portion 37 to be joined to each of the terminals 12 is formed (S1g).
  • the second conductive adhesive portion 37 contains the conductive filler at a second content higher than that of the first content.
  • the method for manufacturing a power semiconductor module according to the present embodiment includes sealing the power semiconductor chip 20, the chip capacitor 27, and the electronic element 25 with a sealing member 40 (S2).
  • the second conductive adhesive portion 37 is easily formed on a portion of more than half of the first region 11r and a portion of more than half of the second region 12r without protruding from the first edge portion 11p and the second edge portion 12p. Can be done. It is possible to more reliably prevent the insulation reliability of the power semiconductor module 1 from being lowered. The reliability of the electrical connection of the second conductive adhesive portion 37 can be improved.
  • Embodiment 2 The power semiconductor module 1b of the second embodiment will be described with reference to FIG.
  • the power semiconductor module 1b of the present embodiment has the same configuration as the power semiconductor module 1 of the first embodiment and has the same effect, but is mainly different in the following points.
  • the plurality of lead terminals includes a plurality of protrusions protruding from the sealing member 40.
  • the plurality of protrusions are bent into a gull wing shape.
  • the first lead terminal 11 includes a first protruding portion 11c (not shown in FIG. 16) protruding from the sealing member 40.
  • the second lead terminal 12 includes a second protruding portion 12c that protrudes from the sealing member 40.
  • the fifth lead terminal 15 includes a third protruding portion 15c that protrudes from the sealing member 40.
  • the first protruding portion 11c, the second protruding portion 12c, and the third protruding portion 15c are bent into a gull wing shape.
  • the plurality of lead terminals include a plurality of terminals extending along the plurality of pads (for example, the first pad 11a, the second pad 12a, the third pad 14a, and the fourth pad 15a).
  • the first protruding portion 11c of the first lead terminal 11 further includes a seventh protruding portion (not shown) in addition to the first protruding portion 11d and the second protruding portion 11e (see FIG. 1). ..
  • the seventh protruding portion extends horizontally from the second protruding portion 11e in the direction opposite to the first protruding portion 11d.
  • the seventh protruding portion is bent with respect to the second protruding portion 11e.
  • the seventh protruding portion functions as a first terminal portion of the first lead terminal 11.
  • the second protruding portion 12c of the second lead terminal 12 further includes an eighth protruding portion 12f in addition to the third protruding portion 12d and the fourth protruding portion 12e.
  • the eighth protruding portion 12f extends horizontally from the fourth protruding portion 12e in the direction opposite to that of the third protruding portion 12d.
  • the eighth protruding portion 12f is bent with respect to the fourth protruding portion 12e.
  • the eighth protruding portion 12f functions as a second terminal portion of the second lead terminal 12.
  • the third protruding portion 15c of the fifth lead terminal 15 further includes a ninth protruding portion 15f in addition to the fifth protruding portion 15d and the sixth protruding portion 15e.
  • the ninth protruding portion 15f extends horizontally from the sixth protruding portion 15e in the direction opposite to the fifth protruding portion 15d.
  • the ninth protruding portion 15f is bent with respect to the sixth protruding portion 15e.
  • the ninth protruding portion 15f functions as a third terminal portion of the fifth lead terminal 15.
  • electronic components power semiconductor chip 20, control semiconductor chip 23, chip capacitor 27, electronic element 25
  • SOP small outline package
  • the power semiconductor module 1b is a surface mount type module.
  • the manufacturing method of the power semiconductor module 1b of the present embodiment includes the same steps as the manufacturing method of the power semiconductor module 1 of the first embodiment (see FIG. 6), but is mainly different in the following points.
  • the protrusions of the plurality of lead terminals for example, the first protrusion 11c, the second protrusion 12c, and the third protrusion) 15c
  • the protrusions of the plurality of lead terminals is bent into a gull wing shape.
  • a plurality of terminal portions (for example, a seventh protruding portion, an eighth protruding portion 12f, and a ninth protruding portion 15f) are formed on the protruding portions of the plurality of lead terminals.
  • the plurality of terminal portions extend along the plurality of pads (for example, the first pad 11a, the second pad 12a, the third pad 14a, and the fourth pad 15a). In this way, the power semiconductor module 1b shown in FIG. 16 is obtained.
  • the semiconductor device 2b of the second embodiment will be described with reference to FIG.
  • the semiconductor device 2b of the present embodiment has the same configuration as the semiconductor device 2 of the first embodiment and exhibits the same effect, but is mainly different in the following points.
  • the semiconductor device 2b includes a power semiconductor module 1b and a wiring board 51 including a plurality of wirings (for example, wirings 54 and 55).
  • the plurality of wirings are formed on the first main surface 51a of the wiring board 51.
  • the terminal portions of the plurality of lead terminals are joined to the wiring at the solder joint portion.
  • the seventh protruding portion (not shown) of the first lead terminal 11 is joined to the wiring (not shown) at the solder joint portion (not shown).
  • the eighth protruding portion 12f of the second lead terminal 12 is joined to the wiring 54 at the solder joint portion 57.
  • the ninth protruding portion 15f of the fifth lead terminal 15 is joined to the wiring 55 at the solder joint portion 58.
  • the manufacturing method of the semiconductor device 2b of the present embodiment will be described.
  • the method for manufacturing the semiconductor device 2b of the present embodiment includes the same steps as the method for manufacturing the semiconductor device 2 of the first embodiment (see FIG. 15), but differs mainly in the following points.
  • the power semiconductor module 1b electronic components (power semiconductor chip 20, control semiconductor chip 23, chip capacitor 27, electronic element 25) are packaged by a small outline package (SOP) method. Therefore, when the power semiconductor module 1b is mounted on the wiring board 51, a plurality of terminal portions (for example, the eighth protruding portion 12f and the ninth protruding portion 15f) of the plurality of lead terminals are attached to the wiring board by reflow type soldering. Soldered to a plurality of wirings (for example, wirings 54 and 55) of 51. In this way, the semiconductor device 2b shown in FIG. 17 is obtained.
  • SOP small outline package
  • the reflow type soldering in the present embodiment has a higher temperature reached by the package at the time of soldering and a longer time required for soldering than the flow type soldering in the first embodiment. Therefore, when the power semiconductor module 1b is mounted on the wiring board 51 by reflow type soldering, a larger thermal stress is applied to the second conductive adhesive portion 37.
  • the second conductive adhesive portion 37 has a lower electrical resistivity than the first conductive adhesive portion 35.
  • the second conductive filler is made of the same material as the first conductive filler, the second content of the conductive filler in the second conductive adhesive portion 37 is the first conductive adhesive portion. It is higher than the first content of the conductive filler in 35. Therefore, it is possible to increase the margin between the electric resistance of the second conductive adhesive portion 37 and the allowable electric resistance generally required for the joint portion of the chip capacitor 27. Further, even if at least one of partial peeling and cracking is introduced into the second conductive adhesive portion 37 by the stress applied to the second conductive adhesive portion 37, the electricity of the second conductive adhesive portion 37 is increased. The resistance increment can be reduced. The reliability of the electrical connection of the second conductive adhesive portion 37 can be improved.
  • the power semiconductor module 1b of the present embodiment has high reliability.
  • Embodiment 3 The power semiconductor module 1c of the third embodiment will be described with reference to FIG.
  • the power semiconductor module 1c of the present embodiment has the same configuration as the power semiconductor module 1 of the first embodiment and exhibits the same effect, but is mainly different in the following points.
  • the power semiconductor module 1c further includes a heat radiating plate 60.
  • At least one of the plurality of lead terminals includes a third surface 15s facing the power semiconductor chip 20 and a fourth surface 15t opposite to the third surface 15s. ..
  • the heat radiating plate 60 is attached to the fourth surface 15t.
  • the heat radiating plate 60 is made of a material having high thermal conductivity such as copper or aluminum.
  • the heat radiating plate 60 has a heat radiating surface 61 exposed from the sealing member 40.
  • the heat radiating surface 61 efficiently dissipates the heat generated in the power semiconductor chip 20 to the outside of the power semiconductor module 1c.
  • the heat radiating surface 61 may be flush with the surface 42 of the sealing member 40.
  • a plurality of surfaces of the heat radiating plate 60 other than the heat radiating surface 61 may face the sealing member 40.
  • the heat radiating plate 60 is integrated with the sealing member 40.
  • the heat radiating plate 60 is sealed by molding the heat radiating plate 60 with a sealing member 40 together with electronic components (power semiconductor chip 20, control semiconductor chip 23, chip capacitor 27, electronic element 25) and a plurality of lead terminals. It may be integrated with the member 40.
  • the heat radiating plate 60 may be integrated with the sealing member 40 by fitting the heat radiating plate 60 into the recess formed in the sealing member 40.
  • the heat radiating plate 60 may be integrated with the sealing member 40 by attaching the heat radiating plate 60 to the sealing member 40 using a fixing member such as a screw.
  • the power semiconductor module 1c may further include an insulating layer 62.
  • the heat radiating plate 60 may be attached to the fourth surface 15t via the insulating layer 62.
  • the insulating layer 62 may be an insulating resin layer in which insulating particles having high thermal conductivity are dispersed.
  • the insulating particles may be composed of an insulating inorganic material such as silica, alumina or aluminum nitride.
  • the insulating resin layer may be, for example, an epoxy resin layer.
  • the heat radiating plate 60 may be insulated from a plurality of lead terminals by the sealing member 40 and the insulating layer 62.
  • the power semiconductor module 1c of the present embodiment further includes a heat radiating plate 60.
  • At least one of the plurality of lead terminals includes a third surface 15s facing the power semiconductor chip 20 and a fourth surface 15t opposite to the third surface 15s. ..
  • the heat radiating plate 60 is attached to the fourth surface 15t. Therefore, the heat generated from the power semiconductor chip 20 can be efficiently dissipated to the outside of the power semiconductor module 1c through the heat radiating plate 60.
  • the power semiconductor chip 20 and at least one of the plurality of lead terminals are located between the sealing member 40 and the heat radiating plate 60.
  • the sealing member 40 and the heat radiating plate 60 have different coefficients of thermal expansion. Therefore, in the power semiconductor module 1c of the present embodiment, a plurality of lead terminals are warped more than the power semiconductor module 1 of the first embodiment, and a larger thermal stress is applied to the second conductive adhesive portion 37. Will be done.
  • the second conductive adhesive portion 37 has a lower electrical resistivity than the first conductive adhesive portion 35.
  • the second conductive filler is made of the same material as the first conductive filler, the second content of the conductive filler in the second conductive adhesive portion 37 is the first conductive adhesive portion. It is higher than the first content of the conductive filler in 35. Therefore, it is possible to increase the margin between the electric resistance of the second conductive adhesive portion 37 and the allowable electric resistance generally required for the joint portion of the chip capacitor 27. Further, even if at least one of partial peeling and cracking is introduced into the second conductive adhesive portion 37 by the stress applied to the second conductive adhesive portion 37, the electricity of the second conductive adhesive portion 37 is increased. The resistance increment can be reduced. The reliability of the electrical connection of the second conductive adhesive portion 37 can be improved.
  • the power semiconductor module 1c of the present embodiment has high reliability.
  • Embodiment 4 the power semiconductor modules 1, 1b, 1c according to any one of the first to third embodiments are applied to a power conversion device.
  • the case where the power conversion device 200 of the present embodiment is not particularly limited, but is a three-phase inverter will be described below.
  • the power conversion system shown in FIG. 19 includes a power source 100, a power conversion device 200, and a load 300.
  • the power source 100 is a DC power source, and supplies DC power to the power converter 200.
  • the power supply 100 is not particularly limited, but may be composed of, for example, a DC system, a solar cell, or a storage battery, or may be composed of a rectifier circuit or an AC / DC converter connected to an AC system.
  • the power supply 100 may be configured by a DC / DC converter that converts DC power output from the DC system into another DC power.
  • the power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300, converts the DC power supplied from the power supply 100 into AC power, and supplies AC power to the load 300. As shown in FIG. 19, the power conversion device 200 has a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. It is equipped with 203.
  • the load 300 is a three-phase electric motor driven by AC power supplied from the power converter 200.
  • the load 300 is not particularly limited, but is an electric motor mounted on various electric devices, and is used as, for example, an electric motor for a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, or an air conditioner.
  • the main conversion circuit 201 includes a switching element (not shown) and a freewheeling diode (not shown). By switching the voltage supplied from the power supply 100 by the switching element, the main conversion circuit 201 converts the DC power supplied from the power supply 100 into AC power and supplies it to the load 300.
  • the main conversion circuit 201 is a two-level three-phase full bridge circuit, and has six switching elements and each switching element. It may consist of six anti-parallel freewheeling diodes.
  • the power semiconductor modules 1, 1b, 1c are applied to at least one of the switching elements and the freewheeling diodes of the main conversion circuit 201.
  • the six switching elements are connected in series for each of the two switching elements to form an upper and lower arm, and each upper and lower arm constitutes each phase (U phase, V phase and W phase) of the full bridge circuit. Then, the output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.
  • the main conversion circuit 201 is a drive circuit. It has.
  • the drive circuit generates a drive signal for driving the switching element included in the main conversion circuit 201, and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 201.
  • a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrodes of each switching element.
  • the drive signal When the switching element is kept in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when the switching element is kept in the off state, the drive signal is a voltage equal to or lower than the threshold voltage of the switching element. It becomes a signal (off signal).
  • the control circuit 203 controls the switching element of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the time (on time) at which each switching element of the main conversion circuit 201 should be in the on state is calculated based on the power to be supplied to the load 300.
  • the main conversion circuit 201 can be controlled by pulse width modulation (PWM) control that modulates the on-time of the switching element according to the voltage to be output.
  • PWM pulse width modulation
  • a control command is output to the drive circuit included in the main conversion circuit 201 so that an on signal is output to the switching element that should be turned on at each time point and an off signal is output to the switching element that should be turned off. Is output.
  • the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.
  • the power semiconductor modules 1, 1b, 1c according to any one of the first to third embodiments are applied as the power semiconductor module 202 included in the main conversion circuit 201. Ru. Therefore, the power conversion device 200 according to the present embodiment has high reliability.
  • the present invention is not limited to this, and can be applied to various power conversion devices.
  • a two-level power conversion device is used, but a three-level power conversion device or a multi-level power conversion device may be used.
  • the present invention may be applied to a single-phase inverter when the power converter supplies power to a single-phase load.
  • the present invention may be applied to a DC / DC converter or an AC / DC converter.
  • the power conversion device to which the present invention is applied is not limited to the case where the load is an electric motor, for example, a power supply device for an electric discharge machine or a laser machine, or an induction heating cooker or a non-contactor power supply system. Can be incorporated into a power supply.
  • the power conversion device to which the present invention is applied can be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.
  • Embodiments 1-4 disclosed this time are exemplary in all respects and are not restrictive. As long as there is no contradiction, at least two of Embodiments 1-4 disclosed this time may be combined.
  • the scope of the present invention is shown by the scope of claims rather than the above description, and is intended to include all modifications within the meaning and scope of the claims.
  • 1,1b, 1c power semiconductor module, 2,2b semiconductor device 10 lead frame, 10a frame part, 10b opening, 11 first lead terminal, 11a first pad, 11c first protrusion, 11d first protrusion Part, 11e 2nd protruding part, 11p 1st edge part, 11r 1st area, 11s 1st surface, 12 2nd lead terminal, 12a 2nd pad, 12c 2nd protruding part, 12d 3rd protruding part , 12e 4th protruding part, 12f 8th protruding part, 12p 2nd edge, 12r 2nd region, 12s 2nd surface, 13 3rd lead terminal, 14 4th lead terminal, 14a 3rd pad, 15 5th lead terminal, 15a 4th pad, 15b stepped part, 15c 3rd protruding part, 15d 5th protruding part, 15e 6th protruding part, 15f 9th protruding part, 15s 3rd surface, 15t third Surface of 4, 16a 1st

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Inverter Devices (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

La présente invention concerne un module semi-conducteur de puissance (1) pourvu d'une première borne de connexion (11), d'une seconde borne de connexion (12), d'un condensateur intégré (27) et d'un élément électronique (25). L'élément électronique (25) est lié à la première borne de connexion (11) au moyen d'une première partie de liaison conductrice (35). Une première électrode (28a) et une seconde électrode (28b) du condensateur intégré (27) sont respectivement liées à la première borne de connexion (11) et à la seconde borne de connexion (12) au moyen d'une seconde partie de liaison conductrice (37). La seconde partie de liaison conductrice (37) a une teneur en charge conductrice supérieure à celle de la première partie de liaison conductrice (35). Par conséquent, ce module semi-conducteur de puissance (1) a une fiabilité élevée.
PCT/JP2019/016768 2018-05-09 2019-04-19 Module semi-conducteur de puissance, son procédé de production et convertisseur de puissance électrique WO2019216161A1 (fr)

Priority Applications (3)

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DE112019002333.0T DE112019002333T5 (de) 2018-05-09 2019-04-19 Leistungshalbleitermodul, Verfahren zum Herstellen desselben und Leistungswandlungsvorrichtung
JP2020518228A JP6952889B2 (ja) 2018-05-09 2019-04-19 パワー半導体モジュール及びその製造方法並びに電力変換装置
CN201980029908.6A CN112074954B (zh) 2018-05-09 2019-04-19 功率半导体模块及其制造方法以及电力变换装置

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JP2018090488 2018-05-09
JP2018-090488 2018-05-09

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WO2019216161A1 WO2019216161A1 (fr) 2019-11-14
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JP7308793B2 (ja) * 2020-05-28 2023-07-14 三菱電機株式会社 半導体装置
CN115148709B (zh) * 2022-06-28 2023-06-23 爱微(江苏)电力电子有限公司 电池组的电子式初始充电用功率模块及其的制造方法

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JP2006032774A (ja) * 2004-07-20 2006-02-02 Denso Corp 電子装置
JP4380511B2 (ja) * 2004-11-29 2009-12-09 株式会社デンソー リードフレーム
JP5099243B2 (ja) * 2010-04-14 2012-12-19 株式会社デンソー 半導体モジュール
JP2012104633A (ja) * 2010-11-10 2012-05-31 Mitsubishi Electric Corp 半導体装置
EP2894952B1 (fr) * 2012-09-07 2018-06-06 Mitsubishi Electric Corporation Dispositif à semi-conducteur de puissance
JP2014195039A (ja) * 2013-02-26 2014-10-09 Tokai Rika Co Ltd 電子部品の接続構造
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CN112074954A (zh) 2020-12-11
WO2019216161A1 (fr) 2019-11-14

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