WO2021100199A1 - Dispositif à semi-conducteurs, son procédé de production, et dispositif de conversion de courant électrique - Google Patents

Dispositif à semi-conducteurs, son procédé de production, et dispositif de conversion de courant électrique Download PDF

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Publication number
WO2021100199A1
WO2021100199A1 PCT/JP2019/045818 JP2019045818W WO2021100199A1 WO 2021100199 A1 WO2021100199 A1 WO 2021100199A1 JP 2019045818 W JP2019045818 W JP 2019045818W WO 2021100199 A1 WO2021100199 A1 WO 2021100199A1
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WO
WIPO (PCT)
Prior art keywords
circuit pattern
conductive circuit
joint
semiconductor device
terminal
Prior art date
Application number
PCT/JP2019/045818
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English (en)
Japanese (ja)
Inventor
哲 根岸
晃久 福本
仁 上村
吉典 横山
悠策 伊藤
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2021558142A priority Critical patent/JP7237192B2/ja
Priority to PCT/JP2019/045818 priority patent/WO2021100199A1/fr
Publication of WO2021100199A1 publication Critical patent/WO2021100199A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor device, a manufacturing method thereof, and a power conversion device.
  • the terminal includes an external output terminal for outputting the controlled power to the outside.
  • an external output terminal for outputting the controlled power to the outside.
  • Patent Document 1 proposes an external output terminal provided with a protrusion mounted on an insulating substrate. By making the external output terminal self-supporting by the protrusions, the jig that was conventionally required is eliminated, and the joining process is simplified and the yield is improved.
  • One or more supports are connected to the joint and are located in a region other than the region where the joint is joined in the conductive circuit pattern in such a manner that they are in contact with the conductive circuit pattern, and the joint layer is interposed. Maintain the distance between the junction surface of the body and the conductive circuit pattern.
  • the terminal includes a joint including the joint surface and one or more supports that maintain a distance between the joint surface and the conductive circuit pattern, whereby the joint layer is provided.
  • the distance between the joint body and the conductive circuit pattern corresponding to the thickness of the joint layer is maintained, and the thickness of the joint layer becomes a desired thickness.
  • the reliability of the joint portion between the terminal and the conductive circuit pattern can be ensured, which contributes to the extension of the life of the semiconductor device. it can.
  • FIG. It is a top view which shows an example of the terminal applied to the semiconductor device in the same embodiment. It is a front view which shows an example of the terminal applied to the semiconductor device in the same embodiment. It is a side view which shows an example of the terminal applied to the semiconductor device in the same embodiment. It is a perspective view which shows an example of the terminal applied to the semiconductor device in the same embodiment. It is sectional drawing which shows one step of the manufacturing method of the semiconductor device in the same embodiment. It is sectional drawing which shows the process performed after the process shown in FIG. 6 in the same embodiment. It is sectional drawing which shows the process performed after the process shown in FIG. 7 in the same embodiment.
  • the insulating substrate 5 includes an insulating substrate main body 7, conductive circuit patterns 9a, 9b, 9c, and a heat radiating material 11.
  • the insulating substrate 5 has a first main surface and a second main surface that face each other.
  • the conductive circuit pattern 9a, the conductive circuit pattern 9b, and the conductive circuit pattern 9c are arranged on the side of the first main surface of the substrate main body 7 at intervals.
  • the heat radiating material 11 is arranged on the side of the second main surface of the substrate body 7.
  • the conductive circuit patterns 9a, 9b, 9c may be formed of a conductive material, and for example, a metal material such as copper (Cu) or aluminum (Al) is preferable.
  • the conductive material does not have to be a single conductive material and may be formed from, for example, an alloy. Further, the conductive circuit patterns 9a, 9b, 9c may have a multi-layer structure.
  • the heat radiating material 11 is joined to the base plate 3 by, for example, solder.
  • the heat radiating material 11 and the base plate 3 may be integrally formed of, for example, the same member.
  • heat radiating material 11 and the base plate 3 are formed of a single member, heat is dissipated without passing through the joint portion between the heat radiating material 11 and the base plate 3, as compared with the case where the heat radiating material 11 and the base plate 3 are formed of different members. Will be done. Therefore, the heat radiating material 11 and the base plate 3 formed of a single member are more preferable because the thermal resistance from the semiconductor element 15 to the back surface of the base plate 3 can be reduced.
  • the bonding layer 17 may be a conductive material, and a metal material such as solder, sintered silver (Ag), or sintered copper (Cu) is preferable.
  • the conductive material does not have to be a single conductive material and may be formed from, for example, an alloy. Further, the bonding layer 17 may have a multilayer structure.
  • the bonding layer 17 is, for example, solder
  • the bonding layer 17 solder
  • the thickness of the bonding layer 17 corresponds to the distance between the bonding surface 23a of the bonding body 23 and the conductive circuit pattern 9c. This thickness (distance) is preferably constant over the entire joint surface 23a.
  • the support 25 is arranged so as to be in contact with the conductive circuit pattern 9c.
  • the distance L (see FIG. 10) between the joint surface 23a and the conductive circuit pattern 9c is maintained in a state where the support 25 is in contact with the conductive circuit pattern 9c. That is, the support 25 has a function of holding a distance corresponding to the thickness of the bonding layer 17 at a constant distance.
  • a film may be appropriately formed on the surface of the conductive circuit pattern 9b by plating or the like, depending on the material to be the bonding material 13.
  • a silver (Ag) sintered body or a copper (Cu) sintered body is used as the material of the bonding material 13 13
  • appropriate pressure is applied to the surface of the semiconductor element 15 at the time of bonding to assist the bonding. You may try to do it.
  • the semiconductor element 15 and the conductive circuit pattern 9a are electrically connected by the conductive wire 19a using a wire bonding device (not shown).
  • the semiconductor element 15 and the conductive circuit pattern 9c are electrically connected by the conductive wire 19b.
  • the conductive wire 19a is joined to, for example, the gate electrode or sense (neither shown) of the semiconductor element 15.
  • the conductive wire 19b is joined to an electrode (not shown) from which the current of the semiconductor element 15 is output.
  • a frame may be bonded to the electrode to which the current is output.
  • the insulating substrate 5 on which the semiconductor element 15 is mounted is joined to the base plate 3.
  • a bonding material such as solder is placed on the base plate 3.
  • the insulating substrate 5 is placed on the bonding material using, for example, a jig (not shown).
  • the base plate 3 is put into a high-temperature furnace such as a reflow furnace, and the solder is melted in the high-temperature furnace. By solidifying the molten solder, the insulating substrate 5 is joined to the base plate 3.
  • each of the conductive circuit patterns 9a, 9b, and 9c is electrically connected to the outside.
  • a connection mode a direct coupling may be used in which the terminals and the conductive circuit pattern are bonded by a bonding layer using terminals.
  • indirect joining may be used in which the terminal and the conductive circuit pattern are joined via a wire.
  • the case 31 is filled with the insulating sealing material 33 for insulating sealing.
  • an insulating sealing material 33 such as gel or epoxy resin is filled so that no bubbles remain.
  • a high temperature treatment is appropriately performed to cure the insulating sealing material 33.
  • a lid (not shown) that covers the insulating sealing material 33 may be attached.
  • a lid such as PPS may be adhered to the case 31 using a silicone resin.
  • the shape of the external connection body 27 of the terminal 21 may be changed by bending the external connection body 27 of the terminal 21 according to the connection specifications with the outside, for example. In this way, the semiconductor device 1 shown in FIG. 1 is completed.
  • the support 25 also functions as a heat dissipation path. As shown in FIG. 14, the heat generated in the joint layer 17 is dissipated through three paths including the first heat dissipation path P1 and the second heat dissipation path P2 plus the third heat dissipation path P3.
  • the third heat dissipation path P3 flows from the joint layer 17 through the joint 23, then through the support 25, and from the support 25 through the portion of the conductive circuit pattern 9c located directly below the support 25, and flows through the base. This is a heat dissipation path that flows to the plate 3.
  • the support 25 becomes a part of the third heat dissipation path P3 and can contribute to the heat dissipation of the bonding layer 17.
  • the temperature of the bonding layer 17 can be effectively lowered.
  • the thermal stress generated in the bonding layer 17 and the like can be alleviated, and the deformation of the peripheral portion of the bonding layer 17 can be suppressed. As a result, it is possible to contribute to extending the life of the semiconductor device 1.
  • the number of supports 25 is not limited to one, and terminals 21 having a plurality of supports 25 may be applied. As shown in FIGS. 18, 19 and 20, for example, a terminal provided with three supports 25, a support 25a and 25b as the first part of the support and a support 25c as the second part of the support. 21 may be applied.
  • Embodiment 2 The semiconductor device according to the second embodiment will be described. As shown in FIG. 21, in the semiconductor device 1, the bonding layer 17 is formed so as to surround the support 25 from a region where the bonding 23 is bonded to the conductive circuit pattern 9c to a region where the support 25 is located. There is. Since the other configurations are the same as those of the semiconductor device 1 shown in FIG. 1 and the like, the same members are designated by the same reference numerals, and the description thereof will not be repeated unless necessary.
  • the power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300, converts the DC power supplied from the power supply 100 into AC power, and supplies the AC power to the load 300. As shown in FIG. 28, the power conversion device 200 has a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. And have.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

Par rapport à un dispositif à semi-conducteurs (1) selon la présente invention, un élément semi-conducteur (15) est monté sur un substrat isolant (5). Le substrat isolant (5) comprend : un corps principal de substrat isolant (7) ; des motifs de circuit conducteur (9a, 9b, 9c) ; et un matériau de dissipation de chaleur (11). L'élément semi-conducteur (15) est lié au motif de circuit conducteur (9b), tout en étant électriquement connecté au motif de circuit conducteur (9c). Une borne (21) comprend un corps de liaison (23), un corps de support (25) et un corps de connexion externe (27). Le corps de liaison (23) est lié au motif de circuit conducteur (9c) au moyen d'une couche de liaison (17). Le corps de support (25) est agencé de manière à être en contact avec le motif de circuit conducteur (9c). Une surface de liaison (23a) du corps de liaison (23) et le motif de circuit conducteur (9c) sont maintenus à une certaine distance au moyen du corps de support (25). L'épaisseur de la couche de liaison (17) correspond à la distance.
PCT/JP2019/045818 2019-11-22 2019-11-22 Dispositif à semi-conducteurs, son procédé de production, et dispositif de conversion de courant électrique WO2021100199A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2021558142A JP7237192B2 (ja) 2019-11-22 2019-11-22 半導体装置およびその製造方法ならびに電力変換装置
PCT/JP2019/045818 WO2021100199A1 (fr) 2019-11-22 2019-11-22 Dispositif à semi-conducteurs, son procédé de production, et dispositif de conversion de courant électrique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2019/045818 WO2021100199A1 (fr) 2019-11-22 2019-11-22 Dispositif à semi-conducteurs, son procédé de production, et dispositif de conversion de courant électrique

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WO2021100199A1 true WO2021100199A1 (fr) 2021-05-27

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017188528A (ja) * 2016-04-04 2017-10-12 三菱電機株式会社 半導体装置
JP2018160618A (ja) * 2017-03-23 2018-10-11 株式会社三社電機製作所 外部導出用自立端子及び半導体モジュールの製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7238277B2 (ja) 2018-06-14 2023-03-14 富士電機株式会社 半導体装置、リードフレーム及び半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017188528A (ja) * 2016-04-04 2017-10-12 三菱電機株式会社 半導体装置
JP2018160618A (ja) * 2017-03-23 2018-10-11 株式会社三社電機製作所 外部導出用自立端子及び半導体モジュールの製造方法

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