CN113646876A - 功率半导体模块以及电力变换装置 - Google Patents
功率半导体模块以及电力变换装置 Download PDFInfo
- Publication number
- CN113646876A CN113646876A CN201980094857.5A CN201980094857A CN113646876A CN 113646876 A CN113646876 A CN 113646876A CN 201980094857 A CN201980094857 A CN 201980094857A CN 113646876 A CN113646876 A CN 113646876A
- Authority
- CN
- China
- Prior art keywords
- power semiconductor
- metal member
- bonding layer
- electrode
- semiconductor module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 271
- 238000006243 chemical reaction Methods 0.000 title claims description 41
- 229910052751 metal Inorganic materials 0.000 claims abstract description 164
- 239000002184 metal Substances 0.000 claims abstract description 164
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 239000002082 metal nanoparticle Substances 0.000 claims description 54
- 230000017525 heat dissipation Effects 0.000 claims description 41
- 239000004020 conductor Substances 0.000 claims description 40
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 claims description 9
- 229910016570 AlCu Inorganic materials 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 233
- 238000004519 manufacturing process Methods 0.000 description 22
- 238000000034 method Methods 0.000 description 22
- 239000010949 copper Substances 0.000 description 18
- 238000007789 sealing Methods 0.000 description 15
- 238000005304 joining Methods 0.000 description 14
- 239000002105 nanoparticle Substances 0.000 description 12
- 238000010438 heat treatment Methods 0.000 description 11
- 238000005245 sintering Methods 0.000 description 10
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 239000007769 metal material Substances 0.000 description 9
- 229910052709 silver Inorganic materials 0.000 description 9
- 239000004332 silver Substances 0.000 description 9
- 230000002250 progressing effect Effects 0.000 description 8
- 239000011347 resin Substances 0.000 description 8
- 229920005989 resin Polymers 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 7
- 238000005336 cracking Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 230000008646 thermal stress Effects 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 6
- 230000035882 stress Effects 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- FOIXSVOLVBLSDH-UHFFFAOYSA-N Silver ion Chemical compound [Ag+] FOIXSVOLVBLSDH-UHFFFAOYSA-N 0.000 description 5
- 239000000945 filler Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000003566 sealing material Substances 0.000 description 3
- 239000004925 Acrylic resin Substances 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 2
- 239000004734 Polyphenylene sulfide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229920000069 polyphenylene sulfide Polymers 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052810 boron oxide Inorganic materials 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 239000011575 calcium Substances 0.000 description 1
- -1 calcium nitride Chemical class 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical compound O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920006122 polyamide resin Polymers 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229920002803 thermoplastic polyurethane Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/0219—Material of the auxiliary member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05666—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29347—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
- H01L2224/48491—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being an additional member attached to the bonding area through an adhesive or solder, e.g. buffer pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/495—Material
- H01L2224/49505—Connectors having different materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83053—Bonding environment
- H01L2224/83054—Composition of the atmosphere
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83053—Bonding environment
- H01L2224/83054—Composition of the atmosphere
- H01L2224/83075—Composition of the atmosphere being inert
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/83424—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83447—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/85424—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85447—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Dispersion Chemistry (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Die Bonding (AREA)
- Inverter Devices (AREA)
Abstract
功率半导体模块(1)具备电路基板(10)、包含半导体基板(20)的功率半导体元件(19)以及至少一个接合部(5)。至少一个接合部(5)包含远离半导体基板(20)的第1金属构件(12)、靠近半导体基板(20)的第2金属构件(23)以及将第1金属构件(12)和第2金属构件(23)互相接合的接合层(15)。在同一温度下,第1金属构件(12)的0.2%屈服强度比第2金属构件(23)的0.2%屈服强度更小,并且比接合层(15)的剪切强度更小。
Description
技术领域
本发明涉及功率半导体模块及电力变换装置。
背景技术
日本特开2008-41707号公报(专利文献1)公开了具备半导体元件、金属基板和将半导体元件接合到金属基板的接合层的半导体装置。在该半导体装置中,在同一温度下,接合层的0.2%屈服强度等于金属基板的0.2%屈服强度或者更大。
现有技术文献
专利文献
专利文献1:日本特开2008-41707号公报
发明内容
本发明的目的是延长功率半导体模块及电力变换装置的寿命。
用于解决课题的手段
本发明的功率半导体模块具备电路基板、包含半导体基板的功率半导体元件以及至少一个接合部。至少一个接合部包含远离半导体基板的第1金属构件、靠近半导体基板的第2金属电路构件以及将第1金属构件和第2金属构件互相接合的接合层。在同一温度下,第1金属构件的0.2%屈服强度比第2金属构件的0.2%屈服强度更小,并且比接合层的剪切强度更小。
本发明的电力变换装置具备主变换电路和控制电路。主变换电路具有本发明的功率半导体模块,并且被构成为将所输入的电力进行变换并输出。控制电路被构成为将控制主变换电路的控制信号输出到主变换电路。
发明效果
第1金属构件的0.2%屈服强度比第2金属构件的0.2%屈服强度更小,并且比接合层的剪切强度更小。因此,即使对功率半导体模块施加冷热循环,也会在远离半导体基板的第1金属构件中选择性地产生裂纹。通过接合层,防止该裂纹进展到功率半导体元件中。能够防止在功率半导体元件中发生裂纹。根据本发明的功率半导体模块及电力变换装置,能够延长功率半导体模块及电力变换装置的寿命。
附图说明
图1是实施方式1的功率半导体模块的概要平面图。
图2是实施方式1的功率半导体模块的在图1中所示出的剖面线II-II中的概要剖面图。
图3是示出实施方式1的功率半导体模块的制造方法的一个工序的概要剖面图。
图4是示出实施方式1的功率半导体模块的制造方法中的在图3中所示出的工序的后继工序的概要剖面图。
图5是示出实施方式1的功率半导体模块的制造方法中的在图4中所示出的工序的后继工序的概要剖面图。
图6是示出实施方式1的功率半导体模块的制造方法中的在图5中所示出的工序的后继工序的概要剖面图。
图7是示出实施方式1的功率半导体模块的制造方法中的在图6中所示出的工序的后继工序的概要剖面图。
图8是实施方式2的功率半导体模块的概要剖面图。
图9是实施方式3的功率半导体模块的概要平面图。
图10是实施方式3的功率半导体模块的在图9中所示出的剖面线X-X中的概要剖面图。
图11是实施方式4的功率半导体模块的概要剖面图。
图12是示出实施方式5的电力变换系统的结构的框图。
(附图标记说明)
1、1b、1c、1d:功率半导体模块;5:第1接合部;6:第2接合部;7:第3接合部;10电路基板;11:绝缘基板;11a:第1主面;11b:第2主面;12:电路图案;13:背面导体层;15:第1接合层;19:功率半导体元件;20:半导体基板;21:栅电极;22:源电极;23:漏电极;24:绝缘膜;25、26、27:引线端子;28、29:导电导线;30:壳;31:散热构件;31a:第3主面;31b:第4主面;31f:凸片;32:金属覆盖层;35:焊料层;35b:第2接合层;37:外围体;38:密封构件;41:导电焊盘;42:基底层;43:第3接合层;100:电源;200:电力变换装置;201:主变换电路;202:半导体模块;203:控制电路;300:负载。
具体实施方式
以下,说明本发明的实施方式。另外,对同样的结构附加同样的参照编号,不重复其说明。
实施方式1.
参照图1及图2,说明实施方式1的功率半导体模块1。功率半导体模块1主要具备电路基板10、功率半导体元件19以及至少一个接合部(第1接合部5)。
电路基板10包含电路图案12。电路基板10也可以进一步包含绝缘基板11。电路基板10也可以进一步包含背面导体层13。
绝缘基板11包含与功率半导体元件19相向的第1主面11a以及与第1主面11a相反侧的第2主面11b。绝缘基板11例如由氧化铝(Al2O3)、氮化铝(AlN)、氮化硅(Si3N4)、二氧化硅(SiO2)或氮化硼(BN)这样的无机陶瓷材料形成。绝缘基板11也可以是玻璃环氧基板这样的绝缘树脂基板。
电路图案12设置于绝缘基板11的第1主面11a之上。电路图案12例如由Al、AlSi、AlCu或AlSiCu这样的导电性金属材料形成。电路图案12例如也可以具有0.1mm以上且1.0mm以下的厚度。背面导体层13设置于绝缘基板11的第2主面11b之上。背面导体层13未特别限定,由Al箔和Cu箔互相层叠的金属层叠体形成。背面导体层13的Al箔设置于背面导体层13的Cu箔与绝缘基板11之间。背面导体层13也可以是单层。背面导体层13例如也可以具有0.1mm以上且0.6mm以下的厚度。
功率半导体元件19未特别限定,是纵向型的金属氧化物半导体场效应晶体管(MOSFET)。功率半导体元件19也可以是横向型的MOSFET或绝缘栅型双极晶体管(IGBT)等。功率半导体元件19包含半导体基板20。半导体基板20包含与电路图案12相向的第1面以及与第1面相反侧的第2面。第1面也可以是半导体基板20的背面,第2面也可以是半导体基板20的正面。半导体基板20例如由硅(Si)、或者炭化硅(SiC)、氮化钙(GaN)或金刚石这样的宽能带隙半导体材料形成。
功率半导体元件19还包含与电路图案12相向的第1电极。第1电极也可以是漏电极23。第1电极(漏电极23)设置于半导体基板20的第1面之上。功率半导体元件19还包含设置于远离电路基板10的一侧的第2电极。第2电极也可以包含栅电极21和源电极22。第2电极(栅电极21及源电极22)设置于半导体基板20的第2面之上。第1电极(漏电极23)及第2电极(栅电极21及源电极22)由AlSi、AlCu、AlSiCu或Cu这样的导电性金属材料形成。第1电极(漏电极23)及第2电极(栅电极21及源电极22)例如也可以具有2μm以上且10μm以下的厚度。
也可以在与半导体基板20相向的第2电极(栅电极21及源电极22)的表面之上,设置Ti层这样的阻挡金属层(未图示)。也可以在半导体基板20与第1电极(漏电极23)之间,设置NiSi膜这样的硅化物膜。
功率半导体元件19也可以进一步包含绝缘膜24。绝缘膜24设置于半导体基板20的第2面之上。绝缘膜24形成于第2电极(栅电极21及源电极22)的外缘上以及栅电极21与源电极22之间。绝缘膜24提高栅电极21与源电极22之间的电绝缘性。绝缘膜24例如由聚酰亚胺这样的绝缘性树脂形成。
功率半导体元件19装载于电路图案12之上。功率半导体元件19通过第1接合层15接合到电路图案12。具体地,功率半导体元件19的第1电极(漏电极23)通过第1接合层15接合到电路图案12。
至少一个接合部包含远离半导体基板20的第1金属构件、靠近半导体基板20的第2金属构件以及将第1金属构件和第2金属构件互相接合的接合层。具体地,至少一个接合部包含第1接合部5。第1金属构件是电路图案12,第2金属构件是第1电极(漏电极23),接合层是第1接合层15。也就是说,第1接合部5包含远离半导体基板20的电路图案12、靠近半导体基板20的第1电极(漏电极23)以及将电路图案12和第1电极(漏电极23)互相接合的第1接合层15。
在同一温度下,第1金属构件(电路图案12)的0.2%屈服强度比第2金属构件(第1电极(漏电极23))的0.2%屈服强度更小。在表1中示出在室温下测量的金属材料的0.2%屈服强度。在表1中,AlSi(Si 1wt%)是包含1重量%的Si的AlSi合金。AlCu(Cu 0.5wt%)是包含0.5重量%的Cu的AlCu合金。AlSiCu(Si 1wt%、Cu 0.5wt%)是包含1重量%的Si和0.5重量%的Cu的AlSiCu合金。一般地,材料的0.2%屈服强度是材料的拉伸破坏强度的指标。第1金属构件的0.2%屈服强度与第2金属构件的0.2%屈服强度之间的大小关系在功率半导体模块1的使用温度范围(例如,-55℃以上且小于300℃)中不变。在本说明书中,功率半导体模块1的使用温度范围的意思是功率半导体元件19的工作中或停止中的功率半导体模块1的温度范围。
[表1]
按照表1,能够适用于第1金属构件(电路图案12)和第2金属构件(第1电极(漏电极23))的金属材料的组合的例子如下。在第1金属构件(电路图案12)由Al形成的情况下,第2金属构件(第1电极(漏电极23))能够由AlSi、AlCu、AlSiCu或Cu形成。在第1金属构件(电路图案12)由AlSi形成的情况下,第2金属构件(第1电极(漏电极23))能够由AlCu、AlSiCu或Cu形成。在第1金属构件(电路图案12)由AlCu形成的情况下,第2金属构件(第1电极(漏电极23))能够由AlSiCu或Cu形成。在第1金属构件(电路图案12)由AlSiCu形成的情况下,第2金属构件(第1电极(漏电极23))能够由Cu形成。在本实施方式的一例中,第1金属构件(电路图案12)由Al形成,在室温下具有30MPa的0.2%屈服强度,第2金属构件(第1电极(漏电极23))由AlSi(Si 1wt%)形成,在室温下具有45MPa的0.2%屈服强度。
在同一温度下,第1金属构件(电路图案12)的0.2%屈服强度比接合层(第1接合层15)的剪切强度更小。特定地,在同一温度下,第2金属构件(第1电极(漏电极23))的0.2%屈服强度也可以比接合层(第1接合层15)的剪切强度更大。接合层(第1接合层15)未特别限定,也可以由金属纳米粒子烧结体形成。金属纳米粒子例如具有10nm以下的直径。由金属纳米粒子烧结体形成的接合层(第1接合层15)不包含0.1μm以上的空隙。金属纳米粒子烧结体例如通过将银纳米粒子或铜纳米粒子这样的金属纳米粒子在空气气氛或氮气氛中以300℃以下的低温进行烧结得到。
在本实施方式的一例中,第1金属构件(电路图案12)由Al形成,在室温下具有30MPa的0.2%屈服强度,接合层(第1接合层15)由银纳米粒子烧结体形成,在室温下具有大于30MPa且40MPa以下的剪切强度。具有大于30MPa且40MPa以下的剪切强度的银纳米粒子烧结体例如通过将银纳米粒子以250℃以上且300℃以下的温度进行烧结得到。另外,第1金属构件的0.2%屈服强度与接合层(第1接合层15)的剪切强度之间的大小关系在功率半导体模块1的使用温度范围(例如,-55℃以上且小于300℃)中不变。
如果金属纳米粒子的烧结温度产生变化,则金属纳米粒子烧结体的致密度(孔隙率)也变化。因此,通过调整金属纳米粒子的烧结温度,能够调整金属纳米粒子烧结体的剪切强度。如果在烧结金属纳米粒子时对银纳米粒子所施加的载荷产生变化,则金属纳米粒子烧结体的致密度(孔隙率)也变化。因此,也可以通过调整该载荷来调整金属纳米粒子烧结体的剪切强度。
接合层(第1接合层15)例如可以具有20μm以上的厚度,也可以具有35μm以上的厚度。因此,接合层(第1接合层15)的机械强度提高,能够抑制在接合层(第1接合层15)中产生裂纹。即使对功率半导体模块1施加冷热循环,也能够在远离半导体基板20的第1金属构件(电路图案12)中选择性地产生裂纹。接合层(第1接合层15)例如也可以具有100μm以下的厚度,也可以具有50μm以下的厚度。没有必要形成特别的接合层(第1接合层15),因此能够抑制功率半导体模块1的成本的上升。
功率半导体模块1也可以进一步具备引线端子25、26、27。引线端子25、26、27例如由Cu或Al这样的金属材料形成。引线端子25、26、27接合到电路图案12。特定地,引线端子25、26、27超声波接合到电路图案12。引线端子26经由电路图案12电连接到功率半导体元件19的第1电极(漏电极23)。引线端子26也可以是漏极端子。
功率半导体模块1也可以进一步具备导电导线28、29。导电导线28、29由Al、Cu这样的金属材料形成。导电导线28、29也可以由互相相同的金属材料形成。例如,导电导线28,29也可以由Al形成。导电导线28、29也可以由互相不同的材料形成。导电导线28也可以由Cu形成,导电导线29也可以由Al形成。
引线端子25经由导电导线28电连接到功率半导体元件19的第2电极(栅电极21)。引线端子25也可以是栅极端子。引线端子27经由导电导线29电连接到功率半导体元件19的第2电极(源电极22)。引线端子27也可以是源极端子。在功率半导体元件19中,流过源电极22的电流比流过栅电极21的电流更大。因此,导电导线29也可以具有比导电导线28更大的直径。导电导线29的根数也可以比导电导线28的根数更多。
功率半导体模块1也可以进一步具备壳30。壳30收容功率半导体元件19及电路基板10。壳30也可以包含散热构件31和外围体37。电路基板10接合到散热构件31。散热构件31使在功率半导体元件19中发生的热向功率半导体模块1的外部扩散。散热构件31例如也可以由铝这样的金属材料形成。
具体地,散热构件31包含面向电路基板10的第3主面31a以及与第3主面31a相反侧的第4主面31b。在散热构件31的第3主面31a之上设置有金属覆盖层32。金属覆盖层32也可以是Ni-P镀层。电路基板10的背面导体层13和金属覆盖层32互相通过焊料层35接合。焊料层35例如也可以由SnAgCu系无铅焊料形成。散热构件31也可以包含多个凸片31f。多个凸片31f从第4主面31b突出。多个凸片31f使散热构件31的散热能力增加。
外围体37使用螺钉这样的固定构件或粘接剂固定到散热构件31。外围体37也可以由聚苯硫醚(PPS)树脂、环氧树脂、聚酰亚胺树脂或丙烯酸树脂这样的绝缘性树脂形成。
在壳30的内侧空间的至少一部分中设置密封构件38。密封构件38密封功率半导体元件19。密封构件38也可以进一步地密封连接到电路图案12的引线端子25、26、27的端部。密封构件38也可以进一步密封电路基板10。密封构件38例如也可以由硅酮树脂、环氧树脂、氨基甲酸乙酯树脂、聚酰亚胺树脂、聚酰胺树脂或丙烯酸树脂这样的绝缘性树脂形成。
密封构件38也可以包含微粒这样的填料。填料也可以分散在绝缘树脂中。填料例如也可以由二氧化硅(SiO2)、氧化铝(Al2O3)、氮化铝(AlN)、氮化硼(BN)、氮化硅(Si3N4)、金刚石(C)、炭化硅(SiC)或氧化硼(B2O3)这样的无机陶瓷材料形成。通过在绝缘树脂中添加填料,能够调整密封构件38的热膨胀系数。填料也可以具有比作为密封构件38的主成分的绝缘树脂材料更高的热传导率,也可以提高密封构件38的热传导性。
参照图1至图7,说明实施方式1的功率半导体模块1的制造方法。
如图3所示,本实施方式的功率半导体模块1的制造方法具备:使用第1接合层15,将功率半导体元件19接合到电路图案12。具体地,在电路图案12之上,涂敷银纳米粒子膏这样的金属纳米粒子膏。金属纳米粒子膏例如具有20μm以上100μm的厚度。将金属纳米粒子膏例如以100℃以上且200℃以下的第1温度临时烧结,得到金属纳米粒子临时烧结体。
将功率半导体元件19放置在金属纳米粒子临时烧结体之上。功率半导体元件19的第1电极(漏电极23)接触金属纳米粒子临时烧结体。对功率半导体元件19施加载荷,相对于金属纳米粒子临时烧结体将功率半导体元件19进行定位。该载荷例如是1MPa以上且10MPa以下。停止对功率半导体元件19施加载荷。将金属纳米粒子临时烧结体例如以比第1温度更高的第2温度进行烧结,得到由金属纳米粒子烧结体形成的第1接合层15。第2温度例如也可以是300℃以下,也可以是250℃以下。在第2温度下的烧结时间例如是5分钟以上且60分钟以下。由此,功率半导体元件19的第1电极(漏电极23)使用第1接合层15接合到电路图案12。
如图4所示,本实施方式的功率半导体模块1的制造方法具备:将引线端子25、26、27接合到电路图案12。特定地,引线端子25、26、27超声波接合到电路图案12。如图5所示,本实施方式的功率半导体模块1的制造方法具备:将导电导线28、29键合到功率半导体元件19的第2电极(栅电极21及源电极22)和引线端子25、27。导电导线28、29也可以使用楔形接线机进行键合。
如图6及图7所示,本实施方式的功率半导体模块1的制造方法具备:将功率半导体元件19及电路基板10收容在壳30中。具体地,如图6所示,将电路基板10接合到散热构件31。特定地,通过焊料层35将电路基板10的背面导体层13与设置在散热构件31的第3主面31a之上的金属覆盖层32互相接合。然后,如图7所示,将外围体37固定到散热构件31。特定地,使用粘接剂及螺钉将外围体37固定到散热构件31。
然后,本实施方式的功率半导体模块1的制造方法具备:使用密封构件38密封功率半导体元件19。具体地,在壳30的内部空间的至少一部分中提供密封材料。对密封材料施行脱泡处理。对密封材料加热,使其硬化。由此,得到密封功率半导体元件19的密封构件38。密封构件38也可以进一步密封连接到电路图案12的引线端子25、26、27的端部。密封构件38也可以进一步密封电路基板10。由此,得到图1及图2所示的功率半导体模块1。
说明本实施方式的功率半导体模块1的效果。
本实施方式的功率半导体模块1具备电路基板10、包含半导体基板20的功率半导体元件19以及至少一个接合部(第1接合部5)。至少一个接合部(第1接合部5)包含远离半导体基板20的第1金属构件(电路图案12)、靠近半导体基板20的第2金属构件(第1电极(漏电极23))以及将第1金属构件(电路图案12)和第2金属构件(第1电极(漏电极23))互相接合的接合层(第1接合层15)。在同一温度下,第1金属构件(电路图案12)的0.2%屈服强度比第2金属构件(第1电极(漏电极23))的0.2%屈服强度更小,并且比接合层(第1接合层15)的剪切强度更小。
如果功率半导体元件19工作,则功率半导体模块1的温度上升,第1金属构件(电路图案12)和第2金属构件(第1电极(漏电极23))热膨胀。如果功率半导体模块1的温度上升,则可视为对第1金属构件(电路图案12)和第2金属构件(第1电极(漏电极23))施加拉伸应力。另外,在第1金属构件(电路图案12)和第2金属构件(第1电极(漏电极23))由互相不同的材料形成的情况下,第1金属构件(电路图案12)的热膨胀系数与第2金属构件(第1电极(漏电极23))的热膨胀系数不同。接合层(第1接合层15)配置在第1金属构件(电路图案12)与第2金属构件(第1电极(漏电极23))之间,因此剪切应力对接合层(第1接合层15)起作用。
第1金属构件(电路图案12)的0.2%屈服强度比第2金属构件(第1电极(漏电极23))的0.2%屈服强度更小,并且比接合层(第1接合层15)的剪切强度更小。因此,即使对功率半导体模块1施加冷热循环,也在远离半导体基板20的第1金属构件(电路图案12)中选择性地产生裂纹。通过接合层(第1接合层15),防止该裂纹进展到功率半导体元件19中。由此,能够防止在功率半导体元件19中发生裂纹。能够延长功率半导体模块1的寿命。
在本实施方式的功率半导体模块1中,在同一温度下,第2金属构件(第1电极(漏电极23))的0.2%屈服强度也可以比接合层(第1接合层15)的剪切强度更大。因此,即使在远离半导体基板20的第1金属构件(电路图案12)中产生裂纹,第2金属构件(第1电极(漏电极23))也能够防止该裂纹进展到功率半导体元件19中。由此,能够防止在功率半导体元件19中发生裂纹。能够延长功率半导体模块1的寿命。
在本实施方式的功率半导体模块1中,电路基板10包含电路图案12。功率半导体元件19还包含与电路图案12相向的第1电极(漏电极23)。至少一个接合部包含第1接合部5。第1接合部5包含作为第1金属构件的电路图案12、作为第2金属构件的第1电极(漏电极23)以及作为接合层的第1接合层15。因此,即使对功率半导体模块1施加冷热循环,也在远离半导体基板20的电路图案12中选择性地产生裂纹。通过第1接合层15及第1电极(漏电极23),防止该裂纹进展到功率半导体元件19的半导体基板20中。由此,能够防止在功率半导体元件19中发生裂纹。能够延长功率半导体模块1的寿命。
在本实施方式的功率半导体模块1中,接合层(第1接合层15)由金属纳米粒子烧结体形成。通过调整金属纳米粒子的烧结温度等,能够调整金属纳米粒子烧结体的剪切强度。由金属纳米粒子烧结体形成的接合层(第1接合层15)能够扩展第1金属构件(电路图案12)及第2金属构件(第1电极(漏电极23))的材料的选项。因此,能够得到高性能且便宜的功率半导体模块1。
实施方式2.
参照图8,说明实施方式2的功率半导体模块1b。本实施方式的功率半导体模块1b具备与实施方式1的功率半导体模块1同样的结构,但是主要在以下方面不同。
在功率半导体模块1b中,背面导体层13是单层。在本实施方式的一例中,背面导体层13例如也可以由Cu形成。背面导体层13与实施方式1同样地也可以是层叠体。
在功率半导体模块1b中,代替金属覆盖层32及焊料层35(参照图2),使用第2接合层35b,电路基板10接合到散热构件31。第2接合层35b例如也可以具有20μm以上且100μm以下的厚度。第2接合层35b未特别限定,但是也可以由金属纳米粒子烧结体形成。金属纳米粒子例如具有10nm以下的直径。由金属纳米粒子烧结体形成的接合层(第2接合层35b)不包含0.1μm以上的空隙。金属纳米粒子烧结体例如通过将银纳米粒子或铜纳米粒子这样的金属纳米粒子在空气气氛或氮气氛中以300℃以下的低温进行烧结得到。
至少一个接合部包含第2接合部6。第2接合部6包含作为第1金属构件的散热构件31、作为第2金属构件的背面导体层13以及作为接合层的第2接合层35b。在同一温度下,第1金属构件(散热构件31)的0.2%屈服强度比第2金属构件(背面导体层13)的0.2%屈服强度更小,并且比接合层(第2接合层35b)的剪切强度更小。特定地,在同一温度下,第2金属构件(背面导体层13)的0.2%屈服强度也可以比接合层(第2接合层35b)的剪切强度更大。在本实施方式的一例中,散热构件31由Al形成,背面导体层13由Cu形成,第2接合层35b由银纳米粒子烧结体形成。在室温下的第2接合层35b(银纳米粒子烧结体)的剪切强度例如大于30MPa且在40MPa以下。
第2接合部6中的第1金属构件(散热构件31)的0.2%屈服强度也可以比第1接合部5中的第1金属构件(电路图案12)的0.2%屈服强度更低。因此,在对功率半导体模块1b施加冷热循环时,相比于第1接合部5中的第1金属构件(电路图案12),在更离开功率半导体元件19的第2接合部6中的第1金属构件(散热构件31)中更先发生裂纹。能够延长裂纹到达功率半导体元件19为止的时间。能够延长功率半导体模块1b的寿命。
接合层(第2接合层35b)例如也可以具有20μm以上的厚度,也可以具有35μm以上的厚度。因此,接合层(第2接合层35b)的机械强度提高,能够抑制在接合层(第2接合层35b)中产生裂纹。即使对功率半导体模块1b施加冷热循环,也能够在远离功率半导体元件19(半导体基板20)的第1金属构件(散热构件31)中选择性地产生裂纹。接合层(第2接合层35b)例如也可以具有100μm以下的厚度,也可以具有50μm以下的厚度。没有必要形成特别的接合层(第2接合层35b),因此能够抑制功率半导体模块1b的成本的上升。
实施方式2的功率半导体模块1b的制造方法具备与实施方式1的功率半导体模块1的制造方法同样的工序,但是在将电路基板10接合到散热构件31的工序中不同。在本实施方式的功率半导体模块1b的制造方法中,将电路基板10接合到散热构件31包含:将电路基板10的背面导体层13和散热构件31(第3主面31a)通过第2接合层35b相互地接合。
具体地,在散热构件31的第3主面31a之上,涂敷如银纳米粒子膏这样的金属纳米粒子膏。金属纳米粒子膏例如具有20μm以上100μm的厚度。将金属纳米粒子膏例如以100℃以上且200℃以下的第1温度临时烧结,得到金属纳米粒子临时烧结体。
将电路基板10的背面导体层13放置于金属纳米粒子临时烧结体之上。电路基板10的背面导体层13与金属纳米粒子临时烧结体接触。对电路基板10施加载荷,相对于金属纳米粒子临时烧结体,将电路基板10进行定位。该载荷例如是1MPa以上且10MPa以下。停止对电路基板10施加载荷。将金属纳米粒子临时烧结体例如以比第1温度更高的第2温度进行烧结,得到由金属纳米粒子烧结体形成的第2接合层35b。第2温度例如也可以是300℃以下,也可以是250℃以下。在第2温度下的烧结时间例如是5分钟以上且60分钟以下。由此,电路基板10的背面导体层13使用第2接合层35b接合到散热构件31的第3主面31a。
本实施方式的功率半导体模块1b除了实施方式1的功率半导体模块1的效果之外,还取得以下效果。
本实施方式的功率半导体模块1b还具备散热构件31。电路基板10包含绝缘基板11、电路图案12和背面导体层13。绝缘基板11包含与功率半导体元件19相向的第1主面11a和与第1主面11a相反侧的第2主面11b。电路图案12设置于绝缘基板11的第1主面11a之上。背面导体层13设置于绝缘基板11的第2主面11b之上。至少一个接合部包含第2接合部6。第2接合部6包含作为第1金属构件的散热构件31、作为第2金属构件的背面导体层13和作为接合层的第2接合层35b。
如果功率半导体元件19工作,则功率半导体模块1b的温度上升,第1金属构件(散热构件31)和第2金属构件(背面导体层13)热膨胀。如果功率半导体模块1b的温度上升,则可视为对第1金属构件(散热构件31)和第2金属构件(背面导体层13)施加拉伸应力。另外,在第1金属构件(散热构件31)和第2金属构件(背面导体层13)由互相不同的材料形成的情况下,第1金属构件(散热构件31)的热膨胀系数与第2金属构件(背面导体层13)的热膨胀系数不同。接合层(第2接合层35b)配置在第1金属构件(散热构件31)与第2金属构件(背面导体层13)之间,因此剪切应力对接合层(第2接合层35b)起作用。
第1金属构件(散热构件31)的0.2%屈服强度比第2金属构件(背面导体层13)的0.2%屈服强度更小,并且比接合层(第2接合层35b)的剪切强度更小。因此,即使对功率半导体模块1b施加冷热循环,也在远离半导体基板20的第1金属构件(散热构件31)中选择性地产生裂纹。通过接合层(第2接合层35b)及第2金属构件(背面导体层13),防止该裂纹进展到功率半导体元件19中。由此,能够防止在功率半导体元件19中发生裂纹。能够延长功率半导体模块1b的寿命。
在本实施方式的功率半导体模块1b中,在同一温度下,第2金属构件(背面导体层13)的0.2%屈服强度也可以比接合层(第2接合层35b)的剪切强度更大。因此,即使在远离半导体基板20的第1金属构件(散热构件31)中产生裂纹,第2金属构件(背面导体层13)也能够防止该裂纹进展到功率半导体元件19中。由此,能够防止在功率半导体元件19中发生裂纹。能够延长功率半导体模块1b的寿命。
在本实施方式的功率半导体模块1b中,功率半导体元件19还包含与电路图案12相向的第1电极(漏电极23)。至少一个接合部还包含第1接合部5。第1接合部5包含作为第1金属构件的电路图案12、作为第2金属构件的第1电极(漏电极23)和作为接合层的第1接合层15。
也就是说,功率半导体模块1b具备多个接合部(第1接合部5、第2接合部6)。多个接合部(第1接合部5、第2接合部6)的各个包含远离半导体基板20的第1金属构件(电路图案12、散热构件31)、靠近半导体基板20的第2金属构件(第1电极(漏电极23)、背面导体层13)以及将第1金属构件(电路图案12、散热构件31)和第2金属构件(第1电极(漏电极23)、背面导体层13)互相接合的接合层(第1接合层15、第2接合层35b)。在同一温度下,第1金属构件(电路图案12、散热构件31)的0.2%屈服强度比第2金属构件(第1电极(漏电极23)、背面导体层13)的0.2%屈服强度更小,并且比接合层(第1接合层15、第2接合层35b)的剪切强度更小。
因此,在功率半导体模块1b内发生的热应力及热应变能够通过多个接合部(第1接合部5及第2接合部6)负担。对多个接合部(第1接合部5及第2接合部6)的各个起作用的热应力及热应变减少。能够减少在多个接合部(第1接合部5、第2接合部6)之中的最弱部分中的裂纹的进展。能够进一步延长功率半导体模块1b的寿命。
实施方式3.
参照图9及图10说明实施方式3的功率半导体模块1c。本实施方式的功率半导体模块1c具备与实施方式1的功率半导体模块1同样的结构,但是主要在以下方面不同。
功率半导体模块1c还具备导电焊盘41。如图9所示,在俯视第2电极(源电极22)时(俯视绝缘基板11的第1主面11a时),导电焊盘41具有比第2电极(源电极22)更大的面积。因此,即使导电导线29具有比导电导线28更大的直径或者导电导线29的根数比导电导线28的根数更多,导电导线29也能够更容易地键合到导电焊盘41。
另外,导电焊盘41具有比第2电极(源电极22)更大的体积。导电焊盘41具有比第2电极(源电极22)更大的热容量。因此,在功率半导体元件19中发生的热能够从导电焊盘41扩散。导电焊盘41比第2电极(源电极22)更厚。导电焊盘41(除了基底层42以外)例如由Cu形成。导电焊盘41(除了基底层42以外)例如也可以具有0.1mm以上且2.0mm以下的厚度。
导电焊盘41包含与功率半导体元件19相向的导电焊盘部分。导电焊盘部分也可以是基底层42。导电焊盘部分(基底层42)例如由Al形成。导电焊盘41也可以由单一的金属材料形成。导电焊盘部分(基底层42)的厚度比导电焊盘41(除了基底层42以外)的厚度更小。导电焊盘部分(基底层42)例如也可以具有2μm以上且200μm以下的厚度。
至少一个接合部包含第3接合部7。第3接合部7包含作为第1金属构件的导电焊盘部分(基底层42)、作为第2金属构件的第2电极(源电极22)和作为接合层的第3接合层43。第3接合层43例如也可以具有20μm以上且100μm以下的厚度。第3接合层43未特别限定,但是也可以由金属纳米粒子烧结体形成。金属纳米粒子例如具有10nm以下的直径。由金属纳米粒子烧结体形成的接合层(第3接合层43)不包含0.1μm以上的空隙。金属纳米粒子烧结体例如通过将银纳米粒子或铜纳米粒子这样的金属纳米粒子在空气气氛或氮气氛中以300℃以下的低温进行烧结得到。
在同一温度下,第1金属构件(导电焊盘部分(基底层42))的0.2%屈服强度比第2金属构件(第2电极(源电极22))的0.2%屈服强度更小,并且比接合层(第3接合层43)的剪切强度更小。特定地,在同一温度下,第2金属构件(第2电极(源电极22))的0.2%屈服强度也可以比接合层(第3接合层43)的剪切强度更大。在本实施方式的一例中,导电焊盘部分(基底层42)由Al形成,第2电极(源电极22)由AlSi(Si 1wt%)形成,第3接合层43由银纳米粒子烧结体形成。室温下的第3接合层43(银纳米粒子烧结体)的剪切强度是大于30MPa且40MPa以下。
接合层(第3接合层43)例如也可以具有20μm以上的厚度,也可以具有35μm以上的厚度。因此,接合层(第3接合层43)的机械强度提高,能够抑制在接合层(第3接合层43)中产生裂纹。即使对功率半导体模块1c施加冷热循环,也能够在远离半导体基板20的第1金属构件(导电焊盘部分(基底层42))中选择性地产生裂纹。接合层(第3接合层43)例如也可以具有100μm以下的厚度,也可以具有50μm以下的厚度。不需要形成特别的接合层(第3接合层43),因此能够抑制功率半导体模块1c的成本的上升。
实施方式3的功率半导体模块1c的制造方法具备与实施方式1的功率半导体模块1的制造方法同样的工序,但是主要在以下方面不同。本实施方式的功率半导体模块1c的制造方法还具备:使用第3接合层43将导电焊盘41接合到功率半导体元件19。也可以在使用第1接合层15将功率半导体元件19接合到电路图案12之后,使用第3接合层43将导电焊盘41接合到功率半导体元件19。也可以在将引线端子25、26、27接合到电路图案12之前使用第3接合层43将导电焊盘41接合到功率半导体元件19。
具体地,在功率半导体元件19的第2电极(源电极22)之上,涂敷银纳米粒子膏这样的金属纳米粒子膏。金属纳米粒子膏例如具有20μm以上且100μm的厚度。将金属纳米粒子膏例如以100℃以上且200℃以下的第1温度临时烧结,得到金属纳米粒子临时烧结体。
将导电焊盘41放置于金属纳米粒子临时烧结体之上。导电焊盘部分(基底层42)接触到金属纳米粒子临时烧结体。对导电焊盘41施加载荷,相对于金属纳米粒子临时烧结体将导电焊盘41进行定位。该载荷例如是1MPa以上且10MPa以下。停止对导电焊盘41施加载荷。将金属纳米粒子临时烧结体例如以比第1温度更高的第2温度进行烧结,得到由金属纳米粒子烧结体形成的第3接合层43。第2温度例如也可以是300℃以下,也可以是250℃以下。在第2温度下的烧结时间例如是5分钟以上且60分钟以下。由此,导电焊盘41的导电焊盘部分(基底层42)使用第3接合层43接合到功率半导体元件19的第2电极(源电极22)。
本实施方式的功率半导体模块1c的制造方法具备:将导电导线29键合到导电焊盘41而不是功率半导体元件19的第2电极(源电极22)。
说明本实施方式的功率半导体模块1c的效果。
本实施方式的功率半导体模块1c还具备包含与功率半导体元件19相向的导电焊盘部分(基底层42)的导电焊盘41。功率半导体元件19还包含设置于远离电路基板10的一侧的第2电极(源电极22)。在俯视第2电极(源电极22)时,导电焊盘41具有比第2电极(源电极22)更大的面积。至少一个接合部包含第3接合部7。第3接合部7包含作为第1金属构件的导电焊盘部分(基底层42)、作为第2金属构件的第2电极(源电极22)和作为接合层的第3接合层43。
如果功率半导体元件19工作,则功率半导体模块1c的温度上升,第1金属构件(导电焊盘部分(基底层42))和第2金属构件(第2电极(源电极22))热膨胀。如果功率半导体模块1c的温度上升,则可视为对第1金属构件(导电焊盘部分(基底层42))和第2金属构件(第2电极(源电极22))施加拉伸应力。另外,在第1金属构件(导电焊盘部分(基底层42))和第2金属构件(第2电极(源电极22))由互相不同的材料形成的情况下,第1金属构件(导电焊盘部分(基底层42))的热膨胀系数与第2金属构件(第2电极(源电极22))的热膨胀系数不同。接合层(第3接合层43)配置在第1金属构件(导电焊盘部分(基底层42))与第2金属构件(第2电极(源电极22))之间,因此剪切应力对接合层(第3接合层43)起作用。
第1金属构件(导电焊盘部分(基底层42))的0.2%屈服强度比第2金属构件(第2电极(源电极22))的0.2%屈服强度更小,并且比接合层(第3接合层43)的剪切强度更小。因此,即使对功率半导体模块1c施加冷热循环,也在远离半导体基板20的第1金属构件(导电焊盘部分(基底层42))中选择性地产生裂纹。通过接合层(第3接合层43),防止该裂纹进展到功率半导体元件19中。由此,能够防止在功率半导体元件19中发生裂纹。能够延长功率半导体模块1c的寿命。
在本实施方式的功率半导体模块1c中,在同一温度下,第2金属构件(第2电极(源电极22))的0.2%屈服强度也可以比接合层(第3接合层43)的剪切强度更大。因此,即使在远离半导体基板20的第1金属构件(导电焊盘部分(基底层42))中产生裂纹,第2金属构件(第2电极(源电极22))也能够防止该裂纹进展到功率半导体元件19中。由此,能够防止在功率半导体元件19中发生裂纹。能够延长功率半导体模块1c的寿命。
在俯视第2电极(源电极22)时,导电焊盘41具有比第2电极(源电极22)更大的面积。因此,即使增大导电导线29的直径,导电导线29也能够容易地键合到导电焊盘41。通过增大导电导线29的直径,能够减少在第2电极(源电极22)与导电导线29之间的连接部中的电阻。能够减少在该连接部发生的热。能够降低在冷热循环时在功率半导体模块1c中发生的热应力及热应变。能够延长功率半导体模块1c的寿命。
导电焊盘41使在功率半导体元件19中发生的热扩散到功率半导体元件19的外部。能够降低功率半导体元件19工作时的温度。如果功率半导体元件19的温度变低,则功率半导体元件19的短路耐量提高。因此,能够延长功率半导体模块1c的寿命。
在本实施方式的功率半导体模块1c中,功率半导体元件19还包含与电路图案12相向的第1电极(漏电极23)。至少一个接合部还包含第1接合部5。第1接合部5包含作为第1金属构件的电路图案12、作为第2金属构件的第1电极(漏电极23)和作为接合层的第1接合层15。
也就是说,功率半导体模块1c具备多个接合部(第1接合部5、第3接合部7)。多个接合部(第1接合部5、第3接合部7)的各个包含远离半导体基板20的第1金属构件(电路图案12、导电焊盘部分(基底层42))、靠近半导体基板20的第2金属构件(第1电极(漏电极23)、背面导体层13)以及将第1金属构件(电路图案12、散热构件31)和第2金属构件(第1电极(漏电极23)、第2电极(源电极22))互相接合的接合层(第1接合层15、第2接合层35b)。在同一温度下,第1金属构件(电路图案12、导电焊盘部分(基底层42))的0.2%屈服强度比第2金属构件(第1电极(漏电极23)、第2电极(源电极22))的0.2%屈服强度更小,并且比接合层(第1接合层15、第3接合层43)的剪切强度更小。
因此,在功率半导体模块1c内发生的热应力及热应变能够通过多个接合部(第1接合部5及第3接合部7)负担。对多个接合部(第1接合部5及第3接合部7)的各个起作用的热应力及热应变减少。能够减少在多个接合部(第1接合部5、第3接合部7)中的最弱部分中的裂纹的进展。能够进一步延长功率半导体模块1c的寿命。
实施方式4.
参照图11说明实施方式4的功率半导体模块1d。本实施方式的功率半导体模块1d具备与实施方式2的功率半导体模块1b同样的结构,但是主要在以下方面与实施方式2的功率半导体模块1b不同。功率半导体模块1d与实施方式3同样地还具备导电焊盘41。在功率半导体模块1d中,使用实施方式3的第3接合层43将导电焊盘41接合到功率半导体元件19的第2电极(源电极22)。在功率半导体模块1d中,与实施方式3同样地,导电导线29键合到导电焊盘41。
实施方式4的功率半导体模块1d的制造方法具备与实施方式2的功率半导体模块1b的制造方法同样的工序,但是主要在以下方面不同。本实施方式的功率半导体模块1d的制造方法与实施方式3同样地,还具备:使用第3接合层43,将导电焊盘41接合到功率半导体元件19。本实施方式的功率半导体模块1d的制造方法与实施方式3同样地,包含:将导电导线29键合到导电焊盘41。
本实施方式的功率半导体模块1d除了实施方式1至实施方式3的功率半导体模块1、1b、1c的效果,还具有以下的效果。在本实施方式的功率半导体模块1d中,在功率半导体模块1d内发生的热应力及热应变能够通过多个接合部(第1接合部5、第2接合部6及第3接合部7)负担。对多个接合部(第1接合部5、第2接合部6及第3接合部7)的各个起作用的热应力及热应变减少。因此,能够减少在多个接合部(第1接合部5、第2接合部6及第3接合部7)中的最弱部分中的裂纹的进展。能够进一步延长功率半导体模块1d的寿命。
实施方式5.
本实施方式中将实施方式1至实施方式4的功率半导体模块1、1b、1c、1d中的任意功率半导体模块应用于电力变换装置。本实施方式的电力变换装置200未特别地限定,但是以下说明三相的逆变器的情况。
图12所示出的电力变换系统包括电源100、电力变换装置200、负载300。电源100是直流电源,对电力变换装置200提供直流电力。电源100未特别限定,但是例如可以包括直流系统、太阳能电池或蓄电池,也可以包括连接到交流系统的整流电路或AC/DC转换器。电源100也可以包括将从直流系统输出的直流电力变换为其他直流电力的DC/DC转换器。
电力变换装置200是连接在电源100与负载300之间的三相的逆变器,将从电源100提供的直流电力变换成交流电力,并向负载300提供交流电力。电力变换装置200如图12所示,具备将直流电力变换为交流电力并输出的主变换电路201以及将控制主变换电路201的控制信号输出到主变换电路201的控制电路203。
负载300是通过从电力变换装置200提供的交流电力驱动的三相的电动机。另外,负载300未特别地限定,是在各种电气设备中装载的电动机,例如用作面向混合动力汽车、电动汽车、铁道车辆、电梯或者空调设备的电动机。
以下说明电力变换装置200的细节。主变换电路201具备开关元件(未图示)和回流二极管(未图示)。开关元件对从电源100提供的电压进行开关,由此,主变换电路201将从电源100提供的直流电力变换为交流电力,并向负载300提供。主变换电路201的具体的电路结构是各种各样的,但是本实施方式的主变换电路201是2电平的三相全桥电路,能够包括6个开关元件以及与各个开关元件反并联的6个回流二极管。在主变换电路201的各开关元件及各回流二极管的至少某一个中,应用上述的实施方式1至实施方式4的功率半导体模块1、1b、1c、1d中的任意功率半导体模块。关于6个开关元件,将每2个开关元件进行串联连接,构成上下支路,各上下支路构成全桥电路的各相(U相、V相及W相)。然后,各上下支路的输出端子即主变换电路201的3个输出端子连接到负载300。
另外,主变换电路201具备驱动各开关元件的驱动电路(未图示)。驱动电路可以内置于半导体模块202中,也可以与半导体模块202独立地设置。驱动电路生成驱动在主变换电路201中包含的开关元件的驱动信号,向主变换电路201的开关元件的控制电极提供驱动信号。具体地,根据来自控制电路203的控制信号,向各开关元件的控制电极输出使开关元件成为接通状态的驱动信号和使开关元件成为断开状态的驱动信号。在将开关元件维持在接通状态的情况下,驱动信号是开关元件的阈值电压以上的电压信号(接通信号),在将开关元件维持在断开状态的情况下,驱动信号成为开关元件的阈值电压以下的电压信号(断开信号)。
控制电路203控制主变换电路201的开关元件,以对负载300提供期望的电力。具体地,基于对负载300应提供的电力,计算出主变换电路201的各开关元件应成为接通状态的时间(接通时间)。例如,能够通过根据应输出的电压来调制开关元件的接通时间的脉冲宽度调制(PWM)控制,控制主变换电路201。然后,对主变换电路201具备的驱动电路输出控制指令(控制信号),使得在各时间点对于应成为接通状态的开关元件输出接通信号并对于应成为断开状态的开关元件输出断开信号。驱动电路根据该控制信号,对各开关元件的控制电极输出接通信号或断开信号,作为驱动信号。
在本实施方式的电力变换装置200中,作为在主变换电路201中包含的半导体模块202,应用实施方式1至实施方式4的功率半导体模块1、1b、1c、1d中的任意功率半导体模块。因此,本实施方式的电力变换装置200具有被提高的可靠性。
在本实施方式中,说明了在2电平的三相逆变器中应用本发明的例子,但是不限于此,能够在各种各样的电力变换装置中应用。在本实施方式中设为2电平的电力变换装置,但是也可以是3电平的电力变换装置,也可以是多电平的电力变换装置。在电力变换装置对单相负载提供电力的情交下,也可以在单相的逆变器中应用本发明。在电力变换装置对直流负载等提供电力的情况下,也可以在DC/DC转换器或AC/DC转换器中应用本发明。
应用本发明的电力变换装置不限定于负载是电动机的情况,例如能够组装在放电加工机或激光加工机的电源装置、或者感应加热烹调器或非接触器供电系统的电源装置中。应用本发明的电力变换装置能够用作太阳能发电系统或蓄电系统等的功率调节器。
应当认识到,关于本次公开的实施方式1-5,在全部的方面是例示性的,而非制限性的。只要不矛盾,可以组合本次公开的实施方式1-5的至少2个。本发明的范围不是通过上述的说明而是通过权利要求书示出,意图包含与权利要求书同等含义和范围内的全部变更。
Claims (9)
1.一种功率半导体模块,具备:
电路基板;
功率半导体元件,包含半导体基板;以及
至少一个接合部,
所述至少一个接合部包含远离所述半导体基板的第1金属构件、靠近所述半导体基板的第2金属构件以及将所述第1金属构件和所述第2金属构件互相接合的接合层,
在同一温度下,所述第1金属构件的0.2%屈服强度小于所述第2金属构件的0.2%屈服强度,并且小于所述接合层的剪切强度。
2.根据权利要求1所述的功率半导体模块,其中,
在所述同一温度下,所述第2金属构件的所述0.2%屈服强度大于所述接合层的所述剪切强度。
3.根据权利要求1或2所述的功率半导体模块,其中,
所述电路基板包含电路图案,
所述功率半导体元件还包含与所述电路图案相向的第1电极,
所述至少一个接合部包含第1接合部,
所述第1接合部包含作为所述第1金属构件的所述电路图案、作为所述第2金属构件的所述第1电极以及作为所述接合层的第1接合层。
4.根据权利要求1或2所述的功率半导体模块,其中,
所述功率半导体模块还具备散热构件,
所述电路基板包含绝缘基板、电路图案和背面导体层,
所述绝缘基板包含与所述功率半导体元件相向的第1主面以及与所述第1主面相反侧的第2主面,
所述电路图案设置于所述第1主面之上,
所述背面导体层设置于所述第2主面之上,
所述至少一个接合部包含第2接合部,
所述第2接合部包含作为所述第1金属构件的所述散热构件、作为所述第2金属构件的所述背面导体层以及作为所述接合层的第2接合层。
5.根据权利要求4所述的功率半导体模块,其中,
所述功率半导体元件还包含与所述电路图案相向的第1电极,
所述至少一个接合部还包含第1接合部,
所述第1接合部包含作为所述第1金属构件的所述电路图案、作为所述第2金属构件的所述第1电极以及作为所述接合层的第1接合层。
6.根据权利要求1至5中的任一项所述的功率半导体模块,其中,
所述功率半导体模块还具备导电焊盘,该导电焊盘包含与所述功率半导体元件相向的导电焊盘部分,
所述功率半导体元件还包含设置于远离所述电路基板的一侧的第2电极,
在俯视所述第2电极时,所述导电焊盘具有大于所述第2电极的面积,
所述至少一个接合部包含第3接合部,
所述第3接合部包含作为所述第1金属构件的所述导电焊盘部分、作为所述第2金属构件的所述第2电极以及作为所述接合层的第3接合层。
7.根据权利要求1至6中的任一项所述的功率半导体模块,其中,
所述接合层由金属纳米粒子烧结体形成。
8.根据权利要求1至7中的任一项所述的功率半导体模块,其中,
所述第1金属构件由Al形成,
所述第2金属构件由AlSi、AlCu、AlSiCu或Cu形成。
9.一种电力变换装置,具备:
主变换电路,具有权利要求1至8中的任一项所述的所述功率半导体模块,并且该主变换电路将所输入的电力进行变换而输出;以及
控制电路,将控制所述主变换电路的控制信号输出到所述主变换电路。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2019/015471 WO2020208713A1 (ja) | 2019-04-09 | 2019-04-09 | パワー半導体モジュール及び電力変換装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN113646876A true CN113646876A (zh) | 2021-11-12 |
Family
ID=72750639
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201980094857.5A Pending CN113646876A (zh) | 2019-04-09 | 2019-04-09 | 功率半导体模块以及电力变换装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US11908822B2 (zh) |
JP (1) | JP7126609B2 (zh) |
CN (1) | CN113646876A (zh) |
DE (1) | DE112019007175B4 (zh) |
WO (1) | WO2020208713A1 (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110943110A (zh) * | 2019-11-25 | 2020-03-31 | 武汉华星光电半导体显示技术有限公司 | 一种显示装置 |
WO2023190451A1 (ja) * | 2022-03-30 | 2023-10-05 | 三井金属鉱業株式会社 | 接合体の製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1574326A (zh) * | 2003-06-23 | 2005-02-02 | 株式会社电装 | 塑模型半导体器件及其制造方法 |
CN104756250A (zh) * | 2012-11-20 | 2015-07-01 | 丰田自动车株式会社 | 半导体装置 |
US20160300770A1 (en) * | 2013-11-26 | 2016-10-13 | Mitsubishi Electric Corporation | Power module and method of manufacturing power module |
JP2018195724A (ja) * | 2017-05-18 | 2018-12-06 | 三菱電機株式会社 | パワーモジュールおよびその製造方法ならびに電力変換装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5050440B2 (ja) | 2006-08-01 | 2012-10-17 | 日産自動車株式会社 | 半導体装置及びその製造方法 |
JP5808295B2 (ja) | 2012-06-07 | 2015-11-10 | 株式会社豊田中央研究所 | モジュール |
JP5725060B2 (ja) * | 2013-03-14 | 2015-05-27 | 三菱マテリアル株式会社 | 接合体、パワーモジュール用基板、及びヒートシンク付パワーモジュール用基板 |
JP6153076B2 (ja) | 2013-05-22 | 2017-06-28 | 株式会社豊田中央研究所 | 金属ナノ粒子ペースト、それを含有する接合材料、及びそれを用いた半導体装置 |
JP6613806B2 (ja) * | 2015-10-23 | 2019-12-04 | 富士電機株式会社 | 半導体装置 |
JP6522241B2 (ja) | 2016-06-24 | 2019-05-29 | 三菱電機株式会社 | 電力用半導体装置および電力用半導体装置の製造方法 |
-
2019
- 2019-04-09 CN CN201980094857.5A patent/CN113646876A/zh active Pending
- 2019-04-09 JP JP2021513067A patent/JP7126609B2/ja active Active
- 2019-04-09 DE DE112019007175.0T patent/DE112019007175B4/de active Active
- 2019-04-09 WO PCT/JP2019/015471 patent/WO2020208713A1/ja active Application Filing
- 2019-04-09 US US17/429,633 patent/US11908822B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1574326A (zh) * | 2003-06-23 | 2005-02-02 | 株式会社电装 | 塑模型半导体器件及其制造方法 |
CN104756250A (zh) * | 2012-11-20 | 2015-07-01 | 丰田自动车株式会社 | 半导体装置 |
US20160300770A1 (en) * | 2013-11-26 | 2016-10-13 | Mitsubishi Electric Corporation | Power module and method of manufacturing power module |
JP2018195724A (ja) * | 2017-05-18 | 2018-12-06 | 三菱電機株式会社 | パワーモジュールおよびその製造方法ならびに電力変換装置 |
Also Published As
Publication number | Publication date |
---|---|
JPWO2020208713A1 (ja) | 2021-11-25 |
JP7126609B2 (ja) | 2022-08-26 |
DE112019007175T5 (de) | 2021-12-23 |
WO2020208713A1 (ja) | 2020-10-15 |
DE112019007175B4 (de) | 2024-06-13 |
US20220108969A1 (en) | 2022-04-07 |
US11908822B2 (en) | 2024-02-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN109727960B (zh) | 半导体模块、其制造方法以及电力变换装置 | |
JP7091878B2 (ja) | パワーモジュール、電力変換装置、及びパワーモジュールの製造方法 | |
JP2019197842A (ja) | パワーモジュール、電力変換装置、およびパワーモジュールの製造方法 | |
CN113811990A (zh) | 半导体装置、电力变换装置以及半导体装置的制造方法 | |
JP6826665B2 (ja) | 半導体装置、半導体装置の製造方法及び電力変換装置 | |
CN113646876A (zh) | 功率半导体模块以及电力变换装置 | |
JP6927437B1 (ja) | パワーモジュールおよび電力変換装置 | |
JP6952889B2 (ja) | パワー半導体モジュール及びその製造方法並びに電力変換装置 | |
CN111052325A (zh) | 半导体模块以及电力转换装置 | |
CN112204729A (zh) | 半导体装置以及电力变换装置 | |
US11652032B2 (en) | Semiconductor device having inner lead exposed from sealing resin, semiconductor device manufacturing method thereof, and power converter including the semiconductor device | |
WO2022049660A1 (ja) | 半導体装置、電力変換装置、および移動体 | |
US20240030087A1 (en) | Semiconductor device, method of manufacturing semiconductor device, and power conversion device | |
US11887903B2 (en) | Power semiconductor device, method for manufacturing power semiconductor device, and power conversion apparatus | |
JP7418474B2 (ja) | 半導体装置および電力変換装置 | |
WO2024090278A1 (ja) | 半導体装置、電力変換装置および半導体装置の製造方法 | |
WO2022064599A1 (ja) | 半導体装置および電力変換装置 | |
WO2021100199A1 (ja) | 半導体装置およびその製造方法ならびに電力変換装置 | |
JP2024010348A (ja) | 半導体モジュールおよび電力変換装置 | |
CN117438386A (zh) | 半导体装置、半导体装置的制造方法及电力转换装置 | |
CN115023810A (zh) | 半导体装置以及电力变换装置 | |
CN111448653A (zh) | 半导体装置及电力转换装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |