WO2019214440A1 - 薄膜晶体管及其制备方法、显示基板和显示装置 - Google Patents

薄膜晶体管及其制备方法、显示基板和显示装置 Download PDF

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WO2019214440A1
WO2019214440A1 PCT/CN2019/084226 CN2019084226W WO2019214440A1 WO 2019214440 A1 WO2019214440 A1 WO 2019214440A1 CN 2019084226 W CN2019084226 W CN 2019084226W WO 2019214440 A1 WO2019214440 A1 WO 2019214440A1
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film
metal oxide
oxide material
drain electrode
source electrode
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PCT/CN2019/084226
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English (en)
French (fr)
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张文林
孙建明
胡合合
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京东方科技集团股份有限公司
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Priority to US16/608,549 priority Critical patent/US11664460B2/en
Publication of WO2019214440A1 publication Critical patent/WO2019214440A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66265—Thin film bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a thin film transistor and a method of fabricating the same, a display substrate including the same, and a display device.
  • Metal oxide materials are increasingly used in thin film transistors due to their high mobility.
  • metal oxide materials are difficult to replace conductive materials such as metal materials and transparent conductive materials due to their conductivity problems.
  • the steps of fabricating the metal electrode and the transparent electrode need to be performed in separate film forming chambers, which tends to reduce production efficiency and increase production costs.
  • a method for fabricating a thin film transistor comprising the steps of forming a source electrode, a drain electrode, and an active layer, wherein the steps of forming the source electrode, the drain electrode, and the active layer include:
  • the first film is used to form an active layer pattern
  • the second film is used to form a source electrode and a drain electrode, and the second oxygen content is less than the first oxygen content.
  • the step of forming the source electrode, the drain electrode, and the active layer further includes performing an annealing process on the second film at the second temperature.
  • the second oxygen content is less than or equal to 30% (v/v).
  • the second oxygen content is 30% (v/v), and the thickness of the second film is greater than or equal to
  • the second temperature is in the range of 240 ° C to 260 ° C.
  • a gas containing a H atom is introduced into the atmosphere of the second oxygen content, and a second film is formed from the second metal oxide material.
  • water vapor is introduced into an oxygen-free atmosphere, and a second film is formed from the second metal oxide material.
  • the H atom-containing gas is one or more selected from the group consisting of water vapor and ammonia.
  • the water vapor is introduced at a speed greater than or equal to 1 sccm, and the thickness of the second film is greater than or equal to
  • the step of forming the source/drain electrodes and the active layer further comprises performing an annealing process on the first film at a first temperature.
  • the first temperature is in the range of 300 °C to 420 °C.
  • the first metal oxide material and the second metal oxide material are the same metal oxide material.
  • the first film and the second film are formed by the sputtering process in the same chamber and using the same target.
  • the first metal oxide material and the second metal oxide material each comprise a mixture of indium gallium tin oxide and indium oxide, the first metal oxide material and the second metal oxide material
  • the molar content of the indium is greater than or equal to 50% by mole.
  • the steps of forming the source electrode, the drain electrode, and the active layer include:
  • the first film and the second film are subjected to a patterning process to form a source electrode, a drain electrode layer, and an active layer.
  • the step of performing a patterning process on the first film and the second film to form the source/drain electrodes and the active layer includes:
  • the photoresist completely reserved region corresponds to a region where the source electrode and the drain electrode are located, the photoresist portion reserved region corresponds to a region between the source electrode and the drain electrode, and the photoresist non-reserved region corresponds to other regions. region;
  • the remaining photoresist is stripped to form an active layer, a source electrode, and a drain electrode.
  • a thin film transistor fabricated by the method as described above, comprising an active layer, a source electrode, and a drain electrode, wherein the source and drain electrodes and the active layer are Made of the same metal oxide material, the source and drain electrodes have a sheet resistance of less than 5 ⁇ 10 2 ⁇ / ⁇ , and the oxygen content in the metal oxide material after forming the source and drain electrodes is relative to the metal oxide The stoichiometric ratio is at least 0.5% lower than the oxygen content.
  • the first metal oxide material and the second metal oxide material are each a mixture of indium gallium tin oxide and indium oxide, the first metal oxide material and the second metal oxide
  • the molar content of indium in the material is greater than or equal to 75 mole percent.
  • the metal oxide material after forming the source electrode and the drain electrode contains 0.01% to 5% of H atoms with respect to the total atomic number of the metal oxide.
  • a display substrate including the thin film transistor as described above is provided.
  • a display device including the display substrate as described above is provided.
  • FIG. 1 is a schematic structural view of a display substrate according to an embodiment of the present disclosure
  • FIGS. 2 to 8 are schematic views showing a process of preparing a display substrate according to an embodiment of the present disclosure
  • FIG. 9 is a flow chart showing the formation of an active layer, a source electrode, and a drain electrode according to an embodiment of the present disclosure
  • Figure 10 shows a second oxygen content of 30% and a thickness of the second film in the embodiment of the present disclosure. Schematic diagram of the relationship between the annealing temperature and the sheet resistance of the second film prepared at the time;
  • Figure 11 is a view showing the relationship between the thickness of the second film and the sheet resistance prepared when the second oxygen content is 0 and the water vapor introduction rate is 1 sccm in the embodiment of the present disclosure
  • Figure 13 is a graph showing the relationship between the second oxygen content and the sputtering rate of the sputtering process for preparing the second film in the embodiment of the present disclosure.
  • the present disclosure provides a method of producing a thin film transistor which is high in productivity and prepared from a metal oxide material, and a thin film transistor, a display substrate, and a display device thus prepared.
  • the present disclosure provides a method for fabricating a thin film transistor including the steps of forming a source electrode, a drain electrode, and an active layer, wherein the step of forming a source electrode, a drain electrode, and an active layer
  • the method comprises: forming a first film from a first metal oxide material under an atmosphere of a first oxygen content; and forming a second film from the second metal oxide material under an atmosphere of a second oxygen content, wherein the A film is used to form an active layer pattern, the second film is used to form a source electrode and a drain electrode, and the second oxygen content is less than the first oxygen content.
  • the above method of the present disclosure uses a low oxygen content atmosphere in the process of preparing the source electrode and the drain electrode to reduce the oxygen content of the metal oxide material after film formation.
  • the sheet resistivity of the formed film can be lowered to satisfy the electrical conductivity requirements of the source electrode and the drain electrode.
  • This makes it possible to prepare the source and drain electrodes of the thin film transistor from the metal oxide.
  • the source electrode and the drain electrode can be prepared from the same film forming chamber as the active layer, eliminating the separately provided film forming chambers for preparing the source electrode and the drain electrode. This increases production efficiency and reduces production costs.
  • the process for forming the first film and the second film may specifically include, but is not limited to, a sputtering process, vapor deposition, evaporation, and the like.
  • the process for forming the first film and the second film may be selected from a sputtering process in view of controllability and workability of the film forming process.
  • the first metal oxide material and the second metal oxide material may be the same material or different materials.
  • the first metal oxide material and the second metal oxide material each comprise a mixture of indium gallium tin oxide and indium oxide.
  • the second metal oxide material is selected to include a mixture of indium gallium tin oxide and indium oxide. Since the indium content in the mixture is high, the mobility of the film prepared from the second metal oxide material is higher, which is advantageous for obtaining a lower square. resistance. Further, the conductivity performance requirements of the source electrode and the drain electrode are satisfied, thereby improving the performance of the thin film transistor.
  • the molar content of indium in the mixture of indium gallium tin oxide and indium oxide is greater than or equal to 50 mol% (based on the total amount of the metal in the mixture), it is more advantageous to obtain a lower sheet resistance, thereby making the source electrode and The drain electrode has better electrical conductivity.
  • the sheet resistance of the second film may be up to 10 2 or less; when the molar content of indium in the mixture of indium gallium tin oxide and indium oxide is 75 mol% and the thickness of the second film is greater than or equal to
  • the sheet resistance of the second film can be on the order of 0.3 ⁇ 10 2 or less. This order of magnitude of sheet resistance can satisfy the resistance requirements of the source and drain electrodes. As shown in FIG.
  • the lower the oxygen content of the second film after film formation the better, that is, the lower the second oxygen content, the better.
  • the lower the oxygen content the smaller the sheet resistance of the formed second film (i.e., the source electrode and the drain electrode), so that the conductivity performance requirements of the source electrode and the drain electrode can be better satisfied.
  • the formed second film has an oxygen content that is at least 0.5% lower than the stoichiometric content, for example, at least 1%, 3%, 5%, 8%, 12%, 15%, or 20% lower.
  • the sheet resistance of the formed second film is 5 ⁇ 10 2 ⁇ / ⁇ or less, for example, 1 ⁇ 10 2 ⁇ / ⁇ or less, 0.8 ⁇ 10 2 ⁇ / ⁇ or less, 0.5 ⁇ 10 2 ⁇ / ⁇
  • it is 0.3 ⁇ 10 2 ⁇ / port or less or 0.2 ⁇ 10 2 ⁇ / port or less.
  • the second oxygen content is set to be less than or equal to 30% (volume ratio v/v), for example, the second oxygen content is 30% by volume, and the Ar gas content is 70 volumes. %.
  • the second oxygen content is set to be less than or equal to 25% (v/v), 20% (v/v), 15% (v/v), 10% (v/v), 5% (v/v), 3% (v/v), 1% (v/v).
  • the second oxygen content is set to zero, i.e., the second film is prepared in an oxygen-free atmosphere. According to the findings of the inventors of the present disclosure, when the second film is prepared in an atmosphere having a second oxygen content of less than or equal to 30% (volume ratio v/v), a second made of an oxygen-deficient metal oxide can be obtained. film.
  • the step of forming the source electrode, the drain electrode, and the active layer further includes performing an annealing process on the second film at a second temperature.
  • the sheet resistance of the second film can be further adjusted to meet the conductive performance requirements of the source electrode and the drain electrode.
  • the conductivity of the second film can be made to satisfy the source by adjusting one, two or three of the second oxygen content, the second temperature for the annealing process, and the thickness of the second film.
  • the requirements of the electrode and the drain electrode are, for example, a sheet resistance of 30 ⁇ / ⁇ or less.
  • the conductivity of the second film can be made to satisfy the requirements of the source electrode and the drain electrode by adjusting the second temperature, and/or the thickness of the second film.
  • the thickness of the second film is greater than or equal to It is possible to obtain the electrical conductivity (e.g., sheet resistance) requirements that satisfy the source and drain electrodes.
  • the second temperature is in the range of 240° C. to 260° C.
  • the sheet resistance of the second film may be on the order of 10 2 or less, further satisfying the source electrode and the drain electrode.
  • the conductivity requirements is 250 °C.
  • the larger the thickness of the second film the smaller the sheet resistance.
  • the thickness of the second film may be set according to actual needs, and the conductivity of the second film satisfies the conductive performance requirements of the source electrode and the drain electrode by adjusting the second oxygen content and the second temperature for the annealing process.
  • the first film may be annealed at a first temperature.
  • the first temperature may be in the range of 300 ° C to 420 ° C.
  • a gas containing a H atom such as water vapor, ammonia, or the like, may be introduced into the atmosphere of the second oxygen content, and the second metal oxide material may be formed into a second film.
  • the amount of the gas containing H atoms is 2% by volume or less based on the total volume of the gas in the atmosphere.
  • the H atom-containing gas is a reducing H atom-containing gas. Since H atoms are introduced into the metal oxide, electrons are introduced into the metal oxide accordingly. Therefore, the carriers of the metal oxide material forming the second film are increased, thereby lowering the sheet resistance of the second film to satisfy the electrical conductivity requirements of the source electrode and the drain electrode.
  • a second film may be formed from the second metal oxide material by introducing a gas containing H atoms in an oxygen-free atmosphere.
  • the H atom-containing gas is water vapor.
  • the preparation of the second film under an oxygen-free and water-containing vapor atmosphere is more advantageous for realizing a second film having a smaller sheet resistance, thereby further improving the conductivity properties of the source electrode and the drain electrode.
  • the water vapor can be introduced at a speed greater than or equal to 1 sccm.
  • the thickness of the second film may be greater than or equal to For example, when the atmosphere is water vapor, the amount of input gas is 2 sccm, and the performance requirement can be obtained. The second film.
  • the first film may be formed first and the first film is annealed, and then the second film is formed and the second film is annealed.
  • the first film and the second film may be respectively annealed at different temperatures to obtain electrical conductivity such as a sheet resistance value that satisfies the requirements of the source electrode and the drain electrode and the active layer, respectively.
  • the source electrode and the drain electrode can be simultaneously active at the same temperature by adjusting one, two or three conditions of the oxygen content, the thickness of the film, and the velocity of the water vapor.
  • the layer is subjected to an annealing process, and the source and drain electrodes and the active layer satisfy respective conductivity performance requirements.
  • the method according to the present disclosure may simultaneously form the source electrode, the drain electrode, and the active layer by one patterning process to further improve production efficiency and reduce production cost.
  • the steps of forming the source electrode, the drain electrode, and the active layer include: forming the second film on the first film; and performing a patterning process on the first film and the second film to form a source Electrode, drain electrode and active layer.
  • the step of patterning the first film and the second film to form the source electrode, the drain electrode and the active layer may specifically include:
  • the photoresist completely reserved region corresponds to a region where the source electrode and the drain electrode are located, the photoresist portion reserved region corresponds to a region between the source electrode and the drain electrode, and the photoresist non-reserved region corresponds to other regions. region;
  • the remaining photoresist is stripped to form an active layer pattern, a source electrode, and a drain electrode.
  • the present disclosure also provides a thin film transistor fabricated by the above method.
  • the thin film transistor includes an active layer, a source electrode, and a drain electrode, wherein the source and drain electrodes and the active layer are made of the same metal oxide material, and the sheet resistance of the source and drain electrodes Less than or equal to 1 ⁇ 10 2 ⁇ / port.
  • the source and drain electrodes have a sheet resistance of 0.8 ⁇ 10 2 ⁇ / ⁇ or less, 0.5 ⁇ 10 2 ⁇ / ⁇ , 0.3 ⁇ 10 2 ⁇ / ⁇ or less, or 0.2 ⁇ 10 2 ⁇ / ⁇ or less.
  • the formed second film (or source electrode and drain electrode layer) has an oxygen content that is at least 0.5% lower than the stoichiometric content, for example, at least 1%, 3%, 5%, 8%, and 12% lower. %, 15% or 20%.
  • the thin film transistor of the present disclosure includes an active layer, a source electrode, and a drain electrode, wherein a material of the source electrode and the drain electrode and the active layer is a mixture of indium gallium tin oxide and indium oxide, and The molar content of indium in the mixture is 50% by mole or more, or even more than 75% by mole; and the oxide of the mixture after forming the source electrode and the drain electrode is oxygen-deficient with respect to the stoichiometric oxide, for example, at least overall lacking 0.5 mole% oxygen, optionally at least 1%, 3%, 5%, 8%, 12 mole% oxygen; alternatively at least 15 mole% oxygen, even at least 20 mole% oxygen.
  • the metal oxide after forming the source and drain electrodes contains the incorporated H atoms.
  • it contains at least 0.01 mole % of H atoms relative to the total number of atoms of the metal oxide; optionally contains at least 0.05 mole % of H atoms, even containing at least 0.1 mole % of H atoms.
  • the amount of H atoms contained does not exceed 2 mol%.
  • the thin film transistor of the present disclosure is fabricated by the same metal oxide material in the same film forming chamber. Since only the oxygen content in the film forming atmosphere is adjusted in the process of fabricating the source electrode and the drain electrode, the resulting film satisfies the sheet resistance requirements of the source electrode and the drain electrode. This solves the problem that the metal oxide of the related art has low conductivity and is difficult to replace the metal material as a material for the source electrode and the drain electrode.
  • the present disclosure also provides a display substrate including the thin film transistor described above.
  • the present disclosure also provides a display device including the above display substrate.
  • the bottom gate type thin film transistor is taken as an example to specifically introduce the technical solution of the present disclosure. It should be noted that the technical solution of the present disclosure is not limited to a bottom gate type thin film transistor, and is also applicable to a top gate type thin film transistor and a coplanar type thin film transistor.
  • an embodiment of the present disclosure provides a method of fabricating a thin film transistor, the method comprising the following steps S1-S4.
  • Step S1 Providing the substrate 100, when applied to the display product, the substrate 100 is a transparent substrate such as a quartz substrate, a glass substrate, an organic resin substrate or the like.
  • Step S2 forming a gate metal film on the substrate 100 by using a gate metal, and patterning the gate metal film to form a gate electrode 1.
  • a gate metal material may be sputtered on the substrate 100 using a magnetron sputtering apparatus to form a gate metal film.
  • the material of the gate metal may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, or an alloy of these metals. It may be a single layer structure or a multilayer structure.
  • the multilayer structure is, for example, Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, or the like.
  • the thickness of the gate metal film can be
  • Step S3 forming a gate insulating layer 103 covering the gate electrode 1, as shown in FIG.
  • the gate insulating layer 103 may be a single layer or a composite layer structure made of an insulating material such as silicon nitride, silicon oxide or silicon oxynitride.
  • the gate insulating layer 103 is formed by a plasma enhanced chemical vapor deposition method, and the thickness thereof may be
  • Step S4 forming an active layer 2, a source electrode 3 and a drain electrode 4 on a surface of the gate insulating layer 103 facing away from the gate electrode 1, the source electrode 3 and the drain electrode 4 overlapping the gate electrode 1 of the active layer 2 On the surface, see Figure 4 for details.
  • the material of the active layer 2 and the source electrode 3 and the drain electrode 4 are each selected from a metal oxide material.
  • the steps of forming the active layer 2, the source electrode 3, and the drain electrode 4 on the surface of the gate insulating layer 103 facing away from the gate electrode 1 include:
  • the first film 101 and the second film 102 are subjected to a patterning process to form the active layer 2, the source electrode 3, and the drain electrode 4.
  • the above method reduces the oxygen content of the metal oxide material at the time of film formation, thereby reducing the sheet resistivity of the film formation. Further, the second metal oxide film satisfies the requirements of the conductivity of the source electrode and the drain electrode, whereby the source electrode and the drain electrode of the thin film transistor can be formed by the metal oxide. Since the same metal oxide material is used, the source and drain electrodes can be prepared from the same film forming chamber as the active layer. This increases production efficiency and reduces production costs. Moreover, by simultaneously forming the source electrode, the drain electrode, and the active layer by one patterning process, the production efficiency can be further improved, and the production cost can be reduced.
  • the step of performing a patterning process on the first film 101 and the second film 102 to form the source electrode 3, the drain electrode 4, and the active layer 2 may specifically include :
  • a photoresist 200 is coated on the second film 102. After the photoresist 200 is exposed and developed, a photoresist completely remaining region 201, a photoresist portion remaining region 202, and a photoresist are not retained.
  • the remaining photoresist is peeled off to form the active layer 2, the source electrode 3, and the drain electrode 4.
  • the first metal oxide material and the second metal oxide material may each comprise a mixture of indium gallium tin oxide and indium oxide.
  • the second metal oxide material selection includes a mixture of indium gallium tin oxide and indium oxide, because the indium content is high, the mobility is higher, which is advantageous for obtaining a lower sheet resistance and satisfying the conductive performance requirements of the source electrode and the drain electrode. It also improves the performance of thin film transistors.
  • the thickness of the first film may be any thickness of the first film.
  • the thickness of the first film may be any thickness of the first film.
  • the first metal oxide material and the second metal oxide material both comprise a mixture of indium gallium tin oxide and indium oxide
  • the first film and the first film are etched using H 2 SO 4 +HNO 4 due to the high indium content. Two films, the etching rate is
  • first metal oxide material and the second metal oxide material may also be selected for the first metal oxide material and the second metal oxide material.
  • the first metal oxide material and the second metal oxide material may also be selected from different metal oxide materials.
  • the second oxygen content is set to be less than or equal to 30%.
  • the second oxygen content is set to be less than or equal to 25% (v/v), 20% (v/v), 15% (v/v), 10% (v/v), 5% (v/v), 3% (v/v), 1% (v/v). It is even possible to optionally set the second oxygen content to zero.
  • the steps of forming the source electrode, the drain electrode, and the active layer further include:
  • the first film is subjected to an annealing process at a first temperature
  • the second film is subjected to an annealing process at a second temperature
  • the first temperature and the second temperature may be different.
  • the above steps can further adjust the sheet resistance of the first film and the second film by annealing the first film and the second film at different temperatures to satisfy the electrical conductivity requirements of the semiconductor and the conductive material, respectively.
  • the first temperature may be in the range of 300 ° C to 420 ° C.
  • the second film may be annealed according to the second oxygen content and the second film thickness to select a suitable temperature so that the sheet resistance of the second film satisfies the conductive performance requirements of the source electrode and the drain electrode.
  • a suitable temperature for example, when the second oxygen content is 30%, the thickness of the second film is greater than or equal to
  • the annealing process of the second film at a temperature of 250 ° C can make the sheet resistance of the second film be of the order of 10 2 or less, satisfying the electrical conductivity requirements of the source electrode and the drain electrode, as shown in FIG. 10 .
  • the second film is prepared by a sputtering process
  • the sputtering conditions are: power: 3 KW, access rate of Ar: 50 sccm to 80 sccm, pressure: 0.3 Pa to 0.6 Pa, and access rate of O 2 : 20 sccm;
  • the second film is annealed at a temperature of 250 ° C, and the thickness of the second film is When the left and right sides are concerned, the sheet resistance of the prepared second film can satisfy the conductive performance requirements of the source electrode and the drain electrode.
  • the relationship between the second oxygen content and the sputtering rate of the sputtering process for preparing the second film is shown by the solid line in FIG.
  • the broken line in Fig. 13 indicates the correspondence relationship between the second oxygen content and the sputtering rate of the sputtering process for preparing the second thin film satisfying a certain linear relationship.
  • the disclosure may also pass a gas containing H atoms, such as water vapor, ammonia, etc., under a second oxygen content atmosphere, and form a second film from the second metal oxide material to reduce the square of the second film.
  • a gas containing H atoms such as water vapor, ammonia, etc.
  • the resistor is such that it satisfies the conductive performance requirements of the source and drain electrodes.
  • water vapor may be introduced in an oxygen-free atmosphere to form a second film from the second metal oxide material.
  • the anaerobic and venting atmosphere gases are more advantageous for achieving a second film having a smaller sheet resistance, improving the conductivity of the source and drain electrodes.
  • the water vapor can be introduced at a speed greater than or equal to 1 sccm, and the thickness of the second film can be greater than or equal to For example, as shown in FIG.
  • the sputtering film forming process power is 3 KW
  • the thickness of the second film is for When the sheet resistance is 70 ⁇ / ⁇ , it satisfies the conductive performance requirements of the transparent electrode.
  • the present disclosure also provides a thin film transistor which is fabricated by the above method.
  • the material of the active layer, the source electrode and the drain electrode of the obtained thin film transistor is a metal oxide material, and the sheet resistance of the source electrode and the drain electrode is smaller than the sheet resistance of the active layer. Since the source and drain electrodes and the active layer are made of the same metal oxide material, they can be made from the same film forming chamber. In the process of preparing the source electrode and the drain electrode, it is only necessary to adjust the oxygen content in the film forming atmosphere, so that the obtained film satisfies the sheet resistance requirement of the source electrode and the drain electrode, thereby improving the mass production efficiency and reducing the product. Cost of production.
  • the method for preparing the display substrate includes the above method for preparing a thin film transistor, and simultaneously forming a gate electrode 1 by a patterning process.
  • a gate line (not shown) of the display substrate and a common signal line 20 are prepared;
  • a data line 10 of the display substrate is simultaneously prepared by a patterning process of fabricating the source electrode 3 and the drain electrode 4.
  • the method for preparing the display substrate further includes the following steps S5-S8.
  • Step S5 As shown in FIG. 5, a passivation layer 104 and a planarization layer 105 covering the thin film transistor are sequentially formed, and a first via hole 11, a second via hole 12, and a first via hole 12 are formed in the planarization layer 105 by a first etching process.
  • the third via 13 is provided.
  • the first via 11 is disposed corresponding to a region where the drain electrode 4 is located
  • the second via 12 is disposed corresponding to a region where the common signal line 20 is located
  • the third via 13 is disposed corresponding to a region where the data line 10 is located.
  • the passivation layer 104 under the first via hole 11 is removed by a second etching process to expose the drain electrode 4; and the passivation layer 104 under the second via hole 12 is removed to expose the common signal line 20;
  • the passivation layer 104 under the three vias 13 exposes the data lines 10, as shown in Figures 6 and 7.
  • the passivation layer 104 may be a SiO 2 , SiON, SiN film layer or a combination thereof, and the thickness may be
  • the passivation layer 104 can be formed by a plasma enhanced chemical vapor deposition method, and an annealing process is performed in a temperature range of 250 ° C to 350 ° C to ensure characteristics of the TFT.
  • the flat layer 105 may be made of an organic resin to provide a flat surface, and may have a thickness of 1.7 to 2.2 ⁇ m.
  • Step S6 forming a common electrode 6 and a connection electrode 7 on the surface of the flat layer 105 facing away from the passivation layer 104.
  • the common electrode 6 is in electrical contact with the common signal line 20 through the second via hole 12, and the connection electrode 7 passes through the third pass.
  • the hole 13 is in electrical contact with the data line 10, as shown in particular in Figures 6 and 7.
  • the common electrode 6 is made of a transparent metal oxide such as HIZO, ZnO, TiO 2 , CdSnO, MgZnO, IGO, IZO, ITO or IGZO.
  • a transparent metal oxide such as HIZO, ZnO, TiO 2 , CdSnO, MgZnO, IGO, IZO, ITO or IGZO.
  • the thickness of the common electrode 6 may be
  • Step S7 forming an interlayer insulating layer 106 covering the common electrode 6, and forming a fourth via hole 14 in the interlayer insulating layer 106 by a second etching process to expose the drain electrode 4 while being in the interlayer insulating layer 106.
  • a fifth via hole 17 is formed in the middle to expose the connection electrode 7, as shown in FIG.
  • the interlayer insulating layer 106 may be a SiO 2 , SiON, SiN film layer or a combined film layer of these film layers, and the thickness is
  • Step S8 forming a pixel electrode 5 on the interlayer insulating layer 106.
  • the pixel electrode 5 is in electrical contact with the drain electrode 4 through the fourth via hole 14, and the pixel electrode 5 is in electrical contact with the connection electrode 7 through the fifth via hole 15.
  • the pixel electrode 5 is electrically connected to the data line 10 through the connection electrode 7, as shown in FIG.
  • the pixel electrode 5 is made of a transparent metal oxide such as HIZO, ZnO, TiO 2 , CdSnO, MgZnO, IGO, IZO, ITO or IGZO.
  • a transparent metal oxide such as HIZO, ZnO, TiO 2 , CdSnO, MgZnO, IGO, IZO, ITO or IGZO.
  • the transparent electrode including the pixel electrode and the common electrode
  • the source electrode, the drain electrode and the active layer can adopt the same film forming chamber, which can greatly improve production efficiency and reduce production cost.
  • the materials of the transparent electrode, the source electrode, the drain electrode and the active layer of the display substrate prepared by the above method are all metal oxide materials, so each layer can be made of the same film forming chamber.
  • the display device is the display substrate described above, the mass production efficiency of the display device can be improved and the production cost can be reduced.

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Abstract

本公开涉及一种薄膜晶体管及其制备方法、显示基板。所述薄膜晶体管的制备方法包括形成源电极、漏电极和有源层的步骤，其中，所述形成源电极、漏电极和有源层的步骤包括在第一氧含量的气氛中，由第一金属氧化物材料形成第一薄膜；以及在第二氧含量的气氛中，由第二金属氧化物材料形成第二薄膜，其中，所述第一薄膜用于形成有源层，所述第二薄膜用于形成源电极和漏电极，并且所述第二氧含量小于所述第一氧含量。

Description

薄膜晶体管及其制备方法、显示基板和显示装置
相关申请的交叉参考
本申请主张在2018年5月11日在中国提交的中国专利申请号No.201810450327.7的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，特别是涉及一种薄膜晶体管及其制作方法、包括该薄膜晶体管的显示基板和显示装置。
背景技术
金属氧化物材料因其迁移率高，越来越广泛地应用到薄膜晶体管中。但是，在现有的显示产品量产技术中，金属氧化物材料因其导电性问题，很难做到代替金属材料、透明导电材料等导电材料。而且，制作金属电极和透明电极的步骤需要在独立的成膜腔室中进行，势必会降低生产效率，增加生产成本。
发明内容
在本公开的一个方面，提供一种用于制备薄膜晶体管的方法，包括形成源电极、漏电极和有源层的步骤，其中，所述形成源电极、漏电极和有源层的步骤包括：
在第一氧含量的气氛中，由第一金属氧化物材料形成第一薄膜；以及
在第二氧含量的气氛中，由第二金属氧化物材料形成第二薄膜，
其中，所述第一薄膜用于形成有源层图形，所述第二薄膜用于形成源电极和漏电极，并且所述第二氧含量小于所述第一氧含量。
在如上所述的方法中，所述形成源电极、漏电极和有源层的步骤还包括在第二温度下对所述第二薄膜进行退火工艺。
在如上所述的方法中，所述第二氧含量小于或等于30％(v/v)。
在如上所述的方法中，所述第二氧含量为30％(v/v)，所述第二薄膜的 厚度大于或等于
Figure PCTCN2019084226-appb-000001
在如上所述的方法中，所述第二温度在240℃～260℃范围内。
在如上所述的方法中，在第二氧含量的气氛中，通入含H原子的气体，由所述第二金属氧化物材料形成第二薄膜。
在如上所述的方法中，在无氧的气氛中，通入水蒸气，由所述第二金属氧化物材料形成第二薄膜。
在如上所述的方法中，所述含H原子的气体为选自水蒸气和氨气中的一种或多种。
在如上所述的方法中，所述水蒸气的通入速度大于或等于1sccm，所述第二薄膜的厚度大于或等于
Figure PCTCN2019084226-appb-000002
在如上所述的方法中，所述形成源电极/漏电极和有源层的步骤还包括在第一温度下对所述第一薄膜进行退火工艺。
在如上所述的方法中，所述第一温度在300℃-420℃范围内。
在如上所述的方法中，所述第一金属氧化物材料和第二金属氧化物材料为同种金属氧化物材料。
在如上所述的方法中，第一薄膜和第二薄膜是在同一腔室和使用相同靶材通过溅射工艺来形成的。
在如上所述的方法中，所述第一金属氧化物材料和第二金属氧化物材料均包括氧化铟镓锡和氧化铟的混合物，所述第一金属氧化物材料和第二金属氧化物材料中铟的摩尔含量大于或等于50摩尔％。
在如上所述的方法中，所述形成源电极、漏电极和有源层的步骤包括：
在所述第一薄膜上形成所述第二薄膜；和
对所述第一薄膜和第二薄膜进行一次构图工艺以形成源电极、漏电极层和有源层。
在如上所述的方法中，所述对所述第一薄膜和第二薄膜进行一次构图工艺以形成源电极/漏电极和有源层的步骤包括：
在所述第二薄膜上涂覆光刻胶，对所述光刻胶进行曝光、显影后，形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶不保留区域，其中，所述光刻胶完全保留区域对应所述源电极和漏电极所在的区域，所述光刻胶部 分保留区域对应所述源电极和漏电极之间的区域，所述光刻胶不保留区域对应其他区域；
去除光刻胶不保留区域的第一薄膜和第二薄膜；
通过灰化工艺去除所述光刻胶部分保留区域的光刻胶，然后去除所述光刻胶部分保留区域的第二薄膜；以及
剥离剩余的光刻胶，形成有源层、源电极和漏电极。
在本公开的另一个方面，提供一种采用如上所述的方法制得的薄膜晶体管，包括有源层、源电极和漏电极，其中，所述源电极和漏电极与所述有源层由同种金属氧化物材料制成，所述源电极和漏电极的方块电阻小于5×10 2Ω/口，形成源电极和漏电极后的金属氧化物材料中的氧含量相对于该金属氧化物的化学计量比氧含量低至少0.5％。
在如上所述的薄膜晶体管中，所述第一金属氧化物材料和第二金属氧化物材料均为氧化铟镓锡和氧化铟的混合物，所述第一金属氧化物材料和第二金属氧化物材料中铟的摩尔含量大于或等于75摩尔％。
在如上所述的薄膜晶体管中，相对于金属氧化物的总原子数，形成源电极和漏电极后的金属氧化物材料含有0.01％～5％的H原子。
在本公开的再一个方面，提供一种显示基板，包括如上所述的薄膜晶体管。
在本公开的再一个方面，提供一种显示装置，包括如上所述的显示基板。
附图说明
为了更清楚地说明本公开实施方式或相关技术中的技术方案，下面将对本公开的实施方式或相关技术描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图或实施方式。
图1表示本公开实施例的显示基板的结构示意图；
图2-图8表示本公开实施例的显示基板的制备过程示意图；
图9表示本公开实施例的形成有源层、源电极和漏电极的流程示意图；
图10表示本公开实施例中第二氧含量为30％、第二薄膜的厚度为
Figure PCTCN2019084226-appb-000003
时所制备的第二薄膜的退火温度与方块电阻的关系示意图；
图11表示本公开实施例中第二氧含量为0、水蒸气的通入速率为1sccm时所制备的第二薄膜的厚度与方块电阻的对应关系图；
图12表示本公开实施例中当氧化铟镓锡和氧化铟的混合物中铟的摩尔含量为75摩尔％时所制备的第二薄膜的厚度与方块电阻的关系图；
图13表示本公开实施例中第二氧含量与制备第二薄膜的溅射工艺的溅射速率的关系示意图。
具体实施方式
以下结合附图对本公开的特征和原理进行详细说明，所给出的具体实施方式仅用于解释本公开，并不是限制本公开的保护范围。
由于金属氧化物具有高的迁移率，越来越广泛地应用于薄膜晶体管。但是金属氧化物因其导电性问题，很难替代金属材料作为电极材料。这导致薄膜晶体管的源电极和漏电极与有源层需要不同的成膜腔室来制作，降低了产品的生产效率，增加生产成本。为了解决相关技术中的上述问题，本公开提供了一种生产效率高且由金属氧化物材料来制备薄膜晶体管的方法、以及由此制备的薄膜晶体管、显示基板和显示装置。
根据本公开的一个方面，本公开提供一种用于制备薄膜晶体管的方法，包括形成源电极、漏电极和有源层的步骤，其中，所述形成源电极、漏电极和有源层的步骤包括：在第一氧含量的气氛下，由第一金属氧化物材料形成第一薄膜；以及在第二氧含量的气氛下，由第二金属氧化物材料形成第二薄膜，其中，所述第一薄膜用于形成有源层图形，所述第二薄膜用于形成源电极和漏电极，并且所述第二氧含量小于所述第一氧含量。
本公开的上述方法在制备源电极和漏电极的过程中，采用低氧含量的气氛，降低了金属氧化物材料在形成膜后的氧含量。因而，能够降低所形成的膜的方块电阻率，使其满足源电极和漏电极的导电性能要求。这使得由金属氧化物制备薄膜晶体管的源电极和漏电极成为可能。进而，源电极和漏电极可以与有源层由同一成膜腔室制备，省去单独设置的用于制备源电极和漏电 极的成膜腔室。这提高了生产效率，降低了生产成本。
用于形成所述第一薄膜和第二薄膜的工艺可以具体包括但不局限于溅射工艺、气相沉积、蒸镀等。从成膜工艺的可控性和操作性来看，用于形成所述第一薄膜和第二薄膜的工艺可选为溅射工艺。
所述第一金属氧化物材料和第二金属氧化物材料可以为同种材料，也可以为不同种材料。在本公开的实施方式中，所述第一金属氧化物材料和第二金属氧化物材料均包括氧化铟镓锡和氧化铟的混合物。可选地，在第一薄膜和第二薄膜成膜的过程中，只需调整氧含量即可，不需要更换靶材，进一步提高生产效率。另外，第二金属氧化物材料选择包括氧化铟镓锡和氧化铟的混合物，由于该混合物中铟含量高，第二金属氧化物材料制备的膜的迁移率更高，有利于获得更低的方块电阻。进而，满足源电极和漏电极的导电性能需求，由此提升薄膜晶体管的性能。
通过设置氧化铟镓锡和氧化铟的混合物中铟的摩尔含量大于或等于50摩尔％(基于该混合物中的金属的摩尔总量)，更有利于获得更低的方块电阻，从而使源电极和漏电极具有更好的导电性能。例如，当氧化铟镓锡和氧化铟的混合物中铟的摩尔含量为50摩尔％且第二薄膜的厚度大于或等于
Figure PCTCN2019084226-appb-000004
时，第二薄膜的方块电阻可以达到10 2以下数量级；当氧化铟镓锡和氧化铟的混合物中铟的摩尔含量为75摩尔％且第二薄膜的厚度大于或等于
Figure PCTCN2019084226-appb-000005
时，第二薄膜的方块电阻可以达到0.3×10 2以下数量级。该数量级的方块电阻可以满足源电极和漏电极的电阻需求。如图12所示，其表示当氧化铟镓锡和氧化铟的混合物中铟的摩尔含量为75摩尔％时第二薄膜的厚度与相应方块电阻之间的关系。由图12可以看出，第二薄膜的厚度越厚，则方块电阻越小；当第二薄膜的厚度大于或等于
Figure PCTCN2019084226-appb-000006
时，第二薄膜的方块电阻为10 2以下数量级；并且当厚度大于
Figure PCTCN2019084226-appb-000007
则方块电阻趋于平缓地降低。
在制备源电极和漏电极的过程中，第二薄膜在成膜后的氧含量越低越好，即，所述第二氧含量越低越好。因为氧含量越低，形成的第二薄膜(即源电极和漏电极)的方块电阻越小，从而能够更好满足源电极和漏电极的导电性能需求。可选地，形成后的第二薄膜的氧含量相对于化学计量比含量低至少0.5％，例如，低至少1％、3％、5％、8％、12％、15％或20％。可选地，形成 后的第二薄膜的方块电阻为5×10 2Ω/口以下，例如，1×10 2Ω/口以下、0.8×10 2Ω/口以下、0.5×10 2Ω/口以下、0.3×10 2Ω/口以下或0.2×10 2Ω/口以下。
在本公开的一种实施方式中，所述第二氧含量被设置为小于或等于30％(体积比v/v)，例如，第二氧含量为30体积％，Ar气的含量为70体积％。可选地，所述第二氧含量被设置为小于或等于25％(v/v)、20％(v/v)、15％(v/v)、10％(v/v)、5％(v/v)、3％(v/v)、1％(v/v)。甚至可选地，所述第二氧含量被设置为0，即在无氧的气氛中制备第二薄膜。根据本公开发明人的发现，当在第二氧含量为小于或等于30％(体积比v/v)的气氛中制备第二薄膜时，可以获得由缺氧的金属氧化物制成的第二薄膜。
在本公开的一种实施方式中，所述形成源电极、漏电极和有源层的步骤还包括在第二温度下对所述第二薄膜进行退火工艺。
在上述步骤中，通过对第二薄膜进行退火工艺，能够进一步调整第二薄膜的方块电阻，使其满足源电极和漏电极的导电性能需求。
在根据本公开的方法中，通过调整第二氧含量、用于退火工艺的第二温度和第二薄膜的厚度中的一个、二个或三个条件，可以使第二薄膜的导电性能满足源电极和漏电极的需求，例如，方块电阻为30Ω/口以下。当所述第二氧含量为可选范围的特定值时，可以通过调整所述第二温度、和/或第二薄膜的厚度，使第二薄膜的导电性满足源电极和漏电极的需求。
具体地，当所述第二氧含量为30％时，所述第二薄膜的厚度大于或等于
Figure PCTCN2019084226-appb-000008
可以获得满足源电极和漏电极的导电性能(例如方块电阻)要求。进一步，当对第二薄膜进行退火工艺，且所述第二温度在240℃～260℃的范围内时，可以使得第二薄膜的方块电阻为10 2以下数量级，更进一步满足源电极和漏电极的导电性能需求。可选地，所述第二温度为250℃。显然地，第二薄膜的厚度越大，其方块电阻越小。可以根据实际需求设置第二薄膜的厚度，并且通过调整第二氧含量和用于退火工艺的第二温度，使得第二薄膜的导电性能满足源电极和漏电极的导电性能需求。
可选地，也可以在第一温度下对所述第一薄膜进行退火工艺。可选地，所述第一温度可以在300℃-420℃范围内，在使得第一薄膜满足半导体的方块电阻要求时，还能够减少有源层的缺陷态，提升TFT的稳定性。
在本公开的可选实施方式中，还可以在第二氧含量的气氛下，通入含H原子的气体，如：水蒸气、氨气等，由所述第二金属氧化物材料形成第二薄膜。例如，基于该气氛的气体的总体积量，含H原子的气体量为2体积％以下。可选地，所述含H原子气体为还原性含H原子气体。由于H原子会被引入到金属氧化物中，所以相应地会引入电子到金属氧化物中。因此，形成第二薄膜的金属氧化物材料的载流子增多，从而降低了第二薄膜的方块电阻，使其满足源电极和漏电极的导电性能需求。
在可选的实施方式中，可以在无氧的气氛下，通入含H原子的气体，由所述第二金属氧化物材料形成第二薄膜。可选地，所述含H原子的气体为水蒸气。在无氧和含水蒸气的气氛下制备第二薄膜，更有利于实现具有更小方块电阻的第二薄膜，从而进一步提高源电极和漏电极的导电性能。可选地，水蒸气的通入速度可以大于或等于1sccm。可选地，所述第二薄膜的厚度可以大于或等于
Figure PCTCN2019084226-appb-000009
例如，当氛围气为水蒸气时，其输入气体的量为2sccm，可以获得满足性能要求的
Figure PCTCN2019084226-appb-000010
的第二薄膜。
在可选的实施方式中，可以先形成第一薄膜并对第一薄膜进行退火工艺，然后再形成第二薄膜并对第二薄膜进行退火工艺。可以选择在不同温度下分别对第一薄膜和第二薄膜进行退火工艺，以获得分别满足源电极和漏电极与有源层需求的导电性能如方块电阻值。
在根据本公开的实施方式中，通过调整氧含量、薄膜的厚度、水蒸气的通入速度中的一个、两个或三个条件，可以在同一温度下同时对源电极和漏电极与有源层进行退火工艺，并使得源电极和漏电极与有源层满足各自的导电性能需求。
可选地，根据本公开的方法还可以通过一次构图工艺同时形成源电极、漏电极和有源层，以进一步提高生产效率，降低生产成本。可选地，形成源电极、漏电极和有源层的步骤包括：在所述第一薄膜上形成所述第二薄膜；以及对所述第一薄膜和第二薄膜进行一次构图工艺，形成源电极、漏电极和有源层。
在可选的实施方式中，对所述第一薄膜和第二薄膜进行一次构图工艺，形成源电极、漏电极和有源层的步骤具体地可以包括：
在所述第二薄膜上涂覆光刻胶，对所述光刻胶进行曝光、显影后，形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶不保留区域，其中，所述光刻胶完全保留区域对应所述源电极和漏电极所在的区域，所述光刻胶部分保留区域对应所述源电极和漏电极之间的区域，所述光刻胶不保留区域对应其他区域；
去除光刻胶不保留区域的第一薄膜和第二薄膜；
通过灰化工艺去除所述光刻胶部分保留区域的光刻胶，然后去除所述光刻胶部分保留区域的第二薄膜；以及
剥离剩余的光刻胶，以形成有源层图形、源电极和漏电极。
根据本公开的另一方面，本公开还提供一种采用上述方法制得的薄膜晶体管。所述薄膜晶体管包括有源层、源电极和漏电极，其中，所述源电极和漏电极与所述有源层由同种金属氧化物材料构成，并且所述源电极和漏电极的方块电阻小于或等于1×10 2Ω/口。可选地，所述源电极和漏电极的方块电阻为0.8×10 2Ω/口以下、0.5×10 2Ω/口、0.3×10 2Ω/口以下或0.2×10 2Ω/口以下。可选地，形成后的第二薄膜(或源电极和漏电极层)的氧含量相对于化学计量比含量低至少0.5％，例如，低至少1％、3％、5％、8％、12％、15％或20％。
可选地，本公开的薄膜晶体管包括有源层、源电极和漏电极，其中，所述源电极和漏电极与所述有源层的材料为氧化铟镓锡和氧化铟的混合物，并且该混合物中铟的摩尔含量为50摩尔％以上，甚至为75摩尔％以上；并且该混合物在形成源电极和漏电极后的氧化物相对于化学计量比氧化物是缺氧的，例如整体上缺少至少0.5摩尔％的氧，可选地至少1％、3％、5％、8％、12摩尔％的氧；可选地至少15摩尔％的氧，甚至至少20摩尔％的氧。可选地，在形成源电极和漏电极后的金属氧化物含有掺入的H原子。可选地，相对于金属氧化物的总原子数，含有至少0.01摩尔％的H原子；可选含有至少0.05摩尔％的H原子，甚至含有至少0.1摩尔％的H原子。可选地，含有的H原子量不超过2摩尔％。
基于相同的发明构思，本公开的薄膜晶体管是通过由相同的金属氧化物材料在同一成膜腔室制得的。由于在制作源电极和漏电极的过程中，仅调整 成膜气氛中的氧含量，使得制得的薄膜满足源电极和漏电极的方块电阻需求。这解决了相关技术中金属氧化物的导电性低难以替代金属材料作为源电极和漏电极用材料的问题。
根据本公开的再一个方面，本公开还提供一种显示基板，所述显示基板包括上述的薄膜晶体管。
根据本公开的再一个方面，本公开还提供一种显示装置，所述显示装置包括上述的显示基板。
下面将结合附图和具体实施例，对本公开的具体实施方式作进一步详细描述。以下具体实施例仅用于说明本公开，但不用来限制本公开的范围。
本实施例中以底栅型薄膜晶体管为例来具体介绍本公开的技术方案。需要说明的是，本公开的技术方案并不局限于适用于底栅型薄膜晶体管，还适用于顶栅型薄膜晶体管，共面型薄膜晶体管。
参见图2-图4所示，本公开的实施例提供一种制备薄膜晶体管的方法，该方法包括以下步骤S1-S4。
步骤S1：提供基底100，当应用于显示产品时，基底100为石英基底、玻璃基底、有机树脂基底等透明基底。
步骤S2：利用栅金属在基底100上形成栅金属薄膜，对所述栅金属薄膜进行构图工艺，形成栅电极1，具体参见图2所示。具体地，可以利用磁控溅射设备在基底100上溅射栅金属材料以形成栅金属薄膜。该栅金属的材料可以是Cu、Al、Ag、Mo、Cr、Nd、Ni、Mn、Ti、Ta、W等金属以及这些金属的合金。可以是单层结构或者多层结构。多层结构比如为Cu\Mo、Ti\Cu\Ti、Mo\Al\Mo等。栅金属薄膜的厚度可以为
Figure PCTCN2019084226-appb-000011
步骤S3：形成覆盖栅电极1的栅绝缘层103，参见图3所示。栅绝缘层103可以为由氮化硅、氧化硅或氮氧化硅等绝缘材料制得的单层或复合层结构。具体地，通过等离子体增强化学的气相沉积法形成栅绝缘层103，其厚度可以为
Figure PCTCN2019084226-appb-000012
步骤S4：在栅绝缘层103的背离栅电极1的表面上形成有源层2、源电极3和漏电极4，源电极3和漏电极4搭接在有源层2的背离栅电极1的表面上，具体参见图4所示。有源层2与源电极3和漏电极4的材料均选择金 属氧化物材料。
结合图2和图9所示，在栅绝缘层103的背离栅电极1的表面上形成有源层2、源电极3和漏电极4的步骤包括：
在第一氧含量的气氛下，由第一金属氧化物材料在栅绝缘层103的背离栅电极1的表面上形成第一薄膜101；
在第二氧含量的气氛下，由第二金属氧化物材料在第一薄膜101的背离栅绝缘层103的表面上形成第二薄膜102，其中，所述第二氧含量小于所述第一氧含量；以及
对所述第一薄膜101和第二薄膜102进行一次构图工艺以形成有源层2、源电极3和漏电极4。
上述方法在制备源电极和漏电极的过程中，降低了金属氧化物材料在成膜时的氧含量，从而能够降低成膜的方块电阻率。进而，使第二金属氧化物膜满足源电极和漏电极的导电性能要求，由此能够通过金属氧化物来制作薄膜晶体管的源电极和漏电极。由于采用了同种的金属氧化物材料，所以源电极和漏电极可以与有源层由同一成膜腔室来制备。这提高了生产效率，降低了生产成本。而且，通过一次构图工艺同时形成源电极、漏电极和有源层，能够进一步提高了生产效率，降低生产成本。
在上述制备方法中，结合图3和图4所示，对所述第一薄膜101和第二薄膜102进行一次构图工艺以形成源电极3、漏电极4和有源层2的步骤具体可以包括：
在所述第二薄膜102上涂覆光刻胶200，对所述光刻胶200进行曝光、显影后，形成光刻胶完全保留区域201、光刻胶部分保留区域202和光刻胶不保留区域203，其中，光刻胶完全保留区域201对应源电极3和漏电极4所在的区域，光刻胶部分保留区域202对应有源层2之间的区域，光刻胶不保留区域203对应其他区域；
去除光刻胶不保留区域203的第一薄膜和第二薄膜；
通过灰化工艺去除光刻胶部分保留区域202的光刻胶，然后去除光刻胶部分保留区域201的第二薄膜；以及
剥离剩余的光刻胶，形成有源层2、源电极3和漏电极4。
在本实施例中，所述第一金属氧化物材料和第二金属氧化物材料可以均包括氧化铟镓锡和氧化铟的混合物。在通过成膜工艺形成第一薄膜和第二薄膜的过程中，只需调整氧含量即可，不需要更换靶材，有利于提高生产效率。另外，第二金属氧化物材料选择包括氧化铟镓锡和氧化铟的混合物，因为铟含量高，迁移率更高，有利于获得更低的方块电阻，满足源电极和漏电极的导电性能需求，而且还能够提升薄膜晶体管的性能。
可选地，第一薄膜的厚度可以为
Figure PCTCN2019084226-appb-000013
当所述第一金属氧化物材料和第二金属氧化物材料均包括氧化铟镓锡和氧化铟的混合物时，由于铟含量高，采用H 2SO 4+HNO 4来刻蚀第一薄膜和第二薄膜，刻蚀速率为
Figure PCTCN2019084226-appb-000014
当然，所述第一金属氧化物材料和第二金属氧化物材料也可以选择其它金属氧化物材料。所述第一金属氧化物材料和第二金属氧化物材料还可以选择不同种金属氧化物材料。
可选地，设置所述第二氧含量小于或等于30％。可选地，所述第二氧含量被设置为小于或等于25％(v/v)、20％(v/v)、15％(v/v)、10％(v/v)、5％(v/v)、3％(v/v)、1％(v/v)。甚至可选地设置所述第二氧含量为0。因为氧含量越低，形成的第二薄膜的方块电阻越小，利用所述第二薄膜制得的源电极和漏电极的方块电阻也就越小，能够更好满足源电极和漏电极的导电性能需求。
在一种可选的实施方式中，形成源电极、漏电极和有源层的步骤还包括：
在第一温度下对所述第一薄膜进行退火工艺，在第二温度下对所述第二薄膜进行退火工艺，所述第一温度和第二温度可以不同。上述步骤通过在不同温度下对第一薄膜和第二薄膜进行退火工艺，能够进一步调整第一薄膜和第二薄膜的方块电阻，使其分别满足半导体和导电材料的导电性能需求。
可选地，所述第一温度可以在300℃～420℃范围内。
可以根据所述第二氧含量和第二薄膜厚度来选择合适的第二温度来对第二薄膜进行退火工艺，以使得第二薄膜的方块电阻满足源电极和漏电极的导电性能需求。例如：当所述第二氧含量为30％时，所述第二薄膜的厚度大于或等于
Figure PCTCN2019084226-appb-000015
进一步，在250℃温度下对所述第二薄膜进行退火工艺，可以 使得第二薄膜的方块电阻为10 2以下数量级，满足源电极和漏电极的导电性能需求，如图10所示。
还可以根据不同的氧含量气氛，选择合适的第二温度对第二薄膜进行退火工艺，并由此选取第二薄膜的厚度大于某设定值，可以满足源电极和漏电极的导电性能需求。例如：通过溅射工艺制备第二薄膜时，溅射条件为：功率：3KW，Ar的通入速率：50sccm～80sccm，压力：0.3Pa～0.6Pa，O 2的通入速率：20sccm；当在250℃温度下对第二薄膜进行退火工艺，并且第二薄膜的厚度为
Figure PCTCN2019084226-appb-000016
左右时，所制备的第二薄膜的方块电阻即可满足源电极和漏电极的导电性能需求。第二氧含量与制备第二薄膜的溅射工艺的溅射速率的关系如图13中的实线所示。图13中的虚线表示第二氧含量与制备第二薄膜的溅射工艺的溅射速率满足某线性关系时的对应关系。
本公开还可以在第二氧含量气氛下，通入含H原子的气体，例如：水蒸气、氨气等，由所述第二金属氧化物材料形成第二薄膜，以降低第二薄膜的方块电阻，使其满足源电极和漏电极的导电性能需求。
具体地，可以在无氧的气氛下，通入水蒸气，由所述第二金属氧化物材料形成第二薄膜。无氧和通入水蒸气的气氛气体更有利于实现具有更小方块电阻的第二薄膜，提高源电极和漏电极的导电性能。水蒸气的通入速度可以大于或等于1sccm，所述第二薄膜的厚度可以大于或等于
Figure PCTCN2019084226-appb-000017
例如：如图11所示，在无氧的气氛下，即，第二氧含量为0，且水蒸气的通入速度为1sccm，溅射成膜工艺的功率为3KW，当第二薄膜的厚度为
Figure PCTCN2019084226-appb-000018
时，其方块电阻为70Ω/□，满足透明电极的导电性能需求。通过增加水蒸气的通入速度和增加功率，可以使得第二薄膜的方块电阻满足源电极和漏电极的导电性能需求。
根据本公开的再一个方面，本公开还提供一种薄膜晶体管，其采用上述方法制得。所制得的薄膜晶体管的有源层、源电极和漏电极的材料均为金属氧化物材料，所述源电极和漏电极的方块电阻小于所述有源层的方块电阻。由于所述源电极和漏电极与有源层由同一金属氧化物材料制得，所以可以由同一成膜腔室制得。在制备源电极和漏电极的过程中，仅需调整成膜气氛中的氧含量，使得制得的薄膜满足源电极和漏电极的方块电阻需求即可，从而 提高了产品的量产效率，降低生产成本。
结合图1、图5-图8所示，当本公开的技术方案应用于显示基板时，所述显示基板的制备方法包括采用上述方法来制备薄膜晶体管，并通过制作栅电极1的构图工艺同时制备显示基板的栅线(图中未示出)和公共信号线20；通过制作源电极3和漏电极4的构图工艺同时制备显示基板的数据线10。
在一种可选的实施方式中，所述显示基板的制备方法还包括以下步骤S5-S8。
步骤S5：如图5所示，依次形成覆盖薄膜晶体管的钝化层104和平坦层105，并通过第一次刻蚀工艺在平坦层105中形成第一过孔11、第二过孔12和第三过孔13。所述第一过孔11对应漏电极4所在的区域设置，第二过孔12对应公共信号线20所在的区域设置，第三过孔13对应数据线10所在的区域设置。然后通过第二次刻蚀工艺去除第一过孔11下方的钝化层104，露出漏电极4；同时去除第二过孔12下方的钝化层104，露出公共信号线20；同时还去除第三过孔13下方的钝化层104，露出数据线10，具体如图6和图7所示。
钝化层104可以为SiO 2、SiON、SiN膜层或者它们的组合膜层，厚度可以为
Figure PCTCN2019084226-appb-000019
具体地，可以通过等离子体增强化学的气相沉积法形成钝化层104，并在250℃～350℃的温度范围内进行退火工艺，保证TFT的特性。
平坦层105可以由有机树脂制得以提供平坦表面，其厚度可以为1.7～2.2μm。
步骤S6：在平坦层105的背离钝化层104的表面上形成公共电极6以及连接电极7，公共电极6通过第二过孔12与公共信号线20电性接触，连接电极7通过第三过孔13与数据线10电性接触，具体如图6和图7所示。
公共电极6由透明的金属氧化物制得，如：HIZO、ZnO、TiO 2、CdSnO、MgZnO、IGO、IZO、ITO或IGZO。在形成制备公共电极6的第一透明导电薄膜时，可以降低成膜气氛中的氧含量，以降低公共电极6的方块电阻，满足透明电极的导电性能需求。具体操作工艺条件可以参见源电极和漏电极的制备工艺条件。
可选地，公共电极6的厚度可以为
Figure PCTCN2019084226-appb-000020
步骤S7：形成覆盖公共电极6的层间绝缘层106，并通过第二次刻蚀工艺在层间绝缘层106中形成第四过孔14，以露出漏电极4，同时在层间绝缘层106中形成第五过孔17，以露出连接电极7，具体如图8所示。
层间绝缘层106可以为SiO 2、SiON、SiN膜层或这些膜层的组合膜层，厚度为
Figure PCTCN2019084226-appb-000021
步骤S8：在层间绝缘层106上形成像素电极5，像素电极5通过第四过孔14与漏电极4电性接触，且像素电极5通过第五过孔15与连接电极7电性接触，像素电极5通过连接电极7与数据线10电性连接，具体如图1所示。
像素电极5由透明的金属氧化物如：HIZO、ZnO、TiO 2、CdSnO、MgZnO、IGO、IZO、ITO或IGZO制得。在形成用于制备像素电极5的第一透明导电薄膜时，可以降低成膜气氛中的氧含量，以降低像素电极5的方块电阻，满足透明电极的导电性能需求。可选择地，像素电极5的厚度为
Figure PCTCN2019084226-appb-000022
至此完成显示基板的制作。
在可选的制备方法中，透明电极(包括像素电极和公共电极)、源电极、漏电极与有源层可以采用同一成膜腔室，能够极大提高生产效率，降低生产成本。在制备透明电极、源电极和漏电极的过程中，仅需调整成膜气氛中的氧含量，使得制得的薄膜满足透明电极、源电极和漏电极的方块电阻需求。
通过上述方法制备的显示基板的透明电极、源电极、漏电极和有源层的材料均为金属氧化物材料，所以各层可以由同一成膜腔室制得。当显示装置采用上述显示基板时，能够提高显示装置的量产效率、降低生产成本。
以上所述仅是本公开的可选实施方式。应当了解的是，对于本技术领域的普通技术人员来说，在不脱离本公开的技术原理的前提下，还可以做出若干改进和替换，这些改进和替换也应视为落入本公开的保护范围内。

Claims (22)

  1. 一种用于制备薄膜晶体管的方法，包括形成源电极、漏电极和有源层的步骤，其中，所述形成源电极、漏电极和有源层的步骤包括：
    在第一氧含量的气氛中，由第一金属氧化物材料形成第一薄膜；以及
    在第二氧含量的气氛中，由第二金属氧化物材料形成第二薄膜，
    其中，所述第一薄膜用于形成有源层，所述第二薄膜用于形成源电极和漏电极，并且所述第二氧含量小于所述第一氧含量。
  2. 根据权利要求1所述的方法，其中，所述形成源电极、漏电极和有源层的步骤还包括在第二温度下对所述第二薄膜进行退火工艺。
  3. 根据权利要求1所述的方法，其中，所述第二氧含量小于或等于30％(v/v)。
  4. 根据权利要求1所述的方法，其中，所述第二氧含量为30％(v/v)，所述第二薄膜的厚度大于或等于
    Figure PCTCN2019084226-appb-100001
  5. 根据权利要求2所述的方法，其中，所述第二温度在240℃～260℃范围内。
  6. 根据权利要求1所述的方法，其中，在第二氧含量的气氛中由第二金属氧化物材料形成第二薄膜的步骤包括：在第二氧含量大于0的气氛中，通入含H原子的气体，由所述第二金属氧化物材料形成第二薄膜。
  7. 根据权利要求1所述的方法，其中，在第二氧含量的气氛中由第二金属氧化物材料形成第二薄膜的步骤包括：在第二氧含量为0的气氛中，通入含H原子的气体，由所述第二金属氧化物材料形成第二薄膜。
  8. 根据权利要求6或7所述的方法，其中，所述含H原子的气体为选自水蒸气和氨气中的一种或多种。
  9. 根据权利要求8所述的方法，其中，所述含H原子的气体为水蒸气，所述水蒸气的通入速度大于或等于1sccm。
  10. 根据权利要求7-9中任一项所述的方法，其中，所述第二薄膜的厚度大于或等于
    Figure PCTCN2019084226-appb-100002
  11. 根据权利要求1所述的方法，其中，所述形成源电极、漏电极和有 源层的步骤还包括在第一温度下对所述第一薄膜进行退火工艺。
  12. 根据权利要求11所述的方法，其中，所述第一温度是在300℃～420℃范围内。
  13. 根据权利要求1-12中任一项所述的方法，其中，所述第一金属氧化物材料和第二金属氧化物材料为同种金属氧化物材料。
  14. 根据权利要求1-13中任一项所述的方法，其中，所述第一薄膜和所述第二薄膜是在同一腔室和使用相同靶材通过溅射工艺来形成的。
  15. 根据权利要求13或14所述的方法，其中，所述第一金属氧化物材料和第二金属氧化物材料均包括氧化铟镓锡和氧化铟的混合物，所述第一金属氧化物材料和第二金属氧化物材料中铟的摩尔含量大于或等于50摩尔％。
  16. 根据权利要求1-15中任一项所述的方法，其中，所述形成源电极、漏电极和有源层的步骤包括：
    在所述第一薄膜上形成所述第二薄膜；以及
    对所述第一薄膜和第二薄膜进行一次构图工艺以形成源电极、漏电极和有源层。
  17. 根据权利要求16所述的方法，其中，所述对所述第一薄膜和第二薄膜进行一次构图工艺以形成源电极、漏电极和有源层的步骤包括：
    在所述第二薄膜上涂覆光刻胶，对所述光刻胶进行曝光、显影后，形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶不保留区域，其中，所述光刻胶完全保留区域对应所述源电极和漏电极所在的区域，所述光刻胶部分保留区域对应所述有源层所在的区域，所述光刻胶不保留区域对应其他区域；
    去除光刻胶不保留区域的第一薄膜和第二薄膜；
    通过灰化工艺去除所述光刻胶部分保留区域的光刻胶，然后去除所述光刻胶部分保留区域的第二薄膜；以及
    剥离剩余的光刻胶，形成有源层、源电极和漏电极。
  18. 一种薄膜晶体管，包括有源层、源电极和漏电极，其中，所述源电极和漏电极与所述有源层由同种金属氧化物材料制成，所述源电极和漏电极的方块电阻小于5×10 2Ω/口，形成源电极和漏电极后的金属氧化物材料中的 氧含量相对于该金属氧化物的化学计量比氧含量低至少0.5％。
  19. 根据权利要求18所述的薄膜晶体管，其中，所述第一金属氧化物材料和第二金属氧化物材料均为氧化铟镓锡和氧化铟的混合物，所述第一金属氧化物材料和第二金属氧化物材料中铟的摩尔含量大于或等于75摩尔％。
  20. 根据权利要求19所述的薄膜晶体管，其中，相对于金属氧化物的总原子数，形成源电极和漏电极后的金属氧化物材料含有0.01％～5％的H原子。
  21. 一种显示基板，包括权利要求18-20中任一项所述的薄膜晶体管。
  22. 一种显示装置，包括权利要求21所述的显示基板。
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