WO2023178763A1 - 薄膜晶体管阵列基板的制造方法及显示面板 - Google Patents

薄膜晶体管阵列基板的制造方法及显示面板 Download PDF

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WO2023178763A1
WO2023178763A1 PCT/CN2022/087106 CN2022087106W WO2023178763A1 WO 2023178763 A1 WO2023178763 A1 WO 2023178763A1 CN 2022087106 W CN2022087106 W CN 2022087106W WO 2023178763 A1 WO2023178763 A1 WO 2023178763A1
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Prior art keywords
metal oxide
thin film
film transistor
transistor array
array substrate
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PCT/CN2022/087106
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English (en)
French (fr)
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赵军
赵斌
肖军城
李珊
吴伟
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广州华星光电半导体显示技术有限公司
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Priority to US17/756,639 priority Critical patent/US20240162253A1/en
Publication of WO2023178763A1 publication Critical patent/WO2023178763A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1277—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using a crystallisation promoting species, e.g. local introduction of Ni catalyst
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present application relates to the field of display technology, and in particular to a manufacturing method of a thin film transistor array substrate and a display panel.
  • metal oxide semiconductor layers usually require a high temperature above 600°C to crystallize, and there is a problem of too high crystallization temperature.
  • the purpose of this application is to provide a manufacturing method of a thin film transistor array substrate and a display panel to reduce the temperature required for crystallization of the crystallized metal oxide semiconductor layer of the thin film transistor.
  • a method of manufacturing a thin film transistor array substrate comprising:
  • the amorphous metal oxide semiconductor layer is annealed to obtain a crystallized metal oxide semiconductor layer.
  • a display panel includes a thin film transistor array substrate, and the thin film transistor array substrate is prepared by the above method for manufacturing a thin film transistor array substrate.
  • the present application provides a method for manufacturing a thin film transistor array substrate and a display panel.
  • a method for manufacturing a thin film transistor array substrate and a display panel By forming a plurality of dispersed metal oxide grains on the substrate, an amorphous metal oxide semiconductor in contact with the plurality of metal oxide grains is formed.
  • layer, at least one metal element in the metal oxide grains is the same as the metal element in the metal oxide semiconductor layer, the amorphous metal oxide semiconductor layer is annealed, and the metal oxide grains are in the metal oxide semiconductor layer It plays the role of inducing crystallization during the layer annealing process, reducing the crystallization temperature required for annealing the amorphous metal oxide semiconductor layer, improving the stability of the metal oxide thin film transistor, and is beneficial to the metal oxide thin film transistor. Display panels achieve mass production.
  • Figure 1 is a schematic flow chart of manufacturing a thin film transistor array substrate in the first embodiment of the present application
  • 2A-2G are schematic diagrams of the manufacturing process of the thin film transistor array substrate in the first embodiment of the present application.
  • Figure 3 is an X-ray diffraction pattern of crystalline indium tin oxide and amorphous indium tin oxide in the metal oxide film layer when the metal oxide film layer in Figure 2C is an indium tin oxide layer;
  • Figure 4 is a scanning electron microscope image of multiple dispersed metal oxide grains
  • Figure 5 is an X-ray diffraction pattern of amorphous indium gallium zinc oxide of the amorphous metal oxide semiconductor layer in Figure 2E and crystallized indium gallium zinc oxide of the crystallized metal oxide semiconductor layer in Figure 2F;
  • Figure 6 is a schematic flow chart of manufacturing a thin film transistor array substrate in the second embodiment of the present application.
  • Figure 7 is a schematic flow chart of manufacturing a thin film transistor array substrate in the third embodiment of the present application.
  • 8A-8F are schematic diagrams of the manufacturing process of the thin film transistor array substrate in the third embodiment of the present application.
  • FIG. 1 is a schematic flow chart of manufacturing a thin film transistor array substrate in the first embodiment of the present application.
  • the method of manufacturing a thin film transistor array substrate includes the following steps:
  • a substrate 10 is provided, a first conductive layer is deposited on the substrate 10 by physical sputtering, and a first patterning process is used to pattern the first conductive layer to obtain a gate electrode 111, as shown in FIG. 2A.
  • the thickness of the first conductive layer ranges from 800 angstroms to 10,000 angstroms, such as 1,000 angstroms, 1,500 angstroms, 1,600 angstroms, 2,000 angstroms, 2,500 angstroms, 3,000 angstroms, 4,000 angstroms and 5,000 angstroms.
  • the first conductive layer is made of at least one material selected from molybdenum, aluminum, titanium, copper, and silver.
  • the metal oxide film layer includes crystalline metal oxide and amorphous metal oxide.
  • the thickness of the gate insulating layer 12 ranges from 800 angstroms to 3000 angstroms, such as 1000 angstroms, 1500 angstroms, 1600 angstroms, 2000 angstroms, 2500 angstroms and 3000 angstroms.
  • the gate insulating layer 12 is made of at least one material selected from silicon nitride or silicon oxide.
  • a metal oxide film layer 13 is formed on the gate insulating layer 12 by magnetron sputtering physical vapor deposition in an inert gas, as shown in FIG. 2C .
  • the metal oxide film layer 13 includes crystalline metal oxide and amorphous metal oxide.
  • the thickness of the metal oxide film layer 13 is greater than or equal to 200 nanometers and less than or equal to 1500 nanometers, such as 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers, 800 nanometers, 1000 nanometers, 1200 nanometers, 1300 nanometers and 1500 nanometers. nanometer.
  • the metal in the metal oxide film layer 13 includes one or two types of In, Ga, Zn, and Sn. Inert gases include argon.
  • the first metal oxide target is indium tin oxide (ITO, Indium Tin Oxide) target
  • the thickness of the metal oxide film layer 13 is 1500 angstroms.
  • the indium tin oxide layer includes crystalline indium tin oxide and amorphous indium tin oxide.
  • the crystallization peak of crystalline indium tin oxide is at 30.69°, and the amorphous oxide layer Indium tin does not show obvious crystallization peaks.
  • indium tin oxide is a mixture of indium oxide (In 2 O 3 ) and tin oxide (SnO 2 ), and the weight proportion of indium oxide (In 2 O 3 ) is about 90%.
  • the crystallized indium tin oxide is mainly indium oxide, and part of the tin oxide is solidly dissolved in the indium oxide lattice.
  • the crystallized indium tin oxide will induce the indium oxide in the amorphous semiconductor layer containing indium oxide to grow along the crystal nucleus, making the amorphous
  • the semiconductor layer is converted into a crystalline semiconductor layer.
  • the metal oxide film layer 13 may also be made of indium oxide, zinc oxide or indium zinc oxide. Compared with the preparation material of the metal oxide film layer 13 which is also indium oxide, zinc oxide or indium zinc oxide, indium tin oxide is a commonly used material in the display panel manufacturing process, and its technology is very mature.
  • wet etching is used to remove a plurality of amorphous metal oxides, and a plurality of dispersed metal oxide crystal grains 131 located on the surface of the gate insulating layer 12 away from the gate electrode 111 are obtained, as shown in FIG. 2D .
  • the size of the metal oxide grain 131 is greater than or equal to 5 nanometers and less than or equal to 100 nanometers.
  • the size of the metal oxide grains is 10 nanometers, 20 nanometers, 30 nanometers, 40 nanometers, 50 nanometers, 60 nanometers, 70 nanometers or 80 nanometers to ensure the inducing crystallization performance of the metal oxide grains 131 while preventing the metal oxide grains 131 from aggregating into flakes.
  • the solvent for wet etching is oxalic acid or nitric sulfuric acid.
  • the etching rate of crystalline metal oxide is much lower than the etching rate of amorphous metal oxide. Therefore, after the amorphous metal oxide is etched, multiple dispersed particles composed of crystalline metal oxide will remain. metal oxide grains.
  • the etching rate of crystalline indium tin oxide is only about 1/100 of the etching rate of amorphous indium tin oxide. Therefore, after etching amorphous indium tin oxide, crystalline indium tin oxide will remain.
  • the crystalline oxide in the metal oxide film layer is more difficult to interact with the amorphous metal oxide semiconductor layer.
  • the problem of contact makes it difficult to induce crystallization of the amorphous metal oxide semiconductor layer.
  • the amorphous metal oxide in the metal oxide film layer is removed, while the metal oxide grains composed of crystalline oxide are retained.
  • the metal oxide The crystal grains are used to induce the crystallization of the subsequently formed amorphous metal oxide semiconductor layer.
  • the metal oxide crystal grains can more fully contact the amorphous metal oxide semiconductor layer, making it easier to induce amorphous metal oxide at lower temperatures.
  • the semiconductor layer crystallizes.
  • the metal oxide film layer 13 is made of indium tin oxide, the indium tin oxide layer is conductive, and the conductive metal oxide film layer 13 is directly used to induce the crystallization of the subsequent amorphous metal oxide semiconductor layer, which will cause This causes a problem that the conductive metal oxide film layer 13 makes the channel of the metal oxide semiconductor layer conductive, thereby causing the channel function of the metal oxide semiconductor layer to fail.
  • the metal oxide film layer 13 is made of indium oxide, zinc oxide or indium zinc oxide, the crystalline oxide in the metal oxide film layer 13 is used to induce the crystallization of the amorphous metal oxide semiconductor layer, which may lead to metal oxidation.
  • the material film layer 13 has a semiconductor front channel, which is inconsistent with the design that the subsequently formed metal oxide semiconductor film layer has a semiconductor front channel.
  • S103 Form an amorphous metal oxide semiconductor layer in contact with multiple metal oxide crystal grains, and at least one metal element in the metal oxide crystal grains is the same as the metal element in the metal oxide semiconductor layer.
  • the thickness of the metal oxide semiconductor layer 14 is greater than or equal to 10 nanometers and less than or equal to 2000 nanometers, for example, 50 nanometers, 100 nanometers, 150 nanometers, 200 nanometers, 300 nanometers, 500 nanometers, 800 nanometers, 1000 nanometers, 1200 nanometers. , 1500 nanometer, 1600 nanometer, 1800 nanometer.
  • the metal elements in the metal oxide semiconductor layer 14 include at least three types of In, Ga, Zn, and Sn.
  • Inert gases include argon.
  • At least one metal element in the metal oxide grains is the same as the metal element in the metal oxide semiconductor layer, so that the metal oxide grains can induce amorphous metal during the annealing process of the amorphous metal oxide semiconductor layer.
  • the oxide semiconductor layer crystallizes.
  • the metal elements in the metal oxide semiconductor layer 14 include In, Ga, and Zn
  • the metal elements in the metal oxide crystal grains 131 include at least one of In, Ga, and Zn.
  • the metal elements in the metal oxide semiconductor layer include In, Ga, and Sn
  • the metal elements in the metal oxide crystal grains include at least one of In, Ga, and Sn.
  • the metal oxide film layer 13 is an indium tin oxide layer
  • the second metal oxide target material is an indium gallium zinc oxide layer
  • the metal oxide semiconductor layer 14 is an indium gallium zinc oxide layer.
  • line 1 and line 2 in Figure 5 are the X-ray diffraction patterns of amorphous indium gallium zinc oxide obtained under different deposition powers.
  • the dotted line box is the crystallization characteristic peak of the glass substrate, and no other related crystallization characteristics appear. Therefore, amorphous indium gallium zinc oxide does not have crystalline characteristic peaks.
  • S104 Perform annealing treatment on the amorphous metal oxide semiconductor layer to obtain a crystallized metal oxide semiconductor layer.
  • the amorphous metal oxide semiconductor layer 14 is heated at an annealing temperature greater than or equal to 300 degrees and less than or equal to 450 degrees for 0.5 to 1.5 hours, and then a second patterning process is used to oxidize the annealed metal.
  • the physical semiconductor layer 14 is patterned to obtain a crystallized metal oxide semiconductor layer 141, as shown in FIG. 2F.
  • the annealing temperature can be 320 degrees, 350 degrees, 380 degrees, 400 degrees, 420 degrees and 450 degrees
  • the annealing time can be 30 minutes, 40 minutes, 50 minutes, 60 minutes or 80 minutes.
  • line 3 and line 4 in Figure 5 are the X-ray diffraction patterns of crystalline indium gallium zinc oxide obtained by annealing after obtaining amorphous indium gallium zinc oxide layer under different deposition powers. Crystalline indium gallium oxide The crystallization characteristic peak of zinc is about 30°. Combining lines 3 and 4 in Figure 5, it can be seen that depositing amorphous indium gallium zinc oxide layers under different deposition conditions will not affect the crystallization of crystalline indium gallium zinc oxide.
  • the lattice parameters of the crystals in the metal oxide grains are the same as those in the crystalline metal oxide semiconductor layer.
  • the lattice parameters of the crystals are similar.
  • the metal oxide grains serve as crystal nuclei to induce the amorphous metal oxide semiconductor layer to crystallize at a temperature lower than 450 degrees. Compared with the crystallization temperature of the traditional metal oxide semiconductor layer Greater than or equal to 600 degrees, it significantly reduces the crystallization temperature of the amorphous metal oxide semiconductor layer, which is beneficial to the mass production of crystallized metal oxide thin film transistors and improves the device stability of metal oxide transistors.
  • S105 Form source and drain electrodes on the substrate, and contact the source and drain electrodes with the crystallized metal oxide semiconductor layer to obtain a thin film transistor array substrate.
  • the thin film transistor array substrate includes source and drain electrodes, and the source and drain electrodes include source electrodes 151 and drain electrodes 152, as shown in Figure 2G.
  • the thickness of the second conductive layer is 1,000 angstroms to 10,000 angstroms.
  • the second conductive layer is made of at least one material selected from molybdenum, aluminum, titanium, copper and silver.
  • the manufacturing method of the thin film transistor array substrate in this embodiment forms a plurality of dispersed metal oxide crystal grains on the substrate to form an amorphous metal oxide semiconductor layer in contact with the plurality of metal oxide crystal grains.
  • the metal oxide At least one metal element in the crystal grains is the same as the metal element in the metal oxide semiconductor layer.
  • the amorphous metal oxide semiconductor layer is annealed, and the metal oxide crystal grains are annealed during the annealing process of the metal oxide semiconductor layer. It plays the role of inducing crystallization, reduces the crystallization temperature required for annealing the amorphous metal oxide semiconductor layer, improves the stability of metal oxide thin film transistors, and is conducive to the mass production of metal oxide thin film transistor array substrates. .
  • FIG. 6 is a schematic flow chart of manufacturing a thin film transistor array substrate in the second embodiment of the present application.
  • the flow diagram shown in Figure 6 is basically similar to the flow diagram shown in Figure 1, except that S106 in Figure 6 replaces S101 in Figure 1, and S107 in Figure 6 replaces S102 in Figure 1.
  • S106 is basically similar to S101, except that the thickness of the metal oxide film layer 13 is greater than or equal to 10 nanometers and less than or equal to 200 nanometers, that is, the thickness of the metal oxide film layer 13 in S106 is thinner, for example, 10 nanometers, 15nm, 20nm, 50nm or 100nm.
  • S107 is to perform annealing treatment on the metal oxide film layer 13 to obtain a plurality of dispersed metal oxide crystal grains 131 .
  • the conditions for the annealing treatment are that the temperature is greater than or equal to 100 degrees and less than or equal to 400 degrees, and the time is greater than or equal to 1 minute and less than or equal to 2 hours.
  • the annealing temperature of the metal oxide film layer 13 can be 120 degrees, 150 degrees, 180 degrees, 200 degrees, 220 degrees, 250 degrees, 300 degrees, 320 degrees, 350 degrees, 380 degrees.
  • the annealing time of the metal oxide film layer 13 It is 1min, 3min, 15min, 30min, 50min, 60min, 80min, 90min or 120min.
  • this embodiment is by manufacturing a thinner metal oxide film layer.
  • the metal oxide film layer is a thin metal oxide film layer after annealing.
  • the thin metal oxide film layer crystallizes and shrinks in volume during the annealing process, thereby obtaining multiple dispersed metal oxide grains.
  • FIG. 7 is a schematic flow chart of manufacturing a thin film transistor array substrate in the third embodiment of the present application.
  • the method of manufacturing a thin film transistor array substrate includes:
  • S200 Form multiple dispersed metal oxide crystal grains on the substrate.
  • steps S101 and S102 in the first embodiment are used in sequence, or the methods in steps S106 and S107 in the second embodiment are used in sequence to form a plurality of dispersed metals on the surface of the substrate 10 Oxide grains 131 are shown in Figure 8A.
  • S201 Form an amorphous metal oxide semiconductor layer in contact with multiple metal oxide crystal grains, and at least one metal element in the metal oxide crystal grains is the same as the metal element in the metal oxide semiconductor layer.
  • step S103 in the first embodiment is used to form an amorphous metal oxide semiconductor layer 14 covering the substrate 10 and a plurality of dispersed metal oxide grains 131, as shown in FIG. 8B.
  • step S104 in the first embodiment is used to form the crystallized metal oxide semiconductor layer 141, as shown in FIG. 8C; chemical vapor deposition is used to form a gate covering the crystallized metal oxide semiconductor layer 141 and the substrate 10. Extremely insulating layer 12, as shown in Figure 8D.
  • S203 Form a gate on the substrate.
  • the gate electrode 111 is formed on the side of the gate insulating layer 12 away from the crystallized metal oxide semiconductor layer 141; chemical vapor deposition is used to form the interlayer insulating layer 16 covering the gate electrode 111 and the gate insulating layer 12, and The yellow photo process and the etching process process the interlayer insulating layer 16 and the gate insulating layer 12 to obtain the first contact hole 16a and the second contact hole 16b penetrating the interlayer insulating layer 16 and the gate insulating layer 12.
  • the hole 16a and the second contact hole 16b are located on opposite sides of the gate electrode 111 and are provided corresponding to the crystallized metal oxide semiconductor layer 141, as shown in FIG. 8E.
  • the thickness of the interlayer insulating layer 16 is 3000 angstroms to 6000 angstroms.
  • the interlayer insulating layer 16 is made of at least one material selected from silicon nitride and silicon oxide.
  • S204 Form source and drain electrodes on the substrate, and contact the source and drain electrodes with the crystallized metal oxide semiconductor layer to obtain a thin film transistor array substrate.
  • step S105 in the first embodiment is used to form the source electrode 151 and the drain electrode 152.
  • the source electrode 151 contacts the crystallized metal oxide semiconductor layer 141 through the first contact hole 16a, and the drain electrode 152 passes through the second contact hole 16a.
  • the contact hole 16b is in contact with the crystallized metal oxide semiconductor layer 141, as shown in FIG. 8F.
  • This application also provides a thin film transistor array substrate, which is prepared by any of the above manufacturing methods for a thin film transistor array substrate.
  • This application also provides a display panel, which includes the above-mentioned thin film transistor array substrate.

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Abstract

本申请提供一种薄膜晶体管阵列基板的制造方法及显示面板，包括：于基板上形成多个分散的金属氧化物晶粒；形成与多个金属氧化物晶粒接触的非晶态的金属氧化物半导体层，金属氧化物晶粒中的至少一种金属元素与金属氧化物半导体层中的金属元素相同；对非晶态的金属氧化物半导体层进行退火处理，得到结晶化金属氧化物半导体层。

Description

薄膜晶体管阵列基板的制造方法及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种薄膜晶体管阵列基板的制造方法及显示面板。
 背景技术
随着显示面板向着大尺寸、高分辨率、高频率及自发光显示模式等方向发展，显示面板对于控制开关和驱动显示的薄膜晶体管的迁移率和稳定性提出了越来越高的要求，而目前显示行业常用的非晶硅薄膜晶体管器件的迁移率低，开态电流低，无法满足高阶显示产品的需求，而金属氧化物晶体管迁移率为非晶硅晶体管的10倍~100倍，可以满足高阶显示产品的需求，因此金属氧化物晶体管越来越受到业界的重视。
然而，常用的金属氧化物半导体层通常需要在600℃以上的高温下才会发生结晶行为，存在结晶温度过高的问题。
 技术问题
本申请的目的在于提供一种薄膜晶体管阵列基板的制造方法及显示面板，以降低薄膜晶体管的结晶化金属氧化物半导体层结晶所需的温度。
 技术解决方案
一种薄膜晶体管阵列基板的制造方法，所述方法包括：
于基板上形成多个分散的金属氧化物晶粒；
形成与多个所述金属氧化物晶粒接触的非晶态的金属氧化物半导体层，所述金属氧化物晶粒中的至少一种金属元素与所述金属氧化物半导体层中的金属元素相同；
对非晶态的所述金属氧化物半导体层进行退火处理，得到结晶化金属氧化物半导体层。
一种显示面板，所述显示面板包括薄膜晶体管阵列基板，所述薄膜晶体管阵列基板由上述薄膜晶体管阵列基板的制造方法制备得到。
 有益效果
本申请提供一种薄膜晶体管阵列基板的制造方法及显示面板，通过于基板上形成多个分散的金属氧化物晶粒，形成与多个金属氧化物晶粒接触的非晶态的金属氧化物半导体层，金属氧化物晶粒中的至少一种金属元素与金属氧化物半导体层中的金属元素相同，对非晶态的金属氧化物半导体层进行退火处理，金属氧化物晶粒在金属氧化物半导体层退火处理过程中起到诱导结晶的作用，降低对非晶态的金属氧化物半导体层进行退火处理所需的结晶温度，提高金属氧化物薄膜晶体管稳定性的同时，有利于金属氧化物薄膜晶体管显示面板实现量产。
 附图说明
图1为本申请第一实施例中制造薄膜晶体管阵列基板的流程示意图；
图2A-图2G为本申请第一实施例中薄膜晶体管阵列基板的制造过程示意图；
图3为图2C中金属氧化物膜层为氧化铟锡层时金属氧化物膜层中结晶氧化铟锡和非结晶氧化铟锡的X射线衍射图；
图4为多个分散的金属氧化物晶粒的扫描电镜图；
图5为图2E中非结晶的金属氧化物半导体层的非结晶氧化铟镓锌和图2F中结晶化金属氧化物半导体层的结晶氧化铟镓锌的X射线衍射图；
图6为本申请第二实施例中制造薄膜晶体管阵列基板的流程示意图；
图7为本申请第三实施例中制造薄膜晶体管阵列基板的流程示意图；
图8A-图8F为本申请第三实施例中薄膜晶体管阵列基板的制造过程示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，其为本申请第一实施例中制造薄膜晶体管阵列基板的流程示意图。制造薄膜晶体管阵列基板的方法包括如下步骤：
S100：于基板上形成栅极。
提供一基板10，采用物理溅射沉积于基板10上形成第一导电层，采用第一次构图工艺对第一导电层进行图案化，得到栅极111，如图2A所示。其中，第一导电层的厚度为800埃-10000埃，例如为1000埃、1500埃、1600埃、2000埃、2500埃、3000埃、4000埃以及5000埃。第一导电层的制备材料选自钼、铝、钛、铜、银中的至少一种。
S101：于基板上形成金属氧化物膜层，金属氧化物膜层包括结晶金属氧化物和非结晶金属氧化物。
首先，采用化学气相沉积形成覆盖栅极111和基板10的栅极绝缘层12，如图2B所示。其中，栅极绝缘层12的厚度为800埃-3000埃，例如为1000埃、1500埃、1600埃、2000埃、2500埃以及3000埃。栅极绝缘层12的制备材料选自氮化硅或氧化硅中的至少一种。
继而，以第一金属氧化物靶材作为原料，利用磁控溅射物理气相沉积在惰性气体中于栅极绝缘层12上形成金属氧化物膜层13，如图2C所示。金属氧化物膜层13包括结晶金属氧化物和非结晶金属氧化物。金属氧化物膜层13的厚度大于或等于200纳米且小于或等于1500纳米，例如为300纳米、400纳米、500纳米、600纳米、700纳米、800纳米、1000纳米、1200纳米、1300纳米以及1500纳米。金属氧化物膜层13中的金属包括In，Ga，Zn，Sn中的一种或两种。惰性气体包括氩气。
具体地，第一金属氧化物靶为氧化铟锡（ITO，Indium Tin Oxide）靶，金属氧化物膜层13的厚度为1500埃。
如图3所示，金属氧化物膜层13为氧化铟锡层时，氧化铟锡层包括结晶氧化铟锡和非结晶氧化铟锡，结晶氧化铟锡的结晶峰在30.69°，非结晶氧化物铟锡没有出现明显的结晶峰。
需要说明的是，氧化铟锡为氧化铟（In 2O 3）和氧化锡（SnO 2）的混合物，氧化铟（In 2O 3）的重量占比约为90%。结晶氧化物铟锡是以氧化铟为主，部分氧化锡固溶在氧化铟晶格中，结晶氧化铟锡会诱导含有氧化铟的非结晶半导体层中的氧化铟沿晶核生长，使得非结晶半导体层转换为结晶态的半导体层。
可以理解的是，金属氧化物膜层13的制备材料也可以为氧化铟、氧化锌或者氧化铟锌。相较于金属氧化物膜层13的制备材料也为氧化铟、氧化锌或者氧化铟锌，氧化铟锡是显示面板制程中常用的材料，其工艺非常成熟。
S102：去除非结晶金属氧化物，得到多个分散的金属氧化物晶粒。
采用湿法蚀刻去除多个非结晶金属氧化物，得到多个位于栅极绝缘层12远离栅极111的表面上的分散的金属氧化物晶粒131，如图2D所示。其中，金属氧化物晶粒131的尺寸大于或等于5纳米且小于或等于100纳米，例如，金属氧化物晶粒的尺寸为10纳米、20纳米、30纳米、40纳米、50纳米、60纳米、70纳米或者80纳米，以保证金属氧化物晶粒131诱导结晶性能的同时，避免金属氧化物晶粒131聚集成片状。湿法蚀刻的溶剂为草酸或者硝硫酸。
如图4所示，金属氧化物膜层13为氧化铟锡时，多个结晶氧化铟锡晶粒（白色部分）无规律地分散。
需要说明的是，由于湿法蚀刻时，结晶金属氧化物的蚀刻速率远小于非结晶金属氧化物的蚀刻速率，故非结晶金属氧化物蚀刻完后，会残留结晶金属氧化物组成的多个分散的金属氧化物晶粒。例如，结晶氧化铟锡的蚀刻速率仅为非结晶氧化铟锡的蚀刻速率约1/100，因此，非结晶氧化铟锡蚀刻后，结晶态氧化铟锡会残留。
另外，相较于以金属氧化物膜层中的结晶氧化物诱导后续的非结晶金属氧化物半导体层结晶，存在金属氧化物膜层中的结晶氧化物较难与非结晶的金属氧化物半导体层接触的问题，导致较难诱导非结晶的金属氧化物半导体层结晶，本申请将金属氧化物膜层中非结晶金属氧化物去除，而保留结晶氧化物组成的金属氧化物晶粒，金属氧化物晶粒用于诱导后续形成的非结晶的金属氧化物半导体层结晶，金属氧化物晶粒能更充分与非结晶的金属氧化物半导体层接触，更容易在较低温度下诱导非结晶金属氧化物半导体层结晶。
再者，由于金属氧化物膜层13的制备材料为氧化铟锡时，氧化铟锡层具有导电性，直接以导电的金属氧化物膜层13诱导后续非结晶的金属氧化物半导体层结晶，会导致导电的金属氧化物膜层13使金属氧化物半导体层的沟道导通的问题，进而导致金属氧化物半导体层的沟道功能失效。另外，金属氧化物膜层13的制备材料为氧化铟、氧化锌或者氧化铟锌时，以金属氧化物膜层13中的结晶氧化物诱导非结晶的金属氧化物半导体层结晶，会导致金属氧化物膜层13具有半导体前沟道，与后续形成的金属氧化物半导体膜层具有半导体前沟道的设计不符。
S103：形成与多个金属氧化物晶粒接触的非晶态的金属氧化物半导体层，金属氧化物晶粒中的至少一种金属元素与金属氧化物半导体层中的金属元素相同。
以第二金属氧化物靶材为原料，利用磁控溅射物理气相沉积在惰性气体和氧气的混合气氛中于栅极绝缘层12上形成非结晶的金属氧化物半导体层14，如图2E所示。其中，金属氧化物半导体层14的厚度大于或等于10纳米且小于或等于2000纳米，例如为50纳米、100纳米、150纳米、200纳米、300纳米、500纳米、800纳米、1000纳米、1200纳米、1500纳米、1600纳米、1800纳米。金属氧化物半导体层14中的金属元素包括In，Ga，Zn，Sn中的至少三种。惰性气体包括氩气。
金属氧化物晶粒中的至少一种金属元素与金属氧化物半导体层中的金属元素相同，以使得非结晶态的金属氧化物半导体层退火过程中金属氧化物晶粒能诱导非结晶态的金属氧化物半导体层结晶。例如，金属氧化物半导体层14中的金属元素包括In、Ga以及Zn，金属氧化物晶粒131中的金属元素包括In、Ga、Zn中的至少一种。或者，金属氧化物半导体层中的金属元素包括In、Ga以及Sn，金属氧化物晶粒中的金属元素包括In、Ga以及Sn中的至少一种。
具体地，在金属氧化物膜层13为氧化铟锡层时，第二金属氧化物靶材为氧化铟镓锌，金属氧化物半导体层14为氧化铟镓锌层。
如图5所示，图5中线1和线2为不同沉积功率下得到的非晶态氧化铟镓锌的X射线衍射图，虚线框中为玻璃基板的结晶特征峰，未出现其他相关结晶特征峰，因此，非结晶氧化铟镓锌物没有结晶特征峰。
S104：对非晶态的金属氧化物半导体层进行退火处理，得到结晶化金属氧化物半导体层。
具体地，在退火温度大于或等于300度且小于或等于450度条件下对非晶态的金属氧化物半导体层14加热0.5小时至1.5小时，再采用第二次构图工艺对退火处理的金属氧化物半导体层14进行图案化，得到结晶化金属氧化物半导体层141，如图2F所示。其中，退火温度可以为320度、350度、380度、400度、420度以及450度，退火时间可以为30分钟、40分钟、50分钟、60分钟或者80分钟。
如图5所示，图5中线3和线4是以不同沉积功率下得到非晶态的氧化铟镓锌层后经过退火处理得到的结晶氧化铟镓锌的X射线衍射图，结晶氧化铟镓锌的结晶特征峰约在30°。结合图5中线3和线4可知，不同沉积条件沉积非晶态氧化铟镓锌层不会对结晶氧化铟镓锌的结晶造成影响。
需要说明的是，由于金属氧化物晶粒中的至少一种金属元素与金属氧化物半导体层中的金属元素相同，使得金属氧化物晶粒中晶体的晶格参数与结晶金属氧化物半导体层中晶体的晶格参数相近，金属氧化物晶粒作为晶核起到诱导非晶态的金属氧化物半导体层在低于450度条件下结晶的作用，相较于传统金属氧化物半导体层的结晶温度大于或等于600度，显著地降低非晶态的金属氧化物半导体层结晶的温度，有利于结晶金属氧化物薄膜晶体管的量产，提高金属氧化物晶体管的器件稳定性。
S105：于基板上形成源漏电极，源漏电极与结晶化金属氧化物半导体层接触，得到薄膜晶体管阵列基板。
具体地，采用物理溅射沉积形成覆盖结晶化金属氧化物半导体层141和栅极绝缘层12的第二导电层，采用第三次构图工艺对第二导电层进行图案化，得到薄膜晶体管阵列基板，薄膜晶体管阵列基板包括源漏电极，源漏电极包括源极151和漏极152，如图2G所示。其中，第二导电层的厚度为1000埃-10000埃。第二导电层的制备材料选自钼、铝、钛、铜以及银中的至少一种。
本实施例制造薄膜晶体管阵列基板的制造方法通过于基板上形成多个分散的金属氧化物晶粒，形成与多个金属氧化物晶粒接触的非晶态的金属氧化物半导体层，金属氧化物晶粒中的至少一种金属元素与金属氧化物半导体层中的金属元素相同，对非晶态的金属氧化物半导体层进行退火处理，金属氧化物晶粒在金属氧化物半导体层退火处理过程中起到诱导结晶的作用，降低对非晶态的金属氧化物半导体层进行退火处理所需的结晶温度，提高金属氧化物薄膜晶体管稳定性的同时，有利于金属氧化物薄膜晶体管阵列基板实现量产。
请参阅图6，其为本申请第二实施例中制造薄膜晶体管阵列基板的流程示意图。图6所示流程示意图与图1所示流程示意图基本相似，不同之处在于，图6中S106替代图1中S101，且图6中S107替代图1中S102。
S106与S101基本相似，不同之处在于，金属氧化物膜层13的厚度大于或等于10纳米且小于或等于200纳米，即S106中金属氧化物膜层13的厚度更薄，例如为10纳米、15纳米、20纳米、50纳米或者100纳米。
S107为对金属氧化物膜层13进行退火处理，得到多个分散的金属氧化物晶粒131。其中，退火处理的条件为温度大于或等于100度且小于或等于400度，且时间大于或等于1min且小于或等于2h。金属氧化物膜层13的退火温度可以为120度、150度、180度、200度、220度、250度、300度、320度、350度、380度，金属氧化物膜层13的退火时间为1min、3min、15min、30min、50min、60min、80min、90min或者120min。
相较于第一实施例中通过制造厚度较厚的金属氧化物膜层，再经过蚀刻厚度较厚的金属氧化物膜层得到多个金属氧化物晶粒，本实施例通过制造厚度较薄的金属氧化物膜层，经过退火处理厚度较薄的金属氧化物膜层，厚度较薄的金属氧化物膜层在退火过程中结晶而体积收缩，进而得到多个分散的金属氧化物晶粒。
请参阅图7，其为本申请第三实施例中制造薄膜晶体管阵列基板的流程示意图，制造薄膜晶体管阵列基板的方法包括：
S200：于基板上形成多个分散的金属氧化物晶粒。
具体地，依次采用上述第一实施例中步骤S101和步骤S102中的方法，或者，依次采用第二实施例中步骤S106和步骤S107中的方法，在基板10的表面上形成多个分散的金属氧化物晶粒131，如图8A所示。
S201：形成与多个金属氧化物晶粒接触的非晶态的金属氧化物半导体层，金属氧化物晶粒中的至少一种金属元素与金属氧化物半导体层中的金属元素相同。
具体地，采用上述第一实施例中步骤S103的方法，形成覆盖基板10和多个分散的金属氧化物晶粒131的非晶态的金属氧化物半导体层14，如图8B所示。
S202：对非晶态的金属氧化物半导体层进行退火，得到结晶化金属氧化物半导体层。
具体地，采用上述第一实施例中步骤S104的方法，形成结晶化金属氧化物半导体层141，如图8C所示；采用化学气相沉积形成覆盖结晶化金属氧化物半导体层141和基板10的栅极绝缘层12，如图8D所示。
S203：于基板上形成栅极。
具体地，于栅极绝缘层12远离结晶化金属氧化物半导体层141的一侧形成栅极111；采用化学气相沉积形成覆盖栅极111和栅极绝缘层12的层间绝缘层16，且采用黄光制程以及蚀刻工艺对层间绝缘层16和栅极绝缘层12进行处理，得到贯穿层间绝缘层16和栅极绝缘层12的第一接触孔16a和第二接触孔16b，第一接触孔16a和第二接触孔16b位于栅极111的相对两侧且对应结晶化金属氧化物半导体层141设置，如图8E所示。
其中，层间绝缘层16的厚度为3000埃至6000埃。层间绝缘层16的制备材料选自氮化硅、氧化硅中的至少一种。
S204：于基板上形成源漏电极，源漏电极与结晶化金属氧化物半导体层接触，得到薄膜晶体管阵列基板。
具体地，采用上述第一实施例中步骤S105的方法，形成源极151和漏极152，源极151通过第一接触孔16a与结晶化金属氧化物半导体层141接触，漏极152通过第二接触孔16b与结晶化金属氧化物半导体层141接触，如图8F所示。
本申请还提供一种薄膜晶体管阵列基板，薄膜晶体管阵列基板由上述任意一种薄膜晶体管阵列基板的制造方法制备得到。
本申请还提供一种显示面板，显示面板包括上述薄膜晶体管阵列基板。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种薄膜晶体管阵列基板的制造方法，其中，所述方法包括：
    于基板上形成多个分散的金属氧化物晶粒，所述金属氧化物晶粒的尺寸大于或等于5纳米且小于或等于100纳米；
    形成与多个所述金属氧化物晶粒接触的非晶态的金属氧化物半导体层，所述金属氧化物晶粒中的至少一种金属元素与所述金属氧化物半导体层中的金属元素相同，所述金属氧化物半导体层中的金属元素包括In，Ga，Zn，Sn中的至少三种，所述金属氧化物晶粒中的金属元素包括In，Ga，Zn，Sn中的一种或两种；
    对非晶态的所述金属氧化物半导体层进行退火处理，得到结晶化金属氧化物半导体层。
  2. 根据权利要求1所述薄膜晶体管阵列基板的制造方法，其中，所述于基板上形成多个分散的金属氧化物晶粒包括：
    于所述基板上形成金属氧化物膜层；
    对所述金属氧化物膜层进行退火处理，得到多个分散的所述金属氧化物晶粒。
  3. 根据权利要求2所述薄膜晶体管阵列基板的制造方法，其中，所述金属氧化物膜层的厚度大于或等于10纳米且小于或等于200纳米。
  4. 根据权利要求2所述薄膜晶体管阵列基板的制造方法，其中，所述退火处理的条件为温度大于或等于100度且小于或等于400度。
  5. 根据权利要求1所述薄膜晶体管阵列基板的制造方法，其中，所述于基板上形成多个分散的金属氧化物晶粒包括：
    于所述基板上形成金属氧化物膜层，所述金属氧化物膜层包括结晶金属氧化物和非结晶金属氧化物；
    去除多个所述非结晶金属氧化物，得到多个分散的所述金属氧化物晶粒。
  6. 根据权利要求5所述薄膜晶体管阵列基板的制造方法，其中，所述金属氧化物膜层的厚度大于或等于200纳米且小于或等于1500纳米。
  7. 一种薄膜晶体管阵列基板的制造方法，其中，所述方法包括：
    于基板上形成多个分散的金属氧化物晶粒；
    形成与多个所述金属氧化物晶粒接触的非晶态的金属氧化物半导体层，所述金属氧化物晶粒中的至少一种金属元素与所述金属氧化物半导体层中的金属元素相同；
    对非晶态的所述金属氧化物半导体层进行退火处理，得到结晶化金属氧化物半导体层。
  8. 根据权利要求7所述薄膜晶体管阵列基板的制造方法，其中，所述于基板上形成多个分散的金属氧化物晶粒包括：
    于所述基板上形成金属氧化物膜层；
    对所述金属氧化物膜层进行退火处理，得到多个分散的所述金属氧化物晶粒。
  9. 根据权利要求8所述薄膜晶体管阵列基板的制造方法，其中，所述金属氧化物膜层的厚度大于或等于10纳米且小于或等于200纳米。
  10. 根据权利要求8所述薄膜晶体管阵列基板的制造方法，其中，所述退火处理的条件为温度大于或等于100度且小于或等于400度。
  11. 根据权利要求7所述薄膜晶体管阵列基板的制造方法，其中，所述于基板上形成多个分散的金属氧化物晶粒包括：
    于所述基板上形成金属氧化物膜层，所述金属氧化物膜层包括结晶金属氧化物和非结晶金属氧化物；
    去除多个所述非结晶金属氧化物，得到多个分散的所述金属氧化物晶粒。
  12. 根据权利要求11所述薄膜晶体管阵列基板的制造方法，其中，所述金属氧化物膜层的厚度大于或等于200纳米且小于或等于1500纳米。
  13. 根据权利要求11所述薄膜晶体管阵列基板的制造方法，其中，所述去除多个所述非结晶金属氧化物包括：
    蚀刻去除多个所述非结晶金属氧化物。
  14. 根据权利要求7所述薄膜晶体管阵列基板的制造方法，其中，所述金属氧化物晶粒的尺寸大于或等于5纳米且小于或等于100纳米。
  15. 根据权利要求7所述薄膜晶体管阵列基板的制造方法，其中，所述金属氧化物半导体层中的金属元素包括In，Ga，Zn，Sn中的至少三种，所述金属氧化物晶粒中的金属元素包括In，Ga，Zn，Sn中的一种或两种。
  16. 根据权利要求15所述薄膜晶体管阵列基板的制造方法，其中，所述金属氧化物晶粒的制备材料为氧化铟锡，所述金属氧化物半导体层的制备材料为铟镓锌氧化物。
  17. 根据权利要求7所述薄膜晶体管阵列基板的制造方法，其中，所述对非晶态的所述金属氧化物半导体层进行退火处理包括：
    在温度大于或等于300度且小于或等于450度条件下对非晶态的所述金属氧化物半导体层加热0.5小时至1.5小时。
  18. 根据权利要求7所述薄膜晶体管阵列基板的制造方法，其中，在基板上形成多个分散的金属氧化物晶粒之前，所述方法还包括：
    于基板上形成栅极；以及
    于所述栅极和所述基板上形成栅极绝缘层；
    所述于所述基板上形成多个分散的金属氧化物晶粒包括：
    于所述栅极绝缘层远离栅极的表面上形成多个分散的所述金属氧化物晶粒。
  19. 根据权利要求7所述薄膜晶体管阵列基板的制造方法，其中，所述于所述基板上形成多个分散的金属氧化物晶粒包括：
    于所述基板的表面上形成多个分散的所述金属氧化物晶粒；
    在形成所述结晶化金属氧化物半导体层之后，所述方法还包括：
    于所述结晶化金属氧化物半导体层上形成栅极绝缘层；以及
    于所述栅极绝缘层上形成栅极。
  20. 一种显示面板，其中，所述显示面板包括薄膜晶体管阵列基板，所述薄膜晶体管阵列基板由权利要求7所述薄膜晶体管阵列基板的制造方法制备得到。
PCT/CN2022/087106 2022-03-24 2022-04-15 薄膜晶体管阵列基板的制造方法及显示面板 WO2023178763A1 (zh)

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CN112599703A (zh) * 2020-12-14 2021-04-02 深圳市华星光电半导体显示技术有限公司 显示基板及其制备方法、显示面板
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US20110133197A1 (en) * 2009-12-03 2011-06-09 Hitachi Displays, Ltd. Thin film transistor and manufacturing method thereof
CN107507866A (zh) * 2017-07-17 2017-12-22 华南理工大学 一种多晶氧化物柔性薄膜晶体管及其制备方法
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