WO2022115992A1 - 氧化物薄膜晶体管及其制备方法、显示装置 - Google Patents

氧化物薄膜晶体管及其制备方法、显示装置 Download PDF

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WO2022115992A1
WO2022115992A1 PCT/CN2020/133087 CN2020133087W WO2022115992A1 WO 2022115992 A1 WO2022115992 A1 WO 2022115992A1 CN 2020133087 W CN2020133087 W CN 2020133087W WO 2022115992 A1 WO2022115992 A1 WO 2022115992A1
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Prior art keywords
layer
film layer
base substrate
protective
drain
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PCT/CN2020/133087
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English (en)
French (fr)
Inventor
林滨
李增荣
郭航乐
邹振游
李梁梁
乐发垫
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京东方科技集团股份有限公司
福州京东方光电科技有限公司
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Priority to PCT/CN2020/133087 priority Critical patent/WO2022115992A1/zh
Priority to US17/772,669 priority patent/US20240170579A1/en
Priority to EP20963841.0A priority patent/EP4160697A4/en
Priority to CN202080003139.5A priority patent/CN114846623A/zh
Publication of WO2022115992A1 publication Critical patent/WO2022115992A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present application relates to the field of display technology, and in particular, to an oxide thin film transistor, a preparation method thereof, and a display device.
  • Indium gallium zinc oxide (IGZO) is widely used in the preparation of active layers in thin film transistors due to its high mobility, good uniformity and good transparency.
  • an oxide thin film transistor includes:
  • the source and drain layers comprising: a source electrode and a drain electrode arranged at intervals;
  • the protective layer is arranged between the channel layer and the source-drain layer, and the protective layer is in contact with both the source-drain layer and the channel layer, and the protective layer is on the lining
  • the orthographic projection on the base substrate covers the orthographic projection of the channel layer on the base substrate, and the protective layer includes a first portion, a second portion, and a third portion located in different regions of the protective layer;
  • the first part has two surfaces, and the two surfaces of the first part are respectively in contact with the channel layer and the source electrode;
  • the second part has two surfaces, and the two surfaces of the second part Contact with the channel layer and the drain, respectively;
  • the third part has two surfaces, one of the two surfaces of the third part is in contact with the channel layer, and the other surface is not in contact with the source and the drain;
  • the conductivity of the surface of the first portion in contact with the source electrode and the conductivity of the surface of the second portion in contact with the drain electrode are both greater than the conductivity of the third portion.
  • the multi-component metal oxide of the channel layer is nanocrystalline oxide or amorphous oxide
  • the multi-component metal oxide on the side of the protective layer close to the channel layer is a C-axis crystalline oxide.
  • the materials of the channel layer and the protective layer are both indium gallium zinc oxide;
  • the indium gallium zinc oxide of the channel layer is nanocrystalline oxide or amorphous oxide
  • the indium gallium zinc oxide on the side of the protective layer close to the channel layer is a C-axis crystalline oxide.
  • the protective layer includes: a first film layer and a second film layer arranged in layers; the first film layer is in contact with the channel layer; the second film layer includes a first sub-layer in contact with the source electrode a film layer, and a second sub-film layer in contact with the drain electrode;
  • the second sub-film layer is the part of the second part in contact with the drain
  • the first film layer includes the third portion, a portion of the first portion away from the source electrode, and a portion of the second portion away from the drain electrode; the conductivity of the first film layer is less than the conductivity of the second film layer.
  • the channel layer and the second film layer are nanocrystalline crystalline indium gallium zinc oxide film layers
  • the first film layer is a C-axis crystalline indium gallium zinc oxide film layer.
  • the indium gallium zinc atomic ratio of the nanocrystalline crystalline indium gallium zinc oxide film layer is 4:2:3.
  • the thickness of the channel layer ranges from 1 nanometer to 30 nanometers
  • the thickness of the first film layer ranges from 1 nanometer to 30 nanometers
  • the thickness of the second film layer ranges from 1 nanometer to 100 nanometers.
  • the first film layer and the second film layer are both C-axis crystalline indium gallium zinc oxide film layers, and the number of oxygen vacancies in the second film layer is greater than the number of oxygen vacancies in the first film layer;
  • the The second film layer is a film layer obtained by subjecting the C-axis crystalline indium gallium zinc oxide film layer to plasma treatment, and the temperature range of the plasma treatment is 200°C to 300°C.
  • the surface of the first sub-film layer away from the first film layer and the surface of the second sub-film layer away from the first film layer are both uneven structures obtained after plasma treatment.
  • the thickness of the protective layer ranges from 20 nanometers to 50 nanometers.
  • the nanocrystalline oxide has a grain size in the range of 2 nanometers to 4 nanometers.
  • the thickness of the third portion is smaller than the thickness of the first portion, and the thickness of the third portion is smaller than the thickness of the second portion.
  • oxide thin film transistor comprising:
  • the orthographic projection of the protective layer on the base substrate covers the orthographic projection of the channel layer on the base substrate, and the protective layer includes a first part, a second part, and a third part ;
  • the orthographic projection of the first portion on the base substrate covers a first region, where the first region is the orthographic projection of the source electrode on the base substrate and the channel layer on the substrate
  • the orthographic projection of the second portion on the base substrate covers a second area, and the second area is the orthographic projection of the drain on the base substrate and the overlapping area of the orthographic projection of the channel layer on the base substrate;
  • the orthographic projection of the third part on the base substrate covers the third area;
  • the third area is a spaced area in an overlapping area of the orthographic projection on the base substrate and the orthographic projection of the channel layer on the base substrate, and the spacer area is an area between the source electrode and the drain electrode;
  • the conductivity of the side of the first portion away from the channel layer and the conductivity of the side of the second portion away from the channel layer are both greater than the conductivity of the third portion away from the channel layer. conductivity on one side.
  • the protective layer includes: a first film layer and a second film layer stacked in sequence along a direction away from the base substrate;
  • the orthographic projection of the first film layer on the base substrate covers the orthographic projection of the channel layer on the base substrate;
  • the second film layer includes a first sub-film layer and a second sub-film layer arranged at intervals, the orthographic projection of the first sub-film layer on the base substrate covers the first region, and the second sub-film layer covers the first region. the orthographic projection of the sub-film layer on the base substrate covers the second region;
  • the conductivity of the channel layer and the conductivity of the second film layer are both greater than the conductivity of the first film layer.
  • the material of the channel layer, the first film layer, and the second film layer are all multi-element metal oxides
  • the multi-component metal oxides of the channel layer and the second film layer are nanocrystalline oxides or amorphous oxides
  • the multi-component metal oxide of the first film layer is a C-axis crystalline oxide
  • the indium gallium zinc oxide of the channel layer and the second film layer is nanocrystalline oxide or amorphous oxide
  • the indium gallium zinc oxide of the first film layer is a C-axis crystalline oxide
  • the channel layer and the second film layer are nanocrystalline crystalline indium gallium zinc oxide film layers
  • the first film layer is a C-axis crystalline indium gallium zinc oxide film layer.
  • the first film layer and the second film layer are both C-axis crystalline indium gallium zinc oxide film layers, and the number of oxygen vacancies in the second film layer is greater than the number of oxygen vacancies in the first film layer;
  • the The second film layer is a film layer obtained by subjecting the C-axis crystalline indium gallium zinc oxide film layer to plasma treatment, and the temperature range of the plasma treatment is 200°C to 300°C.
  • a preparation method of an oxide thin film transistor comprising:
  • a gate electrode, a gate insulating layer, a channel layer, a protective layer, and a source and drain layer are formed on the base substrate, and the source and drain layers include: a source electrode and a drain electrode arranged at intervals;
  • the protective layer is arranged between the channel layer and the source-drain layer, and the protective layer is in contact with both the source-drain layer and the channel layer, and the protective layer is on the lining
  • the orthographic projection on the base substrate covers the orthographic projection of the channel layer on the base substrate, and the protective layer includes a first portion, a second portion, and a third portion located in different regions of the protective layer;
  • the first part has two surfaces, and the two surfaces of the first part are respectively in contact with the channel layer and the source electrode;
  • the second part has two surfaces, and the two surfaces of the second part Contact with the channel layer and the drain, respectively;
  • the third part has two surfaces, one of the two surfaces of the third part is in contact with the channel layer, and the other surface is not in contact with the source and drain;
  • the conductivity of the surface of the first part in contact with the source electrode and the conductivity of the surface of the second part in contact with the drain electrode are both greater than those of the third part not in contact with the source electrode the conductivity of the other surface in contact with the drain.
  • a first protective film layer is formed on the base substrate by using a magnetron sputtering equipment, wherein, when the first protective film layer is formed, the oxygen content of the sputtering gas of the magnetron sputtering equipment is in the range of 80% to 100%, and the temperature range of the base substrate is 100°C to 300°C;
  • the material of the first protective film layer includes C-axis crystalline indium gallium zinc oxide, and the material of the second protective film layer includes nanocrystalline crystalline indium gallium zinc oxide.
  • Forming the protective layer on the base substrate includes:
  • the third protective film layer is patterned to obtain a second protective pattern, and the orthographic projection of the second protective pattern on the base substrate covers the positive direction of the channel layer on the base substrate. projection;
  • plasma processing is performed on the side of the second protection pattern away from the base substrate;
  • the second protection pattern is The etching depth of the pattern is smaller than the thickness of the second protection pattern.
  • a display device comprising: a base substrate, and a plurality of the oxide thin film transistors arranged on the base substrate.
  • FIG. 1 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another display device provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another display device provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of still another display device provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of an oxide thin film transistor provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a partial structure of the oxide thin film transistor shown in FIG. 5;
  • Fig. 7 is another partial structural schematic diagram of the oxide thin film transistor shown in Fig. 5;
  • FIG. 8 is a flowchart of a method for manufacturing an oxide thin film transistor provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of forming a channel film layer, a first protective film layer and a second protective film layer according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of obtaining a first protection pattern, a first film layer and a channel layer according to an embodiment of the present application;
  • FIG. 11 is a schematic diagram of forming a source-drain film layer according to an embodiment of the present application.
  • FIG. 12 is a schematic diagram of obtaining a source-drain layer and a second film layer provided by an embodiment of the present application
  • FIG. 13 is a flowchart of another method for fabricating an oxide thin film transistor provided by an embodiment of the present application.
  • FIG. 14 is a schematic diagram of forming a channel film layer and a third protective film layer provided by an embodiment of the present application.
  • 15 is a schematic diagram of obtaining a channel layer and a second protection pattern provided by an embodiment of the present application.
  • 16 is a schematic diagram of performing plasma processing on the side of the second protection pattern away from the base substrate;
  • FIG. 17 is a schematic diagram of forming a source-drain film layer according to an embodiment of the present application.
  • FIG. 18 is a schematic diagram of obtaining a source-drain layer and a protective layer according to an embodiment of the present application.
  • a thin film transistor includes: a gate electrode, an insulating layer, an active layer, and a source and drain layer stacked in sequence along a direction away from the base substrate.
  • the source-drain layer when forming the source-drain layer, it is necessary to use an etching solution to etch the pre-formed source-drain film layer, the source-drain layer includes a source electrode and a drain electrode arranged at intervals, the source electrode and the drain electrode are It can be turned on through the active layer.
  • the thin film transistor may further include: a protective layer located between the active layer and the source and drain layers.
  • the orthographic projection of the protective layer on the base substrate covers the orthographic projection of the active layer on the base substrate, and the protective layer can be used to prevent the active layer from being etched by the etching solution.
  • the protective layer since the protective layer is located between the active layer and the source-drain layer, the current needs to flow into the protective layer from the source or drain first, and then flow into the active layer from the protective layer, so as to realize the conduction between the source and the drain.
  • the active layer is prepared from nanocrystalline IGZO
  • the protective layer is prepared from crystalline oxide.
  • FIG. 1 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the oxide thin film transistor 10 may include: a gate 101 disposed on a substrate 20, a gate insulator 102, a channel layer 103, a protection layer 104 , and source and drain layers 105 .
  • the source-drain layer 105 may include: a source (source) 1051 and a drain (drain) 1052 arranged at intervals.
  • the protective layer 104 may be disposed between the channel layer 103 and the source/drain layer 105 , and the protective layer 104 may be connected to the source/drain layer 105 and the channel layer 103 all contact.
  • the orthographic projection of the protective layer 104 on the base substrate 20 may cover the orthographic projection of the channel layer 103 on the base substrate 20 .
  • the protective layer 104 can be used to protect the channel layer 103 , to prevent the side of the channel layer 103 away from the base substrate 20 from being etched by the etching solution, and to ensure the reliability of current transmission through the channel layer 103 .
  • the protective layer 104 may include a first portion 1041 , a second portion 1042 , and a third portion 1043 located in different regions of the protective layer 104 .
  • the first part 1041 may have two surfaces, and the two surfaces of the first part 1041 are in contact with the channel layer 103 and the source electrode 1051, respectively.
  • the second part 1042 may have two surfaces, and the two surfaces of the second part 1042 may be in contact with the channel layer 103 and the drain electrode 1052, respectively.
  • the third part 1043 may have two surfaces, one of the two surfaces of the third part 1043 may be in contact with the channel layer 103 , and the other surface may not be in contact with the source electrode 1051 and the drain electrode 1052 .
  • the third portion 1043 may be located between the first portion 1041 and the second portion 1042 .
  • the conductivity of the surface of the first part 1041 in contact with the source electrode 1051 and the conductivity of the surface of the second part 1042 in contact with the drain electrode 1052 may both be greater than those of the third part 1043 that are not in contact with the source electrode 1051 and the drain electrode 1052 conductivity of a surface. That is, the conductivity of the surface of the first part 1041 in contact with the source electrode 1051 and the conductivity of the surface of the second part 1042 in contact with the drain electrode 1052 may be better, and the third part 1043 is not connected to the source electrode 1051 and the drain electrode 1051.
  • the other surface that 1052 contacts may be less conductive.
  • the conductivity of the other surface of the third portion 1043 that is not in contact with the source electrode 1051 and the drain electrode 1052 is poor, after the current of the source electrode 1051 flows from the first portion 1041, it will not be transmitted to the second portion through the third portion 1043. part 1042 , and the current of the drain 1052 flows from the second part 1042 , and will not be transmitted to the first part 1041 through the third part 1043 . Since the channel layer 103 located on the side of the protective layer 104 close to the base substrate 20 has better conductivity, after the current of the source 1051 flows from the first part 1041, it can pass through the channel layer 103 and the protective layer 104 in sequence. The second portion 1042 is transferred to the drain 1052 . After the current of the drain 1052 flows from the second part 1042 , it can be transferred to the source 1051 through the channel layer 103 and the first part 1041 of the protective layer 104 in sequence.
  • the conductivity of the surface of the first part 1041 of the protective layer 104 in contact with the source electrode 1051 and the conductivity of the surface of the second part 1042 in contact with the drain electrode 1052 are both good, the current flows from the source electrode 1051 Or when the drain 1052 flows into the protective layer 104 , the protective layer 104 does not generate a large amount of heat, which improves the reliability of the oxide thin film transistor 10 .
  • the oxide thin film transistor 10 may include: a gate electrode 101 disposed on the base substrate 20 , a gate insulating layer 102 , a channel layer 103 , a protective layer 104 , and the source and drain layers 105 .
  • the source-drain layer 105 may include: a source electrode 1051 and a drain electrode 1052 arranged at intervals.
  • the orthographic projection of the protective layer 104 on the base substrate 20 may cover the orthographic projection of the channel layer 103 on the base substrate 20 .
  • the protective layer 104 can be used to protect the channel layer 103 , to prevent the side of the channel layer 103 away from the base substrate 20 from being etched by the etching solution, and to ensure the reliability of current transmission through the channel layer 103 .
  • the protective layer 104 may include: a first part 1041 , a second part 1042 , and a third part 1043 .
  • the orthographic projection of the first portion 1041 on the base substrate 20 covers the first area a1
  • the orthographic projection of the second portion 1042 on the base substrate 20 covers the second area a2
  • the third portion 1043 is on the base substrate 20
  • the orthographic projection of covers the third area a3.
  • the first region a1 is an overlapping region of the orthographic projection of the source electrode on the base substrate 20 and the orthographic projection of the channel layer 103 on the base substrate 20 .
  • the second region a2 is an overlapping region of the orthographic projection of the drain electrode on the base substrate 20 and the orthographic projection of the channel layer 103 on the base substrate 20 .
  • the third region a3 is an overlapping region of the orthographic projection of the spacer region on the base substrate 20 and the orthographic projection of the channel layer 103 on the base substrate 20 .
  • the spacer region is the region between the source electrode 1051 and the drain electrode 1052 .
  • the third portion 1043 may be located between the first portion 1041 and the second portion 1042 .
  • the conductivity of the side of the first portion 1041 away from the channel layer 103 and the conductivity of the side of the second portion 1042 away from the channel layer 103 are both greater than the conductivity of the side of the third portion 1043 away from the channel layer 103 .
  • the conductivity of the side of the first portion 1041 away from the channel layer 103 and the conductivity of the side of the second portion 1042 away from the channel layer 103 may be better, and the conductivity of the side of the third portion 1043 away from the channel layer 103 can be worse.
  • the conductivity of the side of the third portion 1043 away from the channel layer 103 is poor, after the current of the source electrode 1051 flows from the first portion 1041, it will not be transmitted to the second portion 1042 through the third portion 1043, and the drain electrode 1051 will not be transmitted to the second portion 1042 through the third portion 1043 After the current of 1052 flows from the second part 1042, it will not be transmitted to the first part 1041 through the third part 1043. Since the channel layer 103 located on the side of the protective layer 104 close to the base substrate 20 has better conductivity, after the current of the source 1051 flows from the first part 1041, it can pass through the channel layer 103 and the second part of the protective layer 104 in sequence. The second portion 1042 is transferred to the drain 1052 . After the current of the drain 1052 flows from the second part 1042 , it can be transferred to the source 1051 through the channel layer 103 and the first part 1041 of the protective layer 104 in sequence.
  • the conductivity of the side of the first portion 1041 of the protective layer 104 away from the channel layer 103 and the conductivity of the side of the second portion 1042 away from the channel layer 103 are both better, the current flows from the source When the electrode 1051 or the drain 1052 flows into the protective layer 104 , the protective layer 104 does not generate a large amount of heat, which improves the reliability of the oxide thin film transistor 10 .
  • the materials of the channel layer 103 and the protective layer 104 may both be multi-element metal oxides.
  • the multi-component metal oxide of the channel layer 103 may be nanocrystalline oxide or amorphous oxide.
  • the multi-component metal oxide on the side of the protective layer 104 close to the channel layer 103 may be a C-axis crystalline oxide.
  • the materials of the channel layer 103 and the protective layer 104 may be both indium gallium zinc oxide.
  • the indium gallium zinc oxide of the channel layer 103 may be a nanocrystalline oxide or an amorphous oxide.
  • the indium gallium zinc oxide on the side of the protective layer 104 close to the channel layer 103 may be a C-axis crystalline oxide.
  • the grain size range of the nanocrystal is greater than 1 nm, and may be 2 nm (nanometer) to 4 nm, such as 3 nm.
  • the protective layer 104 may include: a first film layer b1 and a second film layer b2 that are arranged in layers.
  • the two film layers in the protective layer 104 can be prepared by two patterning processes respectively, and are not formed by one process.
  • the first film layer b1 may be in contact with the channel layer 103 . 1 and 2 , the first film layer b1 may include a third portion 1043 located between the source electrode 1051 and the drain electrode 1052 , a portion of the first portion 1041 under the source electrode that is far from the source electrode 1051 and under the drain electrode 1052 A portion of the second portion 1042 of the 1042 away from the drain electrode 1052.
  • the second film layer b2 may include: a first sub-film layer b21 in contact with the source electrode 1051 , and a second sub-film layer b22 in contact with the drain electrode 1052 . Referring to FIG. 1 and FIG.
  • the first sub-film layer b21 may be the part of the first part 1041 that is in contact with the source electrode 1051 and plays a conductive role.
  • the second sub-film layer b22 may be a portion of the second portion 1042 that is in contact with the drain electrode 1052 and plays a conductive role.
  • the first film layer b1 and the second film layer b2 are divided by material, not just by position. The conductivity of the first film layer b1 is higher than that of the second film layer b2.
  • the conductivity of the first film layer b1 may be lower than the conductivity of the second film layer b2.
  • the number of oxygen vacancies of the first sub-film layer b21 in the second film layer b2 and the second The oxygen vacancy number of the second sub-film layer b22 in the film layer b2 may all be greater than the oxygen vacancy number of the first film layer b1. In this way, the greater the number of oxygen vacancies, the greater the number of free electrons and the higher the conductivity.
  • the first film layer b1 of the protective layer may have two surfaces, and one of the two surfaces of the first film layer b1 may be in contact with the channel layer 103 .
  • the other surface may include: a first surface area in contact with the first sub-film layer b21, a second surface area in contact with the second sub-film layer b22, and a second surface area located between the first surface area and the second surface area and not in contact with The third surface area where the first sub-film layer b21 and the second sub-film layer b22 are in contact.
  • the first sub-film layer b21 of the second film layer b2 and the portion of the first film layer b1 overlapping with the first sub-film layer b21 may constitute the first portion 1041 of the protective layer 104 .
  • the second sub-film layer b22 of the second film layer b2 and the portion of the first film layer b1 overlapping with the second sub-film layer b22 may constitute the second portion 1042 of the protective layer 104 .
  • the portion of the first film layer b1 that does not overlap with the first sub-film layer b21 and the second sub-film layer b22 constitutes the third portion 1043 of the protective layer 104 .
  • the conductivity of the channel layer 103 and the conductivity of the second film layer b2 may both be greater than the conductivity of the first film layer b1. Since the second film layer b2 is close to the source and drain layers 105 relative to the first film layer b1, the current of the source and drain layers 105 can flow into the channel layer 103 through the second film layer b2 and the first film layer b1 in sequence.
  • the second film layer b2 since the second film layer b2 has good electrical conductivity, when the current flows into the second film layer b2, the second film layer b2 will not generate a large amount of heat, and the second film layer b2 can generate heat
  • the function of buffering prevents defects of the channel layer 103 from being affected by a large amount of heat, and ensures the conductivity of the oxide thin film transistor 10 .
  • the first film layer b1 is a C-axis crystalline oxide film layer
  • the second film layer b2 is a nanocrystalline oxide film layer.
  • the nanocrystalline IGZO film layer is dense (the density of the nanocrystalline IGZO film layer is >6.4g/cm3 (g/cm3), and the conventional amorphous IGZO ⁇ 5.7g/cm3).
  • the top layer nanocrystalline IGZO is matched with the middle layer C-axis crystalline IGZO. Due to its own certain crystalline properties, nanocrystalline IGZO can better transition with the middle layer crystalline IGZO in terms of film layer, and has better matching in terms of grain structure. , can avoid unnecessary contact resistance.
  • the channel layer 103 and the second film layer b2 may be nanocrystalline crystalline indium gallium zinc oxide film layers. That is, the material of the channel layer 103 and the second film layer b2 may be nanocrystalline crystalline indium gallium zinc oxide.
  • the first film layer b1 may be a C-axis crystalline indium gallium zinc oxide film layer. That is, the material of the first film layer b1 may be C-axis crystalline indium gallium zinc oxide (CAAC-IGZO).
  • the ratio of the atomic numbers of each element in the material of the channel layer 103, the ratio of the atomic number of each element in the material of the first film layer b1, and the ratio of the atomic number of each element in the material of the second film layer b2 are the same. Therefore, in the process of preparing the channel layer 103, the first film layer b1, and the second film layer b2 by means of magnetron sputtering, there is no need to replace the target material.
  • the channel layer 103 and the second film layer b2 can be the same, the channel layer 103 and the second film layer b2 can be prepared by using the same process.
  • the material of the first part 1041 in the protective layer 104 may include: nanocrystalline crystalline indium gallium zinc oxide and C-axis crystalline indium gallium zinc oxide, and the material of the second part 1042 in the protective layer 104 may be Including nanocrystalline crystalline indium gallium zinc oxide and c-axis crystalline indium gallium zinc oxide, the material of the third portion 1043 in the protective layer 104 may include c-axis crystalline indium gallium zinc oxide.
  • the thickness of the channel layer 103 may range from 1 nm to 30 nm
  • the thickness of the first film layer b1 may range from 1 nm to 30 nm
  • the thickness of the second film layer b2 may range from 1 nm to 100 nm.
  • the first portion 1041 and the second portion 1042 have an additional second film layer b2 relative to the third portion 1043 .
  • Both the thickness of the first portion 1041 and the thickness of the second portion 1042 may be equal to the total thickness of the first film layer b1 and the second film layer b2.
  • the thickness of the third portion 1043 is equal to the thickness of the first film layer b1. That is, the thickness of the third part 1043 may be smaller than the thickness of the first part 1041 and the thickness of the second part 1042 .
  • the protective layer 104 may include: a first film layer b1 and a second film layer b2 that are arranged in layers.
  • the first film layer b1 and the second film layer b2 can be prepared by the same patterning process.
  • the first film layer b1 and the second film layer b2 are both C-axis crystalline indium gallium zinc oxide film layers.
  • the second film layer b2 may be a film layer obtained by subjecting the C-axis crystalline indium gallium zinc oxide film layer to plasma treatment. The temperature range for this plasma treatment is 200°C to 300°C.
  • the first film layer b1 and the second film layer b2 are both C-axis crystalline indium gallium zinc oxide film layers, that is, the materials of the first film layer b1 and the second film layer b2 can both be C-axis crystalline indium gallium zinc oxide film layers oxide.
  • the indium gallium zinc atomic ratio of the C-axis crystalline indium gallium zinc oxide film layer is 4:2:3.
  • the channel layer 103 may be a nanocrystalline crystalline indium gallium zinc oxide film layer as described in any one of the above embodiments.
  • the channel layer 103 and the protective layer 103 are prepared by magnetron sputtering. There is no need to replace the target during the layer 104 process.
  • the ratio of the atomic numbers of each element in the material of the channel layer 103 can be different from the ratio of the atomic number of each element in the material of the protective layer 104 , then the channel layer 103 is prepared by magnetron sputtering. And the process of protecting the layer 104 needs to replace the target.
  • the conductivity of the channel layer 103 prepared from the nanocrystalline crystalline indium gallium zinc oxide may be good, and the source electrode 1051 or the drain electrode 1052 can pass through the channel layer 103.
  • the channel layer 103 is turned on.
  • the conductivity of the C-axis crystalline indium gallium zinc oxide is smaller than that of the nanocrystalline IGZO. 3 and 4, in order to improve the conductivity of the surface of the first part 1041 of the protective layer 104 in contact with the source electrode 1051, and to improve the conductivity of the surface of the second part 1042 in contact with the drain electrode 1052, the protective layer 104
  • the surface of the first part 1041 of the protective layer 104 in contact with the source electrode 1051 and the surface of the second part 1042 of the protective layer 104 in contact with the drain electrode 1052 are plasma treated.
  • the first part 1041 and the second part 1042 are bombarded by the strong energy of the gas released during the plasma treatment, the surfaces of the first part 1041 in contact with the source electrode 1051 and the second part 1042 and the The indium-oxygen (In-O) bond on the surface contacted by the drain 1052 is broken (since the bond energy of the indium-oxygen bond is small relative to the bond energy of the gallium-oxygen bond and the bond energy of the zinc-oxygen bond, the indium-oxygen bond is relatively small relative to the gallium-oxygen bond. and zinc-oxygen bonds are more easily broken).
  • In-O indium-oxygen
  • the surface of the first part 1041 in contact with the source electrode 1051 and the surface of the second part 1042 in contact with the drain electrode 1052 both have a large amount of indium ions.
  • the surface of the first portion 1041 in contact with the source electrode 1051 and the surface of the second portion 1042 in contact with the drain electrode 1052 can form an N-type semiconductor, and the resistance thereof is reduced and the conductivity thereof is increased.
  • the N-type semiconductor may refer to an impurity semiconductor whose free electron concentration is much larger than that of holes.
  • the surface of the first part 1041 in contact with the source electrode 1051 and the surface of the second part 1042 in contact with the drain electrode 1052 can be improved and the conductivity of the surface of the second portion 1042 in contact with the drain 1052. In this way, it can be avoided that a large amount of heat is generated when the current flows into the protective layer 104 from the source electrode 1051 or the drain electrode 1052 , thereby preventing the channel layer 103 from being affected by a large amount of heat and causing defects, and ensuring the performance of the oxide thin film transistor 10 .
  • Conductivity is
  • the third part 1043 is prevented from not being in contact with the source electrode 1051 and the drain electrode 1052
  • the conductivity of one surface of the third part 1043 is better, so that the other surface of the third part 1043 which is not in contact with the source electrode 1051 and the drain electrode 1052 is not subjected to plasma treatment.
  • plasma treatment may be performed on the side of the second protective pattern 104 a for forming the protective layer 104 that is away from the channel layer 103 .
  • the conductivity of the side of the second protection pattern 104a away from the channel layer 103 after the plasma treatment is relatively high.
  • etching is performed on the surface of the region where the plasma-treated second protective pattern 104a does not overlap with the source electrode 1051 and the drain electrode 1052, so that the conductivity of the region is restored to the conductivity without the plasma treatment. .
  • a part of the second protective pattern 104a divided into two parts may be the first sub-film b21 of the second film layer b2, and the other part may be the second sub-film of the second film layer b2 layer b22, and the portion of the second protection pattern 104a that is not etched may be the first film layer b1.
  • the surface of the first sublayer b21 away from the first film layer b1 ie, the surface of the first part 1041 in contact with the source electrode 1051
  • the second sublayer The flatness of the surface of the b22 away from the first film layer b1 (ie, the surface of the second portion 1042 in contact with the drain electrode 1052 ) is poor. That is, the surface of the first sub-film layer b21 away from the first film layer b1 and the surface of the second sub-film layer b22 away from the first film layer b1 may both have uneven structures.
  • the surface of the first sub-layer b21 away from the first film layer b1 and the surface of the second sub-layer b22 away from the first film layer b1 are easy to contact and discharge with the source and drain layers 105 .
  • the contact resistance between the surface of the first sub-layer b21 far away from the first film layer b1 and the source electrode 1051 can be reduced, and the contact resistance between the surface of the second sub-layer b22 far away from the first film layer b1 and the drain electrode 1052 can be reduced. contact resistance between.
  • the portion of the second protection pattern 104a overlapping the source electrode 1051 constitutes the first portion 1041 of the protection layer 104 .
  • the portion of the second protection pattern 104 a overlapping the drain electrode 1052 constitutes the second portion 1042 of the protection layer 104 .
  • the portion of the second protection pattern 104 a that does not overlap with the source electrode 1051 and the drain electrode 1052 constitutes the third portion 1043 of the protection layer 104 .
  • the thickness of the third portion 1043 may be smaller than the thickness of the third portion 1043.
  • the thickness of the part 1041 may be smaller than the thickness of the second part 1042 .
  • the etching depth of the second protection pattern 104a may be smaller than the thickness of the second protection pattern 104a. That is, the second protection pattern 104a will not be etched through.
  • the thickness of the third portion 1043 of the protective layer 104 may range from 10 nm to 20 nm.
  • the thickness of the channel layer 103 may range from 1 nm to 30 nm.
  • the thickness of the protective layer 104 may range from 20 nm to 50 nm.
  • the gate 101 , the gate insulating layer 102 , the channel layer 103 , the protective layer 104 and the source and drain layers 105 can be stacked in sequence along the direction away from the base substrate 20 .
  • FIG. 5 is a schematic diagram of an oxide thin film transistor provided by an embodiment of the present application. Referring to FIG. 5 , it can be seen that the thicknesses of the channel layer 103 and the protective layer 104 in the oxide thin film transistor 10 can be much smaller than the thicknesses of other film layers.
  • FIG. 6 is a schematic diagram of a partial structure of the oxide thin film transistor shown in FIG. 5 .
  • FIG. 7 is another partial structural schematic diagram of the oxide thin film transistor shown in FIG. 5 . 6 and 7 , the total thickness d1 of the channel layer 103 and the third portion 1043 of the protective layer 104 may be 35.1 nm, and the total thickness d2 of the channel layer 103 and the second portion 1042 of the protective layer 104 may be 49.6nm. Wherein, the total thickness of the channel layer 103 and the first portion 1041 of the protective layer 104 may be equal to the total thickness of the channel layer 103 and the second portion 1042 of the protective layer 104 .
  • a method for fabricating an oxide thin film transistor 10 provided in an embodiment of the present application can be used to fabricate the oxide thin film transistor 10 shown in FIG. 1 .
  • the method may include: forming a gate electrode 101 , a gate insulating layer 102 , a channel layer 103 , a protective layer 104 , and a source and drain layer 105 on the base substrate 20 .
  • the source-drain layer 105 may include: a source electrode 1051 and a drain electrode 1052 arranged at intervals.
  • the prepared protective layer 104 may be located between the channel layer 103 and the source/drain layer 105 , and the protective layer 104 may be in contact with both the source/drain layer 105 and the channel layer 103 .
  • the orthographic projection of the protective layer 104 on the base substrate 20 may cover the orthographic projection of the channel layer 103 on the base substrate 20 .
  • the protective layer 104 can be used to protect the channel layer 103 , to prevent the side of the channel layer 103 away from the base substrate 20 from being etched by the etching solution, and to ensure the reliability of current transmission through the channel layer 103 .
  • the third portion 1043 may be located between the first portion 1041 and the second portion 1042 .
  • the conductivity of the surface of the first part 1041 in contact with the source electrode 1051 and the conductivity of the surface of the second part 1042 in contact with the drain electrode 1052 may both be greater than those of the third part 1043 that are not in contact with the source electrode 1051 and the drain electrode 1052 conductivity of a surface. That is, the conductivity of the surface of the first part 1041 in contact with the source electrode 1051 and the conductivity of the surface of the second part 1042 in contact with the drain electrode 1052 may be better, and the third part 1043 is not connected to the source electrode 1051 and the drain electrode 1051.
  • the other surface that 1052 contacts may be less conductive.
  • the conductivity of the other surface of the third portion 1043 that is not in contact with the source electrode 1051 and the drain electrode 1052 is poor, after the current of the source electrode 1051 flows from the first portion 1041, it will not be transmitted to the second portion through the third portion 1043. part 1042 , and the current of the drain 1052 flows from the second part 1042 , and will not be transmitted to the first part 1041 through the third part 1043 . Since the channel layer 103 located on the side of the protective layer 104 close to the base substrate 20 has better conductivity, after the current of the source 1051 flows from the first part 1041, it can pass through the channel layer 103 and the protective layer 104 in sequence. The second portion 1042 is transferred to the drain 1052 . After the current of the drain 1052 flows from the second part 1042 , it can be transferred to the source 1051 through the channel layer 103 and the first part 1041 of the protective layer 104 in sequence.
  • the conductivity of the surface of the first part 1041 of the protective layer 104 in contact with the source electrode 1051 and the conductivity of the surface of the second part 1042 in contact with the drain electrode 1052 are both good, the current flows from the source electrode 1051 Or when the drain 1052 flows into the protective layer 104 , the protective layer 104 does not generate a large amount of heat, which improves the reliability of the oxide thin film transistor 10 .
  • the embodiments of the present application provide a method for preparing an oxide thin film transistor.
  • the orthographic projection of the protective layer in the oxide thin film transistor prepared by the method on the base substrate covers the channel layer on the base substrate. orthographic projection on .
  • the protective layer can protect the channel layer, prevent the channel layer from being etched by the etching solution on the side away from the base substrate, and ensure the reliability of current transmission through the channel layer.
  • the first part and the second part in the protective layer have good electrical conductivity, when the current flows into the channel layer through the first part or the second part, the first part and the second part will not generate a large amount of heat , which can avoid defects in the channel layer, and the conductivity of the oxide thin film transistor is better.
  • the materials of the channel layer 103 and the protective layer 104 may be both multi-element metal oxides.
  • the multi-component metal oxide of the channel layer 103 may be nanocrystalline oxide or amorphous oxide.
  • the multi-component metal oxide on the side of the protective layer 104 close to the channel layer 103 may be a C-axis crystalline oxide.
  • the materials of the channel layer 103 and the protective layer 104 may be both indium gallium zinc oxide.
  • the indium gallium zinc oxide of the channel layer 103 may be a nanocrystalline oxide or an amorphous oxide.
  • the indium gallium zinc oxide on the side of the protective layer 104 close to the channel layer 103 may be a C-axis crystalline oxide.
  • FIG. 8 is a flowchart of a method for fabricating an oxide thin film transistor provided by an embodiment of the present application. This method can be used to fabricate the oxide thin film transistor shown in FIG. 1 . Referring to Figure 8, the method may include:
  • Step 301 forming a gate on the base substrate.
  • a base substrate 20 may be obtained first, and a film layer of the gate electrode 101 may be formed on one side of the base substrate 20 , and then the film layer of the gate electrode 101 may be patterned to obtain the gate electrode 101 .
  • the base substrate 20 may be a glass substrate.
  • Step 302 forming a gate insulating layer on the side of the gate away from the base substrate.
  • a gate insulating layer 102 may be formed on the side of the gate 101 away from the base substrate 20 , so that the gate 101 and the subsequently formed source and drain layers 105 are formed in the gate insulating layer 102 .
  • the source 1051 and drain 1052 are insulated.
  • Step 303 forming a channel film layer on the side of the gate insulating layer away from the base substrate.
  • a channel film layer 103 a may be formed on the side of the gate insulating layer 102 away from the base substrate 20 , and the channel film layer 103 a may cover the entire layer of the substrate base substrate 20 .
  • the channel film layer 103a can be prepared by using a material with better conductivity.
  • the material of the channel film layer 103a may be nanocrystalline crystalline indium gallium zinc oxide.
  • the channel film layer 103a may be formed on the side of the gate insulating layer 102 away from the base substrate 20 by using a magnetron sputtering device.
  • the oxygen content of the sputtering gas of the magnetron sputtering equipment may be in the range of 1% to 30%, and the temperature of the base substrate 20 may be in the range of 100° C. (degree Celsius) to 200° C. °C.
  • the power range of the magnetron sputtering equipment can be 10KW (kilowatt) to 40KW.
  • Step 304 forming a first protective film layer on the side of the channel film layer away from the base substrate.
  • a first protective film layer c1 may be formed on the side of the channel film layer 103 a away from the base substrate 20 .
  • the first protective film layer c1 can be prepared from a material with poor conductivity, and the first protective film layer c1 can cover the base substrate 20 as a whole.
  • the material of the first protective film layer c1 may be C-axis crystalline indium gallium zinc oxide.
  • a magnetron sputtering device may be used to form the first protective film layer c1 on the side of the channel film layer 103a away from the base substrate 20 .
  • the oxygen content of the sputtering gas of the magnetron sputtering equipment ranges from 80% to 100%, and the temperature of the base substrate 20 can range from 100°C to 300°C.
  • the power range of the magnetron sputtering equipment can be 10KW to 40KW.
  • Step 305 forming a second protective film layer on the side of the first protective film layer away from the base substrate.
  • a second protective film layer c2 may be formed on the side of the first protective film layer c1 away from the base substrate 20 .
  • the second protective film layer c2 can be prepared from a material with better conductivity, and the second protective film layer c2 can cover the base substrate 20 as a whole.
  • the material of the second protective film layer c2 may be nanocrystalline crystalline indium gallium zinc oxide.
  • the preparation process of the second protective film layer c2 can be the same as that of the channel layer 103 .
  • a magnetron sputtering device may be used to form the second protective film layer c2 on the side of the first protective film layer c1 away from the base substrate 20 .
  • the oxygen content of the sputtering gas of the magnetron sputtering equipment ranges from 1% to 30%, and the temperature of the base substrate 20 can range from 100°C to 200°C.
  • the power range of the magnetron sputtering equipment can be 10KW to 40KW.
  • Step 306 patterning the second protective film layer to obtain a first protective pattern.
  • a photolithography process may be used to pattern the second protective film layer c2 to obtain a first protective pattern m.
  • the photolithography process may include processes such as photoresist (photoresist, PR) coating, exposure, development, etching, and photoresist stripping.
  • the photolithography process may also be referred to as a mask process.
  • Step 307 patterning the first protective film layer to obtain a first film layer.
  • the second protective film layer c2 is patterned, and after obtaining the first protective pattern m, the first protective film layer c1 can be patterned by using a photolithography process.
  • the first film layer b1 is obtained.
  • the orthographic projection of the first protection pattern m on the base substrate 20 covers the orthographic projection of the first film layer b1 on the base substrate 20 .
  • the first film layer b1 may include a third portion 1043 , a portion of the first portion 1041 away from the source electrode 1051 and a portion of the second portion 1042 away from the drain electrode 1052 .
  • the material of the first film layer b1 is also C-axis crystalline indium gallium zinc oxide, and the conductivity of the first film layer b1 is relatively high. Difference.
  • the first film layer b1 may also be referred to as a C-axis crystalline indium gallium zinc oxide film layer.
  • Step 308 patterning the channel film layer to obtain a channel layer.
  • the second protective film layer c2 is patterned to obtain the first film layer b1 , and then the channel film layer 103a can be patterned by a photolithography process.
  • the channel layer 103 is obtained.
  • the orthographic projection of the first film layer b1 on the base substrate 20 covers the orthographic projection of the channel layer 103 on the base substrate 20 .
  • the channel layer 103 is obtained by patterning the channel film layer 103a, the material of the channel layer 103 is also nanocrystalline crystalline indium gallium zinc oxide, and the channel layer 103 has good conductivity.
  • the channel layer 103 may also be referred to as a nanocrystalline crystalline indium gallium zinc oxide film layer.
  • Step 309 forming a source and drain film layer on the side of the first protection pattern away from the base substrate.
  • a source-drain film layer 105a may be formed on the side of the first protection pattern m away from the base substrate 20 .
  • the source-drain film layer 105a may cover the base substrate 20 as a whole.
  • Step 310 etching the source and drain film layers to obtain the source and drain layers.
  • the source and drain film layers 105 a may be wet-etched by using an etchant, thereby obtaining the source and drain layers 105 .
  • the source-drain layer 105 may include: a source electrode 1051 and a drain electrode 1052 arranged at intervals.
  • the orthographic projection of the source electrode 1051 on the base substrate 20 and the orthographic projection of the channel layer 103 on the base substrate 20 have an overlapping area.
  • the orthographic projection of the drain electrode 1052 on the base substrate 20 and the orthographic projection of the channel layer 103 on the base substrate 20 have an overlapping area.
  • a first film layer b1 and a first protection pattern are formed between the channel layer 103 and the source and drain film layers 105a m.
  • the first film layer b1 and the first protection pattern m can be used to protect the channel layer 103 to avoid the influence of the etchant on the channel layer 103 when the source-drain film layer 105a is etched, so as to ensure the protection of the channel layer 103 Yield.
  • the channel layer 103 and the source-drain film layer 105a have the first film layer b1 and the first protection pattern m between them, the channel layer 103 is not easily affected by material diffusion in the source-drain film layer 105a.
  • Step 311 etching the portion of the first protection pattern that does not overlap with the source electrode and the drain electrode to obtain a second film layer.
  • the first protection pattern m on the side of the source-drain film layer 105a close to the base substrate 20 may be etched continuously. That is, the portion of the region where the first protection pattern m does not overlap with the source electrode 1051 and the drain electrode 1052 can be etched to obtain the second film layer b2.
  • the second film layer b2 includes: a first sub-film layer b21 in contact with the source electrode 1051 , and a second sub-film layer b22 in contact with the drain electrode 1052 .
  • the first sub-film layer b21 can be the part of the first part 1041 of the protective layer 104 that is in contact with the source electrode 1051 to play a superconducting role
  • the second sub-film layer b22 can be the part of the second part 1042 that is in contact with the drain electrode 1052 to play a conductive role part of the action.
  • the first film layer b1 and the second film layer b2 are divided by material, not just by position.
  • the conductivity of the first film layer b1 is higher than that of the second film layer b2.
  • the second film layer b2 prepared in this step 311 and the first film layer b1 prepared in the above step 307 may constitute the protective layer 104 of the oxide thin film transistor 10 .
  • the etching depth of the protection layer 104 may be greater than or equal to the thickness of the first protection pattern m. That is, the first protection pattern m may be engraved through.
  • the channel layer 103 may be affected.
  • the etching depth of the protective layer 104 is made smaller than the total thickness of the first protective pattern m and the first film layer b1.
  • the etching depth of the protective layer 104 can be controlled by controlling the etching duration. For example, in FIG. 12 , the etching depth of the protective layer 104 may be equal to the thickness of the first protective pattern m.
  • the material of the second film layer b2 also includes nanometers. crystalline indium gallium zinc oxide, the conductivity of the second film layer b2 is good.
  • the oxygen vacancy number of the first sub-film layer b21 in the second film layer b2 and the oxygen vacancy number of the second sub-film layer b22 in the second film layer b2 are both larger than the oxygen vacancy number of the first film layer b1.
  • the second film layer b2 may also be referred to as a nanocrystalline crystalline indium gallium zinc oxide film layer. In this way, the greater the number of oxygen vacancies, the greater the number of free electrons and the higher the conductivity.
  • the second film layer b2 Since the second film layer b2 is close to the source and drain layers 105 relative to the first film layer b1, the current of the source and drain layers 105 can flow into the channel layer 103 through the second film layer b2 and the first film layer b1 in sequence. In addition, since the second film layer b2 has good electrical conductivity, when a current flows into the second film layer b2, the second film layer b2 will not generate a large amount of heat.
  • the second film layer b2 can function as a heat buffer, so as to prevent the channel layer 103 from being affected by a large amount of heat to cause defects, and to ensure the conductivity of the prepared oxide thin film transistor 10 .
  • step 308 may be performed before step 304
  • step 307 may be performed before step 305
  • the order of steps 303 to 308 can be adjusted as: step 303, step 308, step 304, step 307, step 305 and step 306.
  • steps 306 to 308 may be performed simultaneously. That is, the first protection pattern, the first film layer, and the channel layer can be prepared by the same patterning process.
  • the embodiments of the present application provide a method for preparing an oxide thin film transistor.
  • the orthographic projection of the protective layer in the oxide thin film transistor prepared by the method on the base substrate covers the channel layer on the base substrate. orthographic projection on .
  • the protective layer can protect the channel layer, prevent the channel layer from being etched by the etching solution on the side away from the base substrate, and ensure the reliability of current transmission through the channel layer.
  • the conductivity of the second film in the protective layer is good, when the current passes through the second film of the protective layer from the source or drain, and then flows into the channel layer through the first film of the protective layer, the The second film layer can play the role of heat buffer, so as to avoid defects of the channel layer due to the influence of large heat, and to ensure the conductivity of the prepared oxide thin film transistor.
  • FIG. 13 is a flowchart of a method for fabricating an oxide thin film transistor according to an embodiment of the present application. This method can be used to fabricate the oxide thin film transistor shown in FIG. 3 . Referring to Figure 13, the method may include:
  • Step 401 forming a gate on the base substrate.
  • a base substrate 20 may be obtained first, and a film layer of the gate electrode 101 may be formed on one side of the base substrate 20 , and then the film layer of the gate electrode 101 may be patterned to obtain the gate electrode 101 .
  • the base substrate 20 may be a glass substrate.
  • Step 402 forming a gate insulating layer on the side of the gate away from the base substrate.
  • a gate insulating layer 102 may be formed on the side of the gate 101 away from the base substrate 20 , so that the gate 101 and the subsequently formed source and drain layers 105 are formed in the gate insulating layer 102 .
  • the source 1051 and drain 1052 are insulated.
  • Step 403 forming a channel film layer on the side of the gate insulating layer away from the base substrate.
  • a channel film layer 103 a can be formed on the side of the gate insulating layer 102 away from the base substrate 20 , and the channel film layer 103 a can cover the lining base substrate 20 .
  • the channel film layer 103a can be prepared by using a material with better conductivity.
  • the material of the channel film layer 103a may be nanocrystalline crystalline indium gallium zinc oxide.
  • the channel film layer 103a may be formed on the side of the gate insulating layer 102 away from the base substrate 20 by using a magnetron sputtering device.
  • the oxygen content of the sputtering gas of the magnetron sputtering equipment may range from 1% to 30%, and the temperature range of the base substrate 20 may range from 100°C to 200°C.
  • the power range of the magnetron sputtering device can be 10KW to 40KW.
  • Step 404 forming a third protective film layer on the side of the channel film layer away from the base substrate.
  • a third protective film layer c3 may be formed on the side of the channel film layer 103 a away from the base substrate 20 .
  • the third protective film layer c3 can be prepared from a material with poor conductivity, and the third protective film layer c3 can cover the base substrate 20 as a whole.
  • the material of the third protective film layer c3 may be C-axis crystalline indium gallium zinc oxide.
  • a magnetron sputtering device may be used to form the third protective film layer c3 on the side of the channel film layer 103a away from the base substrate 20 .
  • the oxygen content of the sputtering gas of the magnetron sputtering equipment ranges from 80% to 100%, and the temperature range of the base substrate 20 can be from 100°C to 300°C.
  • the power range of the magnetron sputtering equipment can be 10KW to 40KW.
  • a photolithography process may be used to pattern the third protective film layer c3 to obtain a second protective pattern 104a.
  • the photolithography process may include processes such as photoresist coating, exposure, development, etching, and photoresist stripping.
  • the photolithography process may also be referred to as a mask process.
  • Step 406 patterning the channel film layer to obtain a channel layer.
  • the channel film layer 103a can be patterned by using a photolithography process to obtain channel layer 103 .
  • the orthographic projection of the second protection pattern 104 a on the base substrate 20 may cover the orthographic projection of the channel layer 103 on the base substrate 20 .
  • the channel layer 103 is obtained by patterning the channel film layer 103a, the material of the channel layer 103 is also nanocrystalline crystalline indium gallium zinc oxide, and the channel layer 103 has good conductivity.
  • the channel layer 103 may also be referred to as a nanocrystalline crystalline indium gallium zinc oxide film layer.
  • Step 407 using plasma processing equipment to perform plasma processing on the side of the second protection pattern away from the base substrate.
  • argon gas (Ar) released by the plasma processing equipment may be used to perform plasma processing on the side of the second protection pattern 104a away from the channel layer 103 .
  • the pressure range of the plasma treatment equipment can be 0.3Pa (Pa) to 0.7Pa
  • the power range is 40KW to 60KW
  • the flow rate of argon gas is 1000sccm (standard milliliter/min) to 2000sccm
  • the processing time range is 5s (seconds). ) to 15s.
  • the side of the second protection pattern 104a away from the channel layer 103 is bombarded by the strong energy of the gas released during the plasma treatment, the indium oxide (In-O) on the side of the second protection pattern 104a away from the channel layer 103 ) bond is broken, so that a large number of indium ions exist on the side of the second protection pattern 104a away from the channel layer 103 .
  • An N-type semiconductor can be formed on the side of the second protection pattern 104a away from the channel layer 103, so that the resistance becomes smaller and the conductivity becomes larger.
  • the surface of the second protection pattern 104a on the side away from the channel layer 103 has poor flatness (the side of the second protection pattern 104a away from the channel layer 103 is uneven structure), it is easy to contact and discharge with the subsequently formed source and drain layers 105 . Thereby, the contact resistance between the side of the second protection pattern 104a away from the channel layer 103 and the source-drain layer 105 can be reduced.
  • Step 408 forming a source-drain film layer on the side of the plasma-treated second protective pattern away from the base substrate.
  • Step 409 etching the source and drain film layers to obtain the source and drain layers.
  • the source and drain film layers 105 a may be wet-etched by using an etchant, thereby obtaining the source and drain layers 105 .
  • the source-drain layer 105 may include: a source electrode 1051 and a drain electrode 1052 arranged at intervals.
  • the orthographic projection of the source electrode 1051 on the base substrate 20 and the orthographic projection of the channel layer 103 on the base substrate 20 have an overlapping area.
  • the orthographic projection of the drain electrode 1052 on the base substrate 20 and the orthographic projection of the channel layer 103 on the base substrate 20 have an overlapping area.
  • Step 410 etching the surface of the plasma-treated second protective pattern that does not overlap with the source electrode and the drain electrode to obtain a protective layer.
  • the conductivity of each region on the side away from the base substrate 20 of the second protection pattern 104a is relatively high.
  • the source and drain film layer 105a can continue to be close to the substrate
  • the second protective pattern 104a on one side of the substrate 20 is etched, thereby preparing the protective layer 104 . That is, the surface of the region of the second protection pattern 104a that does not overlap with neither the source electrode 1051 nor the drain electrode 1052 is etched.
  • the conductivity of the region where the protective layer 104 does not overlap with the source electrode 1051 and the drain electrode 1052 may be relatively small, for example, may be equivalent to the conductivity of the second protective pattern 104a without plasma treatment.
  • the etching of the second protective pattern 104a may be enabled.
  • the depth is smaller than the thickness of the second protection pattern 104a.
  • the etching depth of the second protection pattern 104a can be controlled by controlling the etching duration.
  • one part of the second protective pattern 104a divided into two parts may be the first sub-film layer b21 of the second film layer b2 in the protective layer 104, and the other part may be the second film in the protective layer 104.
  • the second sub-film layer b22 of the layer b2, and the part of the second protection pattern 104a that is not etched may be the first film layer b1 in the protection layer 104 .
  • the contact resistance between the surface of the first sub-layer b21 far away from the first film layer b1 and the source electrode 1051 can be reduced, and the contact resistance between the surface of the second sub-layer b22 far away from the first film layer b1 and the drain electrode 1052 can be reduced. contact resistance between.
  • the portion of the second protection pattern 104 a for overlapping with the source electrode 1051 constitutes the first portion 1041 of the protection layer 104 .
  • the portion of the second protection pattern 104 a overlapping the drain electrode 1052 constitutes the second portion 1042 of the protection layer 104 .
  • the portion of the second protection pattern 104 a that is not in contact with the source electrode 1051 and the drain electrode 1052 constitutes the third portion 1043 of the protection layer 104 .
  • the thickness of the third portion 1043 may be smaller than that of the first portion 1041 , and may be smaller than the thickness of the second portion 1042 .
  • step 406 may be performed before step 404 . That is, the order of steps 403 to 406 can be adjusted to: step 403, step 406, step 404, and step 405, in this case, each time a film layer is formed, the film layer can be patterned . Alternatively, steps 405 and 406 may be performed simultaneously. That is, the second protection pattern and the channel layer can be prepared by the same patterning process. In this case, the orthographic projection of the second protection pattern on the base substrate is the same as that of the channel layer on the base substrate. The orthographic projections overlap. Any person skilled in the art who is familiar with the technical scope disclosed in the present application can easily think of any variation of the method, which should be covered by the protection scope of the present application, and thus will not be repeated here.
  • the display device 00 may include: a base substrate 20 , and the oxide thin film as described in the above embodiments disposed on the base substrate 20 transistor.
  • the oxide thin film transistor may be any of the oxide thin film transistors 10 shown in FIG. 1 to FIG. 4 .
  • the display device may be a liquid crystal display device, an organic light-emitting diode (organic light-emitting diode, OLED) display device, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator, etc. Any product or component that has a display and fingerprint recognition.
  • OLED organic light-emitting diode

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Abstract

本申请公开了一种氧化物薄膜晶体管及其制备方法、显示装置，涉及显示技术领域。该氧化物薄膜晶体管中的保护层在衬底基板上的正投影覆盖沟道层在衬底基板上的正投影。该保护层能够对沟道层起到保护作用，避免沟道层被远离衬底基板的一侧被刻蚀液刻蚀，保证电流通过该沟道层传输的可靠性。并且，由于保护层中的第一部分和第二部分的导电性较好，因此电流通过该第一部分或该第二部分流入沟道层时，该第一部分和第二部分不会产生较大的热量，提高氧化物薄膜晶体管的信赖性。

Description

氧化物薄膜晶体管及其制备方法、显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种氧化物薄膜晶体管及其制备方法、显示装置。
背景技术
铟镓锌氧化物(indium gallium zinc oxide，IGZO)由于其迁移率高，均一性好以及透明性好等优点，被广泛应用于制备薄膜晶体管中的有源层。
发明内容
本申请提供了一种氧化物薄膜晶体管及其制备方法、显示装置，所述技术方案如下：一种氧化物薄膜晶体管，所述氧化物薄膜晶体管包括：
设置在衬底基板上的栅极，栅极绝缘层，沟道层，保护层，以及源漏极层，所述源漏极层包括：间隔设置的源极和漏极；
所述保护层设置在所述沟道层与所述源漏极层之间，且所述保护层与所述源漏极层和所述沟道层均接触，所述保护层在所述衬底基板上的正投影覆盖所述沟道层在所述衬底基板上的正投影，且所述保护层包括位于所述保护层不同区域的第一部分，第二部分，以及第三部分；
所述第一部分具有两个表面，所述第一部分的两个表面分别与所述沟道层和所述源极接触；所述第二部分具有两个表面，所述第二部分的两个表面分别与所述沟道层和所述漏极接触；所述第三部分具有两个表面，所述第三部分的两个表面中的其中一个表面与所述沟道层接触，另一个表面不与所述源极和所述漏极接触；
其中，所述第一部分与所述源极接触的表面的导电性和所述第二部分与所述漏极接触的表面的导电性，均大于所述第三部分的导电性。
一些实施方式中，所述沟道层和所述保护层的材料均为多元金属氧化物；
所述沟道层的多元金属氧化物为纳米结晶氧化物或非晶氧化物；
所述保护层靠近所述沟道层的一侧的多元金属氧化物为C轴结晶氧化物。
一些实施方式中，
所述沟道层和所述保护层的材料均为铟镓锌氧化物；
所述沟道层的铟镓锌氧化物为纳米结晶氧化物或非晶氧化物；
所述保护层靠近所述沟道层的一侧的铟镓锌氧化物为C轴结晶氧化物。
一些实施方式中，
所述保护层包括：层叠设置的第一膜层和第二膜层；所述第一膜层与所述沟道层接触；所述第二膜层包括与所述源极接触的第一子膜层，以及与所述漏极接触的第二子膜层；
所述第一子膜层为所述第一部分中与所述源极接触的部分；
所述第二子膜层为所述第二部分中与所述漏极接触的部分；
所述第一膜层包括所述第三部分、所述第一部分中远离所述源极的部分以及所述第二部分中远离所述漏极的部分；所述第一膜层的导电性小于所述第二膜层的导电性。
一些实施方式中，
所述沟道层和所述第二膜层为纳米晶结晶铟镓锌氧化物膜层；
所述第一膜层为C轴结晶铟镓锌氧化物膜层。
一些实施方式中，
所述纳米晶结晶铟镓锌氧化物膜层的铟镓锌原子数比为4：2：3。
一些实施方式中，
所述沟道层的厚度范围为：1纳米至30纳米；
所述第一膜层的厚度范围为：1纳米至30纳米；
所述第二膜层的厚度范围为：1纳米至100纳米。
一些实施方式中，
所述第一膜层和所述第二膜层均为C轴结晶铟镓锌氧化物膜层，所述第二膜层的氧空位数量大于所述第一膜层的氧空位数量；所述第二膜层为通过对所述C轴结晶铟镓锌氧化物膜层进行等离子体处理的膜层，所述等离子体处理的温度范围为200℃至300℃。
一些实施方式中，
所述第一子膜层远离所述第一膜层的表面以及所述第二子膜层远离所述第一膜层的表面均为等离子体处理后得到的凹凸不平的结构。
一些实施方式中，
所述沟道层的厚度范围为1纳米至30纳米；
所述保护层的厚度范围为20纳米至50纳米。
一些实施方式中，
所述纳米结晶氧化物的晶粒尺寸范围为2纳米至4纳米。
一些实施方式中，
所述第三部分的厚度小于所述第一部分的厚度，且所述第三部分的厚度小于所述第二部分的厚度。
一种氧化物薄膜晶体管，所述氧化物薄膜晶体管包括：
设置在衬底基板上的栅极，栅极绝缘层，沟道层，保护层，以及源漏极层，所述源漏极层包括：间隔设置的源极和漏极；
其中，所述保护层在所述衬底基板上的正投影覆盖所述沟道层在所述衬底基板上的正投影，且所述保护层包括第一部分，第二部分，以及第三部分；
所述第一部分在所述衬底基板上的正投影覆盖第一区域，所述第一区域为所述源极在所述衬底基板上的正投影和所述沟道层在所述衬底基板上的正投影的交叠区域；所述第二部分在所述衬底基板上的正投影覆盖第二区域，所述第二区域为所述漏极在所述衬底基板上的正投影和所述沟道层在所述衬底基板上的正投影的交叠区域；所述第三部分在所述衬底基板上的正投影覆盖第三区域；所述第三区域为间隔区域在所述衬底基板上的正投影和所述沟道层在所述衬底基板上的正投影的交叠区域，所述间隔区域为所述源极和所述漏极之间的区域；
其中，所述第一部分远离所述沟道层的一侧的导电性和所述第二部分远离所述沟道层的一侧的导电性均大于所述第三部分远离所述沟道层的一侧的导电性。
一些实施方式中，
所述保护层包括：沿远离所述衬底基板的方向依次层叠的第一膜层和第二膜层；
所述第一膜层在所述衬底基板上的正投影覆盖所述沟道层在所述衬底基板上的正投影；
所述第二膜层包括间隔设置的第一子膜层和第二子膜层，所述第一子膜层在所述衬底基板上的正投影覆盖所述第一区域，所述第二子膜层在所述衬底基板上的正投影覆盖所述第二区域；
其中，所述沟道层的导电性和所述第二膜层的导电性均大于所述第一膜层 的导电性。
一些实施方式中，
所述沟道层，所述第一膜层，以及所述第二膜层的材料均为多元金属氧化物；
所述沟道层和所述第二膜层的多元金属氧化物为纳米结晶氧化物或非晶氧化物；
所述第一膜层的多元金属氧化物为C轴结晶氧化物；
所述沟道层，所述第一膜层，以及所述第二膜层的材料均为铟镓锌氧化物；
所述沟道层和所述第二膜层的铟镓锌氧化物为纳米结晶氧化物或非晶氧化物；
所述第一膜层的铟镓锌氧化物为C轴结晶氧化物；
所述沟道层和所述第二膜层为纳米晶结晶铟镓锌氧化物膜层；
所述第一膜层为C轴结晶铟镓锌氧化物膜层。
一些实施方式中，
所述第一膜层和所述第二膜层均为C轴结晶铟镓锌氧化物膜层，所述第二膜层的氧空位数量大于所述第一膜层的氧空位数量；所述第二膜层为通过对所述C轴结晶铟镓锌氧化物膜层进行等离子体处理的膜层，所述等离子体处理的温度范围为200℃至300℃。
一种氧化物薄膜晶体管的制备方法，所述方法包括：
在衬底基板上形成栅极，栅极绝缘层，沟道层，保护层，以及源漏极层，所述源漏极层包括：间隔设置的源极和漏极；
所述保护层设置在所述沟道层与所述源漏极层之间，且所述保护层与所述源漏极层和所述沟道层均接触，所述保护层在所述衬底基板上的正投影覆盖所述沟道层在所述衬底基板上的正投影，且所述保护层包括位于所述保护层不同区域的第一部分，第二部分，以及第三部分；
所述第一部分具有两个表面，所述第一部分的两个表面分别与所述沟道层和所述源极接触；所述第二部分具有两个表面，所述第二部分的两个表面分别与所述沟道层和所述漏极接触；所述第三部分具有两个表面，所述第三部分的两个表面中的其中一个表面与所述沟道层接触，另一个表面不与所述源极和漏极接触；
其中，所述第一部分与所述源极接触的表面的导电性和所述第二部分与所 述漏极接触的表面的导电性，均大于所述第三部分中的不与所述源极和漏极接触的所述另一个表面的导电性。
一些实施方式中，
采用磁控溅射设备在所述衬底基板上形成第一保护膜层，其中，形成所述第一保护膜层时，所述磁控溅射设备的溅射气体的氧含量范围为80％至100％，且所述衬底基板的温度范围为100℃至300℃；
采用磁控溅射设备在所述衬底基板上形成第二保护膜层，其中，形成所述第二保护膜层时，所述磁控溅射设备的溅射气体的氧含量范围为1％至30％，且所述衬底基板的温度范围为100℃至200℃；
所述第一保护膜层的材料包括C轴结晶铟镓锌氧化物，所述第二保护膜层的材料包括纳米晶结晶铟镓锌氧化物。
一些实施方式中，
在衬底基板上形成所述保护层，包括：
在所述衬底基板上形成第三保护膜层；
对所述第三保护膜层进行图案化处理，得到第二保护图案，所述第二保护图案在所述衬底基板上的正投影覆盖所述沟道层在所述衬底基板上的正投影；
采用等离子体处理设备，对所述第二保护图案远离所述衬底基板的一侧进行等离子体处理；
对经过等离子体处理后的所述第二保护图案中与所述源极和所述漏极均不交叠的区域的表面进行刻蚀，得到所述保护层，其中，对所述第二保护图案的刻蚀深度小于所述第二保护图案的厚度。
一种显示装置，所述显示装置包括：衬底基板，以及设置在所述衬底基板上的多个所述的氧化物薄膜晶体管。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种显示装置的结构示意图；
图2是本申请实施例提供的另一种显示装置的结构示意图；
图3是本申请实施例提供的又一种显示装置的结构示意图；
图4是本申请实施例提供的再一种显示装置的结构示意图；
图5是本申请实施例提供的一种氧化物薄膜晶体管的示意图；
图6是图5所示的氧化物薄膜晶体管的一种局部结构示意图；
图7是图5所示的氧化物薄膜晶体管的另一种局部结构示意图；
图8是本申请实施例提供的一种氧化物薄膜晶体管的制备方法的流程图；
图9是本申请实施例提供的一种形成沟道膜层，第一保护膜层以及第二保护膜层的示意图；
图10是本申请实施例提供的一种得到第一保护图案，第一膜层和沟道层的示意图；
图11是本申请实施例提供的一种形成源漏极膜层的示意图；
图12是本申请实施例提供的一种得到源漏极层和第二膜层的示意图；
图13是本申请实施例提供的另一种氧化物薄膜晶体管的制备方法的流程图；
图14是本申请实施例提供的一种形成沟道膜层和第三保护膜层的示意图；
图15是本申请实施例提供的一种得到沟道层和第二保护图案的示意图；
图16是对第二保护图案远离衬底基板的一侧进行等离子体处理的示意图；
图17是本申请实施例提供的一种形成源漏极膜层的示意图；
图18是本申请实施例提供的一种得到源漏极层和保护层的示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
相关技术中，薄膜晶体管包括：沿远离衬底基板的方向依次层叠的栅极，绝缘层，有源层，以及源漏极层。其中，在形成该源漏极层时，需要采用刻蚀液对预先形成的源漏极膜层进行刻蚀，该源漏极层包括间隔设置的源极和漏极，该源极和漏极可以通过有源层导通。为了避免刻蚀源漏极膜层的刻蚀液对有源层造成影响，该薄膜晶体管还可以包括：位于有源层和源漏极层之间的保护层。该保护层在衬底基板上的正投影覆盖有源层在衬底基板上的正投影，该保护层可以用于避免刻蚀液刻蚀掉有源层。并且，由于保护层位于有源层和源漏极层之间，因此电流需先从源极或漏极流入保护层，再从保护层流入有源层，从而 实现源极和漏极的导通。其中，该有源层由纳米晶IGZO制备得到，保护层由结晶氧化物制备得到。
但是，由于制备保护层的结晶氧化物的导电性较差，因此电流从源极或漏极流入该保护层时，该保护层会产生较大的热量，该热量会对有源层造成影响，薄膜晶体管的导电性较差。
图1是本申请实施例提供的一种显示装置的结构示意图。参考图1可以看出，该氧化物薄膜晶体管10可以包括：设置在衬底基板(substrate)20上的栅极(gate)101，栅极绝缘层(gate insulator)102，沟道层103，保护层104，以及源漏极层105。该源漏极层105可以包括：间隔设置的源极(source)1051和漏极(drain)1052。
作为一种可选的实施方式，参考图1，该保护层104可以设置在沟道层103与源漏极层105之间，且该保护层104可以与源漏极层105和沟道层103均接触。该保护层104在衬底基板20上的正投影可以覆盖沟道层103在衬底基板20上的正投影。该保护层104可以用于保护沟道层103，避免沟道层103远离衬底基板20的一侧被刻蚀液刻蚀，保证电流通过该沟道层103传输的可靠性。
参考图1还可以看出，该保护层104可以包括位于保护层104不同区域的第一部分1041，第二部分1042，以及第三部分1043。该第一部分1041可以具有两个表面，该第一部分1041的两个表面分别与沟道层103和源极1051接触。该第二部分1042可以具有两个表面，该第二部分1042的两个表面可以分别与沟道层103和漏极1052接触。该第三部分1043可以具有两个表面，该第三部分1043的两个表面中的其中一个表面可以与沟道层103接触，另一个表面可以不与源极1051和漏极1052接触。
参考图1可以看出，该第三部分1043可以位于第一部分1041和第二部分1042之间。该第一部分1041与源极1051接触的表面的导电性和第二部分1042与漏极1052接触的表面的导电性，可以均大于第三部分1043中不与源极1051和漏极1052接触的另一个表面的导电性。也即是，该第一部分1041与源极1051接触的表面的导电性和第二部分1042与漏极1052接触的表面的导电性可以较好，第三部分1043中不与源极1051和漏极1052接触的另一个表面的导电性可以较差。
由于该第三部分1043不与源极1051和漏极1052接触的另一个表面的导电 性较差，因此源极1051的电流从第一部分1041流入后，不会通过第三部分1043传输至第二部分1042，且漏极1052的电流从第二部分1042流入后，不会通过第三部分1043传输至第一部分1041。由于位于保护层104的靠近衬底基板20的一侧的沟道层103的导电性较好，因此源极1051的电流从第一部分1041流入后，可以依次通过沟道层103和保护层104的第二部分1042传输至漏极1052。漏极1052的电流从第二部分1042流入后，可以依次通过该沟道层103和保护层104的第一部分1041传输至源极1051。
在本申请实施例中，由于保护层104的第一部分1041与源极1051接触的表面的导电性和第二部分1042与漏极1052接触的表面的导电性均较好，因此电流从源极1051或漏极1052流入该保护层104时，该保护层104不会产生较大的热量，提高氧化物薄膜晶体管10的信赖性。
作为另一种可选的实施方式，参考图1，该氧化物薄膜晶体管10可以包括：设置在衬底基板20上的栅极101，栅极绝缘层102，沟道层103，保护层104，以及源漏极层105。该源漏极层105可以包括：间隔设置的源极1051和漏极1052。
该保护层104在衬底基板20上的正投影可以覆盖沟道层103在衬底基板20上的正投影。该保护层104可以用于保护沟道层103，避免沟道层103远离衬底基板20的一侧被刻蚀液刻蚀，保证电流通过该沟道层103传输的可靠性。
参考图1还可以看出，该保护层104可以包括：第一部分1041，第二部分1042，以及第三部分1043。该第一部分1041在衬底基板20上的正投影覆盖第一区域a1，该第二部分1042在衬底基板20上的正投影覆盖第二区域a2，该第三部分1043在衬底基板20上的正投影覆盖第三区域a3。
其中，该第一区域a1为源极在衬底基板20上的正投影和沟道层103在衬底基板20上的正投影的交叠区域。该第二区域a2为漏极在衬底基板20上的正投影和沟道层103在衬底基板20上的正投影的交叠区域。该第三区域a3为间隔区域在衬底基板20上的正投影和沟道层103在衬底基板20上的正投影的交叠区域。该间隔区域为源极1051和漏极1052之间的区域。
参考图1可以看出，该第三部分1043可以位于第一部分1041和第二部分1042之间。该第一部分1041远离沟道层103的一侧的导电性和第二部分1042远离沟道层103的一侧的导电性，均大于第三部分1043远离沟道层103的一侧的导电性。该第一部分1041远离沟道层103的一侧的导电性和第二部分1042远离沟道层103的一侧的导电性可以较好，第三部分1043远离沟道层103的一 侧的导电性可以较差。
由于该第三部分1043远离沟道层103的一侧的导电性较差，因此源极1051的电流从第一部分1041流入后，不会通过第三部分1043传输至第二部分1042，且漏极1052的电流从第二部分1042流入后，不会通过第三部分1043传输至第一部分1041。由于位于保护层104靠近衬底基板20的一侧的沟道层103的导电性较好，因此源极1051的电流从第一部分1041流入后，可以依次通过沟道层103和保护层104的第二部分1042传输至漏极1052。漏极1052的电流从第二部分1042流入后，可以依次通过该沟道层103和保护层104的第一部分1041传输至源极1051。
在本申请实施例中，由于保护层104的第一部分1041远离沟道层103的一侧的导电性和第二部分1042远离沟道层103的一侧的导电性均较好，因此电流从源极1051或漏极1052流入该保护层104时，该保护层104不会产生较大的热量，提高了氧化物薄膜晶体管10的信赖性。
在本申请实施例中，在上述两种实施方式中，该沟道层103和保护层104的材料可以均为多元金属氧化物。其中，沟道层103的多元金属氧化物可以为纳米结晶氧化物或非晶氧化物。保护层104靠近沟道层103的一侧的多元金属氧化物可以为C轴结晶氧化物。
或者，该沟道层103和保护层104的材料可以均为铟镓锌氧化物。其中，沟道层103的铟镓锌氧化物可以为纳米结晶氧化物或非晶氧化物。保护层104靠近沟道层103的一侧的铟镓锌氧化物可以为C轴结晶氧化物。
其中，纳米结晶的晶粒尺寸范围大于1nm，可以为2nm(纳米)至4nm，比如3nm。
作为一种可选的实现方式，参考图2，该保护层104可以包括：层叠设置的第一膜层b1和第二膜层b2。保护层104中的两个膜层可以分别由两次构图工艺制备得到，非一次工艺形成。
参考图2，该第一膜层b1可以与沟道层103接触。结合图1和图2，该第一膜层b1可以包括位于源极1051和漏极1052之间的第三部分1043，源极下方的第一部分1041中远离源极1051的部分以及漏极1052下方的第二部分1042中远离漏极1052的部分。参考图2，该第二膜层b2可以包括：与源极1051接触的第一子膜层b21，以及与漏极1052接触的第二子膜层b22。结合图1和图2，该第一子膜层b21可以为第一部分1041中与源极1051接触的起导电作用的部 分。该第二子膜层b22可以为第二部分1042中与漏极1052接触的起到导电作用的部分。第一膜层b1和第二膜层b2以材质划分，而不仅仅以位置划分。第一膜层b1的导电性高于第二膜层b2的导电性。
其中，该第一膜层b1的导电性可以小于第二膜层b2的导电性，一种实施方式为，并且，该第二膜层b2中第一子膜层b21的氧空位数以及第二膜层b2中第二子膜层b22的氧空位数可以均大于第一膜层b1的氧空位数。这样，氧空位数量越多，其自由电子数量较多，导电性较高。
参考图2可以看出，保护层的第一膜层b1可以具有两个表面，该第一膜层b1的两个表面中的其中一个表面可以与沟道层103接触。另一个表面可以包括：与第一子膜层b21接触的第一表面区域，与第二子膜层b22接触的第二表面区域，以及位于第一表面区域和第二表面区域之间且不与第一子膜层b21和第二子膜层b22接触的第三表面区域。
在本申请实施例中，该第二膜层b2的第一子膜层b21，以及第一膜层b1中与第一子膜层b21重叠的部分可以构成保护层104的第一部分1041。该第二膜层b2的第二子膜层b22，以及第一膜层b1中与第二子膜层b22重叠的部分可以构成保护层104的第二部分1042。该第一膜层b1中与第一子膜层b21和第二子膜层b22均不重叠的部分构成保护层104的第三部分1043。
在本申请实施例中，该沟道层103的导电性和第二膜层b2的导电性可以均大于第一膜层b1的导电性。由于第二膜层b2相对于第一膜层b1靠近源漏极层105，因此源漏极层105的电流可以依次通过第二膜层b2和第一膜层b1流入沟道层103。并且，由于该第二膜层b2的导电性较好，因此电流流入该第二膜层b2时，该第二膜层b2不会产生较大的热量，该第二膜层b2能够起到热量缓冲的作用，避免沟道层103受到较大的热量的影响而产生缺陷，保证氧化物薄膜晶体管10的导电性。
可选的，第一膜层b1为C轴结晶型氧化物膜层，第二膜层b2为纳米结晶氧化物膜层。纳米晶IGZO膜层致密(本纳米晶IGZO膜层密度＞6.4g/cm3(克/立方厘米)，常规非晶IGZO＜5.7g/cm3)。顶层纳米晶IGZO搭配中间层C轴结晶型IGZO，纳米晶IGZO由于其本身有一定的结晶性能，与中间层结晶型IGZO在膜层方面能更好的过渡，在晶粒结构方面匹配性较好，能避免不必要的接触电阻的产生。
可选的，该沟道层103和第二膜层b2可以为纳米晶结晶铟镓锌氧化物膜层。 也即是，该沟道层103和第二膜层b2的材料可以为纳米晶结晶铟镓锌氧化物。第一膜层b1可以为C轴结晶铟镓锌氧化物膜层。也即是，该第一膜层b1的材料可以为C轴结晶铟镓锌氧化物(CAAC-IGZO)。
其中，纳米晶结晶铟镓锌氧化物膜层的铟镓锌原子数比可以为4：2：3。也即是，纳米晶结晶铟镓锌氧化物中的铟原子数：镓原子数：锌原子数＝4：2：3。当然，C轴结晶铟镓锌氧化物膜层的铟镓锌原子数比也可以为4：2：3。也即是，C轴结晶铟镓锌氧化物中的铟原子数：镓原子数：锌原子数＝4：2：3。
由此，该沟道层103的材料中各个元素的原子数之比，第一膜层b1的材料中各个元素的原子数之比，以及第二膜层b2的材料中各个元素的原子数之比均相同。因此在采用磁控溅射的方式制备沟道层103，第一膜层b1，以及第二膜层b2的过程中无需更换靶材。
并且，由于沟道层103的材料和第二膜层b2的材料可以相同，因此该沟道层103和第二膜层b2可以采用相同的工艺进行制备。
在本申请实施例中，保护层104中的第一部分1041的材料可以包括：纳米晶结晶铟镓锌氧化物和C轴结晶铟镓锌氧化物，保护层104中的第二部分1042的材料可以包括纳米晶结晶铟镓锌氧化物和C轴结晶铟镓锌氧化物，保护层104中的第三部分1043的材料可以包括C轴结晶铟镓锌氧化物。
可选的，该沟道层103的厚度范围可以为1nm至30nm，该第一膜层b1的厚度范围可以为1nm至30nm，该第二膜层b2的厚度范围可以为1nm至100nm。
在本申请实施例中，第一部分1041和第二部分1042相对于第三部分1043多一层第二膜层b2。该第一部分1041的厚度以及该第二部分1042的厚度均可以等于第一膜层b1和第二膜层b2的总厚度。该第三部分1043的厚度等于第一膜层b1的厚度。也即是，第三部分1043的厚度可以小于第一部分1041的厚度和第二部分1042的厚度。
作为另一种可选的实现方式，参考图3，该保护层104可以包括：层叠设置的第一膜层b1和第二膜层b2。该第一膜层b1和第二膜层b2可以采用同一次构图工艺制备得到。该第一膜层b1和第二膜层b2均为C轴结晶铟镓锌氧化物膜层。并且，该第二膜层b2可以为通过对C轴结晶铟镓锌氧化物膜层进行等离子体处理的膜层。该等离子体处理的温度范围为200℃至300℃。
其中，该第一膜层b1和第二膜层b2均为C轴结晶铟镓锌氧化物膜层，即第一膜层b1和第二膜层b2的材料可以均为C轴结晶铟镓锌氧化物。该C轴结 晶铟镓锌氧化物膜层的铟镓锌原子数比为4：2：3。可选的，该沟道层103可以为如上面任意一个实施例中介绍的纳米晶结晶铟镓锌氧化物膜层。
由于该沟道层103的材料中各个元素的原子数之比，可以与保护层104的材料中各个元素的原子数之比相同，因此在采用磁控溅射的方式制备沟道层103和保护层104的过程中无需更换靶材。当然，若该沟道层103的材料中各个元素的原子数之比，可以与保护层104的材料中各个元素的原子数之比不同，则在采用磁控溅射的方式制备沟道层103和保护层104的过程需要更换靶材。
由于纳米晶结晶铟镓锌氧化物的导电性一般较好，因此由该纳米晶结晶铟镓锌氧化物制备的沟道层103的导电性可以较好，源极1051或漏极1052可以通过该沟道层103导通。
在本申请实施例中，由于C轴结晶铟镓锌氧化物的导电性小于所述纳米结晶IGZO。结合图3和图4，为了提高保护层104的第一部分1041与源极1051接触的表面的导电性，以及提高第二部分1042与漏极1052接触的表面的导电性，可以使得该保护层104的第一部分1041与源极1051接触的表面和该保护层104的第二部分1042与漏极1052接触的表面经等离子体处理。
在经过等离子体处理的过程中，该第一部分1041和第二部分1042在等离子体处理时释放的气体的强大的能量轰击下，该第一部分1041与源极1051接触的表面和第二部分1042与漏极1052接触的表面的铟氧(In-O)键断裂(由于铟氧键的键能相对于镓氧键的键能和锌氧键的键能小，因此铟氧键相对于镓氧键和锌氧键更容易断裂)。该第一部分1041与源极1051接触的表面和第二部分1042与漏极1052而接触的表面均存在大量的铟离子。由此，该第一部分1041与源极1051接触的表面和第二部分1042与漏极1052而接触的表面可以形成N型半导体，其电阻变小，导电性变大。该N型半导体可以是指自由电子浓度远大于空穴浓度的杂质半导体。
在本申请实施例中，通过对第一部分1041与源极1051接触的表面和第二部分1042与漏极1052而接触的表面进行等离子体处理，可以提高该第一部分1041与源极1051接触的表面和第二部分1042与漏极1052接触的表面的导电性。由此即可避免电流从源极1051或漏极1052流入该保护层104时产生较大的热量，进而避免沟道层103受到较大的热量的影响而产生缺陷，保证氧化物薄膜晶体管10的导电性。
当然，为了在提高第一部分1041与源极1051接触的表面和第二部分1042 与漏极1052而接触的表面的导电性的前提下，避免第三部分1043不与源极1051和漏极1052接触的一个表面的导电性较好，可以使得该第三部分1043不与源极1051和漏极1052接触的另一个表面不经等离子体处理。
在本申请实施例中，为了简化该保护层104的制备工艺，可以对用于形成该保护层104的第二保护图案104a远离沟道层103的一侧进行等离子体处理。经过等离子体处理之后的该第二保护图案104a远离沟道层103的一侧的导电性较大。之后，对经过等离子体处理的第二保护图案104a与源极1051和漏极1052均不交叠的区域的表面进行刻蚀，从而使得该区域的导电性恢复至未经过等离子体处理的导电性。并且，刻蚀完成后，第二保护图案104a中被划分为两部分的其中一部分可以为第二膜层b2的第一子膜层b21，另一部分可以为第二膜层b2的第二子膜层b22，而未被刻蚀的第二保护图案104a的部分可以为第一膜层b1。
参考图3和图4，经过等离子体处理以及刻蚀处理之后，第一子膜层b21远离第一膜层b1的表面(即第一部分1041与源极1051接触的表面)和第二子膜层b22远离第一膜层b1的表面(即第二部分1042与漏极1052接触的表面)的平整性较差。即该第一子膜层b21远离第一膜层b1的表面以及第二子膜层b22远离第一膜层b1的表面可以均为凹凸不平的结构。该第一子膜层b21远离第一膜层b1的表面，以及第二子膜层b22远离第一膜层b1的表面容易与源漏极层105接触放电。由此，可以减小第一子膜层b21远离第一膜层b1的表面和源极1051之间的接触电阻，以及第二子膜层b22远离第一膜层b1的表面和漏极1052之间的接触电阻。
其中，经过等离子体处理以及刻蚀处理之后，该第二保护图案104a中与源极1051交叠的部分构成保护层104的第一部分1041。该第二保护图案104a中与漏极1052交叠的部分构成保护层104的第二部分1042。该第二保护图案104a中与源极1051和漏极1052均不交叠的部分构成保护层104的第三部分1043。
由于第三部分1043是第二保护图案104a经过刻蚀得到的，而第一部分1041和第二部分1042是第二保护图案104a未经刻蚀得到的，因此该第三部分1043的厚度可以小于第一部分1041的厚度，且可以小于第二部分1042的厚度。
当然，为了使得保护层104能够对沟道层103起到保护作用，对第二保护图案104a的刻蚀深度可以小于第二保护图案104a的厚度。也即是，该第二保护图案104a不会被刻透。可选的，该保护层104的第三部分1043的厚度范围可 以为10nm至20nm。
在本申请实施例中，该沟道层103的厚度范围可以为1nm至30nm。该保护层104的厚度范围可以为20nm至50nm。
参考图1至图4可以看出，该显示装置中，栅极101，栅极绝缘层102，沟道层103，保护层104以及源漏极层105可以沿远离衬底基板20的方向依次层叠。
图5是本申请实施例提供的一种氧化物薄膜晶体管的示意图。参考图5可以看出，该氧化物薄膜晶体管10中的沟道层103以及保护层104的厚度可以远远小于其他膜层的厚度。图6是图5所示的氧化物薄膜晶体管的一种局部结构示意图。图7是图5所示的氧化物薄膜晶体管的另一种局部结构示意图。参考图6和图7，该沟道层103和保护层104的第三部分1043的总厚度d1可以为35.1nm，该沟道层103和保护层104的第二部分1042的总厚度d2可以为49.6nm。其中，沟道层103和保护层104的第一部分1041的总厚度可以等于沟道层103和保护层104的第二部分1042的总厚度。
本申请实施例提供的一种氧化物薄膜晶体管10的制备方法，该方法可以用于制备图1所示的氧化物薄膜晶体管10。该方法可以包括：在衬底基板20上形成栅极101，栅极绝缘层102，沟道层103，保护层104，以及源漏极层105。该源漏极层105可以包括：间隔设置的源极1051和漏极1052。
其中，制备得到的该保护层104可以位于在沟道层103与源漏极层105之间，且该保护层104可以与源漏极层105和沟道层103均接触。该保护层104在衬底基板20上的正投影可以覆盖沟道层103在衬底基板20上的正投影。该保护层104可以用于保护沟道层103，避免沟道层103远离衬底基板20的一侧被刻蚀液刻蚀，保证电流通过该沟道层103传输的可靠性。
参考图1，该保护层104可以包括位于保护层104不同区域的第一部分1041，第二部分1042，以及第三部分1043。该第一部分1041可以具有两个表面，该第一部分1041的两个表面分别与沟道层103和源极1051接触。该第二部分1042可以具有两个表面，该第二部分1042的两个表面可以分别与沟道层103和漏极1052接触。该第三部分1043可以具有两个表面，该第三部分1043的两个表面中的其中一个表面可以与沟道层103接触，另一个表面可以不与源极1051和漏极1052接触。
参考图1还可以看出，该第三部分1043可以位于第一部分1041和第二部分1042之间。该第一部分1041与源极1051接触的表面的导电性和第二部分1042与漏极1052接触的表面的导电性，可以均大于第三部分1043中不与源极1051和漏极1052接触的另一个表面的导电性。也即是，该第一部分1041与源极1051接触的表面的导电性和第二部分1042与漏极1052接触的表面的导电性可以较好，第三部分1043中不与源极1051和漏极1052接触的另一个表面的导电性可以较差。
由于该第三部分1043不与源极1051和漏极1052接触的另一个表面的导电性较差，因此源极1051的电流从第一部分1041流入后，不会通过第三部分1043传输至第二部分1042，且漏极1052的电流从第二部分1042流入后，不会通过第三部分1043传输至第一部分1041。由于位于保护层104的靠近衬底基板20的一侧的沟道层103的导电性较好，因此源极1051的电流从第一部分1041流入后，可以依次通过沟道层103和保护层104的第二部分1042传输至漏极1052。漏极1052的电流从第二部分1042流入后，可以依次通过该沟道层103和保护层104的第一部分1041传输至源极1051。
在本申请实施例中，由于保护层104的第一部分1041与源极1051接触的表面的导电性和第二部分1042与漏极1052接触的表面的导电性均较好，因此电流从源极1051或漏极1052流入该保护层104时，该保护层104不会产生较大的热量，提高了氧化物薄膜晶体管10的信赖性。
综上所述，本申请实施例提供了一种氧化物薄膜晶体管的制备方法，该方法制备得到的氧化物薄膜晶体管中的保护层在衬底基板上的正投影覆盖沟道层在衬底基板上的正投影。该保护层能够对沟道层起到保护作用，避免沟道层被远离衬底基板的一侧被刻蚀液刻蚀，保证电流通过该沟道层传输的可靠性。并且，由于保护层中的第一部分和第二部分的导电性较好，因此电流通过该第一部分或该第二部分流入沟道层时，该第一部分和第二部分不会产生较大的热量，能够避免沟道层产生缺陷，氧化物薄膜晶体管的导电性较好。
在本申请实施例中，该沟道层103和保护层104的材料可以均为多元金属氧化物。其中，沟道层103的多元金属氧化物可以为纳米结晶氧化物或非晶氧化物。保护层104靠近沟道层103的一侧的多元金属氧化物可以为C轴结晶氧化物。
或者，该沟道层103和保护层104的材料可以均为铟镓锌氧化物。其中， 沟道层103的铟镓锌氧化物可以为纳米结晶氧化物或非晶氧化物。保护层104靠近沟道层103的一侧的铟镓锌氧化物可以为C轴结晶氧化物。
图8是本申请实施例提供的一种氧化物薄膜晶体管的制备方法的流程图。该方法可以用于制备图1所示的氧化物薄膜晶体管。参考图8，该方法可以包括：
步骤301、在衬底基板上形成栅极。
在本申请实施例中，可以先获取一衬底基板20，并在衬底基板20的一侧形成栅极101膜层，之后对该栅极101膜层进行图案化处理，从而得到栅极101。其中，该衬底基板20可以为玻璃基板。
步骤302、在栅极远离衬底基板的一侧形成栅极绝缘层。
在本申请实施例中，在形成栅极101之后，可以在该栅极101远离衬底基板20的一侧形成栅极绝缘层102，以使得栅极101与后续形成的源漏极层105中的源极1051和漏极1052绝缘。
步骤303、在栅极绝缘层远离衬底基板的一侧形成沟道膜层。
在形成栅极绝缘层102之后，参考图9，可以在该栅极绝缘层102远离衬底基板20的一侧形成沟道膜层103a，并且，该沟道膜层103a可以整层覆盖该衬底基板20。该沟道膜层103a可以采用导电性较好的材料进行制备。例如，该沟道膜层103a的材料可以为纳米晶结晶铟镓锌氧化物。
可选的，可以采用磁控溅射设备在栅极绝缘层102远离衬底基板20的一侧形成该沟道膜层103a。其中，形成该沟道膜层103a时，该磁控溅射设备的溅射气体的氧含量范围可以为1％至30％，该衬底基板20的温度范围可以为100℃(摄氏度)至200℃。并且，形成该沟道膜层103a时，该磁控溅射设备的功率范围可以为10KW(千瓦)至40KW。
步骤304、在沟道膜层远离衬底基板的一侧形成第一保护膜层。
在本申请实施例中，参考图9，可以在该沟道膜层103a远离衬底基板20的一侧形成第一保护膜层c1。该第一保护膜层c1可以由导电性较差的材料制备得到，且该第一保护膜层c1可以整层覆盖该衬底基板20。可选的，该第一保护膜层c1的材料可以为C轴结晶铟镓锌氧化物。
可选的，可以采用磁控溅射设备在沟道膜层103a远离衬底基板20的一侧形成第一保护膜层c1。其中，形成该第一保护膜层c1时，该磁控溅射设备的溅射气体的氧含量范围为80％至100％，该衬底基板20的温度范围可以为100℃至300℃。并且，形成该第一保护膜层c1时，该磁控溅射设备的功率范围可以为 10KW至40KW。
步骤305、在第一保护膜层远离衬底基板的一侧形成第二保护膜层。
在本申请实施例中，参考图9，可以在第一保护膜层c1远离衬底基板20的一侧形成第二保护膜层c2。该第二保护膜层c2可以由导电性较好的材料制备得到，且该第二保护膜层c2可以整层覆盖该衬底基板20。可选的，该第二保护膜层c2的材料可以为纳米晶结晶铟镓锌氧化物。
由于沟道膜层103a的材料和第二保护膜层c2的材料相同，因此该第二保护膜层c2的制备工艺可以与沟道层103的制备工艺相同。可选的，可以采用磁控溅射设备在第一保护膜层c1远离衬底基板20的一侧形成第二保护膜层c2。其中，形成该第二保护膜层c2时，该磁控溅射设备的溅射气体的氧含量范围为1％至30％，该衬底基板20的温度范围可以为100℃至200℃。并且，形成该第二保护膜层c2时，该磁控溅射设备的功率范围可以为10KW至40KW。
步骤306、对第二保护膜层进行图案化处理，得到第一保护图案。
在本申请实施例中，参考图10，可以采用光刻工艺对该第二保护膜层c2进行图案化处理，得到第一保护图案m。其中，该光刻工艺可以包括：光刻胶(photo resist，PR)涂覆、曝光、显影、刻蚀和光刻胶剥离等工艺。该光刻工艺也可以称为掩膜板(Mask)工艺。
步骤307、对第一保护膜层进行图案化处理，得到第一膜层。
在本申请实施例中，参考图10，对第二保护膜层c2进行图案化处理，得到第一保护图案m之后，可以继续采用光刻工艺对该第一保护膜层c1进行图案化处理，得到第一膜层b1。该第一保护图案m在衬底基板20上的正投影覆盖第一膜层b1在衬底基板20上的正投影。该第一膜层b1可以包括第三部分1043，第一部分1041中远离源极1051的部分以及第二部分1042中远离漏极1052的部分。
由于该第一膜层b1由第一保护膜层c1经过图案化处理得到，因此该第一膜层b1的材料也为C轴结晶铟镓锌氧化物，该第一膜层b1的导电性较差。其中，该第一膜层b1也可以称为C轴结晶铟镓锌氧化物膜层。
步骤308、对沟道膜层进行图案化处理，得到沟道层。
在本申请实施例中，参考图10，对该第二保护膜层c2进行图案化处理，得到第一膜层b1之后，可以继续采用光刻工艺对该沟道膜层103a进行图案化处理，得到沟道层103。该第一膜层b1在衬底基板20上的正投影覆盖沟道层103 在衬底基板20上的正投影。
由于该沟道层103由沟道膜层103a经过图案化处理得到，因此该沟道层103的材料也为纳米晶结晶铟镓锌氧化物，该沟道层103的导电性较好。其中，该沟道层103还可以称为纳米晶结晶铟镓锌氧化物膜层。
步骤309、在第一保护图案远离衬底基板的一侧形成源漏极膜层。
在本申请实施例中，参考图11，在形成第一保护图案m之后，可以在该第一保护图案m远离衬底基板20的一侧形成源漏极膜层105a。其中，该源漏极膜层105a可以整层覆盖该衬底基板20。
步骤310、对源漏极膜层进行刻蚀，得到源漏极层。
在本申请实施例中，参考图12，可以采用刻蚀剂对源漏极膜层105a进行湿法刻蚀，从而得到源漏极层105。该源漏极层105可以包括：间隔设置的源极1051和漏极1052。该源极1051在衬底基板20上的正投影与沟道层103在衬底基板20上的正投影存在交叠区域。该漏极1052在衬底基板20上的正投影与沟道层103在衬底基板20上的正投影存在交叠区域。
在本申请实施例中，参考图11，在对源漏极膜层105a进行刻蚀之前，沟道层103与该源漏极膜层105a之间形成有第一膜层b1和第一保护图案m。该第一膜层b1和第一保护图案m可以用于保护该沟道层103，避免刻蚀源漏极膜层105a时，刻蚀剂对沟道层103造成影响，保证沟道层103的良率。并且，由于沟道层103和源漏极膜层105a之间具有第一膜层b1和第一保护图案m，因此该沟道层103不易受到源漏极膜层105a中材料扩散的影响。
步骤311、对第一保护图案中与源极和漏极均不交叠的部分进行刻蚀，得到第二膜层。
由于第一保护图案m的导电性较好，因此为了避免源极1051或漏极1052的电流通过该第一保护图案m进行传输，参考图12，对源漏极膜层105a刻蚀完成后，可以继续对该源漏极膜层105a靠近衬底基板20的一侧的第一保护图案m进行刻蚀。也即是，可以对该第一保护图案m与源极1051和漏极1052均不交叠的区域部分进行刻蚀，得到第二膜层b2。并且，该第二膜层b2包括：与源极1051接触的第一子膜层b21，以及与漏极1052接触的第二子膜层b22。该第一子膜层b21可以为保护层104的第一部分1041中与源极1051接触起超导电作用的部分，第二子膜层b22可以为与第二部分1042中与漏极1052接触起导电作用的部分。第一膜层b1和第二膜层b2以材质划分，而不仅仅以位置划 分。第一膜层b1的导电性高于第二膜层b2的导电性。
在本申请实施例中，该步骤311制备得到的第二膜层b2以及上述步骤307制备得到的第一膜层b1可以构成氧化物薄膜晶体管10的保护层104。其中，对该保护层104的刻蚀深度可以大于或等于该第一保护图案m的厚度。也即是，该第一保护图案m可以被刻透。
并且，为了使得保护层104能够对沟道层103起到保护作用，避免后续在源漏极膜层105a远离衬底基板20的一侧形成其他膜层时对该沟道层103造成影响，可以使得保护层104的刻蚀深度小于第一保护图案m和第一膜层b1的总厚度。可选的，可以通过控制刻蚀时长控制该保护层104的刻蚀深度。示例的，图12中，保护层104的刻蚀深度可以等于第一保护图案m的厚度。
由于该第二膜层b2由第一保护图案m经过刻蚀得到，且该第一保护图案m由第二保护膜层c2经过图案化处理得到，因此该第二膜层b2的材料也包括纳米晶结晶铟镓锌氧化物，该第二膜层b2的导电性较好。并且，第二膜层b2中第一子膜层b21的氧空位数以及第二膜层b2中第二子膜层b22的氧空位数均大于第一膜层b1的氧空位数。该第二膜层b2还可以称为纳米晶结晶铟镓锌氧化物膜层。这样，氧空位数量越多，其自由电子数量较多，导电性较高。
由于第二膜层b2相对于第一膜层b1靠近源漏极层105，因此源漏极层105的电流可以依次通过第二膜层b2和第一膜层b1流入沟道层103。并且，由于该第二膜层b2的导电性较好，因此电流流入该第二膜层b2时，该第二膜层b2不会产生较大的热量。该第二膜层b2能够起到热量缓冲的作用，避免沟道层103受到较大的热量的影响而产生缺陷，保证制备得到的氧化物薄膜晶体管10的导电性。
需要说明的是，本申请实施例提供的氧化物薄膜晶体管10的制备方法的步骤的先后顺序可以进行适当调整，步骤也可以根据情况进行相应增减。例如，步骤308可以在步骤304之前执行，步骤307可以在步骤305之前执行。也即是，步骤303至步骤308的顺序可以调整为：步骤303、步骤308，步骤304，步骤307，步骤305以及步骤306，此种情况下，每形成一层膜层，即可对该膜层进行图案化处理。或者，步骤306至步骤308可以同步执行。也即是，第一保护图案，第一膜层，以及沟道层可以采用同一次图案化处理制备得到，此种情况下，第一保护图案在衬底基板上的正投影，第一膜层在衬底基板上的正投影以及沟道层在衬底基板上的正投影均重叠。任何熟悉本技术领域的技术人员 在本申请揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本申请的保护范围之内，因此不再赘述。
综上所述，本申请实施例提供了一种氧化物薄膜晶体管的制备方法，该方法制备得到的氧化物薄膜晶体管中的保护层在衬底基板上的正投影覆盖沟道层在衬底基板上的正投影。该保护层能够对沟道层起到保护作用，避免沟道层被远离衬底基板的一侧被刻蚀液刻蚀，保证电流通过该沟道层传输的可靠性。并且，由于保护层中第二膜层的导电性较好，因此电流从源极或漏极通过保护层的第二膜层之后，再通过保护层的第一膜层流入沟道层时，该第二膜层能够起到热量缓冲的作用，避免沟道层受到较大的热量的影响而产生缺陷，保证制备得到的氧化物薄膜晶体管的导电性。
图13是本申请实施例提供的一种氧化物薄膜晶体管的制备方法的流程图。该方法可以用于制备图3所示的氧化物薄膜晶体管。参考图13，该方法可以包括：
步骤401、在衬底基板上形成栅极。
在本申请实施例中，可以先获取一衬底基板20，并在衬底基板20的一侧形成栅极101膜层，之后对该栅极101膜层进行图案化处理，从而得到栅极101。其中，该衬底基板20可以为玻璃基板。
步骤402、在栅极远离衬底基板的一侧形成栅极绝缘层。
在本申请实施例中，在形成栅极101之后，可以在该栅极101远离衬底基板20的一侧形成栅极绝缘层102，以使得栅极101与后续形成的源漏极层105中的源极1051和漏极1052绝缘。
步骤403、在栅极绝缘层远离衬底基板的一侧形成沟道膜层。
在形成栅极绝缘层102之后，参考图14，可以在该栅极绝缘层102远离衬底基板20的一侧形成沟道膜层103a，并且，该沟道膜层103a可以整层覆盖该衬底基板20。该沟道膜层103a可以采用导电性较好的材料进行制备。例如，该沟道膜层103a的材料可以为纳米晶结晶铟镓锌氧化物。
可选的，可以采用磁控溅射设备在栅极绝缘层102远离衬底基板20的一侧形成该沟道膜层103a。其中，形成该沟道膜层103a时，该磁控溅射设备的溅射气体的氧含量范围可以为1％至30％，该衬底基板20的温度范围可以为100℃至200℃。并且，形成该沟道膜层103a时，该磁控溅射设备的功率范围可以为10KW 至40KW。
步骤404、在沟道膜层远离衬底基板的一侧形成第三保护膜层。
在本申请实施例中，参考图14，可以在沟道膜层103a远离衬底基板20的一侧形成第三保护膜层c3。该第三保护膜层c3可以由导电性较差的材料制备得到，且该第三保护膜层c3可以整层覆盖该衬底基板20。可选的，该第三保护膜层c3的材料可以为C轴结晶铟镓锌氧化物。
可选的，可以采用磁控溅射设备在沟道膜层103a远离衬底基板20的一侧形成第三保护膜层c3。其中，形成该第三保护膜层c3时，该磁控溅射设备的溅射气体的氧含量范围为80％至100％，该衬底基板20的温度范围可以为100℃至300℃。并且，形成该第三保护膜层c3时，该磁控溅射设备的功率范围可以为10KW至40KW。
步骤405、对该第三保护膜层进行图案化处理，得到第二保护图案。
在本申请实施例中，参考图，可以采用光刻工艺对该第三保护膜层c3进行图案化处理，得到第二保护图案104a。其中，该光刻工艺可以包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离等工艺。该光刻工艺也可以称为掩膜板工艺。
步骤406、对沟道膜层进行图案化处理，得到沟道层。
在本申请实施例中，参考图15，对第三保护膜层c3进行图案化处理，得到第二保护图案104a之后，可以继续采用光刻工艺对该沟道膜层103a进行图案化处理，得到沟道层103。其中，该第二保护图案104a在衬底基板20上的正投影可以覆盖沟道层103在衬底基板20上的正投影。
由于该沟道层103由沟道膜层103a经过图案化处理得到，因此该沟道层103的材料也为纳米晶结晶铟镓锌氧化物，该沟道层103的导电性较好。其中，该沟道层103还可以称为纳米晶结晶铟镓锌氧化物膜层。
步骤407、采用等离子体处理设备，对第二保护图案远离衬底基板的一侧进行等离子体处理。
在本申请实施例中，参考图16，可以采用等离子体处理设备释放的氩气(Ar)对第二保护图案104a远离沟道层103的一侧进行等离子体处理。其中，等离子体处理设备的压力范围可以为0.3Pa(帕)至0.7Pa，功率范围为40KW至60KW，氩气的流量范围为1000sccm(标准毫升/分钟)至2000sccm，处理时长范围为5s(秒)至15s。
该第二保护图案104a远离沟道层103的一侧在等离子体处理时释放的气体的强大的能量轰击下，该第二保护图案104a远离沟道层103的一侧的铟氧(In-O)键断裂，使得第二保护图案104a远离沟道层103的一侧存在大量的铟离子。该第二保护图案104a远离沟道层103的一侧可以形成N型半导体，电阻变小，导电性变大。并且，参考图16，经过等离子体处理之后，第二保护图案104a远离沟道层103的一侧的表面的平整性较差(该第二保护图案104a远离沟道层103的一侧为凹凸不平的结构)，容易与后续形成的源漏极层105接触放电。由此能够减小第二保护图案104a远离沟道层103的一侧和源漏极层105之间的接触电阻。
步骤408、在经过等离子体处理的第二保护图案远离衬底基板的一侧形成源漏极膜层。
在本申请实施例中，参考图17，在对第二保护图案104a远离衬底基板20的一侧进行等离子体处理之后，可以在该第二保护图案104a远离衬底基板20的一侧形成源漏极膜层105a。其中，该源漏极膜层105a可以整层覆盖该衬底基板20。
步骤409、对源漏极膜层进行刻蚀，得到源漏极层。
在本申请实施例中，参考图18，可以采用刻蚀剂对源漏极膜层105a进行湿法刻蚀，从而得到源漏极层105。该源漏极层105可以包括：间隔设置的源极1051和漏极1052。该源极1051在衬底基板20上的正投影与沟道层103在衬底基板20上的正投影存在交叠区域。该漏极1052在衬底基板20上的正投影与沟道层103在衬底基板20上的正投影存在交叠区域。
步骤410、对经过等离子体处理的第二保护图案中与源极和漏极均不交叠的区域的表面进行刻蚀，得到保护层。
由于第二保护图案104a远离衬底基板20的一侧经过等离子体处理，因此该第二保护图案104a远离衬底基板20的一侧的各个区域的导电性均较大。为了避免源极1051或漏极1052的电流通过该第二保护图案104a进行传输，参考图18，对源漏极膜层105a刻蚀完成后，可以继续对该源漏极膜层105a靠近衬底基板20的一侧的第二保护图案104a进行刻蚀，从而制备得到保护层104。也即是，对该第二保护图案104a中与源极1051和漏极1052均不交叠的区域的表面进行刻蚀。其中，该保护层104与源极1051和漏极1052均不交叠的区域的导电性可以较小，例如可以相当于第二保护图案104a未经等离子体处理的导电 性。
在本申请实施例中，为了使得保护层104能够对沟道层103起到保护作用，避免后续形成其他膜层时对该沟道层103造成影响，可以使得对第二保护图案104a的刻蚀深度小于第二保护图案104a的厚度。其中，可以通过控制刻蚀时长，控制该第二保护图案104a的刻蚀深度。
刻蚀完成后，该第二保护图案104a中被划分为两部分的其中一部分可以为保护层104中第二膜层b2的第一子膜层b21，另一部分可以为保护层104中第二膜层b2的第二子膜层b22，而未被刻蚀的第二保护图案104a的部分可以为保护层104中的第一膜层b1。
在经过等离子体处理以及刻蚀处理之后，第一子膜层b21远离第一膜层b1的表面和第二子膜层b22远离第一膜层b1的表面的平整性较差。即该第一子膜层b21远离第一膜层b1的表面以及第二子膜层b22远离第一膜层b1的表面可以均为凹凸不平的结构。该第一子膜层b21远离第一膜层b1的表面，以及第二子膜层b22远离第一膜层b1的表面容易与源漏极层105接触放电。由此，可以减小第一子膜层b21远离第一膜层b1的表面和源极1051之间的接触电阻，以及第二子膜层b22远离第一膜层b1的表面和漏极1052之间的接触电阻。
经过等离子体处理以及刻蚀处理之后，该第二保护图案104a中用于与源极1051交叠的部分构成保护层104的第一部分1041。该第二保护图案104a中与漏极1052交叠的部分构成保护层104的第二部分1042。该第二保护图案104a中与源极1051和漏极1052均不接触的部分构成保护层104的第三部分1043。
由于保护层104中与源极1051和漏极1052均不接触的第三部分1043是第二保护图案104a经过刻蚀得到的，而第一部分1041和第二部分1042是第二保护图案104a未经刻蚀得到的，因此该第三部分1043的厚度可以小于第一部分1041的厚度，且可以小于第二部分1042的厚度。
可选的，该保护层104中第三部分1043的厚度范围可以为10nm至20nm。第一部分1041和第二部分1042的厚度范围可以为20nm至50nm。
需要说明的是，本申请实施例提供的氧化物薄膜晶体管的制备方法的步骤的先后顺序可以进行适当调整，步骤也可以根据情况进行相应增减。例如，步骤406可以在步骤404之前执行。也即是，步骤403至步骤406的顺序可以调整为：步骤403、步骤406，步骤404，以及步骤405，此种情况下，每形成一层膜层，即可对该膜层进行图案化处理。或者，步骤405和步骤406可以同步 执行。也即是，第二保护图案，以及沟道层可以采用同一次图案化处理制备得到，此种情况下，第二保护图案在衬底基板上的正投影与沟道层在衬底基板上的正投影重叠。任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本申请的保护范围之内，因此不再赘述。
综上所述，本申请实施例提供了一种氧化物薄膜晶体管的制备方法，该方法制备得到的氧化物薄膜晶体管中的保护层在衬底基板上的正投影覆盖沟道层在衬底基板上的正投影。该保护层能够对沟道层起到保护作用，避免沟道层被远离衬底基板的一侧被刻蚀液刻蚀，保证电流通过该沟道层传输的可靠性。并且，由于保护层中与源极或漏极接触的部分(经过等离子体处理且未被刻蚀的部分)的导电性较好，因此电流从源极或漏极通过该保护层流入沟道层时，该保护层不会产生较大的热量，能够避免沟道层产生缺陷，氧化物薄膜晶体管的导电性较好。
本申请实施例还提供了一种显示装置，参考图1至图4，该显示装置00可以包括：衬底基板20，以及设置在该衬底基板20的如上述实施例所述的氧化物薄膜晶体管。其中，该氧化物薄膜晶体管可以为图1至图4中任一所示的氧化物薄膜晶体管10。
可选的，该显示装置可以为液晶显示装置、有机发光二极管(organic light-emitting diode，OLED)显示装置、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能以及指纹识别功能的产品或部件。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种氧化物薄膜晶体管，其特征在于，所述氧化物薄膜晶体管包括：
    设置在衬底基板上的栅极，栅极绝缘层，沟道层，保护层，以及源漏极层，所述源漏极层包括：间隔设置的源极和漏极；
    所述保护层设置在所述沟道层与所述源漏极层之间，且所述保护层与所述源漏极层和所述沟道层均接触，所述保护层在所述衬底基板上的正投影覆盖所述沟道层在所述衬底基板上的正投影，且所述保护层包括位于所述保护层不同区域的第一部分，第二部分，以及第三部分；
    所述第一部分具有两个表面，所述第一部分的两个表面分别与所述沟道层和所述源极接触；所述第二部分具有两个表面，所述第二部分的两个表面分别与所述沟道层和所述漏极接触；所述第三部分具有两个表面，所述第三部分的两个表面中的其中一个表面与所述沟道层接触，另一个表面不与所述源极和所述漏极接触；
    其中，所述第一部分与所述源极接触的表面的导电性和所述第二部分与所述漏极接触的表面的导电性，均大于所述第三部分的导电性。
  2. 根据权利要求1所述的氧化物薄膜晶体管，其特征在于，
    所述沟道层和所述保护层的材料均为多元金属氧化物；
    所述沟道层的多元金属氧化物为纳米结晶氧化物或非晶氧化物；
    所述保护层靠近所述沟道层的一侧的多元金属氧化物为C轴结晶氧化物。
  3. 根据权利要求1所述的氧化物薄膜晶体管，其特征在于，
    所述沟道层和所述保护层的材料均为铟镓锌氧化物；
    所述沟道层的铟镓锌氧化物为纳米结晶氧化物或非晶氧化物；
    所述保护层靠近所述沟道层的一侧的铟镓锌氧化物为C轴结晶氧化物。
  4. 根据权利要求2或3所述的氧化物薄膜晶体管，其特征在于，所述保护层包括：层叠设置的第一膜层和第二膜层；所述第一膜层与所述沟道层接触；所述第二膜层包括与所述源极接触的第一子膜层，以及与所述漏极接触的第二子膜层；
    所述第一子膜层为所述第一部分中与所述源极接触的部分；
    所述第二子膜层为所述第二部分中与所述漏极接触的部分；
    所述第一膜层包括所述第三部分、所述第一部分中远离所述源极的部分以 及所述第二部分中远离所述漏极的部分；所述第一膜层的导电性小于所述第二膜层的导电性。
  5. 根据权利要求4所述的氧化物薄膜晶体管，其特征在于，所述沟道层和所述第二膜层为纳米晶结晶铟镓锌氧化物膜层；
    所述第一膜层为C轴结晶铟镓锌氧化物膜层。
  6. 根据权利要求5所述的氧化物薄膜晶体管，其特征在于，所述纳米晶结晶铟镓锌氧化物膜层的铟镓锌原子数比为4：2：3。
  7. 根据权利要求4所述的氧化物薄膜晶体管，其特征在于，所述沟道层的厚度范围为：1纳米至30纳米；
    所述第一膜层的厚度范围为：1纳米至30纳米；
    所述第二膜层的厚度范围为：1纳米至100纳米。
  8. 根据权利要求4所述的氧化物薄膜晶体管，其特征在于，所述第一膜层和所述第二膜层均为C轴结晶铟镓锌氧化物膜层，所述第二膜层的氧空位数量大于所述第一膜层的氧空位数量；所述第二膜层为通过对所述C轴结晶铟镓锌氧化物膜层进行等离子体处理的膜层，所述等离子体处理的温度范围为200℃至300℃。
  9. 根据权利要求8所述的氧化物薄膜晶体管，其特征在于，所述第一子膜层远离所述第一膜层的表面以及所述第二子膜层远离所述第一膜层的表面均为等离子体处理后得到的凹凸不平的结构。
  10. 根据权利要求8所述的氧化物薄膜晶体管，其特征在于，所述沟道层的厚度范围为1纳米至30纳米；
    所述保护层的厚度范围为20纳米至50纳米。
  11. 根据权利要求2或3所述的氧化物薄膜晶体管，其特征在于，所述纳米结晶氧化物的晶粒尺寸范围为2纳米至4纳米。
  12. 根据权利要求1至11任一所述的氧化物薄膜晶体管，其特征在于，所述第三部分的厚度小于所述第一部分的厚度，且所述第三部分的厚度小于所述第二部分的厚度。
  13. 一种氧化物薄膜晶体管，其特征在于，所述氧化物薄膜晶体管包括：
    设置在衬底基板上的栅极，栅极绝缘层，沟道层，保护层，以及源漏极层，所述源漏极层包括：间隔设置的源极和漏极；
    其中，所述保护层在所述衬底基板上的正投影覆盖所述沟道层在所述衬底基板上的正投影，且所述保护层包括第一部分，第二部分，以及第三部分；
    所述第一部分在所述衬底基板上的正投影覆盖第一区域，所述第一区域为所述源极在所述衬底基板上的正投影和所述沟道层在所述衬底基板上的正投影的交叠区域；所述第二部分在所述衬底基板上的正投影覆盖第二区域，所述第二区域为所述漏极在所述衬底基板上的正投影和所述沟道层在所述衬底基板上的正投影的交叠区域；所述第三部分在所述衬底基板上的正投影覆盖第三区域；所述第三区域为间隔区域在所述衬底基板上的正投影和所述沟道层在所述衬底基板上的正投影的交叠区域，所述间隔区域为所述源极和所述漏极之间的区域；
    其中，所述第一部分远离所述沟道层的一侧的导电性和所述第二部分远离所述沟道层的一侧的导电性均大于所述第三部分远离所述沟道层的一侧的导电性。
  14. 根据权利要求13所述的氧化物薄膜晶体管，其特征在于，所述保护层包括：沿远离所述衬底基板的方向依次层叠的第一膜层和第二膜层；
    所述第一膜层在所述衬底基板上的正投影覆盖所述沟道层在所述衬底基板上的正投影；
    所述第二膜层包括间隔设置的第一子膜层和第二子膜层，所述第一子膜层在所述衬底基板上的正投影覆盖所述第一区域，所述第二子膜层在所述衬底基板上的正投影覆盖所述第二区域；
    其中，所述沟道层的导电性和所述第二膜层的导电性均大于所述第一膜层的导电性。
  15. 根据权利要求14所述的氧化物薄膜晶体管，其特征在于，所述沟道层，所述第一膜层，以及所述第二膜层的材料均为多元金属氧化物；
    所述沟道层和所述第二膜层的多元金属氧化物为纳米结晶氧化物或非晶氧化物；
    所述第一膜层的多元金属氧化物为C轴结晶氧化物；
    所述沟道层，所述第一膜层，以及所述第二膜层的材料均为铟镓锌氧化物；
    所述沟道层和所述第二膜层的铟镓锌氧化物为纳米结晶氧化物或非晶氧化物；
    所述第一膜层的铟镓锌氧化物为C轴结晶氧化物；
    所述沟道层和所述第二膜层为纳米晶结晶铟镓锌氧化物膜层；
    所述第一膜层为C轴结晶铟镓锌氧化物膜层。
  16. 根据权利要求14所述的氧化物薄膜晶体管，其特征在于，所述第一膜层和所述第二膜层均为C轴结晶铟镓锌氧化物膜层，所述第二膜层的氧空位数量大于所述第一膜层的氧空位数量；所述第二膜层为通过对所述C轴结晶铟镓锌氧化物膜层进行等离子体处理的膜层，所述等离子体处理的温度范围为200℃至300℃。
  17. 一种氧化物薄膜晶体管的制备方法，其特征在于，所述方法包括：
    在衬底基板上形成栅极，栅极绝缘层，沟道层，保护层，以及源漏极层，所述源漏极层包括：间隔设置的源极和漏极；
    所述保护层设置在所述沟道层与所述源漏极层之间，且所述保护层与所述源漏极层和所述沟道层均接触，所述保护层在所述衬底基板上的正投影覆盖所述沟道层在所述衬底基板上的正投影，且所述保护层包括位于所述保护层不同区域的第一部分，第二部分，以及第三部分；
    所述第一部分具有两个表面，所述第一部分的两个表面分别与所述沟道层和所述源极接触；所述第二部分具有两个表面，所述第二部分的两个表面分别与所述沟道层和所述漏极接触；所述第三部分具有两个表面，所述第三部分的两个表面中的其中一个表面与所述沟道层接触，另一个表面不与所述源极和漏极接触；
    其中，所述第一部分与所述源极接触的表面的导电性和所述第二部分与所述漏极接触的表面的导电性，均大于所述第三部分中的不与所述源极和漏极接触的所述另一个表面的导电性。
  18. 根据权利要求17所述的制备方法，其特征在于，采用磁控溅射设备在所述衬底基板上形成第一保护膜层，其中，形成所述第一保护膜层时，所述磁控溅射设备的溅射气体的氧含量范围为80％至100％，且所述衬底基板的温度范围为100℃至300℃；
    采用磁控溅射设备在所述衬底基板上形成第二保护膜层，其中，形成所述第二保护膜层时，所述磁控溅射设备的溅射气体的氧含量范围为1％至30％，且所述衬底基板的温度范围为100℃至200℃；
    所述第一保护膜层的材料包括C轴结晶铟镓锌氧化物，所述第二保护膜层 的材料包括纳米晶结晶铟镓锌氧化物。
  19. 根据权利要求17所述的制备方法，其特征在于，在衬底基板上形成所述保护层，包括：
    在所述衬底基板上形成第三保护膜层；
    对所述第三保护膜层进行图案化处理，得到第二保护图案，所述第二保护图案在所述衬底基板上的正投影覆盖所述沟道层在所述衬底基板上的正投影；
    采用等离子体处理设备，对所述第二保护图案远离所述衬底基板的一侧进行等离子体处理；
    对经过等离子体处理后的所述第二保护图案中与所述源极和所述漏极均不交叠的区域的表面进行刻蚀，得到所述保护层，其中，对所述第二保护图案的刻蚀深度小于所述第二保护图案的厚度。
  20. 一种显示装置，其特征在于，所述显示装置包括：衬底基板，以及设置在所述衬底基板上的多个如权利要求1至16任一所述的氧化物薄膜晶体管。
PCT/CN2020/133087 2020-12-01 2020-12-01 氧化物薄膜晶体管及其制备方法、显示装置 WO2022115992A1 (zh)

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