WO2019041858A1 - 刻蚀方法、薄膜晶体管的制造方法、工艺设备、显示装置 - Google Patents

刻蚀方法、薄膜晶体管的制造方法、工艺设备、显示装置 Download PDF

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WO2019041858A1
WO2019041858A1 PCT/CN2018/084960 CN2018084960W WO2019041858A1 WO 2019041858 A1 WO2019041858 A1 WO 2019041858A1 CN 2018084960 W CN2018084960 W CN 2018084960W WO 2019041858 A1 WO2019041858 A1 WO 2019041858A1
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Prior art keywords
etched
layer
photoresist layer
etching
plasma
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PCT/CN2018/084960
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English (en)
French (fr)
Inventor
杜生平
苏同上
黄正峰
杨玉
张旺
王磊
马云
刘丽华
刘广东
郭稳
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/305,451 priority Critical patent/US20210225903A1/en
Publication of WO2019041858A1 publication Critical patent/WO2019041858A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing, and in particular, to an etching method, a method of manufacturing a thin film transistor, a process device, and a display device.
  • Etch is a semiconductor manufacturing process, an important step in the microelectronic manufacturing process and the micro-nano manufacturing process. It refers to the process of stripping and removing materials by means of, for example, solution, reactive ions or mechanical means. At present, it mainly includes wet etching (Wet Etch, WE) and dry etching (Dry Etch, DE).
  • the present disclosure provides an etching method, a method of manufacturing a thin film transistor, a process device, and a display device.
  • the present disclosure provides an etching method comprising:
  • a patterned photoresist layer on a surface of the material to be etched, the patterned photoresist layer exposing a region to be etched on a surface of the material to be etched;
  • the photoresist layer is cured by a plasma process
  • the curing process of the photoresist layer by using a plasma process includes:
  • the photoresist layer is cured by a reactive ion etching process.
  • the photoresist layer is formed of an organic polymer material, and the plasma used in the plasma process is generated by ionization of a mixture of carbon tetrafluoride and oxygen.
  • the photoresist layer is formed of a positive photoresist of the type PR1-1000A, and the plasma used in the plasma process is ionized by a mixture of carbon tetrafluoride and oxygen. produce.
  • the etching method further includes:
  • the cured photoresist layer is subjected to ashing treatment using a plasma that oxidizes the photoresist layer.
  • the ashing treatment of the cured photoresist layer by using a plasma capable of oxidizing the photoresist layer comprises:
  • the photoresist layer is subjected to ashing treatment by a reactive ion etching process.
  • the photoresist layer is formed of an organic polymer material, and the plasma capable of oxidizing the photoresist layer is generated by ionization of a mixture of carbon tetrafluoride and oxygen.
  • the present disclosure also provides a method of fabricating a thin film transistor, including:
  • first metal layer to be etched on the substrate, the first metal layer comprising a conductive layer and a protective layer on both sides of the conductive layer;
  • the first metal layer is etched by an etching method of any of the above to form a pattern including a gate electrode in the first metal layer.
  • the manufacturing method of the thin film transistor further includes:
  • a second insulating layer is formed on the active layer and the second metal layer.
  • the conductive layer is made of copper or a copper-containing alloy
  • the protective layer is made of molybdenum or a molybdenum-containing alloy.
  • the present disclosure further provides a process apparatus used in any of the above etching methods, including:
  • a first mechanism for forming a patterned photoresist layer on a surface of the material to be etched on the substrate the patterned photoresist layer exposing a surface to be etched Etched area
  • a second mechanism connected to the first mechanism, configured to receive a substrate processed by the first mechanism, and perform a curing process on the photoresist layer by a plasma process;
  • a third mechanism connected to the second mechanism, configured to receive the processed substrate through the second mechanism, and etch the inside of the region to be etched by using an etching solution corresponding to the material to be etched Material to be etched.
  • the second mechanism is further configured to receive the substrate processed by the first mechanism, and perform a curing process on the photoresist layer by using a reactive ion etching process.
  • the photoresist layer is formed of an organic polymer material, and the plasma used in the plasma process is generated by ionization of a mixture of carbon tetrafluoride and oxygen.
  • the process device further includes:
  • a fourth mechanism connected to the third mechanism for receiving a substrate processed by the third mechanism, and performing a curing of the photoresist layer by using a plasma capable of oxidizing the photoresist layer Ashing treatment.
  • the fourth mechanism is further configured to receive the processed substrate through the third mechanism, and perform ashing treatment on the cured photoresist layer by using a reactive ion etching process.
  • the photoresist layer is formed of an organic polymer material, and the plasma capable of oxidizing the photoresist layer is generated by ionization of a mixture of carbon tetrafluoride and oxygen.
  • the present disclosure also provides a display device including the thin film transistor obtained by the method for manufacturing any one of the above thin film transistors.
  • FIG. 1 is a schematic flow chart of an etching method according to an embodiment of the present disclosure
  • FIG. 2 is a schematic flow chart of a method of manufacturing a thin film transistor according to an embodiment of the present disclosure
  • FIG. 3 to FIG. 10 are schematic cross-sectional structural views of a thin film transistor according to an embodiment of the present disclosure at various stages of a manufacturing process
  • FIG. 11 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 12 is a schematic structural diagram of a process device according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • “Comprising” or similar terms means that the elements or objects that appear before the word include the elements or items that appear after the word and their equivalents, and do not exclude other elements or items.
  • the words “connected” or “connected” and the like are not limited to physical or mechanical connections, but may include electrical connections, and the connections may be direct or indirect.
  • the photoresist when patterning a material by etching, since the photoresist is easily formed by illumination to form a prescribed pattern, it can be used to cover a surface of a part of the material so that the etching is only uncovered. The surface of the material is applied to achieve patterning of the material using the design of the photoresist pattern.
  • the photoresist due to the poor adhesion of the photoresist to certain materials, when etching these materials, the photoresist will have a slight gap at the interface with the material to be etched, so that Etchants can easily penetrate these tiny gaps and cause drilling (also known as "lateral drilling” or "lateral drilling", English: undercut).
  • FIG. 1 is a schematic flow chart of an etching method provided by an embodiment of the present disclosure. Referring to FIG. 1, the etching method includes the following steps:
  • Step 101 Form a patterned photoresist layer on a surface of the material to be etched, and the patterned photoresist layer exposes a region to be etched on a surface of the material to be etched.
  • Step 102 The photoresist layer is cured by a plasma process.
  • Step 103 Etching the material to be etched in the area to be etched by using an etching solution corresponding to the material to be etched.
  • the etching method of the present embodiment can be applied to any application scene that needs to be etched in a specified area on the surface of the material, that is, the material to be etched, the designated area is the material to be etched.
  • the area to be etched on the surface For example, in the process of fabricating an Array substrate, after the step of cleaning the glass substrate and the step of depositing a metal film layer for forming a gate conductive layer on the glass substrate, it is necessary to be etched.
  • the area to be etched on the surface of the metal film layer is etched to obtain a pattern of a pre-designed gate conductive layer (such as a pattern including a gate line, a gate electrode, a common electrode line, etc.),
  • the etching method of this embodiment is applied.
  • the etching method of the embodiment may be applied in an etching step of any one or more patterning processes; considering the simplification of the process And the cost saving, the etching method of the present embodiment can be applied only in an etching step in which the drilling phenomenon is relatively easy to occur.
  • the optional application scenario of this embodiment is not limited to the above example.
  • the patterned photoresist layer may be formed based on a full-surface photoresist layer by a process such as exposure and development based on the distribution position of the region to be etched, and may be used, for example, in the process.
  • the patterning of the photoresist layer does not affect the solution to the drilling problem, and thus the exposure and development of the positive photoresist, negative lithography Gel exposure development, or the use of a Half-Tone Mask (HTM) process or other means to pattern the photoresist layer, is applicable in the etching method of this embodiment.
  • HTM Half-Tone Mask
  • the material for forming the photoresist layer may be selected from any photo resistive (PR) material to the extent possible.
  • PR photo resistive
  • the adhesion between the forming material of the photoresist layer and the material to be etched is poor (for example, the minimum value of the energy required to separate the two from each other is lower than a predetermined threshold), the drilling is prone to occur.
  • the etching method is especially suitable.
  • step 102 the process of curing the photoresist layer by the plasma process actually corresponds to a process that can be observed in the dry etching field and is not suitable for the process:
  • the dry etching mainly utilizes the physical and chemical reaction between the plasma and the material to be etched to achieve etching, but in the process, the photoresist used to protect the region other than the region to be etched from being etched is also The plasma interacts. As the photoresist interacts with the plasma, the photoresist is easily denatured and cured, and the internal molecular alignment becomes more compact, while the texture becomes harder and even difficult to remove by the developer. In order to carry out the subsequent process, the photoresist must be stripped off. At this time, the removal by the developer can be discarded, and other more complicated and costly means are used to strip the photoresist. Moreover, depending on the selected means, there may be cases where the photoresist is not completely peeled off or the structural surface under the photoresist is damaged, which affects the quality of the product.
  • the dry etching technician will try to avoid the photoresist from solidifying under the exposure of the plasma during the etching process, and strip the photoresist as much as possible by using a simple developer removal method, and prevent the peeling and curing.
  • the process of photoresist affects the quality of the product.
  • the inventors of the present application found in practice that the wet etching using the cured photoresist as a mask will significantly reduce the occurrence of the drilling phenomenon, that is, in turn, the photoresist is exposed to the plasma. Curing is a phenomenon that is generally not conducive to the dry etching process to improve the etching effect of the wet etching. In the field, in the field of applications where dry etching has been selected, etchants other than plasma are generally not considered, and the wet etching which is superior in simplicity, speed and low cost does not process the process. A relatively complex and costly plasma treatment is added to the process.
  • a combination of a photoresist and a plasma which are known to undergo a curing phenomenon can be applied to the etching method of the present embodiment, for example, a plasma which is known to be capable of curing a certain photoresist material.
  • the composition can be applied to the curing process of the photoresist layer in the above step 102.
  • a plasma formed by a mixture of helium gas and trifluoromethane can cause a curing action, a plasma formed of a mixture of oxygen and carbon tetrafluoride.
  • the plasma formed by the body and argon ions (Ar + ) also causes it to cure.
  • a developing solution an ultrasonic treatment using an organic solvent such as acetone, an ultrasonic treatment using an alkaline solution such as sodium hydroxide, and an oxidation using a solution such as an oxygen ion are used.
  • the cleaning of the solution did not achieve good peeling of the photoresist layer.
  • the purpose of the curing process in the above step 102 is to cure the photoresist instead of etching the material to be etched, so the plasma process used is compared to the plasma used in dry etching.
  • Body processes can vary. For example, in terms of the complexity of the equipment used, the input power, the reaction time, and the fineness of the control, etc., it can be adjusted to a certain extent to adapt to the actual production application scenario.
  • the material to be etched may also interact with the plasma to produce a certain degree of etching.
  • etching occurs in the area to be etched, and on the other hand
  • the degree of etching may be limited by factors such as input power and reaction time, and thus this phenomenon can be limited to a range that does not greatly affect the implementation of the etching method of the present embodiment.
  • the corresponding etching liquid may be selected according to the material to be etched for etching, for example, hydrochloric acid is used as an etching liquid to etch the metal material to be etched, and hydrofluoric acid is used as the etching.
  • the liquid is used to etch the material to be etched of the silicon dioxide, etc., and the specific implementation manner can refer to the implementation process of the wet etching in various application scenarios, and details are not described herein.
  • the plasma process commonly used for dry etching is applied in wet etching in the embodiment of the present disclosure, and in turn, the photoresist is easily used in the dry etching after contacting the plasma.
  • the process of removing the photoresist layer not shown in FIG. 1 may be further included:
  • Step 104 Perform ashing treatment on the cured photoresist layer by using a plasma capable of oxidizing the photoresist layer.
  • the cured photoresist layer may be oxidized by plasma using oxygen to be removed by ashing.
  • the plasma to be used may be a gas obtained by mixing oxygen or air into argon gas, or a gas obtained by mixing oxygen or air into nitrogen gas, and may not be limited thereto.
  • the above method can completely remove the residual photoresist layer and avoid damage to the surface covered by the photoresist layer, thereby achieving better peeling effect.
  • FIG. 2 is a schematic flow chart of a method of fabricating a thin film transistor according to an embodiment of the present disclosure. Referring to FIG. 2, the manufacturing method of this embodiment includes the following steps:
  • Step 201 Form a first metal layer to be etched on the substrate, the first metal layer comprising a conductive layer and a protective layer on both sides of the conductive layer.
  • the substrate may be, for example, a glass substrate, a silicon wafer, a substrate of an organic polymer material such as polyimide, or the like
  • the conductive layer in the first metal layer may be formed of, for example, copper, aluminum, a copper-containing alloy, or The aluminum-containing alloy or the like
  • the material for forming the protective layer in the first metal layer may be, for example, molybdenum, niobium, an alloy containing molybdenum or an alloy containing niobium or the like.
  • the structure formed by step 201 is as shown in FIG. 3.
  • a physical vapor deposition process of a metal material may be employed on the surface of the substrate 11.
  • PVD Physical Vapor Deposition
  • Step 202 Etching the first metal layer to form a pattern including the gate electrode in the first metal layer.
  • the etching process of the first metal layer may be performed by any one of the above etching methods, and includes a process of removing the photoresist layer after the etching is completed.
  • the specific process of the above step 101 may be performed in the following manner: first, based on the structure shown in FIG. 3, a layer is applied on the first metal layer by, for example, spin coating, as shown in FIG.
  • the photoresist 21 used may be, for example, a positive photoresist.
  • the photoresist 21 in the region to be etched may be irradiated with ultraviolet light through the mask to be fully exposed, and then placed in the developer to pass the light in the region to be etched by the developing process.
  • the photoresist 21 is completely removed, and the remaining photoresist 21 forms a photoresist layer 22 as shown in FIG.
  • the specific process of the above step 102 can be performed as follows: on the basis of the photoresist layer 22 shown in FIG. 5, a reactive ion etching (RIE) process is used as a reactant.
  • RIE reactive ion etching
  • the mixture of oxygen and carbon tetrafluoride is ionized to generate a plasma, and the plasma is applied to the photoresist layer 21 until the curing process is completed.
  • the process parameters used in this process may refer to a known plasma processing process capable of curing the photoresist, and may be calibrated by, for example, prior experiments. And/or theoretical calculations adjust the process parameters to values that are appropriate for the applied scene.
  • the curing process can be implemented by using a dry etching device.
  • the photoresist used is a positive photoresist of type PR1-1000A, and the carbon tetrafluoride and oxygen are introduced.
  • the volume ratio between the two is 1200:1600, and the chamber pressure is set to 10mT (1.33Pa).
  • the power applied to the upper RF power source (Source Power) is set to 30kW, and the power applied to the lower power supply (Bias Power) ) is set to 30kW.
  • the curing process of the photoresist layer can be realized by the above-described dry etching apparatus.
  • the specific process of the above step 103 may be performed by using the cured photoresist layer 22 as a mask and using dilute hydrochloric acid as an etching solution to treat the first metal layer in the region ( The lower protective layer 12c, the conductive layer 12a, and the upper protective layer 12b) are etched so that the remaining first metal layer forms a pattern including the gate electrode EG as shown in FIG. It should be understood that since the photoresist layer 22 is subjected to the curing treatment, there is adhesion even between the photoresist layer 22 before the curing process and the upper surface of the first metal layer (i.e., the upper surface of the upper protective layer 12b).
  • the cured photoresist layer 22 can also be well attached to the upper surface of the first metal layer, helping to prevent the etching solution from being drilled into the photoresist layer 22 and The occurrence of a drilling phenomenon caused between the first metal layers.
  • the above curing process is essentially to increase the bonding energy between the photoresist layer and the surface of the material to be etched (the minimum amount of energy required to separate the two from each other), it can be based on This point pre-tests the change of the above binding energy by the plasma process under different parameters such as different photoresist composition, plasma composition and process parameters, so that plasma processing related in different application scenarios can be selected according to the test results.
  • the parameters of course, the manner in which the relevant parameters are set may not be limited to the manner described above.
  • the above-mentioned photoresist removal layer can be performed in the following manner: on the basis of the structure shown in FIG. 6, the reactive ion etch (RIE) process is used to ionize the oxygen as a reactant. To generate a plasma, a plasma is applied to the photoresist layer 21 until the ashing process is completed. Next, the ash-treated substrate can be cleaned by a liquid such as acetone or alcohol to completely remove the residual photoresist layer 21 and improve the cleanliness and flatness of each surface.
  • RIE reactive ion etch
  • Step 203 forming a first insulating layer on the first metal layer.
  • the material for forming the first insulating layer may be silicon oxide, silicon nitride, a photoresist, an organic polymer material, or the like, and may be fabricated by referring to a method of fabricating a gate insulating layer of the thin film transistor.
  • the structure formed by step 203 is as shown in FIG.
  • a first insulating layer covering the substrate 11 and the first metal layer may be deposited on the substrate 11 and the first metal layer by a chemical vapor deposition process (CVD). 13
  • the thickness of the film layer may need to meet the relevant requirements for the thickness of the gate insulating layer of the thin film transistor, and the setting of parameters such as the thickness of the film layer can be achieved by, for example, adjusting the relevant process parameters.
  • Step 204 forming a pattern including an active layer on the first insulating layer.
  • the forming material of the active layer may be a semiconductor material of amorphous silicon, polycrystalline silicon, single crystal silicon, metal oxide semiconductor or the like, and may be respectively doped in different regions according to the required device structure, and may be specifically prepared according to the desired The type of the thin film transistor and the device parameters are determined and will not be described here.
  • the structure formed through step 204 is as shown in FIG.
  • a layer of a semiconductor material may be formed by, for example, a chemical vapor deposition process, and then subjected to a doping process and a patterning process such as ion implantation to form a desired doping condition and a desired pattern.
  • Step 205 forming a second metal layer to be etched on the first insulating layer and the active layer.
  • Step 206 Etching the second metal layer to form a pattern including the source electrode and the drain electrode in the second metal layer.
  • the forming material and the film layer composition of the second metal layer may be completely the same as the first metal layer, and any one of the above etching methods may be used for etching the second metal layer.
  • the structure formed through step 206 is as shown in FIG.
  • the lower protective layer, the conductive layer and the upper protective layer of the second metal layer may be sequentially deposited by a physical Vapor Deposition (PVD) of a metal material, and then according to the above A process in which a metal layer is etched is performed in a similar process to etch the second metal layer to form a pattern including the source electrode ES and the drain electrode ED as shown in FIG.
  • the source electrode ES and the drain electrode ED are respectively connected to the active layer 14 at different positions, so that the formation of the voltage in the active layer 14 between the source electrode ES and the drain electrode ED can be affected by the voltage on the gate electrode EG.
  • Conductive channels are possible.
  • Step 207 forming a second insulating layer on the active layer and the second metal layer.
  • the material for forming the second insulating layer may be silicon oxide, silicon nitride, a photoresist, an organic polymer material, or the like, and may be fabricated by referring to a method of fabricating a passivation layer of the thin film transistor.
  • the structure formed by step 207 is as shown in FIG. 10.
  • a chemical vapor deposition process may be employed on the substrate 11, the active layer 14, and the second metal layer ( Chemical Vapor Deposition (CVD) deposits a second insulating layer 16 overlying the substrate 11, the active layer 14, and the second metal layer, and the setting of parameters such as the thickness of the film layer can be achieved by, for example, adjusting the relevant process parameters.
  • CVD Chemical Vapor Deposition
  • the manufacturing method of the embodiment may further include other processes not mentioned in the process of the different application scenarios before the step 201, after the step 207, and at any one or more intermediate nodes between the steps.
  • the following requirements are met, for example, after step 207, a device or an electrode connected to the thin film transistor is formed, or a layered structure disposed in the same layer as the second metal layer is formed between step 206 and step 207, and the like.
  • the manufacturing method of this embodiment is not limited.
  • the conductive layer of the first metal layer and/or the second metal layer is made of copper
  • the protective layer of the first metal layer and/or the second metal layer is made of molybdenum.
  • a bismuth alloy whereby the gate electrode and/or the source/drain electrode can have a smaller resistance value and a lower level of signal delay due to the higher conductivity of copper, and the molybdenum-bismuth alloy can be more stable at the same time.
  • Both sides of the copper layer act to prevent atomic diffusion, prevent oxidation of materials, improve surface characteristics, and improve contact resistance.
  • the etching method of any of the above may be utilized to solve the problem that the molybdenum-niobium alloy layer is prone to drilling in this application scenario.
  • Still another embodiment of the present disclosure provides a method of fabricating an array substrate. Referring to Figure 11, the method includes:
  • Step 301 Form a first metal layer to be etched on the substrate, the first metal layer comprising a conductive layer and a protective layer on both sides of the conductive layer.
  • Step 302 Etching the first metal layer to form a pattern including a gate electrode in the first metal layer.
  • Step 303 forming a first insulating layer on the first metal layer.
  • Step 304 forming a pattern including an active layer on the first insulating layer.
  • Step 305 forming a second metal layer to be etched on the first insulating layer and the active layer.
  • Step 306 etching the second metal layer to form a pattern including a source electrode and a drain electrode in the second metal layer.
  • Step 307 forming a second insulating layer on the active layer and the second metal layer.
  • the etching process of the first metal layer and/or the etching process of the second metal layer may respectively adopt an etching method of any one of the above.
  • the conductive layer is made of copper or a copper-containing alloy;
  • the protective layer is made of molybdenum or a molybdenum-containing alloy.
  • FIG. 12 is a schematic structural diagram of a process apparatus according to an embodiment of the present disclosure.
  • the process equipment includes:
  • a first mechanism 31 configured to form a patterned photoresist layer on a surface of the material to be etched on the substrate, wherein the patterned photoresist layer exposes a surface of the material to be etched Area to be etched;
  • a second mechanism 32 connected to the first mechanism 31 for receiving the substrate processed by the first mechanism 31, and curing the photoresist layer by a plasma process;
  • the third mechanism 33 connected to the second mechanism 32 is configured to receive the substrate processed by the second mechanism 32, and etch the to-be-etched region by using an etching solution corresponding to the material to be etched. Etching the material.
  • the second mechanism is further configured to receive the substrate processed by the first mechanism, and perform a curing process on the photoresist layer by using a reactive ion etching process.
  • the photoresist layer is formed of an organic polymer material, and the plasma used in the plasma process is generated by ionization of a mixture of carbon tetrafluoride and oxygen.
  • the process equipment further includes a fourth mechanism, a fourth mechanism and a third mechanism 33, not shown in FIG. 12, for receiving the processed substrate through the third mechanism 33, and adopting energy The plasma that oxidizes the photoresist layer ashes the cured photoresist layer.
  • the fourth mechanism is further configured to receive the processed substrate through the third mechanism, and perform ashing treatment on the cured photoresist layer by using a reactive ion etching process.
  • the photoresist layer is formed of an organic polymer material, and the plasma capable of oxidizing the photoresist layer is generated by ionization of a mixture of carbon tetrafluoride and oxygen.
  • the first mechanism 31 includes a substrate cleaning device, a drying device, a photoresist coating device, an exposure device, and a developing device, which are sequentially disposed
  • the second mechanism 32 includes a dry etching process device and a microscopic device.
  • the photographic apparatus, the third mechanism 33 described above includes a wet etch process apparatus and a photo photographic apparatus, and the functions of the fourth mechanism described above are implemented by the second mechanism 32.
  • the etching method described above can be implemented in a pipelined manner in accordance with, for example, the process illustrated in FIG.
  • the process equipment of the embodiments of the present disclosure innovatively uses the plasma process commonly used for dry etching in wet etching, and in turn utilizes the photoresist in the dry etching to easily contact the plasma.
  • the disadvantage of denaturation after the body is difficult to be stripped, and the contact between the photoresist layer and the material to be etched is enhanced by the plasma before the etching solution reacts with the material to be etched, thereby solving the problem of drilling caused thereby.
  • an embodiment of the present disclosure provides a display device including the thin film transistor obtained by the method for fabricating a thin film transistor of any of the above or the array substrate obtained by the method for fabricating the array substrate of any of the above.
  • the display device in the embodiment of the present disclosure may be any product or component having a display function such as a display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the 13 includes a sub-pixel unit Px disposed in a row and a column in the display area, and the thin film transistor may be disposed in the sub-pixel unit Px to implement adjustment of the gray scale of the display of the sub-pixel unit Px.
  • the array substrate may be disposed inside the display device 400.
  • the array substrate may include at least one thin film transistor in each of the sub-pixel units Px to implement adjustment of the display gray scale of each of the sub-pixel units Px.
  • the display device includes any one of the above-mentioned thin film transistors or any one of the above array substrates
  • the thin film transistor and the array substrate are fabricated by using any of the above etching methods for the gate conductive layer and/or
  • the etching of the source-drain conductive layer can achieve better product performance based on the better etching effect that can be achieved by the etching method.

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Abstract

本公开公开了一种刻蚀方法、薄膜晶体管的制造方法、工艺设备、显示装置，属于半导体制造领域。所述刻蚀方法包括：在待刻蚀材料的表面上形成经过图案化的光刻胶层，所述经过图案化的光刻胶层暴露出所述待刻蚀材料的表面上的待刻蚀区域；采用等离子体工艺对所述光刻胶层进行固化处理；采用与所述待刻蚀材料对应的刻蚀液刻蚀所述待刻蚀区域内的待刻蚀材料。本公开将常用于干法刻蚀的等离子体工艺创新地运用在了湿法刻蚀当中，并反过来利用了干法刻蚀中光刻胶容易在接触等离子体后发生变性而难以被剥离的缺点，在刻蚀液与待刻蚀材料反应之前利用等离子体增强光刻胶层与待刻蚀材料之间的接触，解决了由此而引发的钻刻问题，有助于提升产品良率和产品性能。

Description

刻蚀方法、薄膜晶体管的制造方法、工艺设备、显示装置
本公开要求于2017年8月31日提交中国国家知识产权局、申请号为201710771004.3、发明名称为“刻蚀方法、工艺设备、薄膜晶体管器件及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体制造领域，特别涉及一种刻蚀方法、薄膜晶体管的制造方法、工艺设备、显示装置。
背景技术
刻蚀(Etch)是一种半导体制造工艺，是微电子制造工艺以及微纳制造工艺中的一个重要步骤，指的是通过例如溶液、反应离子或机械等方式来剥离、去除材料的工艺过程，目前主要包括湿法刻蚀(Wet Etch，WE)和干法刻蚀(Dry Etch，DE)两种。
发明内容
本公开提供一种刻蚀方法、薄膜晶体管的制造方法、工艺设备、显示装置。
第一方面，本公开提供了一种刻蚀方法，包括：
在待刻蚀材料的表面上形成经过图案化的光刻胶层，所述经过图案化的光刻胶层暴露出所述待刻蚀材料的表面上的待刻蚀区域；
采用等离子体工艺对所述光刻胶层进行固化处理；
采用与所述待刻蚀材料对应的刻蚀液刻蚀所述待刻蚀区域内的待刻蚀材料。
在一种可能的实现方式中，所述采用等离子体工艺对所述光刻胶层进行固化处理，包括：
采用反应离子刻蚀工艺对所述光刻胶层进行固化处理。
在一种可能的实现方式中，所述光刻胶层的形成材料为有机高分子材料，所述等离子体工艺中使用的等离子体由四氟化碳与氧气的混合物电离产生。
在一种可能的实现方式中，所述光刻胶层的形成材料为PR1-1000A型的正性光刻胶，所述等离子体工艺中使用的等离子体由四氟化碳与氧气的混合物电离产生。
在一种可能的实现方式中，在采用与所述待刻蚀材料对应的刻蚀液刻蚀所述待刻蚀材料之后，所述刻蚀方法还包括：
采用能使所述光刻胶层氧化的等离子体对经过固化处理的光刻胶层进行灰化处理。
在一种可能的实现方式中，所述采用能使所述光刻胶层氧化的等离子体对经过固化处理的光刻胶层进行灰化处理，包括：
采用反应离子刻蚀工艺对所述光刻胶层进行灰化处理。
在一种可能的实现方式中，所述光刻胶层的形成材料为有机高分子材料，所述能使所述光刻胶层氧化的等离子体由四氟化碳与氧气的混合物电离产生。
第二方面，本公开还提供了一种薄膜晶体管的制造方法，包括：
在基板上形成待刻蚀的第一金属层，所述第一金属层包括导电层和位于所述导电层两侧的保护层；
采用上述任意一种的刻蚀方法对所述第一金属层进行刻蚀，以在所述第一金属层中形成包括栅电极的图形。
在一种可能的实现方式中，所述薄膜晶体管的制造方法还包括：
在所述第一金属层上形成第一绝缘层；
在所述第一绝缘层上形成包括有源层的图形；
在所述第一绝缘层和所述有源层上形成待刻蚀的第二金属层；
采用上述任意一种的刻蚀方法对所述第二金属层进行刻蚀，以在所述第二金属层中形成包括源电极和漏电极的图形；
在所述有源层和所述第二金属层上形成第二绝缘层。
在一种可能的实现方式中，所述导电层的材质为铜或者含铜的合金；所述保护层的材质为钼或者含钼的合金。
第三方面，本公开还提供了一种上述任意一种刻蚀方法所采用的工艺设备，包括：
第一机构，用于在基板上的待刻蚀材料的表面上形成经过图案化的光刻胶层，所述经过图案化的光刻胶层暴露出所述待刻蚀材料的表面上的待刻蚀区域；
与所述第一机构相连的第二机构，用于接收经过所述第一机构处理的基板， 并采用等离子体工艺对所述光刻胶层进行固化处理；
与所述第二机构相连的第三机构，用于接收经过所述第二机构的处理的基板，并采用与所述待刻蚀材料对应的刻蚀液刻蚀所述待刻蚀区域内的待刻蚀材料。
在一种可能的实现方式中，所述第二机构进一步用于接收经过所述第一机构处理的基板，并采用反应离子刻蚀工艺对所述光刻胶层进行固化处理。
在一种可能的实现方式中，所述光刻胶层的形成材料为有机高分子材料，所述等离子体工艺中使用的等离子体由四氟化碳与氧气的混合物电离产生。
在一种可能的实现方式中，所述工艺设备还包括：
与所述第三机构相连的第四机构，用于接收经过所述第三机构的处理的基板，并采用能使所述光刻胶层氧化的等离子体对经过固化处理的光刻胶层进行灰化处理。
在一种可能的实现方式中，所述第四机构进一步用于接收经过所述第三机构的处理的基板，并采用反应离子刻蚀工艺对经过固化处理的光刻胶层进行灰化处理。
在一种可能的实现方式中，所述光刻胶层的形成材料为有机高分子材料，所述能使所述光刻胶层氧化的等离子体由四氟化碳与氧气的混合物电离产生。
第四方面，本公开还提供了一种显示装置，所述显示装置包括由上述任意一种薄膜晶体管的制造方法得到的薄膜晶体管。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，这些附图的合理变型也都涵盖在本公开的保护范围中。
图1是本公开一个实施例提供的刻蚀方法的流程示意图；
图2是本公开一个实施例提供的薄膜晶体管的制造方法的流程示意图；
图3至图10是本公开一个实施例提供的薄膜晶体管在制造过程的各个阶段下的剖面结构示意图；
图11是本公开一个实施例提供的阵列基板的制造方法的流程示意图；
图12是本公开一个实施例提供的工艺设备的结构示意图；
图13是本公开一个实施例提供的显示装置的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，且该连接可以是直接的或间接的。
相关技术中，在利用刻蚀进行材料的图案化处理时，由于光刻胶容易通过光照来形成指定图案，因而可以被用来遮盖住材料一部分的表面，使得刻蚀仅在没有被遮盖住的材料表面上进行，从而利用对光刻胶图案的设计来实现材料的图案化。但是，由于光刻胶在某些材料上的粘附性很差，在对这些材料进行刻蚀时，光刻胶在与待刻蚀材料之间的交界面上会产生微小的缝隙，使得刻蚀剂很容易钻入这些微小缝隙而引发钻刻(也可称为“横向钻蚀”或“侧向钻蚀”，英文：undercut)。
针对于上述问题，图1是本公开一个实施例提供的刻蚀方法的流程示意图。参见图1，所述刻蚀方法包括以下步骤：
步骤101、在待刻蚀材料的表面上形成经过图案化的光刻胶层，所述经过图案化的光刻胶层暴露出所述待刻蚀材料的表面上的待刻蚀区域。
步骤102、采用等离子体工艺对所述光刻胶层进行固化处理。
步骤103、采用与所述待刻蚀材料对应的刻蚀液刻蚀所述待刻蚀区域内的待刻蚀材料。
应理解的是，本实施例的刻蚀方法可以应用于任意一种需要在材料表面上的指定区域内进行刻蚀的应用场景，该材料即待刻蚀材料，该指定区域即待刻蚀材料的表面上的待刻蚀区域。例如，在阵列基板(Array substrate)的制作过 程中，在进行了清洗玻璃基板的步骤，以及在玻璃基板上沉积用于形成栅极导电层的金属膜层的步骤之后，需要在待刻蚀的金属膜层的表面上的待刻蚀区域进行刻蚀，以得到预先设计好的栅极导电层的图形(比如包括栅线、栅电极、公共电极线等图形等等)的应用场景中，可以应用本实施例的刻蚀方法。再如，在有机发光二极管(Organic Light-Emitting Diode，OLED)器件的制作过程中，任意一个或多个图案化工艺的刻蚀步骤中可以应用本实施例的刻蚀方法；考虑到工艺的简化和成本的节约，可以仅在比较容易发生钻刻现象的刻蚀步骤中应用本实施例的刻蚀方法。当然，本实施例的可选应用场景并不仅限于以上示例。
在上述步骤101中，经过图案化的光刻胶层可以是基于待刻蚀区域的分布位置利用曝光和显影等过程基于一整面的光刻胶层制作形成的，该过程中可以例如用到所具图案与待刻蚀区域的分布位置相对应的掩膜板。而对于本实施例的刻蚀方法来说，光刻胶层以何种方式图案化并不影响对钻刻问题的解决，因而无论是通过对正性光刻胶曝光显影、对负性光刻胶曝光显影，还是利用半灰阶掩膜(Half-Tone Mask，HTM)工艺或者其他方式来将光刻胶层的图案化，在本实施例的刻蚀方法中都有适用的可能。需要说明的是，光刻胶层的形成材料可以在可能的范围内选自任一种光阻(Photo Resist，PR)材料。并且，对于光刻胶层的形成材料与待刻蚀材料之间粘附性差(比如将两者彼此分开所需要的能量的最小值低于预定阈值)而容易发生钻刻的情形，本实施例的刻蚀方法尤其适用。
在上述步骤102中，采用等离子体工艺对光刻胶层进行固化处理的过程实际上对应于干法刻蚀领域内能够观察到的、不利于工艺正常进行的过程：
干法刻蚀主要利用等离子体与待刻蚀材料之间的物理和化学反应实现刻蚀，但在此过程中用来保护待刻蚀区域以外的区域不被刻蚀的光刻胶也会与等离子体发生相互作用。随着光刻胶与等离子体的相互作用，光刻胶容易变性固化，内部分子排列变得更加紧密，同时质地变得更加坚硬，甚至难以通过显影液去除。而为了进行后续工艺又必须先将光刻胶剥离掉，此时就只能抛弃利用显影液去除的方式，而转用其他更加复杂和高成本的手段来剥离光刻胶。而且，根据所选择手段的不同，还可能出现光刻胶剥离不完全或是损坏光刻胶下方的结构表面的情况，影响产品的品质。
基于此，干法刻蚀的技术人员在刻蚀流程中会尽量避免光刻胶在等离子体的暴露下发生固化，以尽量采用简单的显影液去除的方式剥离光刻胶，并防止 剥离固化的光刻胶的过程对产品的品质造成影响。
但是本申请的发明人在实践过程中发现，利用固化后的光刻胶作为掩膜进行湿法刻蚀将明显减少钻刻现象的发生，即反过来利用光刻胶在等离子体的暴露下发生固化这一通常不利于干法刻蚀工序的现象来改善湿法刻蚀的刻蚀效果。而在本领域中，已经选择使用干法刻蚀的应用场景下一般不会再考虑等离子体以外的刻蚀剂，而以简便、快捷和低成本占优的湿法刻蚀又不会将过程相对复杂和高成本的等离子体处理加入到工序当中。
由此，对于已知会发生固化现象的光刻胶和等离子体的组合，可以应用至本实施例的刻蚀方法中，例如对于已知对某种光刻胶材料能产生固化作用的等离子体的组分，可以应用至上述步骤102中完成对光刻胶层的固化处理。示例性地，对于形成材料为有机高分子材料的光刻胶层，由氦气和三氟甲烷的混合物形成的等离子体能够使其发生固化作用，由氧气和四氟化碳的混合物形成的等离子体以及氩离子(Ar +)形成的等离子体也能使其发生固化作用。而且对于这种情况下发生固化的光刻胶层，使用显影液、使用例如丙酮的有机溶剂进行超声处理、使用例如氢氧化钠的碱性溶液进行超声处理、使用例如含氧离子的溶液的氧化物溶液进行清洗，均不能很好地实现光刻胶层的剥离。
需要说明的是，上述步骤102中的固化处理的目的是使光刻胶固化，而不是对待刻蚀材料进行刻蚀，因此所使用的等离子体工艺相比于干法刻蚀时所使用的等离子体工艺可以有所不同。比如，在所使用的设备的复杂度、输入功率、反应时间和控制的精细程度等等的方面上均可以有一定程度上的下调，以适应于实际的生产应用场景。而随着对光刻胶层的固化处理，待刻蚀材料也有可能与等离子体相互作用而产生一定程度的刻蚀，一方面这种刻蚀都发生在待刻蚀区域内，另一方面这种刻蚀的程度可能受限于输入功率和反应时间等因素而非常微小，因此这一现象可以被限制在不对本实施例的刻蚀方法的实施造成过大影响的范围内。
在上述步骤103中，可以根据待刻蚀材料选取相对应的刻蚀液来进行刻蚀，例如采用盐酸作为刻蚀液来对金属的待刻蚀材料进行刻蚀，采用氢氟酸作为刻蚀液来对二氧化硅的待刻蚀材料进行刻蚀等等，具体实现方式可以参照湿法刻蚀在各种应用场景下的实现过程，在此不在赘述。
可以看出的是，本公开实施例将常用于干法刻蚀的等离子体工艺运用在了湿法刻蚀当中，并反过来利用了干法刻蚀中光刻胶容易在接触等离子体后发生 变性而难以被剥离的缺点，在刻蚀液与待刻蚀材料反应之前利用等离子体增强光刻胶层与待刻蚀材料之间的接触，解决了由此而引发的钻刻问题，有助于提升产品良率和产品性能。
此外，在上述步骤103的刻蚀完成之后，可以还包括未在图1中示出的去除光刻胶层的过程：
步骤104、采用能使光刻胶层氧化的等离子体对经过固化处理的光刻胶层进行灰化处理。
作为一种示例，可以采用氧气的等离子体使固化后的光刻胶层发生氧化反应而以灰化的方式被去除掉。可替代地，所使用等离子体可以是氩气中通入氧气或空气混合而成的气体，或是氮气中通入氧气或空气混合而成的气体，并可以不仅限于此。相比于显影液去除、丙酮超声处理等方式，上述方式能够完整地去除残余的光刻胶层，并避免对光刻胶层所覆盖的表面造成损伤，达到较好的剥离效果。
图2是本公开一个实施例提供的薄膜晶体管的制造方法的流程示意图。参见图2，本实施例的制造方法包括以下步骤：
步骤201、在基板上形成待刻蚀的第一金属层，第一金属层包括导电层和位于导电层两侧的保护层。
其中，基板可以例如是玻璃基板、硅片、如聚酰亚胺的有机高分子材料的基板等等，第一金属层中的导电层的形成材料可以例如是铜、铝、含铜的合金或者含铝的合金等等，第一金属层中的保护层的形成材料可以例如是钼、铌、含钼的合金或者含铌的合金等等。
在一个示例中，经过步骤201所形成的结构如图3所示，在对基板11的表面进行清洗和烘干之后，可以在基板11的表面上采用金属材料的物理气相沉积工艺(Physical Vapor Deposition，PVD)依次沉积第一金属层的下保护层12c、导电层12a和上保护层12b，膜层厚度等参数的设置可以通过例如调整相关工艺参数的手段来实现。
步骤202、对第一金属层进行刻蚀，以在第一金属层中形成包括栅电极的图形。
其中，对第一金属层进行刻蚀的过程可以采用上述任意一种的刻蚀方法，并包含有在刻蚀完成后去除光刻胶层的过程。
在一个示例中，上述步骤101的具体流程可以按照下述方式进行：先在图3 所示结构的基础上，在第一金属层上采用例如旋涂的方式涂覆一层如图4所示的光刻胶21，所采用的光刻胶可以例如是正性光刻胶。接下来，可以采用紫外光透过掩膜板照射全部待刻蚀区域内的光刻胶21以使其充分曝光，再将其置于显影液中以通过显影过程将待刻蚀区域内的光刻胶21全部去除，由余留下来的光刻胶21形成如图5所示的光刻胶层22。
继上一示例，上述步骤102的具体流程可以按照下述方式进行：在图5所示的光刻胶层22的基础上，采用反应离子刻蚀(Reactive Ion Etching，RIE)工艺将作为反应物的氧气和四氟化碳的混合物电离以产生等离子体，使等离子体作用于光刻胶层21直至固化处理完成。需要说明的是，在所有可能实施的应用场景中，这一工序所使用的各项工艺参数可以参照已知的能使光刻胶发生固化的等离子体处理过程，并可以通过例如预先的实验标定和/或理论计算将工艺参数调整至适应于所应用的场景的数值。
作为一种实现方式示例，可以利用干法刻蚀的设备实现上述固化处理，具体所采用的光刻胶为PR1-1000A型的正性光刻胶，所通入的四氟化碳与氧气之间的体积比为1200:1600，同时设备腔体压力被设置为10mT(1.33Pa)，施加在上部射频电源上的功率(Source Power)被设置为30kW，施加在下部电源上的功率(Bias Power)被设置为30kW。在上述参数下，可以藉由上述干法刻蚀的设备实现对光刻胶层的固化处理。
继上一示例，上述步骤103的具体流程可以按照下述方式进行：以经过固化处理的光刻胶层22作为掩膜，采用稀盐酸作为刻蚀液对待刻蚀区域内的第一金属层(包括下保护层12c、导电层12a和上保护层12b)进行刻蚀，使余留下来的第一金属层形成包括如图6所示的栅电极EG的图形。应当理解的是，由于光刻胶层22经过了固化处理，因此即便固化处理前的光刻胶层22与第一金属层的上表面(即上保护层12b的上表面)之间存在粘附性差或是存在微小缝隙的问题，固化处理后的光刻胶层22也能很好地贴附在第一金属层的上表面上，有助于防止刻蚀液钻入光刻胶层22与第一金属层之间而引发的钻刻现象的发生。
还应理解的是，由于上述固化处理本质上是为了增大光刻胶层与待刻蚀材料的表面之间的结合能(将两者彼此分开所需要的能量的最小值)，因此可以基于这一点预先测试不同光刻胶组分、等离子体成分和工艺参数等相关参量下进行的等离子体工艺对上述结合能的改变情况，从而可以根据测试结果选取不同 应用场景下的等离子体处理的相关参量，当然相关参量的设置方式可以不仅限于上文所述及的方式。
承接上一示例，上述去除光刻胶层可以按照下述方式进行：在如图6所示的结构的基础上，采用反应离子刻蚀(Reactive Ion Etching，RIE)工艺将作为反应物的氧气电离以产生等离子体，使等离子体作用于光刻胶层21直至灰化处理完成。接下来，可以通过例如丙酮或酒精的液体对灰化处理后的基板进行清洗，以完全去除残留的光刻胶层21，并提升各表面的整洁度和平整度。
步骤203、在第一金属层上形成第一绝缘层。
其中，第一绝缘层的形成材料可以是氧化硅、氮化硅、光刻胶、有机高分子材料等等，并可以参照薄膜晶体管的栅绝缘层的制作方式来进行制作。
在一个示例中，经过步骤203所形成的结构如图7所示。在完成上述步骤202的全部处理之后，可以在基板11和第一金属层之上采用化学气相沉积工艺(Chemical Vapor Deposition，CVD)沉积覆盖在基板11和第一金属层之上的第一绝缘层13，其膜层厚度可能需要满足对于薄膜晶体管的栅绝缘层的厚度的相关要求，膜层厚度等参数的设置可以通过例如调整相关工艺参数的手段来实现。
步骤204、在第一绝缘层上形成包括有源层的图形。
其中，有源层的形成材料可以是非晶硅、多晶硅、单晶硅、金属氧化物半导体等等的半导体材料，并可以按照所需要的器件结构在不同区域内分别掺杂，具体可以根据所要制作的薄膜晶体管的类型和器件参数确定，在此不再赘述。
在一个示例中，经过步骤204所形成的结构如图8所示。在图7所示结构的基础上，可以先采用例如化学气相沉积工艺的方式形成一层半导体材料层，再经过例如离子注入的掺杂工艺和构图工艺形成具有所需掺杂情况和所需图案的有源层14，其中的有源层14与上述栅电极EG彼此交叠。
步骤205、在第一绝缘层和有源层上形成待刻蚀的第二金属层。
步骤206、对第二金属层进行刻蚀，以在第二金属层中形成包括源电极和漏电极的图形。
其中，第二金属层的形成材料和膜层组成可以与第一金属层完全相同，对第二金属层进行刻蚀时可以采用上述任意一种刻蚀方法。
在一个示例中，经过步骤206所形成的结构如图9所示。在图8所示的结构基础上，可以采用金属材料的物理气相沉积工艺(Physical Vapor Deposition，PVD)依次沉积第二金属层的下保护层、导电层和上保护层，然后按照与上述 对第一金属层进行刻蚀的过程类似的过程实现对第二金属层的刻蚀，形成如图8所示的包括源电极ES和漏电极ED的图形。其中，源电极ES和漏电极ED分别在不同位置处连接上述有源层14，以使在源电极ES和漏电极ED之间的有源层14内形成可受栅电极EG上电压大小影响的导电沟道成为可能。
步骤207、在有源层和第二金属层上形成第二绝缘层。
其中，第二绝缘层的形成材料可以是氧化硅、氮化硅、光刻胶、有机高分子材料等等，并可以参照薄膜晶体管的钝化层的制作方式来进行制作。
在一个示例中，经过步骤207所形成的结构如图10所示，在图9所示的结构基础上，可以在基板11、有源层14和第二金属层之上采用化学气相沉积工艺(Chemical Vapor Deposition，CVD)沉积覆盖在基板11、有源层14和第二金属层之上的第二绝缘层16，其膜层厚度等参数的设置可以通过例如调整相关工艺参数的手段来实现，并由此完成薄膜晶体管的基本结构的制作。
应理解的是，本实施例的制作方法在步骤201之前、步骤207之后和各步骤之间的任意一个或多个的中间节点上还可以包括其他没有述及的过程，以在不同的应用场景下满足不同的应用需求，比如在步骤207之后还包括制作与薄膜晶体管相连的器件或电极，或是在步骤206与步骤207之间制作与第二金属层同层设置的层状结构等等，本实施例的制作方法均不做限制。
此外，在本实施例的一种实现方式中，第一金属层和/或第二金属层的导电层的材质为铜，第一金属层和/或第二金属层的保护层的材质为钼铌合金，由此栅电极和/或源漏电极能因铜所具有的较高的电导率而具有更小的电阻值和更低水平的信号延迟，同时稳定性更好的钼铌合金能在铜层两侧起到阻止原子扩散、防止材料氧化、改善表面特性、改善接触电阻等作用。而且，由于钼铌合金存在一些光刻胶的粘附性差的问题，因此可以利用上述任意一种的刻蚀方法来解决该应用场景下钼铌合金层容易发生钻刻现象的问题。
基于同样的发明构思，本公开的又一实施例提供一种阵列基板的制造方法。参见图11，该方法包括：
步骤301、在基板上形成待刻蚀的第一金属层，所述第一金属层包括导电层和位于所述导电层两侧的保护层。
步骤302、对所述第一金属层进行刻蚀，以在所述第一金属层中形成包括栅电极的图形。
步骤303、在所述第一金属层上形成第一绝缘层。
步骤304、在所述第一绝缘层上形成包括有源层的图形。
步骤305、在所述第一绝缘层和所述有源层上形成待刻蚀的第二金属层。
步骤306、对所述第二金属层进行刻蚀，以在所述第二金属层中形成包括源电极和漏电极的图形。
步骤307、在所述有源层和所述第二金属层上形成第二绝缘层。
其中，对所述第一金属层进行刻蚀的过程和/或对第二金属层进行刻蚀的过程可以分别采用上文所述的任意一种的刻蚀方法。在一种可能的实现方式中，所述导电层的材质为铜或者含铜的合金；所述保护层的材质为钼或者含钼的合金。应当理解的是，由于阵列基板可以由薄膜晶体管阵列排布而成，而两者在结构上的差别可以仅在于每层结构的图案上，因此图2所示的过程也可以视为本实施例的阵列基板的制造方法的示例，相关内容在此不在赘述。
图12是本公开一个实施例提供的工艺设备的结构示意图。参见图12，该工艺设备包括：
第一机构31，用于在基板上的待刻蚀材料的表面上形成经过图案化的光刻胶层，所述经过图案化的光刻胶层暴露出所述待刻蚀材料的表面上的待刻蚀区域；
与第一机构31相连的第二机构32，用于接收经过第一机构31处理的基板，并采用等离子体工艺对所述光刻胶层进行固化处理；
与第二机构32相连的第三机构33，用于接收经过第二机构32的处理的基板，并采用与所述待刻蚀材料对应的刻蚀液刻蚀所述待刻蚀区域内的待刻蚀材料。
在一种可能的实现方式中，所述第二机构进一步用于接收经过所述第一机构处理的基板，并采用反应离子刻蚀工艺对所述光刻胶层进行固化处理。
在一种可能的实现方式中，所述光刻胶层的形成材料为有机高分子材料，所述等离子体工艺中使用的等离子体由四氟化碳与氧气的混合物电离产生。在一种可能的实现方式中，工艺设备还包括未在图12中示出的第四机构，第四机构与第三机构33，用于接收经过第三机构33的处理的基板，并采用能使光刻胶层氧化的等离子体对经过固化处理的光刻胶层进行灰化处理。
在一种可能的实现方式中，所述第四机构进一步用于接收经过所述第三机构的处理的基板，并采用反应离子刻蚀工艺对经过固化处理的光刻胶层进行灰化处理。
在一种可能的实现方式中，所述光刻胶层的形成材料为有机高分子材料，所述能使所述光刻胶层氧化的等离子体由四氟化碳与氧气的混合物电离产生。
在一个示例中，上述第一机构31包括依次设置的基板清洗设备、烘干设备、光刻胶涂覆设备、曝光设备和显影设备，上述第二机构32包括干法刻蚀工艺设备和显微照相设备，上述第三机构33包括湿法刻蚀工艺设备和显微照相设备，而上述第四机构的功能由第二机构32实现。如此，可以依照例如图2所示的过程以流水线的方式实现上述刻蚀方法。
应理解的是，上述各个机构执行操作的具体示例性方式已经在有关方法的实施例中进行了详细描述，而依照各工艺步骤可以设置相应的设备来实现，此处不再一一赘述。
可以看出，本公开实施例的工艺设备将常用于干法刻蚀的等离子体工艺创新地运用在了湿法刻蚀当中，并反过来利用了干法刻蚀中光刻胶容易在接触等离子体后发生变性而难以被剥离的缺点，在刻蚀液与待刻蚀材料反应之前利用等离子体增强光刻胶层与待刻蚀材料之间的接触，解决了由此而引发的钻刻问题，有助于提升产品良率和产品性能。
基于同样的发明构思，本公开实施例提供一种显示装置，该显示装置包括由上述任意一种的薄膜晶体管的制造方法得到的薄膜晶体管或者上述任意一种的阵列基板的制造方法得到的阵列基板。本公开实施例中的显示装置可以为：显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。例如图13所示的显示装置400，其在显示区域内包括行列设置的子像素单元Px，上述薄膜晶体管可以设置在该子像素单元Px内以实现对该子像素单元Px的显示灰阶的调节，上述阵列基板可以设置在显示装置400内部，阵列基板在每个子像素单元Px内可以包括至少一个薄膜晶体管，以实现对每个子像素单元Px的显示灰阶的调节。
可以看出，由于显示装置包括上述任意一种薄膜晶体管或上述任意一种阵列基板，而薄膜晶体管和阵列基板的制作过程中均采用上述任一种刻蚀方法进行了栅极导电层和/或源漏导电层的刻蚀，因此可以基于刻蚀方法所能取得的更优的刻蚀效果而取得更优的产品性能。
以上所述仅为本公开的实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (17)

  1. 一种刻蚀方法，包括：
    在待刻蚀材料的表面上形成经过图案化的光刻胶层，所述经过图案化的光刻胶层暴露出所述待刻蚀材料的表面上的待刻蚀区域；
    采用等离子体工艺对所述光刻胶层进行固化处理；
    采用与所述待刻蚀材料对应的刻蚀液刻蚀所述待刻蚀材料。
  2. 根据权利要求1所述的方法，所述采用等离子体工艺对所述光刻胶层进行固化处理，包括：
    采用反应离子刻蚀工艺对所述光刻胶层进行固化处理。
  3. 根据权利要求1所述的方法，所述光刻胶层的形成材料为有机高分子材料，所述等离子体工艺中使用的等离子体由四氟化碳与氧气的混合物电离产生。
  4. 根据权利要求1所述的方法，所述光刻胶层的形成材料为PR1-1000A型的正性光刻胶，所述等离子体工艺中使用的等离子体由四氟化碳与氧气的混合物电离产生。
  5. 根据权利要求1所述的方法，在采用与所述待刻蚀材料对应的刻蚀液刻蚀所述待刻蚀材料之后，所述方法还包括：
    采用能使所述光刻胶层氧化的等离子体对经过固化处理的光刻胶层进行灰化处理。
  6. 根据权利要求5所述的方法，所述采用能使所述光刻胶层氧化的等离子体对经过固化处理的光刻胶层进行灰化处理，包括：
    采用反应离子刻蚀工艺对所述光刻胶层进行灰化处理。
  7. 根据权利要求5所述的方法，所述光刻胶层的形成材料为有机高分子材料，所述能使所述光刻胶层氧化的等离子体由四氟化碳与氧气的混合物电离产生。
  8. 一种薄膜晶体管的制造方法，包括：
    在基板上形成待刻蚀的第一金属层，所述第一金属层包括导电层和位于所述导电层两侧的保护层；
    采用如权利要求1至7中任一项所述的刻蚀方法对所述第一金属层进行刻蚀，以在所述第一金属层中形成包括栅电极的图形。
  9. 根据权利要求8所述的制造方法，还包括：
    在所述第一金属层上形成第一绝缘层；
    在所述第一绝缘层上形成包括有源层的图形；
    在所述第一绝缘层和所述有源层上形成待刻蚀的第二金属层；
    采用如权利要求1至7中任一项所述的刻蚀方法对所述第二金属层进行刻蚀，以在所述第二金属层中形成包括源电极和漏电极的图形；
    在所述有源层和所述第二金属层上形成第二绝缘层。
  10. 根据权利要求8或9所述的制造方法，所述导电层的材质为铜或者含铜的合金；所述保护层的材质为钼或者含钼的合金。
  11. 一种如权利要求1-7任一项所述的制作方法所采用的工艺设备，包括：
    第一机构，用于在基板上的待刻蚀材料的表面上形成经过图案化的光刻胶层，所述经过图案化的光刻胶层暴露出所述待刻蚀材料的表面上的待刻蚀区域；
    与所述第一机构相连的第二机构，用于接收经过所述第一机构处理的基板，并采用等离子体工艺对所述光刻胶层进行固化处理；
    与所述第二机构相连的第三机构，用于接收经过所述第二机构的处理的基板，并采用与所述待刻蚀材料对应的刻蚀液刻蚀所述待刻蚀区域内的待刻蚀材料。
  12. 根据权利要求11所述的工艺设备，所述第二机构进一步用于接收经过所述第一机构处理的基板，并采用反应离子刻蚀工艺对所述光刻胶层进行固化处理。
  13. 根据权利要求11所述的工艺设备，所述光刻胶层的形成材料为有机高分子材料，所述等离子体工艺中使用的等离子体由四氟化碳与氧气的混合物电离产生。
  14. 根据权利要求11所述的工艺设备，所述工艺设备还包括：
    与所述第三机构相连的第四机构，用于接收经过所述第三机构的处理的基板，并采用能使所述光刻胶层氧化的等离子体对经过固化处理的光刻胶层进行灰化处理。
  15. 根据权利要求14所述的工艺设备，所述第四机构进一步用于接收经过所述第三机构的处理的基板，并采用反应离子刻蚀工艺对经过固化处理的光刻胶层进行灰化处理。
  16. 根据权利要求14所述的工艺设备，所述光刻胶层的形成材料为有机高分子材料，所述能使所述光刻胶层氧化的等离子体由四氟化碳与氧气的混合物电离产生。
  17. 一种显示装置，所述显示装置包括由权利要求8至10中任一项所述的制造方法得到的薄膜晶体管。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498106B1 (en) * 2001-04-30 2002-12-24 Taiwan Semiconductor Manufacturing Company Prevention of defects formed in photoresist during wet etching
CN1689142A (zh) * 2002-08-14 2005-10-26 兰姆研究有限公司 蚀刻工艺中用于硬化光致抗蚀剂的方法和组合物
CN103092009A (zh) * 2011-11-08 2013-05-08 无锡华润华晶微电子有限公司 用作等离子注入的掩蔽层的光刻胶的去除方法
CN103279015A (zh) * 2013-05-31 2013-09-04 上海华力微电子有限公司 光刻胶的处理方法以及半导体器件的制备方法
CN104681416A (zh) * 2013-11-27 2015-06-03 中芯国际集成电路制造(上海)有限公司 半导体器件和栅极的形成方法
CN107564803A (zh) * 2017-08-31 2018-01-09 京东方科技集团股份有限公司 刻蚀方法、工艺设备、薄膜晶体管器件及其制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115449B2 (en) * 2003-06-24 2006-10-03 National Chiao Tung University Method for fabrication of polycrystalline silicon thin film transistors
CN100483261C (zh) * 2006-08-10 2009-04-29 中芯国际集成电路制造(上海)有限公司 光刻图形的形成方法
CN100517605C (zh) * 2006-12-15 2009-07-22 中芯国际集成电路制造(上海)有限公司 镶嵌结构的制造方法
KR20150015978A (ko) * 2013-08-02 2015-02-11 삼성디스플레이 주식회사 표시 장치의 방법
CN104851910A (zh) * 2015-04-13 2015-08-19 京东方科技集团股份有限公司 薄膜晶体管、阵列基板、制备方法、显示面板和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498106B1 (en) * 2001-04-30 2002-12-24 Taiwan Semiconductor Manufacturing Company Prevention of defects formed in photoresist during wet etching
CN1689142A (zh) * 2002-08-14 2005-10-26 兰姆研究有限公司 蚀刻工艺中用于硬化光致抗蚀剂的方法和组合物
CN103092009A (zh) * 2011-11-08 2013-05-08 无锡华润华晶微电子有限公司 用作等离子注入的掩蔽层的光刻胶的去除方法
CN103279015A (zh) * 2013-05-31 2013-09-04 上海华力微电子有限公司 光刻胶的处理方法以及半导体器件的制备方法
CN104681416A (zh) * 2013-11-27 2015-06-03 中芯国际集成电路制造(上海)有限公司 半导体器件和栅极的形成方法
CN107564803A (zh) * 2017-08-31 2018-01-09 京东方科技集团股份有限公司 刻蚀方法、工艺设备、薄膜晶体管器件及其制造方法

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