CN106887436B - 薄膜晶体管阵列基板及其制备方法 - Google Patents

薄膜晶体管阵列基板及其制备方法 Download PDF

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CN106887436B
CN106887436B CN201610749723.0A CN201610749723A CN106887436B CN 106887436 B CN106887436 B CN 106887436B CN 201610749723 A CN201610749723 A CN 201610749723A CN 106887436 B CN106887436 B CN 106887436B
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sublayer
thin
film transistor
layer
array base
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CN106887436A (zh
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高逸群
施博理
张炜炽
吴逸蔚
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Abstract

一种薄膜晶体管阵列基板，其包括绝缘基板、形成于绝缘基板上的半导体层及形成于半导体层上的第二导电层，所述第二导电层形成间隔设置的源极与漏极，所述第二导电层至少包括：第一子层，其形成于半导体层上，其材质为金属氧化物；第二子层，其形成于第一子层上，其材质为铝或铝合金。本发明还提供该种薄膜晶体管阵列基板的制备方法。所述第一子层可作为所述半导体层与第二子层之间的欧姆接触层；另外还避免使用铜作为第二子层。

Description

薄膜晶体管阵列基板及其制备方法
技术领域
本发明涉及一种薄膜晶体管阵列基板以及薄膜晶体管阵列基板的制备方法。
背景技术
现有的平面显示装置通常包括：作为开关元件的薄膜晶体管、传导扫描信号以控制薄膜晶体管的扫描线、传导信号给像素电极的数据线等。薄膜晶体管的性能对平面显示装置有重要影响。
发明内容
鉴于以上内容，有必要提供一种性能良好的薄膜晶体管阵列基板及其制备方法。
一种薄膜晶体管阵列基板，其包括绝缘基板、形成于绝缘基板上的半导体层及形成于半导体层上的第二导电层，所述第二导电层形成间隔设置的源极与漏极，所述第二导电层至少包括：
第一子层，其形成于半导体层上，其材质为金属氧化物；
第二子层，其形成于第一子层上，其材质为铝或铝合金。
一种薄膜晶体管阵列基板的制备方法：
提供一绝缘基板，在所述绝缘基板上形成一半导体层；
在半导体层上形成一第一子层，第一子层的材质为金属氧化物；
在第一子层上形成一第二子层，第二子层的材质为铝或铝合金；
对所述第一子层及所述第二子层进行蚀刻形成一沟道贯穿所述第一子层及所述第二子层，从而使第一子层与第二子层配合形成通过沟道得以间隔设置的源极与漏极。
一种薄膜晶体管阵列基板的制备方法：
提供一绝缘基板，在所述绝缘基板上形成一半导体层；
在半导体层上形成一第一子层，第一子层的材质为金属氧化物；
在第一子层上形成一第二子层，第二子层的材质为铝或铝合金；
在第二子层上形成一第三子层，所述第三子层的材质为金属氧化物；
对所述第一子层、所述第二子层及所述第三子层进行蚀刻形成一沟道贯穿所述第一子层、所述第二子层及所述第三子层，从而使第一子层、第二子层与第三子层配合形成通过沟道得以间隔设置的源极与漏极。
所述薄膜晶体管阵列基板，其包括至少二层结构的第二导电层，所述第二导电层至少包括金属氧化物材质的第一子层，铝或铝合金材质的第二子层，所述第一子层可作为所述半导体层与第二子层之间的欧姆接触层；且蚀刻所述第二导电层形成沟道时，有利于使沟道的尺寸逐渐变小；另外还可避免使用铜作为第二子层，进而此外避免铜原子扩散污染薄膜晶体管阵列基板的其他层。
附图说明
图1是本发明一较佳实施例的薄膜晶体管阵列基板的平面俯视示意图。
图2是图1的薄膜晶体管阵列基板的剖面示意图。
主要元件符号说明
薄膜晶体管阵列基板 100
绝缘基板 110
扫描线 121
栅极 101
栅极绝缘层 102
半导体层 103
数据线 104
源极 105
漏极 106
钝化层 107
第一钝化层 107a
第二钝化层 107b
第一子层 104a、105a、106a
第二子层 104b、105b、106b
第三子层 104c、105c、106c
像素电极 108
接触孔 185
沟道 120
侧壁 122
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
请一并参阅图1及图2，本发明具体实施方式提供一种薄膜晶体管阵列基板100。所述薄膜晶体管阵列基板100包括一绝缘基板110、形成于所述绝缘基板110上的第一导电层，第一导电层定义形成为多条扫描线121及与扫描线121连接的多个栅极101。图1-2仅呈现一个栅极101、两条扫描线121。
本实施例中，所述绝缘基板110的材质为透明的玻璃、透明的石英、或透明的塑料。在其他的实施例中，所述绝缘基板110的材质可为陶瓷或硅。在其他的实施例中，所述绝缘基板110可以为一柔性材料制成。适合制作所述绝缘基板110的柔性材料可选自聚醚砜（PES)、聚萘二甲酸乙二酯（PEN）、聚乙烯（PE）、聚酰亚胺（PI）、聚氯乙烯（PVC）、聚对苯二甲酸乙二醇酯（PET）中的一种或一种以上。
每条扫描线121用以传递扫描信号并沿图1中的横向方向延伸。所述第一导电层（即所述扫描线121与所述栅极101上）的材料可选自铝(Al)、银(Ag)、金(Au)、钴(Co)、铬(Cr)、铜(Cu)、铟(In)、锰(Mn)、钼(Mo)、镍(镍)、钕(Nd)、(pd)钯、铂(Pt)、钛(Ti)、钨(W)、和锌(Zn)中的至少一种。在其他实施例中，所述扫描线121与所述栅极101的材料可为透明导电材料，如选自氧化铟锡(ITO)、氧化铟锌(IZO)、和掺铝氧化锌(AZO)中的一种或一种以上。
所述薄膜晶体管阵列基板100还包括形成在所述第一导电层（即所述扫描线121与所述栅极101上）的一栅极绝缘层102。该栅极绝缘层102的材质为电绝缘材料，该电绝缘材料可选自氧化硅(SiOx)、氮化硅(SiNx)、氧氮化硅(SiOxNy)、氧化铝(AlOx)、氧化钇(Y2O3)、氧化铪(HfOx)、氧化锆(ZrOx)、氮化铝(AlN)、铝氮氧化物(AINO)、氧化钛(TiOx)、钛酸钡(BaTiO3)、钛酸铅(PbTiO3)中的一种或一种以上。
本实施例中，所述栅极绝缘层102可为单层结构，但不限于单层结构。在其他的实施中，所述栅极绝缘层102可为双层或双层以上的结构。
所述薄膜晶体管阵列基板100还包括形成在所述栅极绝缘层102上的一半导体层103。该半导体层103包含合适的半导体材料，如氧化物、单质半导体、化合物半导体、和合金半导体材料中的至少一种，所述氧化物半导体、单质半导体、化合物半导体、和合金半导体材料呈非晶状、晶体状、或多晶状。本实施例中，该半导体层103包含锌、铟、锡、镓、铪中的至少一种的金属氧化物，如铟-镓-锌氧化物（IGZO）、铟-锌-锡氧化物（IZTO）、铟-镓-锡氧化物（IGTO）和铟-铝-锌氧化物（IAZO）。
所述薄膜晶体管阵列基板100还包括形成在所述栅极绝缘层102及所述半导体层103上的第二导电层，所述第二导电层定义形成为多条数据线104、多个源极105、及多个漏极106。所述数据线104连接所述源极105，所述源极105与所述漏极106间隔设置。图1-2仅呈现一个源极105、一个漏极106、及两条数据线104。
每条数据线104用以传递数据信号并沿图1中的纵向方向延伸从而与所述扫描线121绝缘相交。所述源极105由一数据线104延伸形成。
所述第二导电层为多层结构，优选地，每一条数据线104、每一个源极105、每一个漏极106均为多层结构。本实施例为三层结构，每一条数据线104、每一个源极105、每一个漏极106均为三层结构。每一条数据线104可包括一第一子层104a、一第二子层104b及一第三子层104c。每一个源极105可包括一第一子层105a、一第二子层105b及一第三子层105c，且所述第一子层105a、所述第二子层105b及所述第三子层105c依次层叠于所述半导体层103上。每一个漏极106可包括一第一子层106a、一第二子层106b及一第三子层106c，且所述第一子层106a、所述第二子层106b及所述第三子层106c依次层叠于所述半导体层103上。
所述第一子层104a、第一子层105a、及第一子层106a的材质为金属氧化物导电材料。所述第二子层104b、第二子层105b及第二子层106b的材质为导电金属材料，具体为铝或铝合金。所述第三子层104c、第三子层105c及第三子层106c的材质与所述第一子层104a、第一子层105a、及第一子层106a的材质相同，也为金属氧化物导电材料。
如，所述第一子层104a、第一子层105a、及第一子层106a的材质可选自铟-锌氧化物、铟-锌氧化物、铝-锌氧化物中的至少一种。所述第三子层104c、第三子层105c及第三子层106c的材质可选自铟-锌氧化物、铟-锌氧化物、铝-锌氧化物中的至少一种。
每对源极105与漏极106之间形成有一沟道120，沟道120使得源极105与漏极106得以间隔不连通。所述沟道120通过干法蚀刻多层结构的第二导电层得以形成，所述沟道120贯穿第三子层、第二子层及第一子层。
所述第三子层与所述第一子层的材质相同，均为含锌的金属氧化物，但二者中锌的含量不同（第三子层的锌含量高于第一子层的锌含量），导致所述第三子层的蚀刻速率大于第一子层的蚀刻速率。同时铝或铝合金材质的第二子层的蚀刻速率大于金属氧化物材质的第一子层的蚀刻速率。另外，所述第三子层的蚀刻速率大于第二子层的蚀刻速率，而第二子层的蚀刻速率大于第一子层的蚀刻速率，使得蚀刻形成的所述沟道120，且所述沟道120的侧壁122相对所述所述半导体层103倾斜，沿第三子层指向第一子层的方向，沟道120的尺寸逐渐变小。本发明蚀刻速率的大小比较均为使用相同蚀刻液或蚀刻气体的情况下进行的比较。
所述第一子层105a可作为所述半导体层103与第二子层105b之间的欧姆接触层；所述第一子层106a可作为所述半导体层103与第二子层106b之间的欧姆接触层。
所述第二子层104b、第二子层105b及第二子层106b采用铝或铝合金制成，有利于蚀刻形成沟道120并使沟道120的尺寸逐渐变小；且蚀刻形成沟道120可采用湿法蚀刻或是干法蚀刻；另外还可避免使用铜作为第二子层，进而此外避免铜原子扩散污染薄膜晶体管阵列基板100的其他层。
可以理解的，在其他的实施例中，所述第三子层104c、第三子层105c及第三子层106c还可省略去除，即每一条数据线104、每一个源极105、每一个漏极106均包括双层结构。每一条数据线104可包括一第一子层104a及一第二子层104b。每一个源极105可包括一第一子层105a及一第二子层105b。每一个漏极106可包括一第一子层106a及一第二子层106b。此种情况下，所述沟道120贯穿第二子层及第一子层，沿第二子层指向第一子层的方向，沟道120的尺寸逐渐变小。
所述的一个栅极101、一个源极105、一个漏极106、及一个半导体层103配合构成一个薄膜晶体管。另外，所述半导体层103位于源极105与漏极106之间的区域形成为薄膜晶体管的通道区域。
所述薄膜晶体管阵列基板100还包括一钝化层107。所述钝化层107覆盖所述源极105、所述漏极106、所述数据线104及所述半导体层103。所述钝化层107的材质可为无机绝缘材料、有机绝缘材料。无机绝缘材料可为氮化硅或氧化硅。有机绝缘材料可为聚酰亚胺、聚酰胺、丙烯酸（类）树脂、环氧树脂、环烯烃树脂或苯并环丁烯。
在本实施例中，所述钝化层107包括层叠设置的一第一钝化层107a和一第二钝化层107b。本实施例中，所述第一钝化层107a的材质为氧化硅，而所述第二钝化层107b的材质为氮化硅。
所述钝化层107还开设有贯穿钝化层107的多个接触孔185。每一个接触孔185对应一个漏极106设置，使漏极106的一端得以露出。图2仅示出一个接触孔185及一个漏极106。
所述薄膜晶体管阵列基板100还包括形成在所述钝化层107上的多个像素电极108（图2仅示出一个像素电极108）。所述像素电极108延伸到接触孔185中与所述漏极106电性连接，从而接收漏极106的数据电压。
所述像素电极108的材质可为透明导电材料或反射性导电材料。所述透明导电材料，如可选自氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌铝(AZO)、氧化锡镉（CTO）中的一种或一种以上。所述反射性导电材料，如可选自铝、金、银、铜、鉄、钛、钽、钼、铷、钨中的一种或一种以上。另外，所述像素电极108的材质还可为上述透明导电材料与上述反射性导电材料的混合物。在其他的实施例中，像素电极108可为有机发光二极管的电极。
一种薄膜晶体管阵列基板100的制备方法：
提供一绝缘基板110，在所述绝缘基板110上形成一栅极101；
在所述绝缘基板110上形成一栅极绝缘层102覆盖所述栅极101；
在所述栅极绝缘层102上形成一半导体层；
在半导体层上形成一第一子层，第一子层的材质为金属氧化物；
在第一子层上形成一第二子层，第二子层的材质为铝或铝合金；
在第二子层上形成一第三子层，所述第三子层的材质为金属氧化物；
对所述第一子层、所述第二子层及所述第三子层进行蚀刻形成一沟道贯穿所述第一子层、所述第二子层及所述第三子层，从而使第一子层、第二子层与第三子层配合形成通过沟道得以间隔设置的源极与漏极；
形成一钝化层107覆盖所述源极105、所述漏极106、所述半导体层103；
在所述钝化层107还开设贯穿钝化层107的接触孔185，每一个接触孔185对应一个漏极106设置；
在所述钝化层107上形成像素电极108，所述像素电极108延伸到接触孔185中与所述漏极106电性连接。
以上实施方式仅用以说明本发明的技术方案而非限制，尽管参照较佳实施方式对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或等同替换，而不脱离本发明技术方案的精神和范围。

Claims (6)

1.一种薄膜晶体管阵列基板，其包括绝缘基板、形成于绝缘基板上的半导体层及形成于半导体层上的第二导电层，所述第二导电层形成间隔设置的源极与漏极，其特征在于：第二导电层至少包括：
第一子层，其形成于半导体层上，其材质为金属氧化物；
第二子层，其形成于第一子层上，其材质为铝或铝合金；以及
第三子层，形成于第二子层上，其材质为金属氧化物；
所述第一子层和第三子层的材质均为含锌的金属氧化物导电材料，且第三子层的锌含量高于第一子层的锌含量。
2.如权利要求1所述的薄膜晶体管阵列基板，其特征在于：所述源极与漏极之间形成有一贯穿所述第一子层、第二子层与第三子层的沟道，沿第三子层指向第一子层的方向，所述沟道的尺寸逐渐变小。
3.如权利要求1所述的薄膜晶体管阵列基板，其特征在于：所述薄膜晶体管阵列基板还包括绝缘基板、形成于绝缘基板上的栅极、形成于绝缘基板上且覆盖栅极的栅极绝缘层；所述半导体层形成于所述栅极绝缘层上。
4.如权利要求1所述的薄膜晶体管阵列基板，其特征在于：所述薄膜晶体管阵列基板还包括一钝化层覆盖所述半导体层及所述第二导电层、形成在所述钝化层上的多个像素电极，像素电极与所述漏极电性连接。
5.一种薄膜晶体管阵列基板的制备方法：
提供一绝缘基板，在所述绝缘基板上形成一半导体层；
在半导体层上形成一第一子层，第一子层的材质为金属氧化物；
在第一子层上形成一第二子层，第二子层的材质为铝或铝合金；
在第二子层上形成一第三子层，所述第三子层的材质为金属氧化物；
对所述第一子层、所述第二子层及所述第三子层进行蚀刻形成一沟道贯穿所述第一子层、所述第二子层及所述第三子层，从而使第一子层、第二子层与第三子层配合形成通过沟道得以间隔设置的源极与漏极；
其中所述第一子层和第三子层的材质均为含锌的金属氧化物导电材料，且第三子层的锌含量高于第一子层的锌含量。
6.如权利要求5所述的薄膜晶体管阵列基板的制备方法，其特征在于：沿第三子层指向第一子层的方向，所述沟道的尺寸逐渐变小。
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