WO2019205922A1 - 阵列基板及其制造方法、显示面板、电子装置 - Google Patents

阵列基板及其制造方法、显示面板、电子装置 Download PDF

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Publication number
WO2019205922A1
WO2019205922A1 PCT/CN2019/081773 CN2019081773W WO2019205922A1 WO 2019205922 A1 WO2019205922 A1 WO 2019205922A1 CN 2019081773 W CN2019081773 W CN 2019081773W WO 2019205922 A1 WO2019205922 A1 WO 2019205922A1
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Prior art keywords
electrode
thin film
film transistor
forming
display
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PCT/CN2019/081773
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English (en)
French (fr)
Inventor
刘鹏
李付强
樊君
刘白灵
张建军
刘雨生
李梅
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US16/605,588 priority Critical patent/US11469254B2/en
Publication of WO2019205922A1 publication Critical patent/WO2019205922A1/zh

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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Definitions

  • Embodiments of the present disclosure relate to an array substrate, a method of fabricating the same, a display panel, and an electronic device.
  • the thin film transistor includes, for example, a structure such as a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode.
  • Thin film transistors are widely used as pixel switching elements or driving circuit elements in various display devices such as liquid crystal displays, organic light emitting diode displays, electronic paper displays, and the like.
  • a pixel array of a display device is typically formed by a plurality of rows of gate lines and a plurality of columns of data lines interleaved therewith.
  • the thin film transistor is used as a switching element. Under the control of the gate, an external data signal can be written to the pixel electrode in the sub-pixel unit through the thin film transistor, thereby realizing charging and discharging of the sub-pixel unit.
  • the driving of the gate lines can be realized by an integrated driving circuit (IC chip) bonded on the array substrate.
  • the gate driving circuit can be directly prepared and integrated on the array substrate to form a GOA (Gate driver On Array) gate driving circuit to The line is driven.
  • GOA Gate driver On Array
  • a GOA gate driving circuit composed of a plurality of cascaded shift register units may be employed to provide a switching state voltage signal for a plurality of rows of gate lines of the pixel array, for example, to control the plurality of rows of gate lines to be sequentially turned on.
  • GOA technology helps to achieve a narrow bezel of the display device and can reduce production costs.
  • At least one embodiment of the present disclosure provides an array substrate including a display area and a peripheral area, the display area including a pixel area, the pixel area including a first thin film transistor, and the first thin film transistor includes a first a source layer; the peripheral region includes a second thin film transistor, the second thin film transistor includes a second active layer, a material of the first active layer includes an oxide semiconductor, and a material of the second active layer includes Polysilicon semiconductor.
  • the array substrate further includes a base substrate and an interlayer insulating layer on the base substrate, a first gate of the first thin film transistor and the first The active layer is located on a side of the interlayer insulating layer away from the substrate, and the second gate and the second active layer of the second thin film transistor are both located in the interlayer insulating layer. Near one side of the substrate.
  • the array substrate further includes a first passivation layer on a side of the interlayer insulating layer away from the substrate substrate and a first passivation layer a second passivation layer away from a side of the base substrate, the pixel region further comprising a first display electrode and a second display electrode, the first display electrode being located away from the lining of the first passivation layer One side of the base substrate, and the second passivation layer covers the first display electrode; the second display electrode is located on a side of the second passivation layer away from the base substrate, and passes through A first via in the first passivation layer and the second passivation layer is electrically connected to a first source drain of the first thin film transistor.
  • the display area further includes a touch lead, and the touch lead and the first source drain and the second source drain of the first thin film transistor or The first source drain and the second source drain of the second thin film transistor are located in the same layer, and the touch lead is electrically connected to the first display electrode.
  • the display area further includes a first connection electrode, the first connection electrode and the second display electrode are in the same layer, and the first connection electrode passes through the A second via in the first passivation layer and the second passivation layer and a third via in the second passivation layer electrically connect the touch lead to the first display electrode.
  • the first connection electrode and the second display electrode are insulated from each other.
  • the peripheral region includes at least a GOA gate driving circuit
  • the GOA gate driving circuit includes the second thin film transistor, and a second source of the second thin film transistor
  • the drain is electrically connected to the first gate of the first thin film transistor through a gate line, and the first source drain and the second source drain of the second thin film transistor and the first gate of the first thin film transistor Located in the same layer; the gate line is in the same layer as the second gate of the second thin film transistor.
  • the gate line and the second gate are insulated from each other.
  • the peripheral region further includes a connection region including a first electrode, a second electrode, and a second connection electrode, the first electrode and the first electrode a first source drain and a second source drain of the thin film transistor are in the same layer; the second electrode is in the same layer as the first source drain and the second source drain of the second thin film transistor; and the second connection electrode The same layer as the second display electrode, and the second connection electrode passes the first electrode through the fourth via hole and the fifth via hole in the first passivation layer and the second passivation layer Electrically connected to the second electrode.
  • the peripheral region further includes a bonding region including a fourth electrode, a fifth electrode, and a third connecting electrode, the fourth electrode and the fourth electrode a first source drain and a second source drain of the second thin film transistor are in the same layer; the fifth electrode is in the same layer as the second gate of the second thin film transistor; the third connection electrode and the second The display electrode is in the same layer, and the fourth electrode, the fifth electrode, and the third connection electrode are electrically connected to each other.
  • the array substrate further includes a first passivation layer on a side of the interlayer insulating layer away from the substrate substrate and a first passivation layer a second passivation layer away from the side of the base substrate, the pixel region further comprising a first display electrode and a second display electrode, the second display electrode being located away from the lining of the first passivation layer One side of the base substrate, and the second passivation layer covers the second display electrode; the first display electrode is located on a side of the second passivation layer away from the base substrate;
  • the substrate further includes a fourth connection electrode, the fourth connection electrode is disposed in the same layer as the first display electrode and insulated from each other; and the second display electrode and the first source and drain of the first thin film transistor pass through The fourth connecting electrode is electrically connected.
  • At least one embodiment of the present disclosure also provides a display panel including any of the array substrates described above.
  • At least one embodiment of the present disclosure also provides an electronic device including any of the above display panels.
  • At least one embodiment of the present disclosure further provides a method of fabricating an array substrate, the array substrate including a display area and a peripheral area, the display area including a pixel area, the method comprising: forming a first thin film transistor in the pixel area Forming the first thin film transistor includes forming a first active layer; forming a second thin film transistor in the peripheral region, and forming the second thin film transistor includes forming a second active layer, the first active layer
  • the material includes an oxide semiconductor, and the material of the second active layer includes a polysilicon semiconductor.
  • the peripheral region includes at least a GOA gate driving circuit
  • the GOA gate driving circuit includes the second thin film transistor
  • the method further includes: Conducting a thin film to form a gate line and a second gate of the second thin film transistor; and patterning the second conductive film to form a first source drain and a second source and drain of the second thin film transistor And a first gate of the first thin film transistor, a second source drain of the second thin film transistor and a first gate of the first thin film transistor are electrically connected through the gate line.
  • the method further includes: forming a touch lead in the display area, forming a first source drain of the first thin film transistor by patterning the third conductive film a second source drain, and forming the touch lead while forming the first source drain and the second source drain of the first thin film transistor; or forming a first source drain of the second thin film transistor
  • the touch lead is formed simultaneously with the second source and the drain.
  • the array substrate further includes a base substrate, the method further comprising: sequentially forming a first passivation layer and a second passivation layer on the base substrate, And covering the first thin film transistor and the second thin film transistor; forming a first display electrode between the first passivation layer and the second passivation layer in the pixel region; forming the first After the second passivation layer, a first via is formed by an etching process to expose the first source and drain of the first thin film transistor, a second via is formed to expose the touch lead, and a third via is formed.
  • first display electrode Exposing the first display electrode; forming a fourth conductive film and patterning it to form a second display electrode and a first connection electrode; the second display electrode and the first connection electrode are insulated from each other, the first The second display electrode is electrically connected to the first source and drain of the first thin film transistor through the first via hole, and the first connection electrode passes through the second via hole and the third via hole respectively The touch lead and the first display electrode are electrically connected
  • the method further includes forming a first electrode and a second electrode in a connection region of the peripheral region; forming a first source drain and a first portion of the first thin film transistor Forming the first electrode simultaneously with the two source drains, forming the second electrode while forming the first source drain and the second source drain of the second thin film transistor; forming the first via, Forming a fourth via hole simultaneously with the second via hole to expose the second electrode, and forming a fifth via hole to expose the first electrode; and forming the second display
  • the second connection electrode is simultaneously formed by the electrode, and the second connection electrode electrically connects the first electrode and the second electrode through the fourth via hole and the fifth via hole.
  • the method further includes forming a fourth electrode and a fifth electrode in a bonding region of the peripheral region, forming a first source drain of the second thin film transistor and Forming the fourth electrode simultaneously with the second source drain; forming the fifth electrode while forming the second gate of the second thin film transistor; forming the first via, the second via Forming a sixth via hole simultaneously with the third via hole, the fourth via hole, and the fifth via hole to expose at least one of the fourth electrode and the fifth electrode; and forming the The third display electrode is simultaneously formed with the second display electrode; the fourth electrode, the fifth electrode, and the third connection electrode are electrically connected to each other.
  • the first via, the second via, the third via, the fourth via, the fifth via, and the The sixth via is formed using the same mask.
  • 1A is a schematic plan view showing a planar structure of an array substrate according to an embodiment of the present disclosure
  • Figure 1B is a cross-sectional structural view taken along line A-A' in Figure 1A;
  • FIG. 1C is a schematic cross-sectional view of another embodiment of the present disclosure.
  • FIG. 2 is a circuit structural diagram of a GOA gate driving circuit
  • FIG. 3 is a partial cross-sectional structural view of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a partial cross-sectional structural view of an array substrate according to another embodiment of the present disclosure.
  • 5A is a schematic plan view showing a planar structure of an array substrate according to another embodiment of the present disclosure (the left side is a schematic view of the area, and the right side is a top view of a part of the structure in the array substrate);
  • FIG. 5B is a schematic diagram of a planar structure of an array substrate according to an embodiment of the present disclosure (the left side is a schematic view of the area, and the right side is a top view of a part of the structure in the array substrate);
  • 6A-6G are schematic cross-sectional views of an array substrate according to another embodiment of the present disclosure during a manufacturing process.
  • Thin film transistors are one of the core components in display panels, and their performance greatly affects the display quality of display panels.
  • the thin film transistor generally includes a structure such as a gate, a source, a drain, a gate insulating layer, and an active layer. According to the material type of the active layer of the thin film transistor, the thin film transistor can be classified into an amorphous silicon thin film transistor, a polycrystalline silicon thin film transistor (for example, a low temperature polysilicon thin film transistor, a high temperature polysilicon thin film transistor, etc.), an oxide thin film transistor, or the like.
  • amorphous silicon thin film transistor Although the electrical uniformity of amorphous silicon thin film transistor is better, its mobility is low and its stability is poor. Low-temperature polysilicon thin film transistor has low mobility and good stability, but its electrical uniformity is poor and off-state leakage current Larger, it is easy to cause defects such as flicker (Flicker), and the power consumption of the display panel is large, making it difficult to achieve a high refresh rate. Compared with amorphous silicon thin film transistors and low temperature polysilicon thin film transistors, oxide thin film transistors have higher mobility, better stability and better electrical uniformity, and are easier to realize high refresh frequency and large size display panels. Good application prospects.
  • a low-temperature polysilicon thin film transistor is currently generally used.
  • the "grain boundary" provides a leakage path for the low temperature polysilicon thin film transistor.
  • the low temperature polysilicon thin film transistor generates an undesired off-state leakage current, the contrast of the display device including the array substrate of the low temperature polysilicon thin film transistor is generally lowered. And the display quality of the display device is low.
  • At least one embodiment of the present disclosure provides an array substrate including a display area including a pixel area, a pixel area including a first thin film transistor, a first thin film transistor including a first active layer, and a peripheral area including The second thin film transistor includes a second active layer, and the material of the second active layer is different from the material of the first active layer.
  • thin film transistors of different material types are disposed in the display region and the peripheral region of the array substrate.
  • the first thin film transistor of the display region may be an oxide thin film transistor
  • the second thin film transistor of the peripheral region may be a polysilicon thin film transistor, as needed.
  • the array substrate of the embodiment of the present disclosure can be used for a horizontal electric field type liquid crystal display device, a vertical electric field type liquid crystal display device, and can also be used for, for example, an organic light emitting diode display device, an electronic paper display device, or the like.
  • the oxide thin film transistor has the characteristics of high mobility, good stability, good electrical uniformity, and low off-state leakage current
  • the first thin film transistor using an oxide semiconductor material as an active layer is disposed in the display region of the array substrate.
  • the contrast of the display area in the display device including the array substrate can be improved, the power of the display device can be reduced, and the display image quality of the display device can be improved.
  • the polysilicon thin film transistor has high mobility and good stability, when the driving circuit in the peripheral region of the array substrate uses polysilicon as the second thin film transistor of the active layer, compared to, for example, an amorphous silicon thin film transistor, Has a higher drive capacity and refresh rate.
  • embodiments of the present disclosure can make full use of the excellent characteristics of different types of thin film transistors in one array substrate to achieve higher refresh frequency, larger size display panel, better and more stable driving effect and display effect.
  • FIG. 1A is a schematic plan view of the array substrate
  • FIG. 1B is a cross-sectional structural view taken along line A-A' of FIG. 1A.
  • the array substrate 100 may be an array substrate for a liquid crystal display device, specifically an array substrate of a horizontal electric field type liquid crystal display device.
  • the embodiment of the present disclosure is described as an example, but is not limited thereto.
  • the array substrate 100 includes a display area D1 and a peripheral area D2.
  • the display area D1 includes a pixel area corresponding to the sub-pixel unit and other components such as the gate line 105A, the data line 105B, the touch lead 106, and the like, and the pixel area includes the first thin film transistor 104.
  • the peripheral region D2 includes a second thin film transistor 103 corresponding to a driving circuit.
  • the material of the active layer of the first thin film transistor 104 is different from the material of the active layer of the second thin film transistor 103.
  • the peripheral region D2 includes a GOA type gate driving circuit including a plurality of cascaded GOA shift register units, each of the GOA shift register units typically including a plurality of thin film transistors and capacitors, each The output of the shift register unit outputs a scan signal.
  • the second thin film transistor 103 can be an output transistor of the signal output of the GOA gate drive circuit.
  • each GOA shift register unit is connected to a gate line 105A in the display area to supply a gate scan signal to the gate line 105A at a predetermined timing.
  • the input signal of the GOA gate driving circuit includes a clock signal, an on signal STV (ie, a shift trigger signal SR_IN), a high level signal VGH, and a low level signal VGL.
  • the clock signal may include a first clock signal CLK1 and a second clock signal CLK2 as needed to provide a clock signal to a sub-circuit of the GOA gate drive circuit.
  • the clock signal is not limited to two, and may be one or more.
  • the high level signal VGH and the low level signal VGL are used to provide a constant voltage signal for the GOA type gate driving circuit and the sub-pixels of the array substrate.
  • a high level signal VGH and a low level signal VGL may be required, and a plurality of high level signals VGH and a plurality of low level signals VGL may be required, which is not limited by the embodiment of the present disclosure. .
  • FIG. 2 is a partial circuit configuration diagram of the array substrate 100.
  • the circuit 10 includes a GOA gate driving circuit 11 and a sub-pixel circuit 12.
  • a plurality of gate lines 105A and a plurality of data lines 105B are arranged in an array and cross-defining a plurality of sub-pixel units, each of the sub-pixel units generally including at least one first thin film transistor 104 and a liquid crystal capacitor C2.
  • the first thin film transistor 104 serves as a switching element, which is respectively connected to the gate line 105A, the data line 105B, and the pixel electrode 107.
  • the pixel electrode 107 and the common electrode 109 respectively serve as two electrodes of the liquid crystal capacitor C2, and the first thin film transistor 104 receives the gate line 105A.
  • the control of the upper gate scan signal applies a data signal on the data line 105B to the liquid crystal capacitor C2 to be charged, thereby controlling the deflection of the liquid crystal molecules.
  • the shift register unit of the GOA gate driving circuit 11 corresponding to the nth row (n is greater than or equal to 2) sub-pixel unit includes a first transistor T1, a second transistor T2, a third transistor T3, and a Four transistors T4 and storage capacitor C1.
  • the first transistor T1 in the shift register unit is an output transistor of the signal output terminal of the shift register unit, that is, the second thin film transistor 103 in the peripheral region D2 shown in FIG. 1B.
  • the first electrode of the first transistor T1 is connected to the first clock signal CLK1
  • the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2 to obtain the output of the shift register unit, and can be output for
  • the gate scan signal Gn is a square wave pulse signal, and accordingly the pulse portion is turned on, and the pulse portion is turned off.
  • the gate of the first transistor T1 is connected to the pull-up node PU, thereby connecting the first pole of the third transistor T3 and the second pole of the fourth transistor T4.
  • the second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3 and the low level signal VGL.
  • the gate of the second transistor T2 is connected to the gate of the third transistor T3 and the output of the next row, that is, the shift register unit of the n+1th row, to receive the gate scan signal G(n+1) as an output pull-down control. signal.
  • the first pole of the second transistor T2 is connected to the second pole of the first transistor T1, and thus can be turned on under the control of the pull-down control signal, and pulls the output signal of the output terminal to the low-level signal when the gate scan signal Gn is not required to be output. VGL.
  • the first pole of the third transistor T3 is also connected to the pull-up node PU, thereby being electrically connected to the second pole of the fourth transistor T4 and the gate of the first transistor T1.
  • the second electrode of the third transistor T3 is connected to the low level signal VGL.
  • the gate of the third transistor T3 is also connected to the output of the shift register unit of the next row, that is, the n+1th row, to receive the gate scan signal G(n+1) as a reset control signal (which is also an output pull-down control).
  • the signal can be turned on under the control of the reset control signal to reset the pull-up node PU to the low level signal VGL, thereby turning off the first transistor T1.
  • the first transistor of the fourth transistor T4 is connected to the self gate thereof, and is connected to the output terminal of the shift register unit of the upper row, that is, the n-1th row to receive the gate scan signal G(n-1) as an input signal ( Input control signal), the second pole of the fourth transistor T4 is connected to the pull-up node PU, so that the pull-up node PU can be charged when the fourth transistor T4 is turned on, so that the voltage of the pull-up node PU can be the first transistor T1 is turned on, so that the first clock signal CLK1 is output through the output terminal.
  • One end of the storage capacitor C1 is connected to the gate of the first transistor T1, that is, the pull-up node PU, and the other end is connected to the second pole of the first transistor T1, so that the level of the pull-up node PU can be stored, and can be guided in the first transistor T1.
  • the output of the pull-up node PU is continuously pulled up by the bootstrap effect of the output to improve the output performance.
  • the gate driving circuit When the gate driving circuit is in operation, when the gate scanning signal G(n-1) is at a high level, the fourth transistor T4 is turned on and charges the pull-up node PU, and the level of the pull-up node PU is raised to make the first
  • the transistor T1 is turned on, so the first clock signal CLK1 can be outputted at the output through the first transistor T1, that is, the gate scan signal Gn is equal to the first clock signal CLK1.
  • the gate scan signal Gn When the first clock signal CLK1 is at a high level, the gate scan signal Gn also outputs a high level.
  • the shift register unit of the GOA gate drive circuit 11 inputs the high level signal Gn to the gate line 105A of the corresponding row of the array substrate so that the row gate line 105A corresponds to all
  • the first gate 1041 of the first thin film transistor 104 in the sub-pixel unit is applied with the signal such that the first thin film transistors are turned on, and the data signal is input to the corresponding sub-pixel through the first thin film transistor 104 in each sub-pixel.
  • the liquid crystal capacitor C2 of the pixel unit charges the liquid crystal capacitor C2 in the corresponding sub-pixel unit, thereby realizing writing and holding of the signal voltage of the sub-pixel unit.
  • the progressive scan driving function for the array substrate 100 can be realized by the GOA gate driving circuit 11, for example.
  • the source and the drain of each of the above transistors are symmetrical, the source and the drain thereof can be interchanged.
  • the first pole can be, for example, a source or a drain
  • the second pole can be, for example, a drain or a source.
  • the source and drain of the thin film transistor are collectively referred to as "source drain" in the present disclosure, and are distinguished by a first source drain and a second source drain.
  • each of the above transistors may be an N-type transistor.
  • each of the above transistors is not limited to an N-type transistor, and may be at least partially a P-type transistor, whereby the polarity of the corresponding turn-on signal STV and the output scan signal may be changed accordingly.
  • the structure of the shift register unit of the GOA gate driving circuit 11 is not limited to the above-described structure, and the shift register unit of the GOA gate driving circuit 11 may be any applicable.
  • the structure may also include more or less transistors and/or capacitors, for example, sub-circuits for implementing functions such as pull-up node control, pull-down node control, noise reduction, etc., and embodiments of the present disclosure are not limited thereto.
  • the first thin film transistor 104 includes a first gate 1041, a first active layer 1042, a first source drain 1043, a second source drain 1044, and the like; and a second thin film transistor.
  • 103 includes a structure of a second gate electrode 1031, a second active layer 1032, a first source drain 1033, a second source drain 1034, and the like.
  • the first source drain 1043 of the first thin film transistor 104 may be a source or a drain
  • the second source drain 1044 of the first thin film transistor 104 may be a drain or a source, respectively
  • the second thin film transistor 103 The first source drain 1033 may be a source or a drain
  • the second source drain 1034 of the second thin film transistor 103 may be a drain or a source, respectively.
  • the second gate electrode 1031 is electrically connected to a circuit portion (not shown) constituting the pull-up node in the shift register unit of the gate driving circuit, thereby realizing control of the second thin film transistor 103.
  • FIGS. 1A and 1B only show a portion of the pixel electrode 107 and a portion of the common electrode 109 as a schematic, for example, the pixel electrode 107 is a comb electrode and may cover a pixel region of the entire sub-pixel unit, the common electrode 109 may also be a comb electrode and may cover a pixel area of the entire sub-pixel, for example, the comb tooth portion of the pixel electrode 107 and the comb tooth portion of the common electrode 109 may overlap each other or in a direction parallel to the board surface of the array substrate 100. staggered.
  • the common electrode 109 can be connected, for example, to a common electrode line to receive a common voltage.
  • the common electrode 109 can also be multiplexed into a touch-operated touch electrode (self-capacitance electrode).
  • the touch leads 106 can be multiplexed into a common electrode line.
  • the common electrode 109 may also adopt a plate-like structure and have via holes at a required position to facilitate electrical connection between the pixel electrode and the thin film transistor, or to facilitate electrical connection between the common electrode and the touch lead.
  • the pixel electrode 107 is located on the side of the common electrode 109 away from the substrate 101, but the embodiment of the present disclosure is not limited thereto.
  • the pixel electrode 107 may be formed on the base substrate 101 first, and after the second passivation layer 118 is formed, the via hole VH2 exposing the pixel electrode 107 and the exposed first thin film transistor 104 may be formed.
  • the via hole VH1 of the first source drain 1043 further forms the fourth connection electrode 210 while the common electrode 109 is formed to electrically connect the pixel electrode 107 with the first source drain 1043 of the first thin film transistor 104.
  • the fourth connection electrode 210 electrically connects the pixel electrode 107 and the first source and drain electrode 1043 of the first thin film transistor 104 through the via hole VH1 and the via hole VH2.
  • the common electrode 109 is electrically connected to the touch lead 106 through the via 211.
  • the fourth connection electrode 210 and the common electrode 109 are insulated from each other.
  • the common electrode may serve as a first display electrode
  • the pixel electrode may serve as a second display electrode
  • the material of the first active layer 1042 of the first thin film transistor 104 includes an oxide semiconductor or an organic semiconductor material
  • the material of the second active layer 1032 of the second thin film transistor 103 includes a polysilicon semiconductor.
  • the oxide semiconductor material includes a metal oxide semiconductor material (for example, indium gallium zinc oxide (IGZO)), which is not specifically limited in the embodiment of the present disclosure
  • the polycrystalline silicon semiconductor material includes a low temperature polycrystalline silicon semiconductor material or a high temperature polycrystalline silicon semiconductor material. The embodiment of the present disclosure does not specifically limit this.
  • the array substrate 100 further includes a base substrate 101 and an interlayer insulating layer 114 laminated on the base substrate 101, and the first thin film transistor 104 and the second thin film transistor 103 are formed in the lining.
  • the material of the base substrate 101 may be a glass substrate, a quartz substrate, a plastic substrate, or a substrate of another suitable material.
  • Examples of the material of the interlayer insulating layer 114 include SiNx, SiOx, or other suitable materials, which are not limited by the embodiments of the present disclosure.
  • the first gate electrode 1041 of the first thin film transistor 104 and the first active layer 1042 are both formed on the interlayer insulating layer 114, and the second thin film transistor is formed.
  • the second gate electrode 1031 and the second active layer 1032 of 103 are both formed between the interlayer insulating layer 114 and the base substrate 101.
  • the second source drain 1034 of the second thin film transistor 103 is electrically connected to the first gate 1041 of the first thin film transistor 104, and the first source drain 1033 and the second source drain 1034 of the second thin film transistor are The first gate 1041 of a thin film transistor is formed in the same layer. For example, as shown in FIG. 1A and FIG.
  • the second source and drain 1034 of the second thin film transistor 103 are electrically connected to the first gate 1041 of the first thin film transistor 104 through the gate line 105A, and the gate line 105A and the second gate are connected.
  • the poles 1031 are formed in the same layer.
  • Examples of the material of the pole 1033 and the second source drain 1034 include aluminum, aluminum alloy, copper, copper alloy, or any other suitable material, which is not specifically limited in the embodiment of the present disclosure. For example, as shown in FIGS.
  • the second source drain 1044 of the first thin film transistor 104 is electrically connected to the data line 105B or integrally formed with each other, for example, the second source drain 1044 is a portion of the data line 105B.
  • the second gate electrode 1031 and the gate line 105A are insulated from each other.
  • the first thin film transistor 104 may be, for example, a bottom gate back channel etch type structure, or may be of other types, such as a bottom gate channel etch barrier structure.
  • a bottom-gate thin film transistor structure when external light (for example, light provided by a backlight) is irradiated from the substrate 101 side to the first thin film transistor 104, the first thin film transistor 104 is opaque.
  • the first gate 1041 can block part of the light, so that light can be prevented from being irradiated to the first active layer 1042 to some extent to cause an undesired leakage current.
  • the first active layer 1042 of the first thin film transistor 104 of the back channel etch type structure is formed by only one photolithography process, so that the channel size precision can be improved to some extent, which is beneficial to the device.
  • the array substrate 100 further includes a first passivation layer 116 laminated on the interlayer insulating layer 114 and a planarization layer 117 and a second layer laminated on the first passivation layer 116. Passivation layer 118.
  • the array substrate 100 includes a first via 110, a second via 111, and a third via 112.
  • the first via 110 is formed in the second passivation layer 118, the planarization layer 117, and the first At least a portion of the first source drain 1043 is exposed in the passivation layer 116, and the second via 111 is formed in the second passivation layer 118, the planarization layer 117, and the first passivation layer 116 and exposes the touch leads 106 ( At least a portion of the third via 112 is formed in the second passivation layer 118 and exposes at least a portion of the common electrode 109.
  • Examples of materials for the first passivation layer 116 and the second passivation layer 118 include inorganic insulating materials such as SiNx, SiOx, organic insulating materials such as organic resins, or other suitable materials, and embodiments of the present disclosure Not limited.
  • the planarization layer 117 may not be provided.
  • the first via hole 110 is formed in the second passivation layer 118 and the first passivation layer 116
  • the second via hole 111 is formed in the second passivation layer 118 and the first passivation layer 116.
  • the pixel region of the array substrate 100 further includes a pixel electrode 107 and a common electrode 109.
  • the pixel electrode 107 and the common electrode 109 are insulated from each other, and signals can be separately applied to form an electric field, thereby being driven.
  • the liquid crystal molecules rotate.
  • the array substrate 100 including the pixel electrode 107 and the common electrode 109 is formed as a horizontal electric field type array substrate.
  • the pixel electrode 107 and the common electrode 109 in the pixel region may constitute a liquid crystal capacitor (pixel capacitance) C2.
  • the common electrode 109 is formed on the first passivation layer 116 and the second passivation layer 118 covers the common electrode 109.
  • the pixel electrode 107 is formed on the second passivation layer 118, and the pixel electrode 107 passes through the first via 110 of the first passivation layer 116 and the second passivation layer 118 and the first source and drain of the first thin film transistor 104. 1043 electrical connection.
  • the material for the pixel electrode 107 include aluminum, aluminum alloy, copper, copper alloy, molybdenum, molybdenum alloy, titanium, titanium alloy, ITO, IZO, or other suitable materials, which are not limited by the embodiments of the present disclosure.
  • Examples of materials for the common electrode 109 include aluminum, aluminum alloy, copper, copper alloy, ITO, IZO, or other suitable materials, which are not limited by the embodiments of the present disclosure.
  • the display area D1 of the array substrate 100 further includes a touch lead 106 and a first connection electrode 108, and the touch lead 106 and the first source and drain 1043 of the first thin film transistor 104 are
  • the second source drains 1044 are formed in the same layer.
  • the touch lead 106 is formed in the same layer as the first source drain 1043 and the second source drain 1044 of the first thin film transistor, which means that the same metal layer is patterned to form a touch lead. 106.
  • the position of the touch lead 106 includes but is not limited thereto.
  • the touch lead 106 and the first source drain 1033 and the second source drain 1034 of the second thin film transistor 103 may be formed.
  • Examples of materials for the touch leads 106 include aluminum, aluminum alloys, copper, copper alloys, or other suitable materials, which are not limited by the embodiments of the present disclosure.
  • the touch leads 106 and the data lines 105B extend parallel to each other.
  • the first connection electrode 108 and the pixel electrode 107 are formed in the same layer, and the first connection electrode 108 electrically connects the touch lead 106 and the common electrode 109 through the second via 111 and the third via 112.
  • the first connection electrode 108 and the pixel electrode 107 are insulated from each other.
  • a mode in which the common electrode 109 is time-divisionally driven (refer to that the display phase and the touch phase are separately driven) is employed.
  • the common electrode 109 is applied with a common voltage, and cooperates with the pixel electrode 107 to realize a display operation; during the touch period, the common electrode 109 is multiplexed into a touch electrode (for example, a self-capacitance touch electrode), and the touch chip (not It can be seen that the change of the capacitance of the touch electrode can be detected by the touch lead 106, so that the touch operation can be detected.
  • a touch electrode for example, a self-capacitance touch electrode
  • the touch chip not It can be seen that the change of the capacitance of the touch electrode can be detected by the touch lead 106, so that the touch operation can be detected.
  • the common electrode 109 is multiplexed into the touch electrode, for example, when the finger touches the display panel including the array substrate, the capacitance value of the common electrode 109 at the position corresponding to the finger changes, and the touch detection circuit is based on the touch.
  • the touch lead 106 is electrically connected to the common electrode 109 through the first connection electrode 108, thereby avoiding forming a via between the common electrode 109 and the touch lead 106 to directly electrically connect the two, thereby saving a mask process.
  • the material for the first connection electrode 108 may be the same as the material of the pixel electrode 107, for example.
  • the touch lead 106 may also be a common electrode line to apply a display signal to the common electrode 109 through the common electrode line.
  • the array substrate 100 may further include a buffer layer 102, a first insulating layer 113, a second insulating layer 115, and the like.
  • the buffer layer 102 is provided, for example, on the base substrate 101.
  • the buffer layer 102 can prevent impurity ions in the base substrate 101 from being diffused into a circuit layer including the first thin film transistor 104 and the second thin film transistor 103 formed later, preventing the first thin film transistor 104 and the second Characteristics such as threshold voltage and leakage current of the thin film transistor 103 element adversely affect.
  • the buffer layer 102 can also planarize the surface of the base substrate 101. Examples of materials for the buffer layer 102 include SiNx, SiOx, or other suitable materials, which are not specifically limited in the embodiments of the present disclosure.
  • the first insulating layer 113 is disposed on the buffer layer 102 and covers the second active layer 1032 as a gate insulating layer of the second thin film transistor 103.
  • the material for the first insulating layer 113 include SiNx, SiOx, or other suitable materials, which are not specifically limited in the embodiment of the present disclosure.
  • the second insulating layer 115 is disposed on the interlayer insulating layer 114 and covers the first source drain 1033, the second source drain 1034, and the first gate 1041 as a gate insulating layer of the first thin film transistor 104.
  • the material for the second insulating layer 115 include SiNx, SiOx, or other suitable materials, which are not specifically limited in the embodiment of the present disclosure.
  • the planarization layer 117 is disposed between the first passivation layer 116 and the second passivation layer 118, and both the first via hole 110 and the second via hole 111 pass through the planarization layer 117.
  • materials for the planarization layer 117 include SiNx, SiOx, or other suitable materials, which are not specifically limited in the embodiments of the present disclosure.
  • the array substrate 100 may further include a connection region 200.
  • FIG. 3 is a schematic cross-sectional view of the connection region 200.
  • the connection region 200 is located in the peripheral region D2 of the array substrate 100.
  • the connection region 200 includes a structure of the first electrode 201, the second electrode 202, and the second connection electrode 203.
  • the first electrode 201 is or is electrically connected to an extension of the data line or the touch lead
  • the second electrode 202 is a part of the peripheral lead, whereby the data line or the touch lead and the peripheral lead can be connected through the connection area.
  • the connection, and the peripheral leads extend, for example, to the bonding area to be electrically connected to the bonding driver chip or to the multiplexing circuit unit.
  • the second connection electrode 203 can function both as an electrical connection and prevent the first electrode 201 and the second electrode 202 from being exposed to be easily oxidized.
  • the first electrode 201 is in the same layer as the first source and drain 1043 and the second source and drain 1044 of the first thin film transistor 104, and the material of the first electrode 201 may be the same as the first film.
  • the materials of the first source drain 1043 and the second source drain 1044 of the transistor 104 are the same.
  • the second electrode 202 and the first source drain 1033 and the second source drain 1034 of the second thin film transistor 103 are in the same layer, and the material of the second electrode 202 may be the first source and drain 1033 of the second thin film transistor 103.
  • the second source drain 1034 has the same material; the second connection electrode 203 is in the same layer as the pixel electrode 107, and the second connection electrode 203 passes the first electrode 201 and the second electrode through the fourth via 204 and the fifth via 205. 202 is electrically connected, and the material of the second connection electrode 203 may be the same as the material of the pixel electrode 107.
  • the fourth via 204 and the fifth via 205 may be formed by sharing a single mask with the second passivation layer 118. As shown in FIG.
  • the fourth via 204 penetrates from the second passivation layer 118 to the second insulating layer 115 and exposes at least a portion of the surface of the second electrode 202, and the second connection electrode 203 passes through the fourth via 204 and the second via 204.
  • the electrode 202 is electrically connected;
  • the fifth via 205 penetrates from the second passivation layer 118 to the first passivation layer 116 and exposes at least part of the surface of the first electrode 201, and the second connection electrode 203 passes through the fifth via 205 and the first
  • the electrodes 201 are electrically connected.
  • the first electrode 201 and the second electrode 202 are electrically connected by the second connection electrode 203, thereby avoiding forming a via hole in the second insulating layer 115 that directly electrically connects the first electrode 201 and the second electrode 202, thereby It can save a mask process and reduce production costs.
  • connection region 200 may be a connection circuit in the array substrate 100 that electrically connects the leads in the peripheral region D2 and the data lines in the display region D1, and the connection region 200 may also be used in the peripheral region D2 of the array substrate 100.
  • a circuit unit such as a multiplex (MUX) circuit unit and a fan-out area.
  • the MUX circuit unit can divide the driving signal of the driving chip of the array substrate 100 into multiple signals and apply to a plurality of signal lines (for example, touch leads), thereby reducing the number of peripheral leads in the peripheral area; the periphery in the fan-out area
  • the leads can be connected to the corresponding data driving chip and the touch driving chip through the bonding area.
  • the array substrate 100 may further include a bonding region 300.
  • FIG. 4 is a schematic cross-sectional structural view of the bonding region 300.
  • the bonding region 300 is located in the peripheral region D2 of the array substrate 100.
  • the bonding region (bonding electrode) 300 includes a structure of the fourth electrode 301, the fifth electrode 302, and the third connecting electrode 303.
  • the fourth electrode 301 is part of a peripheral lead, for example electrically connected to the second electrode 202 in the connection region 200.
  • the fifth electrode 302 is electrically connected to the fourth electrode 301 so that the resistance of the bonding region can be reduced.
  • the third connection electrode 303 can serve as a connection, and can prevent the fifth electrode 302 and the fourth electrode 301 from being exposed to be easily oxidized.
  • the fourth electrode 301 and the first source drain 1033 and the second source drain 1034 of the second thin film transistor 103 are in the same layer, and the material of the fourth electrode 301 and the second thin film transistor 103 may be The material of one source drain 1033 and the second source drain 1034 is the same; the fifth electrode 302 is in the same layer as the second gate 1031 of the second thin film transistor 103, and the material of the fifth electrode 302 can be the same as that of the second thin film transistor 103.
  • the material of the second gate electrode 1031 is the same; the third connection electrode 303 is in the same layer as the pixel electrode 107, and the material of the third connection electrode 303 may be the same as the material of the pixel electrode 107.
  • the fourth electrode 301, the fifth electrode 302, and the third connection electrode 303 are electrically connected to each other through the sixth via 304.
  • the sixth via 304 penetrates from the second passivation layer 118 to the interlayer insulating layer 114 and exposes at least a portion of the surface of the fifth electrode 302.
  • the sixth via 304 may also penetrate from the second passivation layer 118 to the second insulating layer 115 to expose at least a portion of the surface of the fourth electrode 301.
  • the arrangement of the sixth via 304 is not limited to the above description as long as the fourth electrode 301, the fifth electrode 302, and the third connection electrode 303 can be electrically connected to each other.
  • the bonding area 300 may be a data driving chip mounted in the peripheral area D2 and the touch chip and the data line and the touch lead extending in the display area D1 are electrically connected to the array substrate 100, respectively.
  • the third connection electrode 303 may be connected to the driver chip (data driving chip or touch chip) mounted on the array substrate 100 through an anisotropic conductive adhesive (ACA) or the driver chip
  • ACA anisotropic conductive adhesive
  • FPC flexible printed circuit Since the third connection electrode 303 is electrically connected to the fourth electrode 301 or the fifth electrode 302, so that the driving chip can be electrically connected to the data line or the touch lead in the display area, the driving chip can load the driving signal into the display area D1. .
  • FIG. 5A is another schematic structural diagram of an array substrate 20 according to an embodiment of the present disclosure.
  • the array substrate 20 includes a display area D1 and a peripheral area D2 surrounding the display area D1.
  • the peripheral area D2 includes a GOA gate.
  • a gate driving circuit 11 is provided on both sides of the display region D1 to realize double-sided driving, but the present disclosure is not limited to this setting.
  • two bonding zones 300 are shown as an example in FIG. 5A, wherein one bonding zone 300 is electrically connected to the data line 105B of the display area D1 through the connection area 200 for realizing bonding with the data driving chip, and the other The bonding area 300 is electrically connected to the touch lead 106 of the display area D1 through the connection area 200 for achieving bonding with the touch chip.
  • the data driving chip and the touch chip can be formed in the same integrated chip, so the above two bonding regions 300 can be bonded to the integrated chip.
  • FIGS. 1A, 1B, 3, 4, and 5B may be combined to obtain relative positions and connection relationships between the various components.
  • thin film transistors of different material types are disposed on the display region D1 and the peripheral region D2 of the array substrate.
  • the first thin film transistor 104 in the display region D1 may be an oxide thin film transistor
  • the second thin film transistor 103 in the peripheral region D2 may be a polysilicon thin film transistor
  • the second thin film transistor 103 may be, for example, a GOA gate.
  • the signal output terminal of the drive circuit 11 is a thin film transistor.
  • the second source and drain 1034 of the second thin film transistor 103 are electrically connected to the first gate 1041 of the first thin film transistor 104 through the gate line 105A, and the size of the output voltage of the second thin film transistor 103 is controlled to control the first thin film transistor 104. Open and close, thereby implementing the progressive scan function of the array substrate.
  • the first thin film transistor 104 in the display region D1 of the array substrate is an oxide thin film transistor. Since the oxide thin film transistor has the characteristics of high mobility, good stability, good electrical uniformity, and low off-state leakage current, The contrast of the display area in the display device including the array substrate 100 of the first thin film transistor 104 can be improved, the power consumption of the display device can be reduced, and the display image quality of the display device can be improved.
  • the touch lead 106 is electrically connected to the common electrode 109 through the first connection electrode 108, thereby avoiding forming a via hole in the planarization layer 117 for directly electrically connecting the touch lead 106 and the common electrode 109;
  • the connection electrode 203 electrically connects the first electrode 201 and the second electrode 202, thereby avoiding forming a via hole in the second insulating layer 115 to directly electrically connect the first electrode 201 and the second electrode 202.
  • the touch lead 106 is disposed in the same layer as the first source drain 1043 and the second source drain 1044 of the first thin film transistor 104, and the first connection electrode 108 and the pixel electrode 107 are disposed in the same layer, and the first film
  • the first gate 1041 of the transistor 104 and the first source drain 1033 and the second source drain 1034 of the second thin film transistor 103 are disposed in the same layer, and the mask design can further save the mask process and reduce the production cost. .
  • Another embodiment of the present disclosure provides an array substrate for an organic light emitting diode display device including a first thin film transistor in a display region D1 and a second thin film transistor 103 of a peripheral region D2, which is relative to FIG. 1A and
  • the array substrate for a liquid crystal display device shown in FIG. 1B is different in that a first thin film transistor as a switching element of a sub-pixel unit is not directly connected to a pixel electrode, and the sub-pixel unit further includes a driving transistor and a memory.
  • the source or the drain is connected to the pixel electrode, and the pixel electrode serves as an anode or a cathode of the organic light emitting diode, so that a driving current can be applied to the organic light emitting diode.
  • a structure of a light-emitting layer and a counter electrode, a pixel defining layer, and the like of the organic light emitting diode may be formed on the pixel electrode.
  • Another embodiment of the present disclosure provides an array substrate for an electronic paper display device including a first thin film transistor in a display region D1 and a second thin film transistor 103 of a peripheral region D2, which is relative to FIG. 1A and
  • the array substrate for a liquid crystal display device shown in FIG. 1B is different in that the sub-pixel region may not include a common electrode and a touch lead.
  • an embodiment of the present disclosure further provides a display panel including any of the array substrates described in the above embodiments.
  • the display panel may be, for example, a liquid crystal display panel, an organic light emitting diode display panel, or an electronic paper display panel.
  • the liquid crystal display panel may be, for example, an amorphous silicon liquid crystal display panel or a polycrystalline silicon liquid crystal display panel (for example, a low temperature polysilicon liquid crystal display panel or a high temperature polysilicon liquid crystal display panel).
  • the present example does not specifically limit the type of the display panel.
  • the array substrate and the opposite substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color filter substrate.
  • the pixel electrode of each sub-pixel unit of the array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display panel also includes a backlight that provides backlighting for display if needed.
  • the array substrate may be covered with a package substrate to seal a device such as an organic light emitting diode formed on the array substrate.
  • an electronic ink layer is further formed on the array substrate, and the pixel electrode of each sub-pixel unit functions as a voltage for applying a charged microparticle in the driving electronic ink to perform a display operation.
  • the technical effects of the display panel refer to the technical effects of the array substrate described in the foregoing embodiments, and details are not described herein again.
  • an embodiment of the present disclosure also provides an electronic device including any of the display panels described in the above embodiments.
  • the electronic device can be, for example, any suitable product or component such as a tablet computer, a notebook computer, a video camera, a navigator, or the like.
  • any suitable product or component such as a tablet computer, a notebook computer, a video camera, a navigator, or the like.
  • At least one embodiment of the present disclosure further provides a method for fabricating an array substrate, which is applicable to any of the array substrates described in the above embodiments.
  • FIGS. 6A-6G illustrate an array substrate provided in an embodiment of the present disclosure. Schematic diagram of the cross section structure.
  • the substrate substrate 101 can be, for example, a glass substrate, a quartz substrate, a plastic substrate, or other suitable material.
  • the embodiment of the present disclosure does not specifically limit this.
  • a buffer layer 102 may be deposited on the base substrate 101 by, for example, chemical vapor deposition, physical vapor deposition, or the like, which may prevent, for example, diffusion of impurity ions in the base substrate 101 to be formed later.
  • the buffer layer 102 can also planarize the surface of the base substrate 101, for example. Examples of materials for the buffer layer 102 include SiNx, SiOx, or other suitable materials, which are not limited by the embodiments of the present disclosure.
  • a second active layer 1032 is formed on the buffer layer 102 by a first mask process.
  • the first mask process includes, for example, depositing an active layer film on the buffer layer 102, and patterning the active layer film by, for example, a photolithography process to form a second active layer 1032 in the peripheral region D2 of the array substrate.
  • Forming the second active layer 1032 by a photolithography process includes, for example, forming a photoresist layer (not shown) on the entire surface of the active layer film after depositing the active layer film on the buffer layer 102.
  • the photoresist layer is patterned by photolithography processing including an exposure process and a development process to form a photoresist pattern having a shape corresponding to the second active layer 1032 of a desired shape on the active layer film.
  • the active layer film is then patterned using the above photoresist pattern as an etch mask (an etching process may be employed) to form a second active layer 1032 on the buffer layer 102.
  • the photoresist pattern can be stripped.
  • the mask process described below also includes process steps of exposure, development, etching, stripping, etc., and the corresponding process method can refer to a conventional or known mask method, and the mask process related manufacturing method of the embodiment of the present disclosure No longer.
  • examples of the material for the second active layer 1032 include any suitable material such as amorphous silicon or polycrystalline silicon, which is not specifically limited.
  • the method of forming the polysilicon second active layer 1032 may include, for example, depositing an amorphous silicon active layer film on the buffer layer 102, and then active in amorphous silicon.
  • the inducing metal is deposited by a sputtering method at a selected position on the layer film (usually at a subsequent source/drain region), and then annealed, for example, Rapid Thermal Annealing (RTA), excimer laser annealing ( Annealing methods such as Excimer Laser Annealing, ELA) or furnace annealing.
  • RTA Rapid Thermal Annealing
  • ELA Excimer Laser Annealing
  • the region in which the amorphous silicon active layer film is in direct contact with the metal first undergoes metal-induced crystallization (MIC) to form a MIC polysilicon region, and then the polycrystalline silicon crystal grains are laterally grown without direct contact with the metal.
  • the amorphous silicon region which in turn forms a polycrystalline region of metal-induced lateral crystallization (MILC).
  • MILC metal-induced lateral crystallization
  • the amorphous silicon active layer film is crystallized into a polysilicon active layer film.
  • a photoresist layer (not shown) is formed on the entire surface of the polysilicon active layer film, and the photoresist layer is patterned by photolithography including an exposure process and a development process to form a polysilicon active layer film.
  • a photoresist pattern having a desired shape is formed thereon.
  • the polysilicon active layer film is then patterned using the photoresist pattern as an etch mask to form a patterned polysilicon second active layer 1032 on the buffer layer
  • the first insulating layer 113 covering the second active layer 1032 may be formed, for example, by chemical vapor deposition, physical vapor deposition, or the like.
  • the material for the first insulating layer 113 include SiNx, SiOx, or other suitable materials, which are not limited by the embodiments of the present disclosure.
  • a second gate electrode 1031, a gate line 105A, a fifth electrode 302 of the bonding region 300, and the like are formed on the first insulating layer 113 by a second mask process, and the second gate electrode 1031 is located on the array substrate.
  • the gate line 105A is in the peripheral region D2 of the array substrate and the display region D1.
  • materials for the second gate electrode 1031 and the gate line 105A include aluminum, aluminum alloy, copper, copper alloy, or any other suitable material, which is not limited by the embodiments of the present disclosure.
  • the second gate can be formed by, for example, chemical vapor deposition, physical vapor deposition, or the like.
  • the interlayer insulating layer 114 of the gate electrode 1051 and the gate line 105A, and the first source and drain electrode 1033 and the second source and drain electrode 1034 of the second thin film transistor 103 formed in the interlayer insulating layer 114 are electrically connected to the second active layer 1032. Required vias, etc.
  • the interlayer insulating layer 114 may be formed by a third mask process. Examples of materials for the interlayer insulating layer 114 include SiNx, SiOx, or other suitable materials, which are not limited by the embodiments of the present disclosure.
  • a first source drain 1033 and a second source drain 1034 of the second thin film transistor may be formed on the interlayer insulating layer 114 on the interlayer insulating layer 114, for example, by using a fourth mask process.
  • a gate electrode 1041, a second electrode (peripheral lead) 202 of the connection region 200, a fourth electrode (peripheral lead) 301 of the bonding region 300, etc., a first source drain 1033 and a second source drain of the second thin film transistor 103 1034 is disposed in the peripheral region D2 of the array substrate and electrically connected to the second active layer 1032 through the via hole.
  • the first gate 1041 is disposed in the display region D1 of the array substrate, and the first electrode 201 belonging to the same peripheral lead is The fourth electrodes 301 are electrically connected to each other.
  • Examples of materials for the first source drain 1033, the second source drain 1034, and the first gate 1041 include aluminum, aluminum alloy, copper, copper alloy, or any other suitable material, and embodiments of the present disclosure do not Make a limit.
  • a cover film may be formed by a method such as chemical vapor deposition or physical vapor deposition.
  • Examples of the material for the second insulating layer 115 include SiNx, SiOx, or other suitable materials, which are not limited by the embodiments of the present disclosure.
  • the first active layer 1042 is formed on the second insulating layer 115 by a fifth mask process.
  • the fifth mask process includes, for example, depositing an active layer film on the second insulating layer 115, and patterning the active layer film by, for example, a photolithography process to form a first active in the display region D1 of the array substrate.
  • Forming the first active layer 1042 by a photolithography process includes, for example, forming a photoresist layer (not shown) on the entire surface of the active layer film after depositing the active layer film on the second insulating layer 115.
  • the photoresist layer is patterned by photolithography processing including an exposure process and a development process to form a photoresist pattern having a shape corresponding to the first active layer 1042 of a desired shape on the active layer film.
  • the active layer film is then patterned using the photoresist pattern as an etch mask to form a first active layer 1042 on the second insulating layer 115.
  • the material for the second active layer 1032 include an oxide semiconductor or an organic semiconductor including a metal oxide semiconductor material such as indium gallium zinc oxide (IGZO), etc., an embodiment of the present disclosure There is no specific limit to this.
  • the touch lead 106 (and the corresponding touch of the corresponding connection region 200) may be formed on the first insulating layer 115 by, for example, a sixth mask process.
  • the first electrode 201 of the lead 106 reference may be made to FIG. 5B
  • the touch lead 106 is formed on the first insulating layer 115 in the display region D1, and the first source drain 1043 and the second source drain 1044 are formed in the pixel region of the display region D1.
  • the first active layer 1042 On the first active layer 1042.
  • the position of the touch lead 106 includes but is not limited thereto.
  • the same metal layer may be patterned to form the touch lead 106, the first source drain 1033 and the second of the second thin film transistor 104.
  • the source drain 1034 in this case, may not need to form a connection region corresponding to the touch lead 106, and the touch lead may directly extend to the bonding region of the peripheral region to be electrically connected to the fourth electrode 301.
  • Examples of materials for the first source drain 1043, the second source drain 1044, and the touch lead 106 of the first thin film transistor 104 include aluminum, aluminum alloy, copper, copper alloy, or any other suitable material, the present disclosure The embodiment does not limit this.
  • a passivation layer 116 covers the first source and drain 1043 of the first thin film transistor 104, the second source and drain 1044, and the touch leads 106.
  • materials for the first passivation layer 116 include SiNx, SiOx, or other suitable materials, which are not limited by the embodiments of the present disclosure.
  • the planarization layer 117 may be formed on the first passivation layer 116 by, for example, a seventh mask process.
  • materials for the planarization layer 117 include SiNx, SiOx, or other suitable materials, which are not limited by the embodiments of the present disclosure.
  • a common electrode 109 may be formed on the planarization layer 117 by, for example, an eighth mask process, and the common electrode 109 is located in the pixel region of the array substrate display region D1.
  • the common electrode 109 can also be multiplexed into a touch-operated touch electrode (self-capacitance electrode).
  • materials for the common electrode 109 include aluminum, aluminum alloy, copper, copper alloy, ITO, IZO, or any other suitable material, which is not limited by the embodiments of the present disclosure.
  • a second passivation layer 118 is formed, for example, the first via hole 110, the second via hole 111 and the third via hole 112, and the connection region may be formed by a ninth mask process.
  • the first via 110, the second via 111, the third via 112, and the second passivation layer 118 may be formed by sharing a single mask.
  • the first via 110 penetrates from the second passivation layer 118 to the first passivation layer 116 and exposes at least a portion of the first source drain 1043
  • the second via 111 penetrates from the second passivation layer 118 to the first passivation Layer 116 and exposing at least a portion of touch lead 106
  • third via 112 passes through second passivation layer 118 and exposes at least a portion of common electrode 109.
  • An example of the material used for the second passivation layer 118 is, for example, an inorganic insulating material such as SiNx or SiOx or an organic insulating material such as an organic resin or other suitable material, which is not limited by the embodiment of the present disclosure.
  • the second electrode 202 is exposed through the fourth via 204
  • the first via 201 is exposed through the fifth via 205.
  • at least one of the fourth electrode 301 and the fifth electrode 302 is exposed through the sixth via 304.
  • the pixel electrode 107, the first connection electrode 108, and the second of the connection regions 200 may be formed, for example, on the second passivation layer 118 by a tenth mask process.
  • the connection electrode 203, the third connection electrode 303 of the bonding region 300, and the like are formed in the display region D1 of the array substrate, and the pixel electrode 107 is formed in the pixel region of the display region D1 of the array substrate.
  • the pixel electrode 107 is electrically connected to the first source and drain electrodes 1043 through the first via hole 110.
  • the first connection electrode 108 is electrically connected to the touch lead 106 and the common electrode 109 through the second via 111 and the third via 112, respectively.
  • the touch lead 106 is electrically connected to the common electrode 109.
  • the first connecting electrode 108 electrically connects the touch lead 106 and the common electrode 109 through the second via 111 and the third via 112, so as to avoid forming a mask process between the common electrode 109 and the touch lead 106.
  • the vias are directly electrically connected (for example, via holes are formed in the flat layer 117 and the first passivation layer 116), so that the mask process can be saved and the production cost can be reduced.
  • Examples of materials for the pixel electrode 107 and the first connection electrode 108 include aluminum, aluminum alloy, copper, copper alloy, molybdenum, molybdenum alloy, titanium, titanium alloy, ITO, IZO, or other suitable materials, embodiments of the present disclosure There is no limit to this.
  • the second connection electrode 203 electrically connects the first electrode 201 and the second electrode 202 through the fourth via 204 and the fifth via 205.
  • the fourth electrode 301, the fifth electrode 302, and the third connection electrode 303 are electrically connected to each other.
  • the first thin film transistor 104 is formed in the display region D1 of the array substrate 100, and the second thin film transistor 103 is formed in the peripheral region D2 of the array substrate 100, and
  • the first thin film transistor 104 is an oxide thin film transistor. Since the oxide thin film transistor has characteristics of high mobility, good stability, good electrical uniformity, and low off-state leakage current, the contrast of the display region in the display device including the array substrate 100 of the first thin film transistor 104 can be improved. The power consumption of the display device is reduced, and the display image quality of the display device is improved.
  • the touch lead 106 is formed in the same layer as the first source drain 1043 and the second source drain 1044 of the first thin film transistor 104, and the first connection electrode 108 and the pixel electrode 107 are formed in the same layer, the first film.
  • the first gate 1041 of the transistor 104 and the first source drain 1033 and the second source drain 1034 of the second thin film transistor 103 are formed in the same layer, and the first connection electrode 108 passes through the second via 111 and the third via, respectively.
  • the hole 112 electrically connects the touch lead 106 to the common electrode 109.
  • the array substrate 100 can be formed substantially through ten mask processes, thereby saving the mask process and reducing the production cost. For example, one mask is used in each mask process, that is, the fabrication of the array substrate can be completed using ten masks.
  • forming B while forming A may mean forming A and B in the same patterning process.
  • A, B can be components/components in the array substrate.
  • “same layer” refers to a layer structure formed by forming a film layer for forming a specific pattern by the same film forming process, and then forming the pattern by one patterning process using the same mask.
  • a patterning process may include multiple exposure, development, or etching processes, and the particular pattern in the resulting layer structure may be continuous or discontinuous, and these particular patterns may also be at different heights. Or have different thicknesses.
  • the patterning or patterning process may include only a photolithography process, or a process including a photolithography process and an etching step for forming a predetermined pattern.
  • the preparation method of the embodiment of the present disclosure has been described above by taking the array substrate of the horizontal electric field type liquid crystal display device as an example, but as described above, the embodiment of the present disclosure is not limited thereto, when it is required to form a vertical electric field type according to an embodiment of the present disclosure.
  • the steps of the preparation method may be appropriately modified according to the structure of the array substrate, and the preparation method of the array substrate is also Within the scope of the disclosure.

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Abstract

一种阵列基板及其制造方法、显示面板、电子装置，该阵列基板包括显示区域(D1)和周边区域(D2)，显示区域(D1)包括像素区域，像素区域包括第一薄膜晶体管(104)，第一薄膜晶体管(104)包括第一有源层(1042)；周边区域(D2)包括第二薄膜晶体管(103)，第二薄膜晶体管(103)包括第二有源层(1032)，且第一有源层(1042)的材料包括氧化物半导体，第二有源层(1032)的材料包括多晶硅半导体。该阵列基板可用于显示面板，可以提高显示面板的对比度，节省掩模工艺，降低生产成本。

Description

阵列基板及其制造方法、显示面板、电子装置
相关申请的交叉引用
本专利申请要求于2018年4月26日递交的中国专利申请第201810386494.X号，名称为“阵列基板及其制造方法、显示面板、电子装置”的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种阵列基板及其制造方法、显示面板、电子装置。
背景技术
在有源矩阵显示领域，薄膜晶体管(Thin Film Transistor，简称TFT)为该领域核心技术之一。薄膜晶体管例如包括栅极、栅极绝缘层、有源层、源电极和漏电极等结构。薄膜晶体管作为像素开关元件或驱动电路元件广泛应用于各种显示装置中，这些显示装置例如为液晶显示器、有机发光二极管显示器、电子纸显示器等。显示装置的像素阵列通常由多行栅线和与之交错的多列数据线限定形成。在子像素单元中，薄膜晶体管作为开关元件，在栅极控制下，外部数据信号可以通过薄膜晶体管向子像素单元中的像素电极写入，实现子像素单元的充电和放电。
通常，对栅线的驱动可以通过邦定在阵列基板上的集成驱动电路(IC芯片)实现。近几年随着非晶硅薄膜晶体管或氧化物薄膜晶体管制备工艺的不断发展，也可以将栅极驱动电路直接制备集成在阵列基板上构成GOA(Gate driver On Array)栅极驱动电路来对栅线进行驱动。例如，可以采用由多个级联的移位寄存器单元构成的GOA栅极驱动电路，为像素阵列的多行栅线提供开关态电压信号，例如控制多行栅线依序打开。GOA技术有助于实现显示装置的窄边框，并且可以降低生产成本。
发明内容
本公开至少一个实施例提供一种阵列基板，该阵列基板包括显示区域和 周边区域，所述显示区域包括像素区域，所述像素区域包括第一薄膜晶体管，所述第一薄膜晶体管包括第一有源层；所述周边区域包括第二薄膜晶体管，所述第二薄膜晶体管包括第二有源层，所述第一有源层的材料包括氧化物半导体，所述第二有源层的材料包括多晶硅半导体。
例如，在本公开一个或多个实施例中，阵列基板还包括衬底基板和位于所述衬底基板上的层间绝缘层，所述第一薄膜晶体管的第一栅极和所述第一有源层均位于所述层间绝缘层的远离所述衬底基板的一侧，所述第二薄膜晶体管的第二栅极和所述第二有源层均位于所述层间绝缘层的靠近所述衬底基板的一侧。
例如，在本公开一个或多个实施例中，阵列基板还包括位于所述层间绝缘层的远离所述衬底基板的一侧的第一钝化层以及位于所述第一钝化层的远离所述衬底基板的一侧第二钝化层，所述像素区域还包括第一显示电极和第二显示电极，所述第一显示电极位于所述第一钝化层的远离所述衬底基板的一侧，且所述第二钝化层覆盖所述第一显示电极；所述第二显示电极位于所述第二钝化层的远离所述衬底基板的一侧，且通过所述第一钝化层和所述第二钝化层中的第一过孔与所述第一薄膜晶体管的第一源漏极电连接。
例如，在本公开一个或多个实施例中，所述显示区域还包括触控引线，所述触控引线与所述第一薄膜晶体管的第一源漏极和第二源漏极或与所述第二薄膜晶体管的第一源漏极和第二源漏极位于同一层，且所述触控引线与所述第一显示电极电连接。
例如，在本公开一个或多个实施例中，所述显示区域还包括第一连接电极，所述第一连接电极与所述第二显示电极位于同一层，且所述第一连接电极通过所述第一钝化层和所述第二钝化层中的第二过孔以及所述第二钝化层中的第三过孔将所述触控引线与所述第一显示电极电连接。
例如，在本公开一个或多个实施例中，所述第一连接电极与所述第二显示电极彼此绝缘。
例如，在本公开一个或多个实施例中，所述周边区域至少包括GOA栅极驱动电路，所述GOA栅极驱动电路包括所述第二薄膜晶体管，所述第二薄膜晶体管的第二源漏极通过栅线与所述第一薄膜晶体管的第一栅极电连接，所述第二薄膜晶体管的第一源漏极和第二源漏极与所述第一薄膜晶体管 的第一栅极位于同一层；所述栅线与所述第二薄膜晶体管的第二栅极位于同一层。
例如，在本公开一个或多个实施例中，所述栅线与所述第二栅极彼此绝缘。
例如，在本公开一个或多个实施例中，所述周边区域还包括连接区，所述连接区包括第一电极、第二电极和第二连接电极，所述第一电极与所述第一薄膜晶体管的第一源漏极和第二源漏极同层；所述第二电极与所述第二薄膜晶体管的第一源漏极和第二源漏极同层；所述第二连接电极与所述第二显示电极同层，且所述第二连接电极通过所述第一钝化层和所述第二钝化层中的第四过孔和第五过孔将所述第一电极与所述第二电极电连接。
例如，在本公开一个或多个实施例中，所述周边区域还包括邦定区，所述邦定区包括第四电极、第五电极和第三连接电极，所述第四电极与所述第二薄膜晶体管的第一源漏极和第二源漏极同层；所述第五电极与所述第二薄膜晶体管的第二栅极同层；所述第三连接电极与所述第二显示电极同层，且所述第四电极、第五电极、第三连接电极彼此电连接。
例如，在本公开一个或多个实施例中，阵列基板还包括位于所述层间绝缘层的远离所述衬底基板的一侧的第一钝化层以及位于所述第一钝化层的远离所述衬底基板的一侧第二钝化层，所述像素区域还包括第一显示电极和第二显示电极，所述第二显示电极位于所述第一钝化层的远离所述衬底基板的一侧，且所述第二钝化层覆盖所述第二显示电极；所述第一显示电极位于所述第二钝化层的远离所述衬底基板的一侧；所述阵列基板还包括第四连接电极，所述第四连接电极与所述第一显示电极同层设置并彼此绝缘；且所述第二显示电极与所述第一薄膜晶体管的第一源漏极通过所述第四连接电极电连接。
本公开至少一个实施例还提供一种显示面板，包括如上述任一阵列基板。
本公开至少一个实施例还提供一种电子装置，包括上述任一显示面板。
本公开至少一个实施例还提供一种阵列基板的制造方法，所述阵列基板包括显示区域和周边区域，所述显示区域包括像素区域，所述方法包括：在所述像素区域形成第一薄膜晶体管，形成所述第一薄膜晶体管包括形成第一有源层；在所述周边区域形成第二薄膜晶体管，形成所述第二薄膜晶体管包 括形成第二有源层，所述第一有源层的材料包括氧化物半导体，所述第二有源层的材料包括多晶硅半导体。
例如，在本公开一个或多个实施例中，所述周边区域至少包括GOA栅极驱动电路，所述GOA栅极驱动电路包括所述第二薄膜晶体管，所述方法还包括：通过对第一导电薄膜进行构图以形成栅线和所述第二薄膜晶体管的第二栅极；以及通过对第二导电薄膜进行构图以形成所述第二薄膜晶体管的第一源漏极和第二源漏极和所述第一薄膜晶体管的第一栅极，所述第二薄膜晶体管的第二源漏极与所述第一薄膜晶体管的第一栅极通过所述栅线电连接。
例如，在本公开一个或多个实施例中，该方法还包括：在所述显示区域形成触控引线，通过对第三导电薄膜进行构图形成所述第一薄膜晶体管的第一源漏极和第二源漏极，并在形成所述第一薄膜晶体管的第一源漏极和第二源漏极的同时形成所述触控引线；或者在形成所述第二薄膜晶体管的第一源漏极和第二源漏极的同时形成所述触控引线。
例如，在本公开一个或多个实施例中，所述阵列基板还包括衬底基板，所述方法还包括：在所述衬底基板上依次形成第一钝化层和第二钝化层，以覆盖所述第一薄膜晶体管和所述第二薄膜晶体管；在所述像素区域内的所述第一钝化层和所述第二钝化层之间形成第一显示电极；形成所述第二钝化层后，采用刻蚀工艺形成第一过孔以暴露所述第一薄膜晶体管的第一源漏极，形成第二过孔以暴露所述触控引线，并形成第三过孔以暴露所述第一显示电极；形成第四导电薄膜，并对其进行构图以形成第二显示电极和第一连接电极；所述第二显示电极和所述第一连接电极彼此绝缘，所述第二显示电极通过所述第一过孔与所述第一薄膜晶体管的第一源漏极电连接，所述第一连接电极分别通过所述第二过孔和所述第三过孔与所述触控引线和所述第一显示电极电连接。
例如，在本公开一个或多个实施例中，该方法还包括在所述周边区的连接区形成第一电极和第二电极；在形成所述第一薄膜晶体管的第一源漏极和第二源漏极的同时形成所述第一电极，在形成所述第二薄膜晶体管的第一源漏极和第二源漏极的同时形成所述第二电极；形成所述第一过孔、所述第二过孔和所述第三过孔的同时形成第四过孔以暴露所述第二电极，并形成第五 过孔以暴露所述第一电极；以及在形成所述第二显示电极的同时形成第二连接电极，且所述第二连接电极通过所述第四过孔和所述第五过孔将所述第一电极与所述第二电极电连接。
例如，在本公开一个或多个实施例中，该方法还包括在所述周边区的邦定区形成第四电极和第五电极，在形成所述第二薄膜晶体管的第一源漏极和第二源漏极的同时形成所述第四电极；在形成所述第二薄膜晶体管的第二栅极的同时形成所述第五电极；形成所述第一过孔、所述第二过孔、所述第三过孔、所述第四过孔和所述第五过孔的同时形成第六过孔以暴露所述第四电极和所述第五电极至少之一；以及在形成所述第二显示电极的同时形成第三连接电极；所述第四电极、所述第五电极和所述第三连接电极彼此电连接。
例如，在本公开一个或多个实施例中，所述第一过孔、所述第二过孔、所述第三过孔、所述第四过孔、所述第五过孔和所述第六过孔采用同一掩模板形成。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为本公开一实施例提供的一种阵列基板的平面结构示意图；
图1B为沿着图1A中的A-A’线剖取的剖面结构示意图；
图1C为本公开另一实施例提供的剖面结构示意图；
图2为一种GOA栅极驱动电路的电路结构图；
图3为本公开公开一实施例提供的一种阵列基板的部分剖面结构示意图；
图4为本公开另一实施例提供的一种阵列基板的部分剖面结构示意图；
图5A为本公开另一实施例提供的一种阵列基板的平面结构示意图(左侧为区域示意图，右侧为阵列基板中的部分结构的俯视图)；
图5B为本公开一实施例提供的一种阵列基板的平面结构示意图(左侧为区域示意图，右侧为阵列基板中的部分结构的俯视图)；以及
图6A-图6G为本公开另一实施例提供的阵列基板在制造过程中的剖面 结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
薄膜晶体管是显示面板中核心部件之一，其性能在很大程度上影响着显示面板的显示画质。薄膜晶体管通常包括栅极、源极、漏极、栅绝缘层和有源层等结构。根据薄膜晶体管有源层的材料类型，薄膜晶体管可以分为非晶硅薄膜晶体管、多晶硅薄膜晶体管(例如，低温多晶硅薄膜晶体管、高温多晶硅薄膜晶体管等)、氧化物薄膜晶体管等。
非晶硅薄膜晶体管的电学均一性虽然较好，但是其迁移率低，且稳定性较差；低温多晶硅薄膜晶体管虽然迁移率高且稳定性好，但是其电学均一性较差且关态漏电流较大，容易造成闪烁(Flicker)残像等不良，而且使得显示面板的功耗较大，难以实现高的刷新频率。相比于非晶硅薄膜晶体管和低温多晶硅薄膜晶体管，氧化物薄膜晶体管的迁移率较高，稳定性较好且电学均一性较好，更易于实现高的刷新频率和大尺寸的显示面板，具有较好的应 用前景。
例如，在液晶显示装置的阵列基板的显示区域中，目前通常使用低温多晶硅薄膜晶体管。在形成低温多晶硅薄膜晶体管的工艺过程中，通常需要对薄膜晶体管的非晶硅有源层进行晶化以形成多晶硅有源层。因此，低温多晶硅薄膜晶体管中通常存在着较多的“晶界”，从而较难实现大面积的电学均一性。另外，“晶界”为低温多晶硅薄膜晶体管提供了漏电通道，当低温多晶硅薄膜晶体管产生不希望的关态漏电流时，通常会导致包括该低温多晶硅薄膜晶体管的阵列基板的显示装置的对比度下降，以及显示装置的显示画质较低。
本公开至少一个实施例提供一种阵列基板，该阵列基板包括显示区域和周边区域，显示区域包括像素区域，像素区域包括第一薄膜晶体管，第一薄膜晶体管包括第一有源层；周边区域包括第二薄膜晶体管，第二薄膜晶体管包括第二有源层，且第二有源层的材料与第一有源层的材料不同。在该实施例提供的阵列基板中，在阵列基板的显示区域和周边区域设置不同材料类型的薄膜晶体管。例如，根据需要，显示区域的第一薄膜晶体管可以为氧化物薄膜晶体管，周边区域的第二薄膜晶体管可以为多晶硅薄膜晶体管。
例如，本公开的实施例的阵列基板可以用于水平电场型液晶显示装置、垂直电场型液晶显示装置，还可以用于例如有机发光二极管显示装置、电子纸显示装置等。
由于氧化物薄膜晶体管具有迁移率高、稳定性好、电学均一性较好、关态漏电流较低等特点，当阵列基板的显示区域设置采用氧化物半导体材料作为有源层的第一薄膜晶体管作为子像素单元的开关元件时，相比于其他类型的薄膜晶体管，可以改善包括该阵列基板的显示装置中显示区域的对比度，降低该显示装置的功率，提高该显示装置的显示画质。由于多晶硅薄膜晶体管具有迁移率高、稳定性好的特点，当阵列基板的周边区域中的驱动电路采用多晶硅作为有源层的第二薄膜晶体管时，相比于例如非晶硅薄膜晶体管而言，具有更高的驱动能力和刷新频率。由此，本公开的实施例可以在一个阵列基板中充分利用不同类型的薄膜晶体管的优良特性，以实现更高的刷新频率、更大尺寸的显示面板、更好且更稳定的驱动效果和显示效果。
下面通过几个具体的实施例对本公开进行说明。为了使得以下的说明清 楚且简明，在本公开实施例中，可能省略已知功能和已知部件的详细说明。当本公开实施例的任一部件在一个以上的附图中出现时，该部件在每个附图中可以由相同的参考标号表示。
本公开的至少一个实施例提供一种阵列基板100，图1A为该阵列基板的平面结构示意图，图1B为沿着图1A中的A-A’线剖取的剖面结构示意图。该阵列基板100可为用于液晶显示装置的阵列基板，具体为水平电场型液晶显示装置的阵列基板，本公开的实施例以此为例进行说明，但是不限于此。
例如，如图1A和图1B所示，该阵列基板100包括显示区域D1和周边区域D2。显示区域D1包括对应于子像素单元的像素区域以及例如栅线105A、数据线105B、触控引线106等其他部件，像素区域包括第一薄膜晶体管104。周边区域D2包括对应于驱动电路的第二薄膜晶体管103。这里，第一薄膜晶体管104的有源层的材料与第二薄膜晶体管103的有源层的材料不同。例如，周边区域D2包括GOA型栅极驱动电路，该GOA型栅极驱动电路包括多个级联的GOA移位寄存器单元，每个GOA移位寄存器单元通常包括多个薄膜晶体管以及电容，每个移位寄存器单元的输出端输出扫描信号。例如，在一实施例中，第二薄膜晶体管103可以是GOA栅极驱动电路的信号输出端的输出晶体管。例如，每个GOA移位寄存器单元连接显示区域中的一条栅线105A，以在预定时刻向该栅线105A提供栅极扫描信号。
例如，GOA栅极驱动电路的输入信号包括时钟信号、开启信号STV(即移位触发信号SR_IN)、高电平信号VGH和低电平信号VGL等。时钟信号根据需要可以包括第一时钟信号CLK1和第二时钟信号CLK2，用以为GOA栅极驱动电路的子电路提供时钟信号。根据电路的不同结构，时钟信号不局限于两个，可以为一个或更多个。高电平信号VGH和低电平信号VGL用于为该GOA型栅极驱动电路以及阵列基板的子像素提供恒压信号。根据电路的不同结构，可以需要一个高电平信号VGH和一个低电平信号VGL，也可以需要多个高电平信号VGH和多个低电平信号VGL，本公开的实施例对此不作限制。
例如，图2为阵列基板100的部分电路结构图，如图2所示，该电路10包括GOA栅极驱动电路11和子像素电路12。在阵列基板100中，多条栅线105A和多条数据线105B阵列排布且交叉限定多个子像素单元，每个子像素 单元一般包含至少一个第一薄膜晶体管104和液晶电容C2。第一薄膜晶体管104作为开关元件，分别与栅线105A、数据线105B和像素电极107连接，像素电极107和公共电极109分别作为液晶电容C2的两个电极，第一薄膜晶体管104受栅线105A上的栅极扫描信号的控制将数据线105B上的数据信号施加至液晶电容C2以充电，从而控制液晶分子的偏转。
如图2所示，该GOA栅极驱动电路11的对应于第n行(n大于等于2)子像素单元的移位寄存器单元包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和存储电容C1。
该移位寄存器单元中的第一晶体管T1为该移位寄存器单元的信号输出端的输出晶体管，即为图1B中所示的周边区域D2内的第二薄膜晶体管103。例如，第一晶体管T1的第一极连接第一时钟信号CLK1，第一晶体管T1的第二极连接第二晶体管T2的第一极以得到该移位寄存器单元的输出端，并可输出用于第n行子像素单元的栅极扫描信号Gn，以及用于下一级移位寄存器单元的输入信号。例如，栅极扫描信号Gn为方波脉冲信号，相应地脉冲部分为开启电平而非脉冲部分为关断电平。第一晶体管T1的栅极连接上拉节点PU，由此连接第三晶体管T3的第一极以及第四晶体管T4的第二极。
第二晶体管T2的第二极连接第三晶体管T3的第二极以及低电平信号VGL。第二晶体管T2的栅极连接第三晶体管T3的栅极以及下一行即第n+1行的移位寄存器单元的输出端，以接收栅极扫描信号G(n+1)以作为输出下拉控制信号。第二晶体管T2的第一极连接第一晶体管T1的第二极，因此可以在下拉控制信号的控制下导通，在无需输出栅极扫描信号Gn时将输出端的输出信号下拉至低电平信号VGL。
第三晶体管T3的第一极也连接至上拉节点PU，由此与第四晶体管T4的第二极以及第一晶体管T1的栅极电连接。第三晶体管T3的第二极连接至低电平信号VGL。第三晶体管T3的栅极同样连接下一行即第n+1行的移位寄存器单元的输出端，以接收栅极扫描信号G(n+1)以作为复位控制信号(其同时也是输出下拉控制信号)，从而可以在该复位控制信号的控制下导通，将上拉节点PU复位至低电平信号VGL，从而关闭第一晶体管T1。
第四晶体管T4的第一极和自身栅极相连，并连接上一行即第n-1行的移位寄存器单元的输出端以接收栅极扫描信号G(n-1)以作为输入信号(以及 输入控制信号)，第四晶体管T4的第二极与上拉节点PU连接，从而在第四晶体管T4导通时可以对上拉节点PU充电，以使上拉节点PU的电压可以将第一晶体管T1导通，从而使第一时钟信号CLK1通过输出端输出。存储电容C1的一端连接第一晶体管T1的栅极即上拉节点PU，另一端连接第一晶体管T1的第二极，从而可以存储上拉节点PU的电平，并且可以在第一晶体管T1导通以输出时通过自身的自举效应将上拉节点PU的电平继续上拉以提升输出性能。
该栅极驱动电路工作时，当栅极扫描信号G(n-1)为高电平时，第四晶体管T4导通并对上拉节点PU充电，上拉节点PU升高的电平使得第一晶体管T1导通，因此第一时钟信号CLK1可以通过第一晶体管T1在输出端输出，也即栅极扫描信号Gn等于第一时钟信号CLK1。当第一时钟信号CLK1为高电平时，栅极扫描信号Gn也输出高电平。当栅极扫描信号Gn为高电平时，GOA栅极驱动电路11的移位寄存器单元将该高电平信号Gn输入到阵列基板对应行的栅线105A，以使该行栅线105A对应的所有的子像素单元中的第一薄膜晶体管104的第一栅极1041被施加该信号，以使得这些第一薄膜晶体管均打开，数据信号通过每个子像素中的第一薄膜晶体管104输入到对应的子像素单元的液晶电容C2，以对相应子像素单元内的液晶电容C2实施充电，从而实现对该子像素单元的信号电压写入并保持。当栅极扫描信号G(n+1)为高电平时，第二驱动晶体管T2和第三驱动晶体管T3接通，达到复位上拉节点PU以及将输出端下拉的效果。因此，通过GOA栅极驱动电路11，例如可以实现对该阵列基板100的逐行扫描驱动功能。
由于上述各个晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。第一极例如可以为源极或者漏极，第二极例如可以为漏极或者源极。在本公开中将薄膜晶体管的源极和漏极统称为“源漏极”，并且以第一源漏极和第二源漏极进行区分。例如，上述各个晶体管可以为N型晶体管。当然，上述各个晶体管不限于N型晶体管，也可以至少部分为P型晶体管，由此，将相应的开启信号STV、输出的扫描信号的极性进行相应地改变即可。
需要说明的是，在本公开的各实施例中，GOA栅极驱动电路11的移位寄存器单元的结构不局限于上面描述的结构，GOA栅极驱动电路11的移位寄存器单元可以为任意适用结构，也可以包括更多或更少的晶体管和/或电 容，例如加入用于实现上拉节点控制、下拉节点控制、降噪等功能的子电路等，本公开的实施例对此不作限制。
例如，如图1A和图1B所示，第一薄膜晶体管104包括第一栅极1041、第一有源层1042、第一源漏极1043、第二源漏极1044等结构；第二薄膜晶体管103包括第二栅极1031、第二有源层1032、第一源漏极1033、第二源漏极1034等结构。例如，第一薄膜晶体管104的第一源漏极1043可以是源极或者漏极，第一薄膜晶体管104的第二源漏极1044相应地可以是漏极或者源极；第二薄膜晶体管103的第一源漏极1033可以是源极或者漏极，第二薄膜晶体管103的第二源漏极1034相应地可以是漏极或者源极。例如，第二栅极1031与栅极驱动电路的移位寄存器单元中构成上拉节点的电路部分(未示出)电连接，从而实现对第二薄膜晶体管103的控制。
为了清楚起见，图1A和图1B仅仅示出了像素电极107的一部分以及公共电极109的一部分以作为示意，例如，像素电极107为梳状电极且可以覆盖整个子像素单元的像素区域，公共电极109也可以为梳状电极且可以覆盖整个子像素的像素区域，例如，像素电极107的梳齿部分和公共电极109的梳齿部分可以彼此重叠或在平行于阵列基板100板面的方向上彼此交错。公共电极109例如可以与公共电极线连接以接收公共电压。并且，在该实施例中，公共电极109还可以复用为触控操作的触控电极(自电容电极)。例如，触控引线106可复用为公共电极线。公共电极109也可采用板状结构，并在需要位置处具有过孔以利于像素电极与薄膜晶体管的电连接，或者利于公共电极与触控引线的电连接等。
例如，图1A和图1B，本公开的实施例中，以像素电极107位于公共电极109的远离衬底基板101的一侧为例进行说明，但本公开的实施例不限于此。
例如，如图1C所示，也可以在衬底基板101上先形成像素电极107，并在形成第二钝化层118之后，形成暴露像素电极107的过孔VH2和暴露第一薄膜晶体管104的第一源漏极1043的过孔VH1，再在形成公共电极109的同时，形成第四连接电极210以使得像素电极107与第一薄膜晶体管104的第一源漏极1043电连接。第四连接电极210通过过孔VH1和过孔VH2电连接像素电极107与第一薄膜晶体管104的第一源漏极1043。公共电极109通 过过孔211与触控引线106电连接。例如，第四连接电极210与公共电极109彼此绝缘。
本公开的实施例中，公共电极可作为第一显示电极，像素电极可作为第二显示电极。
例如，第一薄膜晶体管104的第一有源层1042的材料包括氧化物半导体或有机半导体材料，第二薄膜晶体管103的第二有源层1032的材料包括多晶硅半导体。例如，氧化物半导体材料包括金属氧化物半导体材料(例如氧化铟镓锌(IGZO))，本公开的实施例对此不做具体的限定；多晶硅半导体材料包括低温多晶硅半导体材料或者高温多晶硅半导体材料等，本公开的实施例对此不做具体的限定。
例如，如图1A和图1B所示，该阵列基板100还包括衬底基板101以及层叠在衬底基板101上的层间绝缘层114，第一薄膜晶体管104和第二薄膜晶体管103形成在衬底基板101上的不同层中。衬底基板101的材质可以是玻璃基板、石英基板、塑料基板或其他适合材料的基板。层间绝缘层114的材料的示例包括SiNx、SiOx或其它适合的材料，本公开的实施例对此不做限定。
例如，如图1A和图1B所示，相对于衬底基板101，第一薄膜晶体管104的第一栅极1041和第一有源层1042均形成在层间绝缘层114上，第二薄膜晶体管103的第二栅极1031和第二有源层1032均形成在层间绝缘层114和衬底基板101之间。例如，第二薄膜晶体管103的第二源漏极1034与第一薄膜晶体管104的第一栅极1041电连接，且第二薄膜晶体管的第一源漏极1033和第二源漏极1034与第一薄膜晶体管的第一栅极1041形成在同一层。例如，如图1A和图1B所示，第二薄膜晶体管103的第二源漏极1034通过栅线105A与第一薄膜晶体管104的第一栅极1041电连接，且栅线105A与第二栅极1031形成在同一层。例如，用于第一栅极1041、第一薄膜晶体管104的第一源漏极1043和第二源漏极1044、栅线105A、第二栅极1031、第二薄膜晶体管103的第一源漏极1033和第二源漏极1034的材料的示例包括铝、铝合金、铜、铜合金或其他任意适合的材料，本公开的实施例对此不做具体的限定。例如，如图1A和1B所示，第一薄膜晶体管104的第二源漏极1044与数据线105B电连接或彼此一体形成，例如第二源漏极1044为数据线105B的一 部分。例如，如图1A和1B所示，第二栅极1031与栅线105A彼此绝缘。
例如，如图1A和图1B所示，在一个示例中，第一薄膜晶体管104例如可以是底栅背沟道刻蚀型结构，也可以为其他类型，例如底栅沟道刻蚀阻挡型结构。例如，在底栅型薄膜晶体管结构中，当有外部光线(例如背光源提供的光线)从衬底基板101一侧照射到第一薄膜晶体管104时，该第一薄膜晶体管104的不透光的第一栅极1041可以将部分光线遮挡，从而可以在一定程度上避免光线照射到第一有源层1042上进而造成不希望的漏电流。另外，在制造过程中，背沟道刻蚀型结构的第一薄膜晶体管104中的第一有源层1042仅需一次光刻工艺形成，从而可以在一定程度上提高沟道尺寸精度，利于器件小型化的实现。
例如，如图1A和图1B所示，该阵列基板100还包括层叠在层间绝缘层114上的第一钝化层116以及层叠在第一钝化层116上的平坦化层117和第二钝化层118。如图1B所示，该阵列基板100包括第一过孔110、第二过孔111、第三过孔112，第一过孔110形成在第二钝化层118、平坦化层117和第一钝化层116中且暴露第一源漏极1043的至少部分，第二过孔111形成在第二钝化层118、平坦化层117和第一钝化层116中且暴露触控引线106(本文后面将提到)的至少部分，第三过孔112形成在第二钝化层118中且暴露公共电极109的至少部分。用于该第一钝化层116和第二钝化层118的材料的示例包括例如SiNx、SiOx等无机绝缘材料、例如有机树脂等有机绝缘材料或其它适合的材料，本公开的实施例对此不做限定。例如，在其他示例中，也可以不设置平坦化层117。此情况下，第一过孔110形成在第二钝化层118和第一钝化层116中，第二过孔111形成在第二钝化层118和第一钝化层116中。
例如，如图1A和图1B所示，该阵列基板100的像素区域还包括像素电极107和公共电极109，像素电极107和公共电极109彼此绝缘，可被分别施加信号以形成电场，进而可驱动液晶分子旋转。例如，包括该像素电极107和公共电极109的阵列基板100形成为水平电场型阵列基板。例如，像素区域内的像素电极107和公共电极109可以构成液晶电容(像素电容)C2。公共电极109形成在第一钝化层116上且第二钝化层118覆盖公共电极109。像素电极107形成在第二钝化层118上，且像素电极107通过第一钝化层116 和第二钝化层118中的第一过孔110与第一薄膜晶体管104的第一源漏极1043电连接。用于像素电极107的材料的示例包括铝、铝合金、铜、铜合金、钼、钼合金、钛、钛合金、ITO、IZO或其它适合的材料，本公开的实施例对此不做限定。用于公共电极109的材料的示例包括铝、铝合金、铜、铜合金、ITO、IZO或其他适合的材料，本公开的实施例对此不做限定。
例如，如图1A和图1B所示，该阵列基板100的显示区域D1还包括触控引线106和第一连接电极108，触控引线106与第一薄膜晶体管104的第一源漏极1043和第二源漏极1044形成在同一层。例如，在一实施例中，触控引线106与第一薄膜晶体管的第一源漏极1043和第二源漏极1044形成在同一层，指的是对同一金属层进行构图从而形成触控引线106、第一源漏极1043和第二源漏极1044。当然，触控引线106的位置包括但不限于此，例如，在另一个示例中，也可以是触控引线106与第二薄膜晶体管103的第一源漏极1033和第二源漏极1034形成在同一层。用于触控引线106的材料的示例包括铝、铝合金、铜、铜合金或其他适合的材料，本公开的实施例对此不做限定。例如，在阵列基板之上，触控引线106与数据线线105B彼此平行延伸。
第一连接电极108与像素电极107形成在同一层，且第一连接电极108通过第二过孔111以及第三过孔112将触控引线106与公共电极109电连接。例如，如图1B所示，第一连接电极108与像素电极107彼此绝缘。例如，在一个示例中，采用对公共电极109进行分时驱动(指显示阶段和触控阶段分开驱动)的模式。在显示时段，公共电极109被施加公共电压，与像素电极107配合实现显示操作；在触控时段，公共电极109被复用为触控电极(例如自电容触控电极)，触控芯片(未示出)可以通过触控引线106检测该触控电极的电容变化，从而可以对触控操作进行检测。当公共电极109被复用为触控电极时，例如，当手指接触包括该阵列基板的显示面板时，与手指对应位置处的公共电极109的电容数值会发生变化，触控检测电路根据触控点位置电容数值的变化情况，便可计算出触摸点的位置，进而实现对触控操作的检测。通过第一连接电极108使得触控引线106与公共电极109电连接，避免了在公共电极109和触控引线106之间形成使两者直接电连接的过孔，从而节省了一道掩模工艺。用于第一连接电极108的材料例如可以和像素电 极107的材料相同。当公共电极109不复用为触控电极时，触控引线106也可为公共电极线以通过该公共电极线向公共电极109施加显示信号。
例如，如图1A和图1B所示，该阵列基板100还可以包括缓冲层102、第一绝缘层113、第二绝缘层115等结构。
缓冲层102例如设置在衬底基板101上。一方面，该缓冲层102可以防止衬底基板101中的杂质离子扩散到之后形成的包括第一薄膜晶体管104和第二薄膜晶体管103等电路层之中，防止对第一薄膜晶体管104和第二薄膜晶体管103元件的阈值电压和漏电流等特性产生不利影响。另一方面，该缓冲层102还可以平坦化衬底基板101的表面。用于该缓冲层102的材料的示例包括SiNx、SiOx或其它适合的材料，本公开的实施例对此不做具体限定。
例如，第一绝缘层113设置在缓冲层102上且覆盖第二有源层1032，作为第二薄膜晶体管103的栅极绝缘层。用于该第一绝缘层113的材料的示例包括SiNx、SiOx或其它适合的材料，本公开的实施例对此不做具体限定。
例如，第二绝缘层115设置在层间绝缘层114上且覆盖第一源漏极1033、第二源漏极1034以及第一栅极1041，作为第一薄膜晶体管104的栅极绝缘层。用于该第二绝缘层115的材料的示例包括SiNx、SiOx或其它适合的材料，本公开的实施例对此不做具体限定。
例如，平坦化层117设置在第一钝化层116和第二钝化层118之间，且第一过孔110和第二过孔111均穿过该平坦化层117。用于该平坦化层117的材料的示例包括SiNx、SiOx或其它适合的材料，本公开的实施例对此不做具体限定。
例如，如图3所示，该阵列基板100还可以包括连接区200。图3为该连接区200的剖面结构示意图。该连接区200位于阵列基板100的周边区域D2内。例如，连接区200包括第一电极201、第二电极202和第二连接电极203等结构。例如，第一电极201为数据线或触控引线的延伸部分或与之电连接，而第二电极202为周边引线的一部分，由此通过该连接区可以将数据线或触控引线与周边引线连接，而周边引线例如延伸至邦定区以与邦定的驱动芯片电连接或与多路复用电路单元连接。第二连接电极203可以既起到电连接的作用，又可以防止第一电极201和第二电极202暴露而易于氧化。
还参考图1B和图3所示，第一电极201与第一薄膜晶体管104的第一 源漏极1043和第二源漏极1044在同一层，且第一电极201的材料可以与第一薄膜晶体管104的第一源漏极1043和第二源漏极1044的材料相同。第二电极202与第二薄膜晶体管103的第一源漏极1033和第二源漏极1034在同一层，且第二电极202的材料可以与第二薄膜晶体管103的第一源漏极1033和第二源漏极1034的材料相同；第二连接电极203与像素电极107在同一层，且第二连接电极203通过第四过孔204和第五过孔205将第一电极201与第二电极202电连接，第二连接电极203的材料可以与像素电极107的材料相同。例如，第四过孔204和第五过孔205可以与第二钝化层118共用一张掩模板形成。如图3所示，第四过孔204从第二钝化层118贯穿到第二绝缘层115且暴露第二电极202的至少部分表面，第二连接电极203通过第四过孔204与第二电极202电连接；第五过孔205从第二钝化层118贯穿到第一钝化层116且暴露第一电极201的至少部分表面，第二连接电极203通过第五过孔205与第一电极201电连接。例如，通过第二连接电极203将第一电极201与第二电极202电连接，从而避免了在第二绝缘层115中形成将第一电极201与第二电极202直接电连接的过孔，从而可以节省一道掩模工艺，降低生产成本。
例如，连接区200可以是该阵列基板100中使周边区域D2中的引线与显示区域D1中的数据线等电连接的连接电路，该连接区200还可以用于阵列基板100的周边区域D2内的多路复用(MUX)电路单元等电路单元以及扇出(Fan-out)区域。例如，MUX电路单元可以将阵列基板100的驱动芯片的驱动信号分成多路信号，施加至多条信号线(例如触控引线)，从而可以减少周边区中周边引线的数量；扇出区域中的周边引线可以通过邦定区域连接到相应的数据驱动芯片以及触控驱动芯片等。
例如，如图4所示，该阵列基板100还可以包括邦定区300，图4为该邦定区300的剖面结构示意图，该邦定区300位于阵列基板100的周边区域D2内。例如，邦定区(邦定电极)300包括第四电极301、第五电极302和第三连接电极303等结构。第四电极301为周边引线的一部分，例如与连接区200中的第二电极202电连接。第五电极302与第四电极301电连接由此可以降低邦定区的电阻。第三连接电极303可以既起到连接作用，还可以防止第五电极302与第四电极301被暴露而易于氧化。
参考图1B和图4，第四电极301与第二薄膜晶体管103的第一源漏极1033和第二源漏极1034在同一层，第四电极301的材料可以与第二薄膜晶体管103的第一源漏极1033和第二源漏极1034的材料相同；第五电极302与第二薄膜晶体管103的第二栅极1031在同一层，第五电极302的材料可以与第二薄膜晶体管103的第二栅极1031的材料相同；第三连接电极303与像素电极107在同一层，第三连接电极303的材料可以与像素电极107的材料相同。如图4所示，第四电极301、第五电极302、第三连接电极303通过第六过孔304彼此电连接。例如，第六过孔304从第二钝化层118贯穿到层间绝缘层114且暴露第五电极302的至少部分表面。当然，第六过孔304也可以从第二钝化层118贯穿到第二绝缘层115以暴露第四电极301的至少部分表面。第六过孔304的设置方式不限于上述描述，只要可实现第四电极301、第五电极302、第三连接电极303彼此电连接即可。
例如，在一个示例中，邦定区300可以是该阵列基板100中使周边区域D2中安装的数据驱动芯片以及触控芯片与显示区域D1中延伸出的数据线和触控引线分别电连接的连接电路，第三连接电极303可以通过各向异性导电胶(Anisotropic conductive adhesive，ACA)与阵列基板100上安装的驱动芯片(数据驱动芯片或触控芯片)的引脚或者与安装有该驱动芯片的柔性印刷电路板(Flexible printed circuit，FPC)的引脚电连接。由于第三连接电极303与第四电极301或第五电极302电连接，从而使得驱动芯片可以与显示区域中的数据线或触控引线电连接，驱动芯片可将驱动信号加载到显示区域D1内。
图5A为本公开的实施例提供的阵列基板20的另一平面结构示意图，如图5A所示，该阵列基板20包括显示区域D1和围绕显示区域D1的周边区域D2，周边区域D2包括GOA栅极驱动电路11、连接区200、邦定区300等部分。在图5A中，在显示区域D1两侧都设置有栅极驱动电路11以实现双侧驱动，但本公开不限于此设置。
例如，图5A中示出两个邦定区300作为示例，其中一个邦定区300通过连接区200与显示区域D1的数据线105B电连接，用于实现与数据驱动芯片的邦定，另一个邦定区300通过连接区200与显示区域D1的触控引线106电连接，用于实现与触控芯片的邦定。虽然如此，在其他示例中，数据驱动 芯片与触控芯片可以形成在同一个集成芯片之中，因此上述两个邦定区300可以与该集成芯片邦定。
结合图1B、图2和图5A，当GOA栅极驱动电路11的第二薄膜晶体管103的第二源漏极1034通过栅线105将高电平信号加载到显示区域D1的第一薄膜晶体管104的第一栅极1041时，第一薄膜晶体管104的第一栅极1041处于打开状态，数据信号通过其中一个邦定区300输入到第一薄膜晶体管104，进而可以对像素电极107进行充电，实现对包括该像素电极107的子像素单元的信号写入和保持。触控信号通过另外一个邦定区300加载到触控引线106进而使该阵列基板20实现触摸检测功能。该阵列基板20的其它结构及功能，可参考常规阵列基板的结构及功能，在此不再赘述。
本公开一实施例中，可结合图1A、图1B、图3、图4和图5B，以获得各个部件之间的相对位置以及连接关系。
需要说明的是，为表示清楚，附图中并没有示出该阵列基板100的全部结构。为实现阵列基板的必要功能，本领域技术人员可以根据具体应用场景进行设置其他未示出的结构，本公开的实施例对此不做限制。
在本公开至少一个实施例提供的阵列基板中，在阵列基板的显示区域D1和周边区域D2设置不同材料类型的薄膜晶体管。例如，根据需要，显示区域D1内的第一薄膜晶体管104可以为氧化物薄膜晶体管，周边区域D2内的第二薄膜晶体管103可以为多晶硅薄膜晶体管，该第二薄膜晶体管103例如可以是GOA栅极驱动电路11的信号输出端薄膜晶体管。第二薄膜晶体管103的第二源漏极1034通过栅线105A与第一薄膜晶体管104的第一栅极1041电连接，通过控制第二薄膜晶体管103输出电压的大小进而控制第一薄膜晶体管104的打开与关闭，从而实现对该阵列基板的逐行扫描功能。
一方面，阵列基板的显示区域D1内的第一薄膜晶体管104为氧化物薄膜晶体管，由于氧化物薄膜晶体管具有迁移率高、稳定性好、电学均一性好、关态漏电流低等特点，因此可以改善包括该第一薄膜晶体管104的阵列基板100的显示装置中显示区域的对比度，降低显示装置的功率消耗，提高显示装置的显示画质。
另一方面，通过第一连接电极108将触控引线106与公共电极109电连接，避免了在平坦化层117中形成将触控引线106与公共电极109直接电连 接的过孔；通过第二连接电极203将第一电极201和第二电极202电连接，避免了在第二绝缘层115中形成将第一电极201与第二电极202直接电连接的过孔。通过设置第一连接电极108和第二连接电极203，可以节省掩模工艺，降低生产成本。
再一方面，触控引线106与第一薄膜晶体管104的第一源漏极1043和第二源漏极1044设置在同一层，第一连接电极108与像素电极107设置在同一层，第一薄膜晶体管104的第一栅极1041与第二薄膜晶体管103的第一源漏极1033和第二源漏极1034设置在同一层，通过这种膜层设计，可以进一步节省掩模工艺，降低生产成本。
在公开另一个实施例提供了一种用于有机发光二极管显示装置的阵列基板，其包括在显示区域D1中的第一薄膜晶体管和周边区域D2的第二薄膜晶体管103，其相对于图1A和图1B所示出的用于液晶显示装置的阵列基板而言，不同之处在于，作为子像素单元的开关元件的第一薄膜晶体管并不直接连接像素电极，子像素单元还包括驱动晶体管、存储电容等器件，例如第一薄膜晶体管的源极或漏极与驱动晶体管的栅极以及存储电容的一个电极连接，以便将数据信号写入驱动晶体管的栅极并存入存储电容之中，驱动晶体管的源极或漏极与像素电极连接，像素电极作为有机发光二极管的阳极或阴极，从而可以向有机发光二极管施加驱动电流。例如，可以在该像素电极上形成有机发光二极管的发光层和对电极、像素界定层等结构。
在本公开另一个实施例提供了一种用于电子纸显示装置的阵列基板，其包括在显示区域D1中的第一薄膜晶体管和周边区域D2的第二薄膜晶体管103，其相对于图1A和图1B所示出的用于液晶显示装置的阵列基板而言，不同之处在于，子像素区域可不包括公共电极与触控引线。
例如，本公开的一个实施例还提供一种显示面板，该显示面板包括上述实施例描述的任一阵列基板。
该显示面板例如可以是液晶显示面板、有机发光二极管显示面板或电子纸显示面板。
液晶显示面板例如可以是非晶硅液晶显示面板或者多晶硅液晶显示面板(例如，低温多晶硅液晶显示面板或者高温多晶硅液晶显示面板)等，本示例对显示面板的类型不做具体限制。在液晶显示面板中，阵列基板与对置基 板彼此对置以形成液晶盒，在液晶盒中填充有液晶材料。该对置基板例如为彩膜基板。阵列基板的每个子像素单元的像素电极用于施加电场对液晶材料的旋转的程度进行控制从而进行显示操作。如果需要，该液晶显示面板还包括为显示提供背光的背光源。
在有机发光二极管(OLED)显示面板中，阵列基板上可以覆盖有封装基板以对阵列基板上形成的有机发光二极管等器件实现密封。
在电子纸显示面板中，阵列基板上还形成有电子墨水层，每个子像素单元的像素电极作为用于施加驱动电子墨水中的带电微颗粒移动以进行显示操作的电压。该显示面板的技术效果可参见上述实施例描述的阵列基板的技术效果，在此不再赘述。
例如，本公开的一个实施例还提供一种电子装置，该电子装置包括上述实施例描述的任一显示面板。该电子装置例如可以为平板电脑、笔记本电脑、摄像机、导航仪等任意适合的产品或者部件。该电子装置的技术效果，可参见上述实施例描述的阵列基板的技术效果，在此不再赘述。
本公开至少一实施例还提供一种阵列基板的制造方法，该制造方法适用于上述实施例描述的任一阵列基板，图6A-图6G为本公开一实施例提供的阵列基板在制造过程中的剖面结构示意图。
如图6A所示，首先提供衬底基板101，衬底基板101例如可以是玻璃基板、石英基板、塑料基板或其它适合材料的基板，本公开的实施例对此不做具体限定。
如图6A所示，在衬底基板101上例如可以通过化学气相沉积、物理气相沉积等方法沉积缓冲层102，该缓冲层102例如可以防止衬底基板101中的杂质离子扩散到之后形成的包括薄膜晶体管等电路层之中，防止对薄膜晶体管元件的阈值电压和漏电流等特性产生影响；同时该缓冲层102例如还可以平坦化衬底基板101的表面。用于该缓冲层102的材料的示例包括SiNx、SiOx或其它适合的材料，本公开的实施例对此不做限定。
如图6A所示，通过第一掩模工艺在缓冲层102上形成第二有源层1032。该第一掩模工艺例如包括：在缓冲层102上沉积有源层薄膜，并对有源层薄膜例如采用光刻工艺进行构图，以在阵列基板的周边区域D2内形成第二有源层1032。采用光刻工艺形成第二有源层1032例如包括：在缓冲层102上 沉积有源层薄膜之后，在有源层薄膜的整个表面上形成光刻胶层(图中未示出)。通过包括曝光工序以及显影工序的光刻法处理对光刻胶层构图，以在有源层薄膜上形成具有与所需形状的第二有源层1032对应形状的光刻胶图案。然后利用上述光刻胶图案作为蚀刻掩模对有源层薄膜进行构图(可采用刻蚀工艺)，以在缓冲层102上形成第二有源层1032。最后，可剥离光刻胶图案。下述的掩模工艺，也包括曝光、显影、刻蚀、剥离等工艺步骤，相应的工艺方法可参照传统的或已知的掩模方法，本公开的实施例对掩模工艺相关的制造方法不再赘述。
在一实施例中，用于第二有源层1032的材料的示例包括非晶硅或者多晶硅等任意适合的材料，对此不做具体限定。
例如，当第二有源层1032由多晶硅材料构成时，形成多晶硅第二有源层1032的方法例如可以包括：在缓冲层102上沉积非晶硅有源层薄膜之后，在非晶硅有源层薄膜上的选择位置处(通常是后续形成源/漏区域处)采用溅射方法沉积诱导金属，然后进行退火处理，例如可以为快速热退火(Rapid Thermal Annealing，RTA)、准分子激光退火(Excimer Laser Annealing，ELA)或炉退火等退火方法。在退火过程中，非晶硅有源层薄膜与金属直接接触的区域首先发生金属诱导晶化(Metal-induced crystallization，MIC)，形成MIC多晶硅区域，随后多晶硅晶粒横向生长入没有与金属直接接触的非晶硅区域，进而形成金属诱导横向晶化(Metal-induced lateral crystallization，MILC)的多晶硅区域。这样，非晶硅有源层薄膜晶化转变为多晶硅有源层薄膜。然后，在多晶硅有源层薄膜的整个表面上形成光刻胶层(图中未示出)，通过包括曝光工序以及显影工序的光刻法对光刻胶层构图，以在多晶硅有源层薄膜上形成具有所需形状的光刻胶图案。然后利用上述光刻胶图案作为蚀刻掩模对多晶硅有源层薄膜进行构图，以在缓冲层102上形成图案化的多晶硅第二有源层1032。
如图6A所示，在形成第二有源层1032之后，例如可以通过化学气相沉积、物理气相沉积等方法形成覆盖第二有源层1032的第一绝缘层113。用于第一绝缘层113的材料的示例包括SiNx、SiOx或其它适合的材料，本公开的实施例对此不做限定。
如图6B所示，通过第二掩模工艺在第一绝缘层113上形成第二栅极 1031、栅线105A以及邦定区300的第五电极302等，第二栅极1031位于阵列基板的周边区域D2内，栅线105A在阵列基板的周边区域D2和显示区域D1内。用于第二栅极1031和栅线105A的材料的示例包括铝、铝合金、铜、铜合金或其它任意适合的材料，本公开的实施例对此不做限定。
如图6C所示，在同层形成第二栅极1031、栅线105A以及邦定区300的第五电极302等结构之后，例如可以通过化学气相沉积、物理气相沉积等方法形成覆盖第二栅极1031和栅线105A的层间绝缘层114，层间绝缘层114中形成有第二薄膜晶体管103的第一源漏极1033和第二源漏极1034与第二有源层1032电连接所需的过孔等。例如，该层间绝缘层114可以通过第三掩模工艺形成。用于层间绝缘层114的材料的示例包括SiNx、SiOx或其它适合的材料，本公开的实施例对此不做限定。
如图6C所示，在层间绝缘层114上例如可以通过第四掩模工艺在层间绝缘层114上形成第二薄膜晶体管的第一源漏极1033和第二源漏极1034、第一栅极1041、连接区200的第二电极(周边引线)202、邦定区300的第四电极(周边引线)301等，第二薄膜晶体管103的第一源漏极1033和第二源漏极1034设置在阵列基板的周边区域D2内且通过过孔与第二有源层1032电连接，第一栅极1041设置在阵列基板的显示区域D1内，属于同一条周边引线的第一电极201与第四电极301彼此电连接。用于第一源漏极1033、第二源漏极1034和第一栅极1041的材料的示例包括铝、铝合金、铜、铜合金或其它任意适合的材料，本公开的实施例对此不做限定。
如图6D所示，在形成第二薄膜晶体管103的第一源漏极1033、第二源漏极1034和第一栅极1041之后，例如可以通过化学气相沉积、物理气相沉积等方法形成覆盖第一源漏极1033、第二源漏极1034和第一栅极1041的第二绝缘层115。用于第二绝缘层115的材料的示例包括SiNx、SiOx或其它适合的材料，本公开的实施例对此不做限定。
如图6D所示，在形成第二绝缘层115之后，通过第五掩模工艺在第二绝缘层115上形成第一有源层1042。该第五掩模工艺例如包括：在第二绝缘层115上沉积有源层薄膜，并对有源层薄膜例如采用光刻工艺进行构图，以在阵列基板的显示区域D1内形成第一有源层1042。采用光刻工艺形成第一有源层1042例如包括：在第二绝缘层115上沉积有源层薄膜之后，在有源层 薄膜的整个表面上形成光刻胶层(图中未示出)。通过包括曝光工序以及显影工序的光刻法处理对光刻胶层构图，以在有源层薄膜上形成具有与所需形状的第一有源层1042对应形状的光刻胶图案。然后利用上述光刻胶图案作为蚀刻掩模对有源层薄膜构图，以在第二绝缘层115上形成第一有源层1042。例如，用于第二有源层1032的材料的示例包括氧化物半导体或有机半导体，该氧化物半导体材料包括金属氧化物半导体材料(例如氧化铟镓锌(IGZO))等，本公开的实施例对此不做具体的限定。
如图6D所示，在显示区域D1内形成第一有源层1042之后，例如可以通过第六掩模工艺在第一绝缘层115上形成触控引线106(以及相应连接区200的对应触控引线106的第一电极201，可参照图5B)、第一薄膜晶体管104的第一源漏极1043、第二源漏极1044、数据线(以及相应连接区200的对应数据线105B的第一电极201，可参照图5B)，触控引线106形成在显示区域D1内的第一绝缘层115上，第一源漏极1043和第二源漏极1044形成在显示区域D1的像素区域内的第一有源层1042上。
触控引线106的位置包括但不限于此，例如，在另一个示例中，也可以对同一金属层进行构图以形成触控引线106、第二薄膜晶体管104的第一源漏极1033和第二源漏极1034，在这种情况下，可以无需形成对应于触控引线106的连接区域，该触控引线可以直接延伸至周边区域的邦定区域中与第四电极301电连接。用于第一薄膜晶体管104的第一源漏极1043、第二源漏极1044和触控引线106的材料的示例包括铝、铝合金、铜、铜合金或其它任意适合的材料，本公开的实施例对此不做限定。
如图6E所示，在形成第一薄膜晶体管104的第一源漏极1043、第二源漏极1044和第一触控引线106之后，例如可以通过化学气相沉积、物理气相沉积等方法形成第一钝化层116，第一钝化层116覆盖第一薄膜晶体管104的第一源漏极1043、第二源漏极1044和触控引线106。用于第一钝化层116的材料的示例包括SiNx、SiOx或其它适合的材料，本公开的实施例对此不做限定。
如图6E所示，在形成第一钝化层116后，例如可以通过第七掩模工艺在第一钝化层116上形成平坦化层117。用于平坦化层117的材料的示例包括SiNx、SiOx或其它适合的材料，本公开的实施例对此不做限定。
如图6E所示，例如可以通过第八掩模工艺在平坦化层117上形成公共电极109，公共电极109位于阵列基板显示区域D1的像素区域内。例如，在一实施例中，公共电极109还可以复用为触控操作的触控电极(自电容电极)。用于公共电极109的材料的示例包括铝、铝合金、铜、铜合金、ITO、IZO或其它任意适合的材料，本公开的实施例对此不做限定。
如图6F所示，在形成公共电极109之后，形成第二钝化层118，例如可以通过第九掩模工艺形成第一过孔110、第二过孔111和第三过孔112以及连接区200中的第四过孔204和第五过孔205、邦定区300中的第六过孔304等。第一过孔110、第二过孔111、第三过孔112和第二钝化层118可以共用一张掩模板形成。第一过孔110从第二钝化层118贯穿到第一钝化层116且暴露第一源漏极1043的至少部分，第二过孔111从第二钝化层118贯穿到第一钝化层116且暴露触控引线106的至少部分，第三过孔112穿过第二钝化层118且暴露公共电极109的至少部分。用于第二钝化层118的材料的示例例如为SiNx、SiOx等无机绝缘材料或例如有机树脂等有机绝缘材料或其它适合的材料，本公开的实施例对此不做限定。例如，通过第四过孔204暴露第二电极202，通过第五过孔205以暴露第一电极201。例如，通过第六过孔304以暴露第四电极301和第五电极302至少之一。
如图6G所示，在形成第二钝化层118之后，例如可以在第二钝化层118上通过第十掩模工艺形成像素电极107、第一连接电极108、连接区200中的第二连接电极203、邦定区300的第三连接电极303等，第一连接电极108形成在阵列基板的显示区域D1内，像素电极107形成在阵列基板的显示区域D1的像素区域内。像素电极107通过第一过孔110与第一源漏极1043电连接，第一连接电极108通过第二过孔111和第三过孔112分别与触控引线106和公共电极109电连接，从而使得触控引线106与公共电极109电连接。第一连接电极108通过第二过孔111和第三过孔112把触控引线106与公共电极109电连接，避免了在公共电极109和触控引线106之间通过掩模工艺形成使两者直接电连接的过孔(例如，在平坦层117和第一钝化层116中形成过孔)，从而可以节省掩模工序，降低生产成本。用于像素电极107和第一连接电极108的材料的示例包括铝、铝合金、铜、铜合金、钼、钼合金、钛、钛合金、ITO、IZO或其它适合的材料，本公开的实施例对此不做限定。 例如，第二连接电极203通过第四过孔204和第五过孔205将第一电极201与第二电极202电连接。例如，第四电极301、第五电极302、第三连接电极303彼此电连接。
在本公开至少一个实施例提供的阵列基板100的制造方法中，在阵列基板100的显示区域D1内形成第一薄膜晶体管104，在阵列基板100的周边区域D2内形成第二薄膜晶体管103，且第一薄膜晶体管104为氧化物薄膜晶体管。由于氧化物薄膜晶体管具有迁移率高、稳定性好、电学均一性好、关态漏电流低等特点，因此可以改善包括该第一薄膜晶体管104的阵列基板100的显示装置中显示区域的对比度，降低显示装置的功率消耗，提高显示装置的显示画质。
另一方面，触控引线106与第一薄膜晶体管104的第一源漏极1043和第二源漏极1044形成在同一层，第一连接电极108与像素电极107形成在同一层，第一薄膜晶体管104的第一栅极1041与第二薄膜晶体管103的第一源漏极1033和第二源漏极1034形成在同一层，且第一连接电极108分别通过第二过孔111和第三过孔112将触控引线106与公共电极109电连接。在一实施例提供的制造方法中，基本上经过十次掩模工艺便可以形成阵列基板100，从而可以节省掩模工艺，降低生产成本。例如，每个掩模工艺中使用一张掩模板，即，采用十个掩模板即可完成阵列基板的制作。
例如，本公开的实施例中，在形成A的同时形成B可指在同一构图工艺中形成A和B。A、B可为阵列基板中的部件/元件。
这里应该理解的是，在本公开中，“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
应该理解，在本公开的实施例中，构图或构图工艺可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤等用于形成预定图形的工艺。
上面以水平电场型液晶显示装置的阵列基板为例对本公开实施例的制备方法进行了说明，但是如上所述，本公开的实施例不限于此，当需要形成根据本公开实施例的垂直电场型液晶显示装置的阵列基板或OLED显示装置的 阵列基板、电子纸显示装置的阵列基板时，根据这些阵列基板的结构，对制备方法的步骤进行适当修改即可，这些阵列基板的制备方法也在本公开的范围内。
本公开的实施例提供的制作方法的其它技术效果参见上述实施例描述的阵列基板的技术效果，在此不再赘述。
在不冲突的情况下，本公开的各个实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (20)

  1. 一种阵列基板，包括显示区域和周边区域，其中，
    所述显示区域包括像素区域，所述像素区域包括第一薄膜晶体管，所述第一薄膜晶体管包括第一有源层；
    所述周边区域包括第二薄膜晶体管，所述第二薄膜晶体管包括第二有源层；其中，
    所述第一有源层的材料包括氧化物半导体，所述第二有源层的材料包括多晶硅半导体。
  2. 如权利要求1所述的阵列基板，还包括衬底基板和位于所述衬底基板上的层间绝缘层，其中，
    所述第一薄膜晶体管的第一栅极和所述第一有源层均位于所述层间绝缘层的远离所述衬底基板的一侧，所述第二薄膜晶体管的第二栅极和所述第二有源层均位于所述层间绝缘层的靠近所述衬底基板的一侧。
  3. 如权利要求2所述的阵列基板，还包括位于所述层间绝缘层的远离所述衬底基板的一侧的第一钝化层以及位于所述第一钝化层的远离所述衬底基板的一侧第二钝化层，其中，
    所述像素区域还包括第一显示电极和第二显示电极，所述第一显示电极位于所述第一钝化层的远离所述衬底基板的一侧，且所述第二钝化层覆盖所述第一显示电极；
    所述第二显示电极位于所述第二钝化层的远离所述衬底基板的一侧，且通过所述第一钝化层和所述第二钝化层中的第一过孔与所述第一薄膜晶体管的第一源漏极电连接。
  4. 如权利要求3所述的阵列基板，其中，所述显示区域还包括触控引线，
    所述触控引线与所述第一薄膜晶体管的第一源漏极和第二源漏极或与所述第二薄膜晶体管的第一源漏极和第二源漏极位于同一层，且所述触控引线与所述第一显示电极电连接。
  5. 如权利要求4所述的阵列基板，其中，所述显示区域还包括第一连接电极，
    所述第一连接电极与所述第二显示电极位于同一层，且所述第一连接电极通过所述第一钝化层和所述第二钝化层中的第二过孔以及所述第二钝化层 中的第三过孔将所述触控引线与所述第一显示电极电连接。
  6. 如权利要求5所述的阵列基板，其中，所述第一连接电极与所述第二显示电极彼此绝缘。
  7. 如权利要求3-6任一所述的阵列基板，其中，所述周边区域至少包括GOA栅极驱动电路，所述GOA栅极驱动电路包括所述第二薄膜晶体管，所述第二薄膜晶体管的第二源漏极通过栅线与所述第一薄膜晶体管的第一栅极电连接，其中，
    所述第二薄膜晶体管的第一源漏极和第二源漏极与所述第一薄膜晶体管的第一栅极位于同一层；
    所述栅线与所述第二薄膜晶体管的第二栅极位于同一层。
  8. 如权利要求7所述的阵列基板，其中，所述栅线与所述第二栅极彼此绝缘。
  9. 如权利要求3-8任一所述的阵列基板，其中，所述周边区域还包括连接区，所述连接区包括第一电极、第二电极和第二连接电极，其中，
    所述第一电极与所述第一薄膜晶体管的第一源漏极和第二源漏极同层；
    所述第二电极与所述第二薄膜晶体管的第一源漏极和第二源漏极同层；
    所述第二连接电极与所述第二显示电极同层，且所述第二连接电极通过所述第一钝化层和所述第二钝化层中的第四过孔和第五过孔将所述第一电极与所述第二电极电连接。
  10. 如权利要求3-9任一所述的阵列基板，其中，所述周边区域还包括邦定区，所述邦定区包括第四电极、第五电极和第三连接电极，其中，
    所述第四电极与所述第二薄膜晶体管的第一源漏极和第二源漏极同层；
    所述第五电极与所述第二薄膜晶体管的第二栅极同层；
    所述第三连接电极与所述第二显示电极同层，且所述第四电极、第五电极、第三连接电极彼此电连接。
  11. 如权利要求2所述的阵列基板，还包括位于所述层间绝缘层的远离所述衬底基板的一侧的第一钝化层以及位于所述第一钝化层的远离所述衬底基板的一侧第二钝化层，其中，
    所述像素区域还包括第一显示电极和第二显示电极，所述第二显示电极位于所述第一钝化层的远离所述衬底基板的一侧，且所述第二钝化层覆盖所 述第二显示电极；所述第一显示电极位于所述第二钝化层的远离所述衬底基板的一侧；
    所述阵列基板还包括第四连接电极，所述第四连接电极与所述第一显示电极同层设置并彼此绝缘；且所述第二显示电极与所述第一薄膜晶体管的第一源漏极通过所述第四连接电极电连接。
  12. 一种显示面板，包括如权利要求1-11任一所述的阵列基板。
  13. 一种电子装置，包括如权利要求12所述的显示面板。
  14. 一种阵列基板的制造方法，所述阵列基板包括显示区域和周边区域，所述显示区域包括像素区域，所述方法包括：
    在所述像素区域形成第一薄膜晶体管，形成所述第一薄膜晶体管包括形成第一有源层；
    在所述周边区域形成第二薄膜晶体管，形成所述第二薄膜晶体管包括形成第二有源层，
    其中，所述第一有源层的材料包括氧化物半导体，所述第二有源层的材料包括多晶硅半导体。
  15. 如权利要求14所述的方法，其中，所述周边区域至少包括GOA栅极驱动电路，所述GOA栅极驱动电路包括所述第二薄膜晶体管，所述方法还包括：
    通过对第一导电薄膜进行构图以形成栅线和所述第二薄膜晶体管的第二栅极；以及
    通过对第二导电薄膜进行构图以形成所述第二薄膜晶体管的第一源漏极和第二源漏极和所述第一薄膜晶体管的第一栅极，其中，所述第二薄膜晶体管的第二源漏极与所述第一薄膜晶体管的第一栅极通过所述栅线电连接。
  16. 如权利要求15所述的方法，还包括：在所述显示区域形成触控引线，其中，
    通过对第三导电薄膜进行构图形成所述第一薄膜晶体管的第一源漏极和第二源漏极，并在形成所述第一薄膜晶体管的第一源漏极和第二源漏极的同时形成所述触控引线；或者
    在形成所述第二薄膜晶体管的第一源漏极和第二源漏极的同时形成所述触控引线。
  17. 如权利要求16所述的方法，其中，所述阵列基板还包括衬底基板，所述方法还包括：
    在所述衬底基板上依次形成第一钝化层和第二钝化层，以覆盖所述第一薄膜晶体管和所述第二薄膜晶体管；
    在所述像素区域内的所述第一钝化层和所述第二钝化层之间形成第一显示电极；
    形成所述第二钝化层后，采用刻蚀工艺形成第一过孔以暴露所述第一薄膜晶体管的第一源漏极，形成第二过孔以暴露所述触控引线，并形成第三过孔以暴露所述第一显示电极；
    形成第四导电薄膜，并对其进行构图以形成第二显示电极和第一连接电极；所述第二显示电极和所述第一连接电极彼此绝缘，所述第二显示电极通过所述第一过孔与所述第一薄膜晶体管的第一源漏极电连接，所述第一连接电极分别通过所述第二过孔和所述第三过孔与所述触控引线和所述第一显示电极电连接。
  18. 如权利要求17所述的方法，还包括在所述周边区的连接区形成第一电极和第二电极；在形成所述第一薄膜晶体管的第一源漏极和第二源漏极的同时形成所述第一电极，在形成所述第二薄膜晶体管的第一源漏极和第二源漏极的同时形成所述第二电极；
    形成所述第一过孔、所述第二过孔和所述第三过孔的同时形成第四过孔以暴露所述第二电极，并形成第五过孔以暴露所述第一电极；以及
    在形成所述第二显示电极的同时形成第二连接电极，且所述第二连接电极通过所述第四过孔和所述第五过孔将所述第一电极与所述第二电极电连接。
  19. 如权利要求18所述的方法，还包括在所述周边区的邦定区形成第四电极和第五电极，在形成所述第二薄膜晶体管的第一源漏极和第二源漏极的同时形成所述第四电极；在形成所述第二薄膜晶体管的第二栅极的同时形成所述第五电极；
    形成所述第一过孔、所述第二过孔、所述第三过孔、所述第四过孔和所述第五过孔的同时形成第六过孔以暴露所述第四电极和所述第五电极至少之一；以及
    在形成所述第二显示电极的同时形成第三连接电极；所述第四电极、所述第五电极和所述第三连接电极彼此电连接。
  20. 如权利要求19所述的方法，其中，所述第一过孔、所述第二过孔、所述第三过孔、所述第四过孔、所述第五过孔和所述第六过孔采用同一掩模板形成。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111384070A (zh) * 2020-03-25 2020-07-07 京东方科技集团股份有限公司 一种像素结构、阵列基板、显示装置和制作方法
TWI775125B (zh) * 2020-01-14 2022-08-21 友達光電股份有限公司 顯示裝置
CN116185232A (zh) * 2023-04-28 2023-05-30 惠科股份有限公司 一种阵列基板及触控显示面板

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101643835B1 (ko) * 2009-07-10 2016-07-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제조 방법
CN108598087B (zh) 2018-04-26 2021-01-15 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板、电子装置
CN109309101B (zh) * 2018-10-25 2020-12-04 昆山国显光电有限公司 显示面板及显示装置
CN109887932B (zh) * 2019-02-26 2021-11-02 武汉华星光电半导体显示技术有限公司 阵列基板及其制作方法、显示装置
WO2020210939A1 (zh) * 2019-04-15 2020-10-22 京东方科技集团股份有限公司 触控显示基板及其制作方法、显示装置
CN110137183A (zh) * 2019-04-23 2019-08-16 深圳市华星光电技术有限公司 阵列基板及其制造方法
CN110047854B (zh) * 2019-05-08 2021-02-23 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置
CN110349973B (zh) * 2019-06-24 2022-07-12 武汉华星光电技术有限公司 阵列基板及其制作方法、显示装置
US11900884B2 (en) 2019-08-21 2024-02-13 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate having a scan driving circuit with a plurality of shift registers and manufacturing method thereof, display device
JP2022551772A (ja) 2019-08-21 2022-12-14 京東方科技集團股▲ふん▼有限公司 表示基板及びその製造方法、表示装置
CN110600520A (zh) * 2019-09-19 2019-12-20 昆山工研院新型平板显示技术中心有限公司 一种显示面板及显示装置
US11869897B2 (en) * 2020-03-24 2024-01-09 Boe Technology Group Co., Ltd. Array substrate, display apparatus, and method of fabricating array substrate
CN110828477A (zh) * 2019-10-28 2020-02-21 武汉华星光电技术有限公司 一种阵列基板、其制备方法及其显示面板
CN110854137B (zh) * 2019-11-22 2022-12-02 京东方科技集团股份有限公司 显示面板、阵列基板及其制造方法
US11937470B2 (en) * 2020-05-07 2024-03-19 Chengdu Boe Optoelectronics Technology Co., Ltd. Array substrate and display device
CN111785757B (zh) * 2020-07-14 2022-07-05 京东方科技集团股份有限公司 显示装置、显示面板及其制造方法
CN111754920A (zh) * 2020-07-17 2020-10-09 武汉华星光电半导体显示技术有限公司 像素驱动电路及其驱动方法、显示面板
CN111856825B (zh) * 2020-07-28 2023-10-20 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板及显示装置
CN115472626A (zh) * 2021-05-24 2022-12-13 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN113571531B (zh) * 2021-07-12 2023-10-03 武汉华星光电技术有限公司 阵列基底及其制作方法
CN113611712B (zh) * 2021-07-29 2023-10-17 武汉华星光电技术有限公司 阵列基板、显示面板及其制作方法
CN116472514A (zh) * 2021-09-01 2023-07-21 京东方科技集团股份有限公司 阵列基板及显示装置
CN113985662B (zh) * 2021-11-02 2023-07-04 深圳市华星光电半导体显示技术有限公司 显示面板、阵列基板及其制造方法
WO2024065235A1 (zh) * 2022-09-28 2024-04-04 京东方科技集团股份有限公司 显示基板及其制备方法和显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104538352A (zh) * 2014-12-31 2015-04-22 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN104867937A (zh) * 2014-02-24 2015-08-26 乐金显示有限公司 薄膜晶体管基板和使用该薄膜晶体管基板的显示装置
CN106200064A (zh) * 2015-05-29 2016-12-07 乐金显示有限公司 In-cell触摸液晶显示装置及其制造方法
US9568800B1 (en) * 2015-02-03 2017-02-14 Amazon Technologies, Inc. Thin border displays
CN108598087A (zh) * 2018-04-26 2018-09-28 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板、电子装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007133294A (ja) * 2005-11-14 2007-05-31 Epson Imaging Devices Corp 液晶装置及び電子機器
KR101799529B1 (ko) * 2011-04-21 2017-12-20 엘지디스플레이 주식회사 터치센서 인셀 타입 액정표시장치용 어레이 기판 및 이의 제조방법
CN103226272B (zh) * 2013-04-16 2015-07-22 合肥京东方光电科技有限公司 一种阵列基板及其制备方法、显示装置
WO2015052991A1 (ja) * 2013-10-09 2015-04-16 シャープ株式会社 半導体装置およびその製造方法
US9753590B2 (en) * 2014-06-13 2017-09-05 Lg Display Co., Ltd. Display device integrated with touch screen panel and method of fabricating the same
KR20160006880A (ko) * 2014-07-09 2016-01-20 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
KR102363840B1 (ko) * 2015-07-28 2022-02-16 엘지디스플레이 주식회사 터치 표시 장치의 박막트랜지스터를 포함하는 기판
CN105573549B (zh) * 2015-12-08 2018-12-25 上海天马微电子有限公司 阵列基板、触控屏和触控显示装置及其制作方法
TWI561891B (en) * 2016-01-04 2016-12-11 Au Optronics Corp Pixel array substrate
US11107429B2 (en) * 2017-03-27 2021-08-31 Sharp Kabushiki Kaisha Active matrix substrate, liquid crystal display device, and organic EL display device
CN106847834B (zh) * 2017-03-30 2019-05-10 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板
CN107863354A (zh) * 2017-10-20 2018-03-30 武汉华星光电技术有限公司 阵列基板及其制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104867937A (zh) * 2014-02-24 2015-08-26 乐金显示有限公司 薄膜晶体管基板和使用该薄膜晶体管基板的显示装置
CN104538352A (zh) * 2014-12-31 2015-04-22 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
US9568800B1 (en) * 2015-02-03 2017-02-14 Amazon Technologies, Inc. Thin border displays
CN106200064A (zh) * 2015-05-29 2016-12-07 乐金显示有限公司 In-cell触摸液晶显示装置及其制造方法
CN108598087A (zh) * 2018-04-26 2018-09-28 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板、电子装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI775125B (zh) * 2020-01-14 2022-08-21 友達光電股份有限公司 顯示裝置
CN111384070A (zh) * 2020-03-25 2020-07-07 京东方科技集团股份有限公司 一种像素结构、阵列基板、显示装置和制作方法
CN116185232A (zh) * 2023-04-28 2023-05-30 惠科股份有限公司 一种阵列基板及触控显示面板

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