WO2019200666A1 - 一种有机发光显示装置 - Google Patents

一种有机发光显示装置 Download PDF

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Publication number
WO2019200666A1
WO2019200666A1 PCT/CN2018/089411 CN2018089411W WO2019200666A1 WO 2019200666 A1 WO2019200666 A1 WO 2019200666A1 CN 2018089411 W CN2018089411 W CN 2018089411W WO 2019200666 A1 WO2019200666 A1 WO 2019200666A1
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layer
cavity
electrode
auxiliary electrode
disposed
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English (en)
French (fr)
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卢马才
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US16/203,856 priority Critical patent/US10510818B2/en
Publication of WO2019200666A1 publication Critical patent/WO2019200666A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H10K50/8445—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an organic light emitting display device.
  • an organic light emitting display device is a self-luminous display device, which has the advantages of lightness, power saving, fast response, and the like, and has excellent viewing angle and contrast.
  • an organic light emitting display device is composed of an array substrate and an OLED light emitting device disposed above the array substrate, the OLED light emitting device including an anode, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer electron injection layer, and a cathode; Among them, the anode, the hole injection layer, the hole transport layer, the light-emitting layer, the electron transport layer, and the electron injection layer are formed as an OLED semiconductor layer.
  • the organic light emitting display device includes a top emission type, a bottom emission type, and a dual emission type according to the light emission direction.
  • the top emission type the organic light-emitting display device emits light in the opposite direction to the array substrate on which the sub-pixels are disposed. Since the structure can satisfy the aperture ratio requirement of the large-area high-resolution OLED panel, it is often applied to large-area high-resolution. Degree on the OLED panel. However, since the cathode of the OLED light-emitting device on the organic light-emitting display device has a high resistivity, a severe voltage drop phenomenon occurs, and once the organic light-emitting display device is powered on, unevenness in brightness or image quality is caused.
  • the array substrate 1 metal / groove connection electrode 1112 / above 21/1 / is formed of a horizontal plane, such that the cathode 43 / the semiconductor layer on an OLED / can enter the recess 21 / cavity above the metal connection electrode 1112 / and through the metal connection electrode 1112 / connected to the array substrate 1 / auxiliary electrode 122 / to reduce the cathode 4 / resistance to reduce the pressure drop .
  • the inventors have found that the pixel defining layer 2 / and the inverted trapezoidal column a of the organic light-emitting display device in the above method need to form a vertical inverted trapezoidal structure by double exposure and development, which is complicated and time consuming.
  • the technical problem to be solved by the embodiments of the present invention is to provide an organic light emitting display device that not only omits the inverted trapezoidal column to simplify the process, but also improves the conductivity of the cathode on the OLED semiconductor layer, thereby reducing the voltage drop. purpose.
  • an organic light emitting display device including:
  • An array substrate the array substrate includes a pixel electrode and a metal connection electrode and an auxiliary electrode located around the pixel electrode; wherein the metal connection electrode is electrically connected to the auxiliary electrode through a recess formed in the array substrate
  • the recessed hole is located above the auxiliary electrode, and is formed with a first cavity and a second cavity that communicate with each other, and the first cavity is away from the pixel electrode from the second cavity
  • the edge line extends in a direction away from the pixel electrode;
  • a pixel defining layer disposed on the array substrate; wherein the pixel defining layer respectively has a corresponding recess above the recessed hole and the pixel electrode of the array substrate;
  • An OLED semiconductor layer disposed on the array substrate and the pixel defining layer; wherein the OLED semiconductor layer further covers the pixel electrode and the metal connecting electrode and extends to the first of the recessed holes Electrically connecting the auxiliary electrode in the cavity;
  • a cathode disposed on the OLED semiconductor layer; wherein the cathode further extends into the first cavity of the recess to electrically connect with the auxiliary electrode, and is discontinuous with the recess as a break point Connection Status.
  • the array substrate is a TFT array substrate with a double gate structure, and includes:
  • a bottom gate disposed on the base substrate and the auxiliary electrode
  • the buffer layer is provided with a first conductive hole penetrating through the upper surface of the buffer layer and communicating with the auxiliary electrode;
  • An active layer disposed on the buffer layer
  • a gate insulating layer disposed on the active layer
  • a top gate disposed on the gate insulating layer
  • An intermediate dielectric layer covering the active layer, the gate insulating layer, the top gate, and the buffer layer; wherein the intermediate dielectric layer is provided with an upper and lower surface penetrating the intermediate dielectric layer and the first conductive layer a second conductive hole communicating with the hole, and a third conductive hole and a fourth conductive hole penetrating through the upper surface of the intermediate dielectric layer and communicating with the active layer respectively;
  • a source, a drain, and a metal line disposed on the intermediate dielectric layer; wherein the source is electrically connected to the active layer through the third conductive via and the drain passes through the The fourth conductive via is electrically connected to the active layer; or the source is electrically connected to the active layer through the fourth conductive via and the drain passes through the third conductive via and the The source layer is electrically connected; the metal line is electrically connected to the auxiliary electrode through the second conductive hole and the first conductive hole;
  • the flat layer is provided with a fifth layer penetrating the upper surface of the flat layer and communicating with the source or the drain a conductive hole, and the recessed hole communicating with the metal wire;
  • the pixel electrode disposed on the flat layer, electrically connected to the source or the drain through the fifth conductive hole, and connected to the metal through the recessed hole
  • the auxiliary electrode realizes the metal connection electrode electrically connected
  • the OLED semiconductor layer and the cathode are connected to the metal through the recessed holes, and then electrically connected to the auxiliary electrode.
  • the flat layer is a single layer structure prepared from an organic material; wherein the fifth conductive hole, the first cavity and the second cavity of the recess are both disposed in the single layer structure On a flat layer; or
  • a laminated structure in which an inorganic passivation layer prepared from an inorganic material and an organic flat layer prepared from an organic material are superposed; wherein the fifth conductive hole penetrates the upper and lower surfaces of the organic flat layer and penetrates In the inorganic passivation layer, a first cavity of the recessed hole is disposed on the inorganic passivation layer, and a second cavity of the recessed hole is disposed on an organic flat layer above the inorganic passivation layer .
  • the inorganic material is one of SiOx, SiNx, and SiNO; and the organic material is polymethyl methacrylate PMMA or siloxane.
  • the buffer layer is a single layer structure prepared by one of SiOx, SiNx, and SiNO; or a stacked structure prepared by SiNx/SiOx.
  • the active layer is prepared by using indium gallium zinc oxide IGZO or low temperature polysilicon LTPS.
  • the pixel electrode and the auxiliary electrode are both made of one of ITO/Ag/ITO, IZO/Ag/IZO, AZO/Ag/AZO.
  • the present invention also provides another organic light emitting display device, including:
  • An array substrate the array substrate includes a pixel electrode and a metal connection electrode and an auxiliary electrode located around the pixel electrode; wherein the metal connection electrode is electrically connected to the auxiliary electrode through a recess formed in the array substrate
  • the recessed hole is located above the auxiliary electrode, and is formed with a first cavity and a second cavity that communicate with each other, and the first cavity is away from the pixel electrode from the second cavity
  • the edge line extends in a direction away from the pixel electrode;
  • a pixel defining layer disposed on the array substrate; wherein the pixel defining layer respectively has a corresponding recess above the recessed hole and the pixel electrode of the array substrate;
  • An OLED semiconductor layer disposed on the array substrate and the pixel defining layer; wherein the OLED semiconductor layer further covers the pixel electrode and the metal connecting electrode and extends to the first of the recessed holes Electrically connecting the auxiliary electrode in the cavity;
  • a cathode disposed on the OLED semiconductor layer; wherein the cathode further extends into the first cavity of the recess to electrically connect with the auxiliary electrode, and is discontinuous with the recess as a break point Connection Status;
  • the array substrate is a TFT array substrate with a top gate structure, and includes:
  • a light barrier layer disposed on the base substrate and the auxiliary electrode
  • the buffer layer covering the substrate substrate, the light barrier layer, and the auxiliary electrode; wherein the buffer layer is provided with a first conductive hole penetrating through the upper surface of the buffer layer and communicating with the auxiliary electrode;
  • An active layer disposed on the buffer layer
  • a gate insulating layer disposed on the active layer
  • a top gate disposed on the gate insulating layer
  • An intermediate dielectric layer covering the active layer, the gate insulating layer, the top gate, and the buffer layer; wherein the intermediate dielectric layer is provided with an upper and lower surface penetrating the intermediate dielectric layer and the first conductive layer a second conductive hole communicating with the hole, and a third conductive hole and a fourth conductive hole penetrating through the upper surface of the intermediate dielectric layer and communicating with the active layer respectively;
  • a source, a drain, and a metal line disposed on the intermediate dielectric layer; wherein the source is electrically connected to the active layer through the third conductive via and the drain passes through the The fourth conductive via is electrically connected to the active layer; or the source is electrically connected to the active layer through the fourth conductive via and the drain passes through the third conductive via and the The source layer is electrically connected; the metal line is electrically connected to the auxiliary electrode through the second conductive hole and the first conductive hole;
  • the flat layer is provided with a fifth layer penetrating the upper surface of the flat layer and communicating with the source or the drain a conductive hole, and the recessed hole communicating with the metal wire;
  • the pixel electrode disposed on the flat layer, electrically connected to the source or the drain through the fifth conductive hole, and connected to the metal through the recessed hole
  • the auxiliary electrode realizes the metal connection electrode electrically connected
  • the OLED semiconductor layer and the cathode are connected to the metal through the recessed holes, and then electrically connected to the auxiliary electrode.
  • the flat layer is a single layer structure prepared from an organic material; wherein the fifth conductive hole, the first cavity and the second cavity of the recess are both disposed in the single layer structure On a flat layer; or
  • a laminated structure in which an inorganic passivation layer prepared from an inorganic material and an organic flat layer prepared from an organic material are superposed; wherein the fifth conductive hole penetrates the upper and lower surfaces of the organic flat layer and penetrates In the inorganic passivation layer, a first cavity of the recessed hole is disposed on the inorganic passivation layer, and a second cavity of the recessed hole is disposed on an organic flat layer above the inorganic passivation layer .
  • the inorganic material is one of SiOx, SiNx, and SiNO; and the organic material is polymethyl methacrylate PMMA or siloxane.
  • the buffer layer is a single layer structure prepared by one of SiOx, SiNx, and SiNO; or a stacked structure prepared by SiNx/SiOx.
  • the active layer is prepared by using indium gallium zinc oxide IGZO or low temperature polysilicon LTPS.
  • the pixel electrode and the auxiliary electrode are both made of one of ITO/Ag/ITO, IZO/Ag/IZO, AZO/Ag/AZO.
  • the present invention further provides another organic light emitting display device, including:
  • An array substrate the array substrate includes a pixel electrode and a metal connection electrode and an auxiliary electrode located around the pixel electrode; wherein the metal connection electrode is electrically connected to the auxiliary electrode through a recess formed in the array substrate
  • the recessed hole is located above the auxiliary electrode, and is formed with a first cavity and a second cavity that communicate with each other, and the first cavity is away from the pixel electrode from the second cavity
  • the edge line extends in a direction away from the pixel electrode;
  • a pixel defining layer disposed on the array substrate; wherein the pixel defining layer respectively has a corresponding recess above the recessed hole and the pixel electrode of the array substrate;
  • An OLED semiconductor layer disposed on the array substrate and the pixel defining layer; wherein the OLED semiconductor layer further covers the pixel electrode and the metal connecting electrode and extends to the first of the recessed holes Electrically connecting the auxiliary electrode in the cavity;
  • a cathode disposed on the OLED semiconductor layer; wherein the cathode further extends into the first cavity of the recess to electrically connect with the auxiliary electrode, and is discontinuous with the recess as a break point Connection Status;
  • the array substrate is a TFT array substrate of a bottom gate structure, and includes:
  • a bottom gate disposed on the base substrate and the auxiliary electrode
  • the buffer layer is provided with a first conductive hole penetrating through the upper surface of the buffer layer and communicating with the auxiliary electrode;
  • An active layer disposed on the buffer layer
  • An intermediate dielectric layer covering the active layer and the buffer layer; wherein the intermediate dielectric layer is provided with a second conductive layer penetrating through the upper and lower surfaces of the intermediate dielectric layer and communicating with the first conductive via a hole, and a third conductive hole and a fourth conductive hole penetrating through the upper surface of the intermediate dielectric layer and communicating with the active layer respectively;
  • a source, a drain, and a metal line disposed on the intermediate dielectric layer; wherein the source is electrically connected to the active layer through the third conductive via and the drain passes through the The fourth conductive via is electrically connected to the active layer; or the source is electrically connected to the active layer through the fourth conductive via and the drain passes through the third conductive via and the The source layer is electrically connected; the metal line is electrically connected to the auxiliary electrode through the second conductive hole and the first conductive hole;
  • the flat layer is provided with a fifth layer penetrating the upper surface of the flat layer and communicating with the source or the drain a conductive hole, and the recessed hole communicating with the metal wire;
  • the pixel electrode disposed on the flat layer, electrically connected to the source or the drain through the fifth conductive hole, and connected to the metal through the recessed hole
  • the auxiliary electrode realizes the metal connection electrode electrically connected
  • the OLED semiconductor layer and the cathode are connected to the metal through the recessed holes, and then electrically connected to the auxiliary electrode.
  • the flat layer is a single layer structure prepared from an organic material; wherein the fifth conductive hole, the first cavity and the second cavity of the recess are both disposed in the single layer structure On a flat layer; or
  • a laminated structure in which an inorganic passivation layer prepared from an inorganic material and an organic flat layer prepared from an organic material are superposed; wherein the fifth conductive hole penetrates the upper and lower surfaces of the organic flat layer and penetrates In the inorganic passivation layer, a first cavity of the recessed hole is disposed on the inorganic passivation layer, and a second cavity of the recessed hole is disposed on an organic flat layer above the inorganic passivation layer .
  • the inorganic material is one of SiOx, SiNx, and SiNO; and the organic material is polymethyl methacrylate PMMA or siloxane.
  • the buffer layer is a single layer structure prepared by one of SiOx, SiNx, and SiNO; or a stacked structure prepared by SiNx/SiOx.
  • the active layer is prepared by using indium gallium zinc oxide IGZO or low temperature polysilicon LTPS.
  • the pixel electrode and the auxiliary electrode are both made of one of ITO/Ag/ITO, IZO/Ag/IZO, AZO/Ag/AZO.
  • the embodiments of the present invention have the following beneficial effects: Compared with the conventional organic light-emitting display device, the present invention realizes a discontinuous connection state of the cathode on the OLED semiconductor layer through the recessed holes formed in the array substrate, thereby effectively reducing the resistance of the cathode. And the cathode can be extended into the recessed hole to make electrical connection with the auxiliary electrode, thereby achieving the purpose of not only improving the conductivity of the cathode on the OLED semiconductor layer but also reducing the voltage drop; at the same time, saving the traditional organic light-emitting display device
  • the inverted trapezoidal structure column foot simplifies the process process and saves time and effort.
  • FIG. 1 is a cross-sectional view of a prior art organic light emitting display device
  • FIG. 2 is a cross-sectional view showing an organic light emitting display device according to Embodiment 1 of the present invention
  • FIG. 3 is a cross-sectional view showing another organic light emitting display device according to Embodiment 2 of the present invention.
  • FIG. 4 is a cross-sectional view showing still another organic light emitting display device according to Embodiment 3 of the present invention.
  • FIG. 5 is a flowchart of a method for fabricating an organic light emitting display device according to Embodiment 1 of the present invention.
  • an organic light-emitting display device is a structure of the TFT array substrate in which the array substrate is a double-gate structure in the organic light-emitting display device, and specifically includes:
  • the array substrate 1 includes a pixel electrode 1111 and a metal connection electrode 1112 and an auxiliary electrode 122 around the pixel electrode 1111.
  • the metal connection electrode 1112 is electrically connected to the auxiliary electrode 122 through the recess 112 and the auxiliary electrode 122 formed on the array substrate 1.
  • the recessed hole 112 is located above the auxiliary electrode 122, and is formed with a first cavity 1121 and a second cavity 1122 that communicate with each other, and the first cavity 1121 is away from the edge of the second cavity 1122 away from the side of the pixel electrode 1111.
  • the line extends in a direction away from the pixel electrode 1111, so that the cavity size in the horizontal length direction of the array substrate 1 can be expanded by expanding the recessed hole 112, so that the metal connection electrode 1112 and other conductive substances enter the concave hole 112 more favorably. in;
  • a pixel defining layer 2 disposed on the array substrate 1; wherein the pixel defining layer 2 respectively has a corresponding recess 21 above the recessed hole 112 and the pixel electrode 1111 of the array substrate 1 to facilitate the pixel electrode 1111 and the metal connection
  • the electrode 1112 is received in the recess 21 corresponding to the pixel defining layer 2 to prevent the OLED light emitting device from being connected to the pixel electrode 1111 and the metal connecting electrode 1112 to affect the normal illumination of the OLED light emitting device;
  • the OLED semiconductor layer 3 is disposed on the array substrate 1 and the pixel defining layer 2; wherein the OLED semiconductor layer 3 also covers the pixel electrode 1111 and the metal connecting electrode 1112, and extends into the first cavity 1121 of the recess 112.
  • the auxiliary electrode 122 is electrically connected;
  • a cathode 4 disposed on the OLED semiconductor layer 3; wherein the cathode 4 further extends into the first cavity 1121 of the recessed hole 112 to be electrically connected to the auxiliary electrode 122, and is discontinuously connected with the recessed hole 112 as a break point.
  • the cathode 4 is reduced in length to reduce the electrical resistance of the cathode 4.
  • the cavity diameter of the second cavity 1122 in the recessed hole 112 is smaller than the cavity diameter of the first cavity 1121, and the edge line of the second cavity 1122 on the side away from the pixel electrode 1111 is located in the first space.
  • the cross section of the recessed hole 112 may have an "L" shape or a " ⁇ " type, as long as the metal connection electrode 1112, the OLED semiconductor layer 3, and the cathode 4 can be realized with the auxiliary electrode 1112.
  • the requirement of electrical connection can achieve the purpose of improving the conductivity of the cathode 4 on the OLED semiconductor layer 3, and at the same time, the cathode 4 is discontinuously connected with the recessed holes 112 as a break point, so that the overall length of the cathode 4 is reduced, thereby reducing the cathode. 4 resistance.
  • the auxiliary electrode 1112 may be formed by cascading a plurality of metal layers, or may be formed by a single metal layer, and no matter which layer is disposed on the array substrate 1, as long as the concave holes 112 can be assisted.
  • the metal connection electrode 1112 can be electrically connected to the auxiliary electrode 122 through the recess 112 formed in the array substrate 1.
  • the OLED semiconductor layer 3 is formed of an anode, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, and the cathode 4 corresponds to the OLED semiconductor layer 3.
  • the auxiliary electrode 122 in the TFT array substrate of the double-gate structure in the organic light-emitting display device has a multi-level connection structure, and the TFT array substrate of the double-gate structure specifically includes:
  • a base substrate 11 which may be a glass substrate or a plastic substrate;
  • auxiliary electrode 122 disposed on the base substrate 11, and the auxiliary electrode 122 is disposed on the penultimate layer;
  • the buffer layer 13 is a single layer structure prepared by one of SiOx, SiNx, and SiNO; or a stacked structure prepared by SiNx/SiOx;
  • the gate insulating layer 15 is made of an inorganic material, and the inorganic material is one of SiOx, SiNx, and SiNO;
  • top gate 16 disposed on the gate insulating layer 15;
  • the second conductive hole 171 and the first conductive hole 131 are electrically connected to the auxiliary electrode 122 in sequence.
  • the metal connection electrode 1112, the OLED semiconductor layer 3 and the cathode 4 are connected to the auxiliary electrode 1112 as long as they are connected to the metal connection 183. Realize electrical connection;
  • a flat layer 19 covering the source electrode 181, the drain electrode 182, and the metal wiring 183; wherein the flat layer 19 is provided with a fifth conductive hole penetrating through the upper surface of the flat layer 19 and communicating with the source electrode 181 or the drain electrode 182. 191, and a recess 112 in communication with the metal line 183;
  • the pixel electrode 1111 is electrically connected to the source electrode 181 or the drain electrode 183 through the fifth conductive hole 191, and is electrically connected to the auxiliary electrode 122.
  • the OLED semiconductor layer 3 and the cathode 4 are both electrically connected to the auxiliary electrode 122 through the recessed holes 112 and then connected to the metal wiring 183.
  • the pixel electrode 1111 and the auxiliary electrode 1112 may be formed of a conductive metal oxide of a single layer structure, or may be a laminated structure of a metal and a metal oxide.
  • the pixel electrode 1111 and the auxiliary electrode 1112 are both single-layer structures including, but not limited to, ITO, IZO, and the like.
  • the pixel electrode 1111 and the auxiliary electrode 1112 are laminated, and are made of one of ITO/Ag/ITO, IZO/Ag/IZO, AZO/Ag/AZO.
  • the flat layer 19 may be a single layer structure or a laminated structure.
  • the flat layer 19 of the single-layer structure the flat layer 19 is made of an organic material.
  • the fifth conductive hole 191, the first cavity 1121 and the second cavity 1122 of the recess 112 are all disposed in a single layer structure.
  • the flat layer 19 is formed by superposing an inorganic passivation layer 192 made of an inorganic material and an organic flat layer 193 made of an organic material;
  • the fifth conductive via 191 penetrates the upper and lower surfaces of the organic flat layer 193 and penetrates into the inorganic passivation layer 192.
  • the first cavity 1121 of the recess 112 is disposed on the inorganic passivation layer 192, and the second cavity 1122 of the recess 112 is disposed.
  • the inorganic material is one of SiOx, SiNx, SiNO; the organic material includes, but is not limited to, polymethyl methacrylate PMMA and siloxane.
  • another embodiment of the present invention provides a structure of the organic light-emitting display device in which the array substrate is a top-gate TFT array substrate, and specifically includes:
  • the array substrate 1 includes a pixel electrode 1111 and a metal connection electrode 1112 and an auxiliary electrode 122 around the pixel electrode 1111.
  • the metal connection electrode 1112 is electrically connected to the auxiliary electrode 122 through the recess 112 and the auxiliary electrode 122 formed on the array substrate 1.
  • the recessed hole 112 is located above the auxiliary electrode 122, and is formed with a first cavity 1121 and a second cavity 1122 that communicate with each other, and the first cavity 1121 is away from the side of the second cavity 1122 away from the pixel electrode 1111.
  • the edge line extends in a direction away from the pixel electrode 1111, so that the cavity size in the horizontal length direction of the array substrate 1 can be expanded by expanding the recessed hole 112, so that the metal connection electrode 1112 and other conductive substances enter the recessed hole more favorably. 112;
  • a pixel defining layer 2 disposed on the array substrate 1; wherein the pixel defining layer 2 respectively has a corresponding recess 21 above the recessed hole 112 and the pixel electrode 1111 of the array substrate 1 to facilitate the pixel electrode 1111 and the metal connection
  • the electrode 1112 is received in the recess 21 corresponding to the pixel defining layer 2 to prevent the OLED light emitting device from being connected to the pixel electrode 1111 and the metal connecting electrode 1112 to affect the normal illumination of the OLED light emitting device;
  • the OLED semiconductor layer 3 is disposed on the array substrate 1 and the pixel defining layer 2; wherein the OLED semiconductor layer 3 also covers the pixel electrode 1111 and the metal connecting electrode 1112, and extends into the first cavity 1121 of the recess 112.
  • the auxiliary electrode 122 is electrically connected;
  • a cathode 4 disposed on the OLED semiconductor layer 3; wherein the cathode 4 further extends into the first cavity 1121 of the recessed hole 112 to be electrically connected to the auxiliary electrode 122, and is discontinuously connected with the recessed hole 112 as a break point.
  • the cathode 4 is reduced in length to reduce the electrical resistance of the cathode 4.
  • the cavity diameter of the second cavity 1122 in the recessed hole 112 is smaller than the cavity diameter of the first cavity 1121, and the edge line of the second cavity 1122 on the side away from the pixel electrode 1111 is located in the first space.
  • the cross section of the recessed hole 112 may be in the form of "L" type or " ⁇ " type, as long as the metal connection electrode 1112, the OLED semiconductor layer 3 and the cathode 4 can be realized with the auxiliary electrode 1112.
  • the requirement of electrical connection can achieve the purpose of improving the conductivity of the cathode 4 on the OLED semiconductor layer 3, and at the same time, the cathode 4 is discontinuously connected with the recessed holes 112 as a break point, so that the overall length of the cathode 4 is reduced, thereby reducing the cathode. 4 resistance.
  • the auxiliary electrode 1112 may be formed by cascading a plurality of metal layers, or may be formed by a single metal layer, and no matter which layer is disposed on the array substrate 1, as long as the concave holes 112 can be assisted.
  • the metal connection electrode 1112 can be electrically connected to the auxiliary electrode 122 through the recess 112 formed in the array substrate 1.
  • the OLED semiconductor layer 3 is formed of an anode, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, and the cathode 4 corresponds to the OLED semiconductor layer 3.
  • the TFT array substrate of the top gate structure in the second embodiment of the present invention is different from the difference in the TFT array substrate of the double gate structure in the first embodiment of the present invention.
  • the bottom gate 121 of the TFT array substrate of the double gate structure in the first embodiment of the present invention is disposed as the light barrier layer 121, and other components and the TFT array of the double gate structure in the first embodiment of the present invention.
  • the substrate has the same structure and connection relationship. For details, refer to the relevant parts of the TFT array substrate of the double-gate structure in the first embodiment of the present invention, and therefore no further details are provided herein.
  • the flat layer 19 of the TFT array substrate of the top gate structure may have a single layer structure or a stacked structure.
  • the flat layer 19 of the single-layer structure the flat layer 19 is made of an organic material, and the first conductive hole 191 and the first cavity 1121 and the second cavity 1122 of the recessed hole 112 are both disposed in a single layer structure.
  • the flat layer 19 is formed by superposing an inorganic passivation layer 192 made of an inorganic material and an organic flat layer 193 made of an organic material;
  • the fifth conductive holes 191 penetrate through the upper and lower surfaces of the organic flat layer 193 and penetrate into the inorganic passivation layer 192.
  • the first cavity 1121 of the recess 112 is disposed on the inorganic passivation layer 192, and the second cavity 1122 of the recess 112 is disposed.
  • the inorganic material is one of SiOx, SiNx, SiNO; the organic material includes, but is not limited to, polymethyl methacrylate PMMA and siloxane.
  • another embodiment of the present invention provides a structure of the organic light-emitting display device in which the array substrate of the organic light-emitting display device is a bottom-gate TFT array substrate, and specifically includes:
  • the array substrate 1 includes a pixel electrode 1111 and a metal connection electrode 1112 and an auxiliary electrode 122 around the pixel electrode 1111.
  • the metal connection electrode 1112 is electrically connected to the auxiliary electrode 122 through the recess 112 and the auxiliary electrode 122 formed on the array substrate 1.
  • the recessed hole 112 is located above the auxiliary electrode 122, and is formed with a first cavity 1121 and a second cavity 1122 that communicate with each other, and the first cavity 1121 is away from the side of the second cavity 1122 away from the pixel electrode 1111.
  • the edge line extends in a direction away from the pixel electrode 1111, so that the cavity size in the horizontal length direction of the array substrate 1 can be expanded by expanding the recessed hole 112, so that the metal connection electrode 1112 and other conductive substances enter the recessed hole more favorably. 112;
  • a pixel defining layer 2 disposed on the array substrate 1; wherein the pixel defining layer 2 respectively has a corresponding recess 21 above the recessed hole 112 and the pixel electrode 1111 of the array substrate 1 to facilitate the pixel electrode 1111 and the metal connection
  • the electrode 1112 is received in the recess 21 corresponding to the pixel defining layer 2 to prevent the OLED light emitting device from being connected to the pixel electrode 1111 and the metal connecting electrode 1112 to affect the normal illumination of the OLED light emitting device;
  • the OLED semiconductor layer 3 is disposed on the array substrate 1 and the pixel defining layer 2; wherein the OLED semiconductor layer 3 also covers the pixel electrode 1111 and the metal connecting electrode 1112, and extends into the first cavity 1121 of the recess 112.
  • the auxiliary electrode 122 is electrically connected;
  • a cathode 4 disposed on the OLED semiconductor layer 3; wherein the cathode 4 further extends into the first cavity 1121 of the recessed hole 112 to be electrically connected to the auxiliary electrode 122, and is discontinuously connected with the recessed hole 112 as a break point.
  • the cathode 4 is reduced in length to reduce the electrical resistance of the cathode 4.
  • the cavity diameter of the second cavity 1122 in the recessed hole 112 is smaller than the cavity diameter of the first cavity 1121, and the edge line of the second cavity 1122 on the side away from the pixel electrode 1111 is located in the first space.
  • the cross section of the recessed hole 112 may have an "L" shape or a " ⁇ " type, as long as the metal connection electrode 1112, the OLED semiconductor layer 3, and the cathode 4 can be realized with the auxiliary electrode 1112.
  • the requirement of electrical connection can achieve the purpose of improving the conductivity of the cathode 4 on the OLED semiconductor layer 3, and at the same time, the cathode 4 is discontinuously connected with the recessed holes 112 as a break point, so that the overall length of the cathode 4 is reduced, thereby reducing the cathode. 4 resistance.
  • the auxiliary electrode 1112 may be formed by cascading a plurality of metal layers, or may be formed by a single metal layer, and no matter which layer is disposed on the array substrate 1, as long as the concave holes 112 can be assisted.
  • the metal connection electrode 1112 can be electrically connected to the auxiliary electrode 122 through the recess 112 formed in the array substrate 1.
  • the OLED semiconductor layer 3 is formed of an anode, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, and the cathode 4 corresponds to the OLED semiconductor layer 3.
  • the TFT array substrate of the bottom gate structure in the third embodiment of the present invention is different from the difference in the TFT array substrate of the double gate structure in the first embodiment of the present invention.
  • the gate insulating layer 15 and the top gate 16 of the TFT array substrate of the double gate structure in the first embodiment of the present invention are omitted, and other components and the TFT of the double gate structure in the first embodiment of the present invention are omitted.
  • the array substrate has the same structure and connection relationship. For details, refer to the relevant parts of the TFT array substrate of the double-gate structure in the first embodiment of the present invention, and therefore no further details are provided herein.
  • the flat layer 19 of the TFT array substrate of the bottom gate structure may be a single layer structure or a laminated structure.
  • the flat layer 19 of the single-layer structure the flat layer 19 is made of an organic material.
  • the fifth conductive hole 191, the first cavity 1121 and the second cavity 1122 of the recess 112 are all disposed in a single layer structure.
  • the flat layer 19 is formed by superposing an inorganic passivation layer 192 made of an inorganic material and an organic flat layer 193 made of an organic material;
  • the fifth conductive via 191 penetrates the upper and lower surfaces of the organic flat layer 193 and penetrates into the inorganic passivation layer 192.
  • the first cavity 1121 of the recess 112 is disposed on the inorganic passivation layer 192, and the second cavity 1122 of the recess 112 is disposed.
  • the inorganic material is one of SiOx, SiNx, SiNO; the organic material includes, but is not limited to, polymethyl methacrylate PMMA and siloxane.
  • the method shows a process for preparing an organic light emitting display device when a TFT array substrate having a double gate structure is used, and specifically includes the following step:
  • Step S1 selecting a substrate, forming a bottom gate and an auxiliary electrode on the upper surface of the selected substrate, and further covering the upper surface of the selected substrate and the bottom gate and the auxiliary electrode formed thereon Floor;
  • Step S2 a first conductive hole penetrating through the upper surface of the buffer layer and communicating with the auxiliary electrode is formed on the buffer layer, and an active layer is formed above the buffer layer;
  • Step S3 a gate insulating layer and a top gate are sequentially formed over the active layer, and an intermediate dielectric layer is further covered over the active layer, the gate insulating layer and the top gate;
  • Step S4 a second conductive hole penetrating through the upper and lower surfaces of the intermediate dielectric layer and communicating with the first conductive hole is formed on the intermediate dielectric layer, and the upper surface of the intermediate dielectric layer is penetrated and
  • the source layer is respectively connected to the third conductive hole and the fourth conductive hole, and further, the source, the drain and the metal line are disposed on the intermediate dielectric layer, such that the source passes through the third conductive hole and the active layer Electrically connecting, the drain is electrically connected to the active layer through the fourth conductive hole, and the metal wire is electrically connected to the auxiliary electrode through the second conductive hole and the first conductive hole;
  • Step S5 sequentially covering the source, the drain, and the metal line with an inorganic passivation layer and an organic flat layer, and opening the upper and lower surfaces of the organic flat layer and penetrating through the organic flat layer.
  • Step S6 a transparent electrode layer is disposed on the organic flat layer, and the transparent electrode layer is patterned to form a metal connection electrode and a pixel electrode; wherein the pixel electrode passes through the fifth conductive hole
  • the source is electrically connected; the metal connection electrode is connected to the metal through the recess and then electrically connected to the auxiliary electrode;
  • Step S7 providing a pixel defining layer on the organic flat layer, the metal connecting electrode and the pixel electrode, and leaving the pixel defining layer with a groove corresponding to the metal connecting electrode and the pixel electrode;
  • Step S8 disposing an OLED semiconductor layer on the pixel defining layer, the metal connecting electrode and the pixel electrode, and extending the OLED semiconductor layer into the recessed hole to communicate with the metal line to realize the OLED semiconductor layer Electrically connected to the auxiliary electrode;
  • Step S9 disposing a cathode on the OLED semiconductor layer, and extending the cathode to the recessed hole to communicate with the metal line, thereby realizing electrical connection between the cathode and the auxiliary electrode, and further implementing The cathode is in a discontinuous connection state with the concave hole as a break point.
  • a metal layer is sputtered on the upper surface of the selected substrate by physical vapor deposition (PVD) to form a first metal layer, and further, after applying the photoresist on the first metal layer.
  • the first metal layer is exposed to a desired pattern by a yellow light process, and the bottom gate and the auxiliary electrode are formed by wet etching and photoresist stripping according to a desired pattern.
  • the selected substrate can be made of any material of quartz, glass or transparent plastic.
  • the upper surface of the selected substrate substrate and the bottom gate electrode and the auxiliary electrode formed thereon are coated and covered with a layer of silicon nitride by chemical vapor deposition (CVD), and continue to pass through.
  • a chemical vapor deposition method is applied over the silicon nitride layer and covered with a layer of silicon oxide to obtain a buffer layer of the stacked structure, that is, the buffer layer is a silicon nitride film layer and the silicon oxide film is located above the silicon nitride film layer.
  • the laminated structure formed by the layers is a silicon nitride film layer and the silicon oxide film is located above the silicon nitride film layer.
  • the active layer is formed by applying a metal conductive oxide on the buffer layer by physical vapor deposition; it should be noted that the metal conductive oxide includes indium gallium zinc oxide IGZO or other metal conductive oxide;
  • the photoresist After applying a layer of photoresist over the active layer, the photoresist is exposed and developed by using a translucent mask (such as a gray scale mask or a halftone mask), so that the photoresist is patterned into a desired a photoresist pattern such that the photoresist pattern has a stepped shape above the auxiliary electrode; an etching gas (such as SF6, Cl2, CF4, Ar, NF3, etc.) is used for the region of the photoresist pattern not covered by the photoresist.
  • a translucent mask such as a gray scale mask or a halftone mask
  • the active layer removing the photoresist is subjected to a dry etching process except for the pattern reserved area, and the area other than the pattern reserved area on the active layer is etched away; the oxidizing gas (such as O2 and N2O is continuously used).
  • the dry etching process is performed on the photoresist of the reserved area of the active layer pattern to remove the photoresist.
  • a gate insulating layer is formed by applying CVD on the active layer and covered with a layer of silicon nitride, and applying a layer of photoresist over the gate insulating layer, and then using a transparent mask to align the light.
  • the photoresist is exposed and developed to pattern the photoresist into a photoresist pattern corresponding to the pattern reserved area of the gate insulating layer; the photoresist is dry-etched by an oxidizing gas (such as O2 and N2O).
  • an oxidizing gas such as O2 and N2O
  • a second metal layer by sputtering a layer of metal on the upper surface of the gate insulating layer by PVD, and further forming a desired pattern by exposing the second metal layer by a yellow light process after applying the photoresist on the second metal layer,
  • the top gate is formed by wet etching and photoresist stripping according to the desired pattern, and further CVD is applied over the active layer, the gate insulating layer and the top gate by CVD and covered with a thick silicon nitride as an intermediate dielectric.
  • Floor
  • a second conductive via communicating with the first conductive via is formed on the intermediate dielectric layer, and the third conductive via and the fourth conductive a hole; after all the openings of the intermediate dielectric layer are completed, a third metal layer is formed by sputtering a layer of metal on the upper surface of the intermediate dielectric layer by PVD, and the third metal layer passes through the third conductive hole and the fourth conductive hole respectively and is activated.
  • the layers are connected and connected to the auxiliary electrode through the second conductive hole and the first conductive hole;
  • the photoresist After applying a layer of photoresist over the third metal layer, the photoresist is exposed and developed by using a translucent mask (such as a gray scale mask or a halftone mask), so that the photoresist is patterned into a
  • a translucent mask such as a gray scale mask or a halftone mask
  • the photoresist pattern is required such that the photoresist pattern has a step shape above the second conductive hole, the third conductive hole and the fourth conductive hole; and the wet method is performed by a corrosive solution (such as PPC acid, ENF acid, oxalic acid, etc.)
  • the etching process respectively forms a source corresponding to the third conductive via, a drain corresponding to the fourth conductive via, and a metal connection corresponding to the second conductive via.
  • an inorganic passivation layer is formed by CVD over the source, drain and metal lines and covered with a layer of silicon nitride, and continues to be applied over the inorganic passivation layer by CVD and covered with a layer of PMMA.
  • a fifth layer penetrating the upper and lower surfaces of the organic flat layer and penetrating into the inorganic passivation layer and communicating with the source is formed on the organic flat layer and the inorganic passivation layer.
  • a conductive hole, and a recessed hole communicating with the metal line; at this time, the recessed hole should be further etched by 0.1 um to 2 um in a direction away from the pixel electrode, so that the recessed hole is formed with a first cavity that communicates with each other.
  • the first cavity is disposed on the inorganic passivation layer, and the second cavity is disposed on the organic planar layer, the first cavity extends away from the pixel in a direction away from the pixel electrode The edge line on one side of the electrode;
  • a transparent electrode layer is formed by sputtering a metal conductive oxide (such as ITO/Ag/ITO) on the surface of the organic flat layer by PVD, and the transparent electrode layer is patterned into a metal connection electrode and a pixel respectively.
  • a metal conductive oxide such as ITO/Ag/ITO
  • step S7 a layer of silicon nitride is formed on the organic flat layer, the metal connection electrode and the pixel electrode by CVD to form a pixel defining layer, and a layer of photoresist is applied over the pixel defining layer, and then a transparent mask is used.
  • the photoresist is subjected to an exposure and development process, so that the photoresist is patterned into a photoresist pattern required for a pattern reserved area corresponding to the pixel defining layer; the photoresist is dry-etched by an oxidizing gas (such as O2 and N2O).
  • Etching process to remove the photoresist corresponding to the area outside the pattern reserved area of the pixel definition layer using an etching gas (such as SF6, Cl2, CF4, Ar, NF3, etc.) to remove the photoresist from the pixel definition layer
  • Dry etching process is performed outside the retention zone to etch away areas other than the pattern reserved area on the pixel definition layer; continue to use oxidizing gases (such as O2 and N2O) to define a reserved area of the pixel pattern layer
  • the photoresist is subjected to a dry etching process to remove the photoresist, so that the pixel defining layer is provided with a recess corresponding to the metal connecting electrode and the pixel electrode;
  • step S8 the OLED semiconductor layer is deposited on the pixel defining layer, the metal connecting electrode and the pixel electrode by CVD, and the OLED semiconductor layer is extended to the recessed hole to communicate with the metal line, thereby realizing the OLED semiconductor layer and the auxiliary electrode to realize electricity.
  • the OLED semiconductor layer is in a discontinuous connection state with the recessed hole as a break point;
  • a metal such as Ag/Mg
  • the metal of the cathode is extended to the recessed hole to communicate with the metal to realize electrical connection between the cathode and the auxiliary electrode.
  • the cathode is discontinuously connected with the recess as a break point to reduce the resistance of the cathode.
  • the embodiments of the present invention have the following beneficial effects: compared with the conventional organic light-emitting display device, the present invention realizes a discontinuous connection state of the cathode on the OLED semiconductor layer through the recessed holes formed in the array substrate. Effectively reducing the resistance of the cathode and allowing the cathode to extend into the recessed hole to electrically connect with the auxiliary electrode, thereby achieving the purpose of not only improving the conductivity of the cathode on the OLED semiconductor layer but also reducing the voltage drop;
  • the inverted trapezoidal structure column of the conventional organic light-emitting display device simplifies the process process and saves time and effort.

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Abstract

本发明提供一种有机发光显示装置，包括具有像素电极、金属连接电极和辅助电极的阵列基板，金属连接电极通过位于辅助电极上方的凹孔与辅助电极相连；凹孔形成有相互连通的第一和第二空腔，且第一空腔自第二空腔远离像素电极一侧的边缘线起沿远离像素电极的方向延伸；像素定义层在阵列基板上方，分别预留有对应凹孔和像素电极的凹槽；OLED半导体层在像素定义层上方，覆盖像素电极和金属连接电极上，还延伸至第一空腔中与辅助电极相连；阴极在OLED半导体层上方，延伸至第一空腔中与辅助电极相连，并以凹孔为断点呈不连续连接状态。实施本发明，不仅能省略倒梯形柱脚来简化制程工艺，还能提高OLED半导体层上的阴极的导电能力，从而达到减少压降的目的。

Description

一种有机发光显示装置
本申请要求于2018年4月20日提交中国专利局、申请号为201810362778.5、发明名称为“一种有机发光显示装置”的中国专利申请的优先权，上述专利的全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，尤其涉及一种有机发光显示装置。
背景技术
与传统的LCD相对比，有机发光显示装置为自发光显示装置，因不需要背光，具有轻薄、省电、快速响应等优点，同时还具有优秀的视角和对比度。通常，有机发光显示装置由阵列基板以及设置于阵列基板上方的OLED发光器件组成，该OLED发光器件包括阳极、空穴注入层、空穴传输层、发光层、电子传输层电子注入层和阴极；其中，阳极、空穴注入层、空穴传输层、发光层、电子传输层和电子注入层形成为OLED半导体层。
根据发光方向，有机发光显示装置包括顶部发射型、底部发射型和双发射型。在顶部发射型中，有机发光显示装置在与设置有子像素的阵列基板相反的方向出光，因其结构能够满足大面积高解析度的OLED面板的开口率要求，所以常应用于大面积高解析度的OLED面板上。然而，由于有机发光显示装置上的OLED发光器件的阴极具有高电阻率，因此会发生严重的压降现象，一旦有机发光显示装置通电后，就会导致亮度或图像质量出现不均匀性。
如图1所示，为了克服上述问题，通常会采取在阵列基板1 /的像素电极1111 /周围形成倒梯形柱脚a，并通过控制倒梯形柱脚a的尺寸，以及控制像素定义层2 /对应形成在阵列基板1 /的金属连接电极1112 /上方的凹槽21 /的腔 体直径大小及腔体侧壁与阵列基板1 /水平面形成的倾斜角度，使得OLED半导体层3 /上的阴极4 /能够进入金属连接电极1112 /上方的凹槽21 /腔体内，并通过金属连接电极1112 /与阵列基板1 /的辅助电极122 /连接，用以减少阴极4 /电阻来达到减少压降的目的。但是，发明人发现，上述方法中的有机发光显示装置的像素定义层2 /及倒梯形柱脚a分别需要通过两次曝光显影来形成正倒梯形结构，不仅工艺复杂，还费时费力。
发明内容
本发明实施例所要解决的技术问题在于，提供一种有机发光显示装置，不仅能省略倒梯形柱脚来简化制程工艺，还能提高OLED半导体层上的阴极的导电能力，从而达到减少压降的目的。
为了解决上述技术问题，本发明实施例提供了一种有机发光显示装置，包括：
阵列基板，所述阵列基板包括像素电极以及位于所述像素电极周围的金属连接电极和辅助电极；其中，所述金属连接电极通过所述阵列基板上开设的凹孔与所述辅助电极实现电连接；所述凹孔位于所述辅助电极的上方，并形成有相互连通的第一空腔和第二空腔，且所述第一空腔自所述第二空腔远离所述像素电极一侧的边缘线起沿远离所述像素电极的方向进行延伸；
设置于所述阵列基板上的像素定义层；其中，所述像素定义层在所述阵列基板的凹孔和像素电极的上方分别预留有相应的凹槽；
设置于所述阵列基板及所述像素定义层上的OLED半导体层；其中，所述OLED半导体层还覆盖于所述像素电极和所述金属连接电极上，并延伸至 所述凹孔的第一空腔中与所述辅助电极实现电连接；以及
设置于所述OLED半导体层上的阴极；其中，所述阴极还延伸至所述凹孔的第一空腔中与所述辅助电极实现电连接，并以所述凹孔为断点呈不连续连接状态。
其中，所述阵列基板为双栅结构的TFT阵列基板，包括：
衬底基板；
设置于所述衬底基板上的底部栅极以及所述辅助电极；
覆盖于所述衬底基板、底部栅极以及辅助电极上的缓冲层；其中，所述缓冲层上开设有贯穿所述缓冲层上表面并与所述辅助电极相连通的第一导电孔；
设置于所述缓冲层上的有源层；
设置于所述有源层上的栅极绝缘层；
设置于所述栅极绝缘层上的顶部栅极；
覆盖于所述有源层、栅极绝缘层、顶部栅极及缓冲层上的中间电介质层；其中，所述中间电介质层上开设有贯穿所述中间电介质层上下表面并与所述第一导电孔相连通的第二导电孔，以及贯穿所述中间电介质层上表面并与所述有源层分别相连通的第三导电孔和第四导电孔；
设置于所述中间电介质层上的源极、漏极和金属连线；其中，所述源极通过所述第三导电孔与所述有源层实现电相连和所述漏极通过所述第四导 电孔与所述有源层实现电相连；或所述源极通过所述第四导电孔与所述有源层实现电相连和所述漏极通过所述第三导电孔与所述有源层实现电相连；所述金属连线依次通过所述第二导电孔及所述第一导电孔与所述辅助电极实现电相连；
覆盖于所述源极、漏极和金属连线上的平坦层；其中，所述平坦层上开设有贯穿所述平坦层上表面并与所述源极或所述漏极相连通的第五导电孔，以及与所述金属连线相连通的所述凹孔；以及
设置于所述平坦层上，通过所述第五导电孔与所述源极或所述漏极实现电相连的所述像素电极，以及通过所述凹孔与所述金属连线连通后再与所述辅助电极实现电相连的所述金属连接电极；
其中，所述OLED半导体层和所述阴极均通过所述凹孔与所述金属连线连通后再与所述辅助电极实现电相连。
其中，所述平坦层为由有机材料制备而成的单层结构；其中，所述第五导电孔、所述凹孔的第一空腔和第二空腔均设置于所述单层结构的平坦层上；或
由无机材料制备出的无机钝化层和由有机材料制备出的有机平坦层二者叠加而成的叠层结构；其中，所述第五导电孔贯穿所述有机平坦层上下表面并穿入所述无机钝化层中，所述凹孔的第一空腔设置于所述无机钝化层上，所述凹孔的第二空腔设置于位于所述无机钝化层上方的有机平坦层上。
其中，所述无机材料为SiOx、SiNx、SiNO之中其一种；所述有机材料为聚甲基丙烯酸甲酯PMMA或硅氧烷。
其中，所述缓冲层为由SiOx、SiNx、SiNO之中其一种制备而成的单层结构；或由SiNx/SiOx制备而成的叠层结构。
其中，所述有源层采用铟镓锌氧化物IGZO或低温多晶硅LTPS制备而成。
其中，所述像素电极和所述辅助电极均采用ITO/Ag/ITO、IZO/Ag/IZO、AZO/Ag/AZO之中其一种金属氧化物制作而成。
相应于，本发明还提供了另一种有机发光显示装置，包括：
阵列基板，所述阵列基板包括像素电极以及位于所述像素电极周围的金属连接电极和辅助电极；其中，所述金属连接电极通过所述阵列基板上开设的凹孔与所述辅助电极实现电连接；所述凹孔位于所述辅助电极的上方，并形成有相互连通的第一空腔和第二空腔，且所述第一空腔自所述第二空腔远离所述像素电极一侧的边缘线起沿远离所述像素电极的方向进行延伸；
设置于所述阵列基板上的像素定义层；其中，所述像素定义层在所述阵列基板的凹孔和像素电极的上方分别预留有相应的凹槽；
设置于所述阵列基板及所述像素定义层上的OLED半导体层；其中，所述OLED半导体层还覆盖于所述像素电极和所述金属连接电极上，并延伸至所述凹孔的第一空腔中与所述辅助电极实现电连接；以及
设置于所述OLED半导体层上的阴极；其中，所述阴极还延伸至所述凹孔的第一空腔中与所述辅助电极实现电连接，并以所述凹孔为断点呈不连续连接状态；
其中，所述阵列基板为顶栅结构的TFT阵列基板，包括：
衬底基板；
设置于所述衬底基板上的光挡层以及所述辅助电极；
覆盖于所述衬底基板、光挡层以及辅助电极上的缓冲层；其中，所述缓冲层上开设有贯穿所述缓冲层上表面并与所述辅助电极相连通的第一导电孔；
设置于所述缓冲层上的有源层；
设置于所述有源层上的栅极绝缘层；
设置于所述栅极绝缘层上的顶部栅极；
覆盖于所述有源层、栅极绝缘层、顶部栅极及缓冲层上的中间电介质层；其中，所述中间电介质层上开设有贯穿所述中间电介质层上下表面并与所述第一导电孔相连通的第二导电孔，以及贯穿所述中间电介质层上表面并与所述有源层分别相连通的第三导电孔和第四导电孔；
设置于所述中间电介质层上的源极、漏极和金属连线；其中，所述源极通过所述第三导电孔与所述有源层实现电相连和所述漏极通过所述第四导电孔与所述有源层实现电相连；或所述源极通过所述第四导电孔与所述有源 层实现电相连和所述漏极通过所述第三导电孔与所述有源层实现电相连；所述金属连线依次通过所述第二导电孔及所述第一导电孔与所述辅助电极实现电相连；
覆盖于所述源极、漏极和金属连线上的平坦层；其中，所述平坦层上开设有贯穿所述平坦层上表面并与所述源极或所述漏极相连通的第五导电孔，以及与所述金属连线相连通的所述凹孔；以及
设置于所述平坦层上，通过所述第五导电孔与所述源极或所述漏极实现电相连的所述像素电极，以及通过所述凹孔与所述金属连线连通后再与所述辅助电极实现电相连的所述金属连接电极；
其中，所述OLED半导体层和所述阴极均通过所述凹孔与所述金属连线连通后再与所述辅助电极实现电相连。
其中，所述平坦层为由有机材料制备而成的单层结构；其中，所述第五导电孔、所述凹孔的第一空腔和第二空腔均设置于所述单层结构的平坦层上；或
由无机材料制备出的无机钝化层和由有机材料制备出的有机平坦层二者叠加而成的叠层结构；其中，所述第五导电孔贯穿所述有机平坦层上下表面并穿入所述无机钝化层中，所述凹孔的第一空腔设置于所述无机钝化层上，所述凹孔的第二空腔设置于位于所述无机钝化层上方的有机平坦层上。
其中，所述无机材料为SiOx、SiNx、SiNO之中其一种；所述有机材料 为聚甲基丙烯酸甲酯PMMA或硅氧烷。
其中，所述缓冲层为由SiOx、SiNx、SiNO之中其一种制备而成的单层结构；或由SiNx/SiOx制备而成的叠层结构。
其中，所述有源层采用铟镓锌氧化物IGZO或低温多晶硅LTPS制备而成。
其中，所述像素电极和所述辅助电极均采用ITO/Ag/ITO、IZO/Ag/IZO、AZO/Ag/AZO之中其一种金属氧化物制作而成。
相应于，本发明还提供了又一种有机发光显示装置，包括：
阵列基板，所述阵列基板包括像素电极以及位于所述像素电极周围的金属连接电极和辅助电极；其中，所述金属连接电极通过所述阵列基板上开设的凹孔与所述辅助电极实现电连接；所述凹孔位于所述辅助电极的上方，并形成有相互连通的第一空腔和第二空腔，且所述第一空腔自所述第二空腔远离所述像素电极一侧的边缘线起沿远离所述像素电极的方向进行延伸；
设置于所述阵列基板上的像素定义层；其中，所述像素定义层在所述阵列基板的凹孔和像素电极的上方分别预留有相应的凹槽；
设置于所述阵列基板及所述像素定义层上的OLED半导体层；其中，所述OLED半导体层还覆盖于所述像素电极和所述金属连接电极上，并延伸至所述凹孔的第一空腔中与所述辅助电极实现电连接；以及
设置于所述OLED半导体层上的阴极；其中，所述阴极还延伸至所述凹 孔的第一空腔中与所述辅助电极实现电连接，并以所述凹孔为断点呈不连续连接状态；
其中，所述阵列基板为底栅结构的TFT阵列基板，包括：
衬底基板；
设置于所述衬底基板上的底部栅极以及所述辅助电极；
覆盖于所述衬底基板、底部栅极以及辅助电极上的缓冲层；其中，所述缓冲层上开设有贯穿所述缓冲层上表面并与所述辅助电极相连通的第一导电孔；
设置于所述缓冲层上的有源层；
覆盖于所述有源层及所述缓冲层上的中间电介质层；其中，所述中间电介质层上开设有贯穿所述中间电介质层上下表面并与所述第一导电孔相连通的第二导电孔，以及贯穿所述中间电介质层上表面并与所述有源层分别相连通的第三导电孔和第四导电孔；
设置于所述中间电介质层上的源极、漏极和金属连线；其中，所述源极通过所述第三导电孔与所述有源层实现电相连和所述漏极通过所述第四导电孔与所述有源层实现电相连；或所述源极通过所述第四导电孔与所述有源层实现电相连和所述漏极通过所述第三导电孔与所述有源层实现电相连；所述金属连线依次通过所述第二导电孔及所述第一导电孔与所述辅助电极实现电相连；
覆盖于所述源极、漏极和金属连线上的平坦层；其中，所述平坦层上开设有贯穿所述平坦层上表面并与所述源极或所述漏极相连通的第五导电孔，以及与所述金属连线相连通的所述凹孔；以及
设置于所述平坦层上，通过所述第五导电孔与所述源极或所述漏极实现电相连的所述像素电极，以及通过所述凹孔与所述金属连线连通后再与所述辅助电极实现电相连的所述金属连接电极；
其中，所述OLED半导体层和所述阴极均通过所述凹孔与所述金属连线连通后再与所述辅助电极实现电相连。
其中，所述平坦层为由有机材料制备而成的单层结构；其中，所述第五导电孔、所述凹孔的第一空腔和第二空腔均设置于所述单层结构的平坦层上；或
由无机材料制备出的无机钝化层和由有机材料制备出的有机平坦层二者叠加而成的叠层结构；其中，所述第五导电孔贯穿所述有机平坦层上下表面并穿入所述无机钝化层中，所述凹孔的第一空腔设置于所述无机钝化层上，所述凹孔的第二空腔设置于位于所述无机钝化层上方的有机平坦层上。
其中，所述无机材料为SiOx、SiNx、SiNO之中其一种；所述有机材料为聚甲基丙烯酸甲酯PMMA或硅氧烷。
其中，所述缓冲层为由SiOx、SiNx、SiNO之中其一种制备而成的单层结构；或由SiNx/SiOx制备而成的叠层结构。
其中，所述有源层采用铟镓锌氧化物IGZO或低温多晶硅LTPS制备而成。
其中，所述像素电极和所述辅助电极均采用ITO/Ag/ITO、IZO/Ag/IZO、AZO/Ag/AZO之中其一种金属氧化物制作而成。
本发明实施例具有如下有益效果：与传统的有机发光显示装置相比，本发明通过阵列基板上开设的凹孔来实现OLED半导体层上的阴极成不连续连接状态，有效的降低阴极的电阻，并使得阴极能延伸至凹孔内与辅助电极实现电连接，从而达到不仅能提高OLED半导体层上的阴极的导电能力，还能减少压降的目的；同时，由于节省了传统有机发光显示装的倒梯形结构柱脚，从而简化了制程工艺，达到省时省力的目的。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中有机发光显示装置的剖面图；
图2为本发明实施例一中提供的一种有机发光显示装置的剖面图；
图3为本发明实施例二中提供的另一种有机发光显示装置的剖面图；
图4为本发明实施例三中提供的又一种有机发光显示装置的剖面图；
图5为本发明实施例一中提供的有机发光显示装置的制备方法的流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步地详细描述。
如图2所示，为本发明实施例一中，提供的一种有机发光显示装置，示出了有机发光显示装置中阵列基板为双栅结构的TFT阵列基板时的结构，具体包括：
阵列基板1，该阵列基板1包括像素电极1111以及位于像素电极1111周围的金属连接电极1112和辅助电极122；其中，金属连接电极1112通过阵列基板1上开设的凹孔112与辅助电极122实现电连接；凹孔112位于辅助电极122的上方，并形成有相互连通的第一空腔1121和第二空腔1122，且第一空腔1121自第二空腔1122远离像素电极1111一侧的边缘线起沿远离像素电极1111的方向进行延伸，这样就可以通过扩展凹孔112在阵列基板1水平长度方向上的腔体大小，使得金属连接电极1112和其它的导电物质更有利的进入凹孔112中；
设置于阵列基板1上的像素定义层2；其中，像素定义层2在阵列基板1的凹孔112和像素电极1111的上方分别预留有相应的凹槽21，以便于像素电极1111和金属连接电极1112容纳于像素定义层2所对应的凹槽21内，避免OLED发光器件无法与像素电极1111和金属连接电极1112连接而影响OLED发光器件正常发光；
设置于阵列基板1及像素定义层2上的OLED半导体层3；其中，OLED 半导体层3还覆盖于像素电极1111和金属连接电极1112上，并延伸至凹孔112的第一空腔1121中与辅助电极122实现电连接；以及
设置于OLED半导体层3上的阴极4；其中，阴极4还延伸至凹孔112的第一空腔1121中与辅助电极122实现电连接，并以凹孔112为断点呈不连续连接状态，使得阴极4长度减少来降低阴极4的电阻。
应当说明的是，由于凹孔112中第二空腔1122的腔体直径小于第一空腔1121的腔体直径，且第二空腔1122其远离像素电极1111一侧的边缘线位于第一空腔1121的腔体上方，使得凹孔112的轮廊截面可以呈“L”型或“┴”型等结构，只要满足金属连接电极1112、OLED半导体层3及阴极4都能与辅助电极1112实现电连接的要求就可达到提高OLED半导体层3上阴极4的导电能力的目的，同时因阴极4以凹孔112为断点呈不连续连接，使得阴极4的整体长度得到下降，从而减少了阴极4的电阻。
可以理解的是，辅助电极1112可以是多个金属层级联的方式形成，也可以是单个金属层的方式形成，也不管设置在阵列基板1上的哪一层上，只要凹孔112能够与辅助电极1112相连通，则金属连接电极1112就能通过阵列基板1上开设的凹孔112与辅助电极122实现电连接。
需要解释的是，OLED半导体层3由阳极、空穴注入层、空穴传输层、发光层、电子传输层和电子注入层形成，阴极4对应OLED半导体层3。
在本发明实施例一中，有机发光显示装置中双栅结构的TFT阵列基板中 的辅助电极122具有多级连接结构，该双栅结构的TFT阵列基板具体包括：
衬底基板11，该衬底基板可以是玻璃基板或塑料基板；
设置于衬底基板11上的底部栅极121以及辅助电极122，此时辅助电极122设置在倒数第二层上；
覆盖于衬底基板11、底部栅极121以及辅助电极122上的缓冲层13；其中，缓冲层13上开设有贯穿缓冲层13上表面并与辅助电极122相连通的第一导电孔131，该缓冲层13为由SiOx、SiNx、SiNO之中其一种制备而成的单层结构；或由SiNx/SiOx制备而成的叠层结构；
设置于缓冲层13上的有源层14，该有源层14采用铟镓锌氧化物IGZO或低温多晶硅LTPS制备而成；
设置于有源层14上的栅极绝缘层15，该栅极绝缘层15采用无机材料制备而成，该无机材料为SiOx、SiNx、SiNO之中其一种；
设置于栅极绝缘层15上的顶部栅极16；
覆盖于有源层14、栅极绝缘层15、顶部栅极16及缓冲层13上的中间电介质层17；其中，中间电介质层17上开设有贯穿中间电介质层17上下表面并与所述第一导电孔131相连通的第二导电孔171，以及贯穿中间电介质层17上表面并与有源层14分别相连通的第三导电孔172和第四导电孔173；该中间电介质层17采用无机材料制备而成，该无机材料为SiOx、SiNx、SiNO之中其一种；
设置于中间电介质层17上的源极181、漏极182和金属连线183；其中，源极181通过第三导电孔172与有源层14实现电相连和漏极182通过第四导电孔173与有源层14实现电相连；或源极181通过第四导电孔173与有源层14实现电相连和漏极182通过第三导电孔172与有源层14实现电相连；金属连线183依次通过第二导电孔171及第一导电孔131与辅助电极122实现电相连，此时金属连接电极1112、OLED半导体层3及阴极4只要与金属连线183相连，就都能与辅助电极1112实现电连接；
覆盖于源极181、漏极182和金属连线183上的平坦层19；其中，平坦层19上开设有贯穿平坦层19上表面并与源极181或漏极182相连通的第五导电孔191，以及与金属连线183相连通的凹孔112；以及
设置于平坦层19上，通过第五导电孔191与源极181或漏极182实现电相连的像素电极1111，以及通过凹孔112与金属连线183连通后再与辅助电极122实现电相连的所述金属连接电极1112；
其中，OLED半导体层3和阴极4均通过凹孔112与金属连线183连通后再与辅助电极122实现电相连。
在本发明实施例一中，像素电极1111和辅助电极1112可以是单层结构的导电金属氧化物形成，也可以是金属与金属氧化物形成的叠层结构。在一个实施例中，像素电极1111和辅助电极1112均为单层结构，包括但不限于ITO、IZO等。在另一个实施例中，像素电极1111和辅助电极1112均为叠 层结构，采用ITO/Ag/ITO、IZO/Ag/IZO、AZO/Ag/AZO之中其一种金属氧化物制作而成。
在本发明实施例一中，平坦层19可以是单层结构，也可以是叠层结构。在单层结构的平坦层19中，该平坦层19由有机材料制备而成，此时第五导电孔191、凹孔112的第一空腔1121和第二空腔1122均设置于单层结构的平坦层19上；在叠层结构的平坦层19中，该平坦层19由无机材料制备出的无机钝化层192和由有机材料制备出的有机平坦层193二者叠加而成；此时第五导电孔191贯穿有机平坦层193上下表面并穿入无机钝化层192中，凹孔112的第一空腔1121设置于无机钝化层192上，凹孔112的第二空腔1122设置于位于无机钝化层192上方的有机平坦层193上(如图2所示)。该无机材料为SiOx、SiNx、SiNO之中其一种；该有机材料包括但不限于聚甲基丙烯酸甲酯PMMA和硅氧烷。
如图3所示，为本发明实施例二中，提供的另一种有机发光显示装置，示出了有机发光显示装置中阵列基板为顶栅结构的TFT阵列基板时的结构，具体包括：
阵列基板1，该阵列基板1包括像素电极1111以及位于像素电极1111周围的金属连接电极1112和辅助电极122；其中，金属连接电极1112通过阵列基板1上开设的凹孔112与辅助电极122实现电连接；凹孔112位于辅助电极122的上方，，并形成有相互连通的第一空腔1121和第二空腔1122， 且第一空腔1121自第二空腔1122远离像素电极1111一侧的边缘线起沿远离像素电极1111的方向进行延伸，这样就可以通过扩展凹孔112在阵列基板1水平长度方向上的腔体大小，使得金属连接电极1112和其它的导电物质更有利的进入凹孔112中；
设置于阵列基板1上的像素定义层2；其中，像素定义层2在阵列基板1的凹孔112和像素电极1111的上方分别预留有相应的凹槽21，以便于像素电极1111和金属连接电极1112容纳于像素定义层2所对应的凹槽21内，避免OLED发光器件无法与像素电极1111和金属连接电极1112连接而影响OLED发光器件正常发光；
设置于阵列基板1及像素定义层2上的OLED半导体层3；其中，OLED半导体层3还覆盖于像素电极1111和金属连接电极1112上，并延伸至凹孔112的第一空腔1121中与辅助电极122实现电连接；以及
设置于OLED半导体层3上的阴极4；其中，阴极4还延伸至凹孔112的第一空腔1121中与辅助电极122实现电连接，并以凹孔112为断点呈不连续连接状态，使得阴极4长度减少来降低阴极4的电阻。
应当说明的是，由于凹孔112中第二空腔1122的腔体直径小于第一空腔1121的腔体直径，且第二空腔1122其远离像素电极1111一侧的边缘线位于第一空腔1121的腔体上方，使得凹孔112的轮廊截面可以呈“L”型或“┴”型等结构，只要满足金属连接电极1112、OLED半导体层3及阴极4 都能与辅助电极1112实现电连接的要求就可达到提高OLED半导体层3上阴极4的导电能力的目的，同时因阴极4以凹孔112为断点呈不连续连接，使得阴极4的整体长度得到下降，从而减少了阴极4的电阻。
可以理解的是，辅助电极1112可以是多个金属层级联的方式形成，也可以是单个金属层的方式形成，也不管设置在阵列基板1上的哪一层上，只要凹孔112能够与辅助电极1112相连通，则金属连接电极1112就能通过阵列基板1上开设的凹孔112与辅助电极122实现电连接。
需要解释的是，OLED半导体层3由阳极、空穴注入层、空穴传输层、发光层、电子传输层和电子注入层形成，阴极4对应OLED半导体层3。
相应于本发明实施例一中的双栅结构的TFT阵列基板，本发明实施例二中的顶栅结构的TFT阵列基板区别于本发明实施例一中的双栅结构的TFT阵列基板的不同点在于：将本发明实施例一中的双栅结构的TFT阵列基板的底部栅极121设置为光挡层121，除此之外的其它部件与本发明实施例一中的双栅结构的TFT阵列基板都具有相同的结构及连接关系，具体请参见本发明实施例一中的双栅结构的TFT阵列基板的相关部分内容，因此在此不再一一赘述。
应当说明的是，顶栅结构的TFT阵列基板的平坦层19可以是单层结构，也可以是叠层结构。在单层结构的平坦层19中，该平坦层19由有机材料制备而成，此时第五导电孔191、凹孔112的第一空腔1121和第二空腔1122 均设置于单层结构的平坦层19上；在叠层结构的平坦层19中，该平坦层19由无机材料制备出的无机钝化层192和由有机材料制备出的有机平坦层193二者叠加而成；此第五导电孔191贯穿有机平坦层193上下表面并穿入无机钝化层192中，时凹孔112的第一空腔1121设置于无机钝化层192上，凹孔112的第二空腔1122设置于位于无机钝化层192上方的有机平坦层193上(如图3所示)。该无机材料为SiOx、SiNx、SiNO之中其一种；该有机材料包括但不限于聚甲基丙烯酸甲酯PMMA和硅氧烷。
如图4所示，为本发明实施例三中，提供的又一种有机发光显示装置，示出了有机发光显示装置中阵列基板为底栅结构的TFT阵列基板时的结构，具体包括：
阵列基板1，该阵列基板1包括像素电极1111以及位于像素电极1111周围的金属连接电极1112和辅助电极122；其中，金属连接电极1112通过阵列基板1上开设的凹孔112与辅助电极122实现电连接；凹孔112位于辅助电极122的上方，，并形成有相互连通的第一空腔1121和第二空腔1122，且第一空腔1121自第二空腔1122远离像素电极1111一侧的边缘线起沿远离像素电极1111的方向进行延伸，这样就可以通过扩展凹孔112在阵列基板1水平长度方向上的腔体大小，使得金属连接电极1112和其它的导电物质更有利的进入凹孔112中；
设置于阵列基板1上的像素定义层2；其中，像素定义层2在阵列基板 1的凹孔112和像素电极1111的上方分别预留有相应的凹槽21，以便于像素电极1111和金属连接电极1112容纳于像素定义层2所对应的凹槽21内，避免OLED发光器件无法与像素电极1111和金属连接电极1112连接而影响OLED发光器件正常发光；
设置于阵列基板1及像素定义层2上的OLED半导体层3；其中，OLED半导体层3还覆盖于像素电极1111和金属连接电极1112上，并延伸至凹孔112的第一空腔1121中与辅助电极122实现电连接；以及
设置于OLED半导体层3上的阴极4；其中，阴极4还延伸至凹孔112的第一空腔1121中与辅助电极122实现电连接，并以凹孔112为断点呈不连续连接状态，使得阴极4长度减少来降低阴极4的电阻。
应当说明的是，由于凹孔112中第二空腔1122的腔体直径小于第一空腔1121的腔体直径，且第二空腔1122其远离像素电极1111一侧的边缘线位于第一空腔1121的腔体上方，使得凹孔112的轮廊截面可以呈“L”型或“┴”型等结构，只要满足金属连接电极1112、OLED半导体层3及阴极4都能与辅助电极1112实现电连接的要求就可达到提高OLED半导体层3上阴极4的导电能力的目的，同时因阴极4以凹孔112为断点呈不连续连接，使得阴极4的整体长度得到下降，从而减少了阴极4的电阻。
可以理解的是，辅助电极1112可以是多个金属层级联的方式形成，也可以是单个金属层的方式形成，也不管设置在阵列基板1上的哪一层上，只 要凹孔112能够与辅助电极1112相连通，则金属连接电极1112就能通过阵列基板1上开设的凹孔112与辅助电极122实现电连接。
需要解释的是，OLED半导体层3由阳极、空穴注入层、空穴传输层、发光层、电子传输层和电子注入层形成，阴极4对应OLED半导体层3。
相应于本发明实施例一中的双栅结构的TFT阵列基板，本发明实施例三中的底栅结构的TFT阵列基板区别于本发明实施例一中的双栅结构的TFT阵列基板的不同点在于：省略了本发明实施例一中的双栅结构的TFT阵列基板的栅极绝缘层15和顶部栅极16，除此之外的其它部件与本发明实施例一中的双栅结构的TFT阵列基板都具有相同的结构及连接关系，具体请参见本发明实施例一中的双栅结构的TFT阵列基板的相关部分内容，因此在此不再一一赘述。
应当说明的是，底栅结构的TFT阵列基板的平坦层19可以是单层结构，也可以是叠层结构。在单层结构的平坦层19中，该平坦层19由有机材料制备而成，此时第五导电孔191、凹孔112的第一空腔1121和第二空腔1122均设置于单层结构的平坦层19上；在叠层结构的平坦层19中，该平坦层19由无机材料制备出的无机钝化层192和由有机材料制备出的有机平坦层193二者叠加而成；此时第五导电孔191贯穿有机平坦层193上下表面并穿入无机钝化层192中，凹孔112的第一空腔1121设置于无机钝化层192上，凹孔112的第二空腔1122设置于位于无机钝化层192上方的有机平坦层193 上(如图4所示)。该无机材料为SiOx、SiNx、SiNO之中其一种；该有机材料包括但不限于聚甲基丙烯酸甲酯PMMA和硅氧烷。
如图5所示，对本发明实施例一中提供的有机发光显示装置的制备方法进行详细说明，该方法示出了采用双栅结构的TFT阵列基板时制备有机发光显示装置的流程，具体包括以下步骤：
步骤S1、选定一衬底基板，在所选衬底基板上表面形成底部栅极以及辅助电极，并进一步在所选衬底基板上表面及其形成的底部栅极和辅助电极上方覆盖有缓冲层；
步骤S2、在所述缓冲层上开设有贯穿所述缓冲层上表面并与所述辅助电极相连通的第一导电孔，并在所述缓冲层上方形成有源层；
步骤S3、在所述有源层的上方依次形成有栅极绝缘层和顶部栅极，并进一步在所述有源层、栅极绝缘层和顶部栅极上方覆盖有中间电介质层；
步骤S4、在所述中间电介质层上开设有贯穿所述中间电介质层上下表面并与所述第一导电孔相连通的第二导电孔，以及贯穿所述中间电介质层上表面并与所述有源层分别相连通的第三导电孔和第四导电孔，并进一步在所述中间电介质层上设置源极、漏极和金属连线，使得所述源极通过第三导电孔与有源层实现电相连、漏极通过第四导电孔与所述有源层实现电相连以及所述金属连线依次通过第二导电孔及所述第一导电孔与所述辅助电极实现电相连；
步骤S5、在所述源极、漏极和金属连线上依次覆盖有无机钝化层和有机平坦层，并在所述有机平坦层上开设有贯穿所述有机平坦层上下表面并穿入所述无机钝化层中与所述源极相连通的第五导电孔，以及与所述金属连线相连通的凹孔；其中，所述凹孔形成有相互连通的第一空腔第二空腔，且所述第一空腔沿远离所述像素电极的方向延伸出所述第二空腔远离所述像素电极一侧的边缘线；所述第一空腔设置于所述无机钝化层上，所述第二空腔设置于所述有机平坦层上；
步骤S6、在所述有机平坦层上设有透明电极层，并使得所述透明电极层经图案化处理后形成金属连接电极和像素电极；其中，所述像素电极通过所述第五导电孔与所述源极实现电相连；所述金属连接电极通过所述凹孔与所述金属连线连通后再与所述辅助电极实现电相连；
步骤S7、在所述有机平坦层、金属连接电极和像素电极上设有像素定义层，并使得像素定义层预留有对应容纳金属连接电极和像素电极的凹槽；
步骤S8、将OLED半导体层设置在所述像素定义层、金属连接电极和像素电极上，并延伸所述OLED半导体层至所述凹孔中与所述金属连线连通，实现所述OLED半导体层与所述辅助电极实现电相连；
步骤S9、将阴极设置在所述OLED半导体层上，并延伸所述阴极至所述凹孔中与所述金属连线连通，实现所述阴极与所述辅助电极实现电相连，且进一步实现所述阴极以所述凹孔为断点呈不连续连接状态。
具体过程为，在步骤S1中，通过物理气相沉积法(PVD)在所选衬底基板的上表面溅镀一层金属形成第一金属层，且进一步通过在第一金属层涂抹光刻胶后采用黄光制程对第一金属层进行曝光形成所需图案，再根据所需图案通过湿法刻蚀和光阻剥离形成底部栅极以及辅助电极。其中，所选衬底基板可以由石英、玻璃或透明塑料之中任一材料制作而成。
在制备出底部栅极以及辅助电极后，通过化学气相沉积法(CVD)在所选衬底基板上表面及其形成的底部栅极和辅助电极上方涂抹并覆盖有一层氮化硅，并继续通过化学气相沉积法在所述氮化硅层上方涂抹并覆盖有一层氧化硅，从而得到叠层结构的缓冲层，即缓冲层为氮化硅膜层以及位于氮化硅膜层上方的氧化硅膜层所形成的叠层结构。
在步骤S2中，通过物理气相沉积法在缓冲层上涂抹金属导电氧化物形成有源层；应当说明的是，金属导电氧化物包括铟镓锌氧化物IGZO或其它金属导电氧化物；
在有源层上方涂抹一层光刻胶后，通过采用半透明光罩(如灰阶光罩或半色调光罩)对光刻胶进行曝光、显影制程，使得光刻胶图形化为所需的光阻图案，使得光阻图案在位于辅助电极的上方具有阶梯状；采用刻蚀气体(如SF6、Cl2、CF4、Ar和NF3等)对光阻图案中未被光刻胶覆盖的区域均进行干法刻蚀制程，形成贯穿有源层上下表面及缓冲层上下表面并与辅助电极相连通的第一导电孔；确定有源层的图案预留区，并采用氧化性气体(如 O2和N2O等)对光阻进行干法刻蚀制程来去除有源层除图案预留区之外区域所对应的光阻；采用刻蚀气体(如SF6、Cl2、CF4、Ar和NF3等)对已去除光阻的有源层除图案预留区之外区域进行干法刻蚀制程，刻蚀掉有源层上除图案预留区之外的区域；继续采用氧化性气体(如O2和N2O等)对有源层图案预留区的光阻进行干法刻蚀制程来去除光阻。
在步骤S3中，通过化CVD在有源层的上方涂抹并覆盖有一层氮化硅形成栅极绝缘层，并在栅极绝缘层上方涂抹一层光刻胶后，通过采用透明光罩对光刻胶进行曝光、显影制程，使得光刻胶图形化为对应栅极绝缘层的图案预留区所需的光阻图案；采用氧化性气体(如O2和N2O等)对光阻进行干法刻蚀制程来去除栅极绝缘层除图案预留区之外区域所对应的光阻；采用刻蚀气体(如SF6、Cl2、CF4、Ar和NF3等)对已去除光阻的栅极绝缘层除图案预留区之外区域进行干法刻蚀制程，刻蚀掉栅极绝缘层上除图案预留区之外的区域；继续采用氧化性气体(如O2和N2O等)对栅极绝缘层图案预留区的光阻进行干法刻蚀制程来去除光阻；
通过PVD在栅极绝缘层的上表面溅镀一层金属形成第二金属层，且进一步通过在第二金属层涂抹光刻胶后采用黄光制程对第二金属层进行曝光形成所需图案，再根据所需图案通过湿法刻蚀和光阻剥离形成顶部栅极，并进一步通过CVD在有源层、栅极绝缘层和顶部栅极上方涂抹并覆盖有一层很厚的氮化硅作为中间电介质层；
在步骤S4中，采用步骤S2中有源层上开设第一导电孔的相同方式，在中间电介质层上开设与第一导电孔相连通的第二导电孔，以及第三导电孔和第四导电孔；待中间电介质层所有开孔完成后，通过PVD在中间电介质层上表面溅镀一层金属形成第三金属层，且第三金属层分别通过第三导电孔和第四导电孔与有源层相连以及通过第二导电孔及第一导电孔与辅助电极相连；
在第三金属层上方涂抹一层光刻胶后，通过采用半透明光罩(如灰阶光罩或半色调光罩)对光刻胶进行曝光、显影制程，使得光刻胶图形化为所需的光阻图案，使得光阻图案在位于第二导电孔、第三导电孔和第四导电孔的上方具有阶梯状；采用腐蚀性溶液(如PPC酸、ENF酸、草酸等)进行湿法刻蚀制程，分别形成对应第三导电孔的源极、对应第四导电孔的漏极和对应第二导电孔的金属连线。
在步骤S5中，通过CVD在源极、漏极和金属连线的上方涂抹并覆盖有一层氮化硅形成无机钝化层，并继续通过CVD在无机钝化层的上方涂抹并覆盖有一层PMMA形成有机平坦层，此时平坦层为无机钝化层和有机平坦层形成的叠层结构；
采用步骤S2中有源层上开设第一导电孔的相同方式，在有机平坦层及无机钝化层上开设贯穿有机平坦层上下表面并穿入无机钝化层中与源极相连通的第五导电孔，以及与金属连线相连通的凹孔；此时，应继续对凹孔沿 远离像素电极的方向进行刻蚀0.1um～2um，使得凹孔形成有相互连通的第一空腔第二空腔；其中，第一空腔设置于无机钝化层上，第二空腔设置于有机平坦层上，该第一空腔是沿远离像素电极的方向延伸出第二空腔远离所述像素电极一侧的边缘线；
在步骤S6中，通过PVD在有机平坦层上表面溅镀一层金属导电氧化物(如ITO/Ag/ITO)形成透明电极层，透明电极层经图案化处理后分别形成为金属连接电极和像素电极；其中，像素电极通过第五导电孔与源极实现电相连；金属连接电极通过凹孔与金属连线连通后再与辅助电极实现电相连；
在步骤S7中、通过CVD在有机平坦层、金属连接电极和像素电极上覆盖一层氮化硅形成像素定义层，并在像素定义层上方涂抹一层光刻胶后，通过采用透明光罩对光刻胶进行曝光、显影制程，使得光刻胶图形化为对应像素定义层的图案预留区所需的光阻图案；采用氧化性气体(如O2和N2O等)对光阻进行干法刻蚀制程来去除像素定义层除图案预留区之外区域所对应的光阻；采用刻蚀气体(如SF6、Cl2、CF4、Ar和NF3等)对已去除光阻的像素定义层除图案预留区之外区域进行干法刻蚀制程，刻蚀掉像素定义层上除图案预留区之外的区域；继续采用氧化性气体(如O2和N2O等)对像素定义层图案预留区的光阻进行干法刻蚀制程来去除光阻，使得像素定义层预留有对应容纳金属连接电极和像素电极的凹槽；
在步骤S8中、通过CVD蒸镀OLED半导体层设置在像素定义层、金 属连接电极和像素电极上，并延伸OLED半导体层至凹孔中与金属连线连通，实现OLED半导体层与辅助电极实现电相连，同时由于凹孔中第一腔体和第二腔体形成的缺口，使得OLED半导体层以凹孔为断点呈不连续连接状态；
在步骤S9中、通过PVD在OLED半导体层上表面溅镀一层金属(如Ag/Mg)形成阴极，并延伸阴极的金属至凹孔中与金属连线连通，实现阴极与辅助电极实现电相连，用以提高阴极的导电能力；同时由于凹孔中第一腔体和第二腔体形成的缺口，使得实现阴极以凹孔为断点呈不连续连接状态，用以降低阴极的电阻。
综上所述，实施本发明实施例，具有如下有益效果：与传统的有机发光显示装置相比，本发明通过阵列基板上开设的凹孔来实现OLED半导体层上的阴极成不连续连接状态，有效的降低阴极的电阻，并使得阴极能延伸至凹孔内与辅助电极实现电连接，从而达到不仅能提高OLED半导体层上的阴极的导电能力，还能减少压降的目的；同时，由于节省了传统有机发光显示装的倒梯形结构柱脚，从而简化了制程工艺，达到省时省力的目的。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (19)

  1. 一种有机发光显示装置，其中，包括：
    阵列基板，所述阵列基板包括像素电极以及位于所述像素电极周围的金属连接电极和辅助电极；其中，所述金属连接电极通过所述阵列基板上开设的凹孔与所述辅助电极实现电连接；所述凹孔位于所述辅助电极的上方，并形成有相互连通的第一空腔和第二空腔，且所述第一空腔自所述第二空腔远离所述像素电极一侧的边缘线起沿远离所述像素电极的方向进行延伸；
    设置于所述阵列基板上的像素定义层；其中，所述像素定义层在所述阵列基板的凹孔和像素电极的上方分别预留有相应的凹槽；
    设置于所述阵列基板及所述像素定义层上的OLED半导体层；其中，所述OLED半导体层还覆盖于所述像素电极和所述金属连接电极上，并延伸至所述凹孔的第一空腔中与所述辅助电极实现电连接；以及
    设置于所述OLED半导体层上的阴极；其中，所述阴极还延伸至所述凹孔的第一空腔中与所述辅助电极实现电连接，并以所述凹孔为断点呈不连续连接状态。
  2. 如权利要求1所述的有机发光显示装置，其中，所述阵列基板为双栅结构的TFT阵列基板，包括：
    衬底基板；
    设置于所述衬底基板上的底部栅极以及所述辅助电极；
    覆盖于所述衬底基板、底部栅极以及辅助电极上的缓冲层；其中，所述缓冲层上开设有贯穿所述缓冲层上表面并与所述辅助电极相连通的第一导电孔；
    设置于所述缓冲层上的有源层；
    设置于所述有源层上的栅极绝缘层；
    设置于所述栅极绝缘层上的顶部栅极；
    覆盖于所述有源层、栅极绝缘层、顶部栅极及缓冲层上的中间电介质层；其中，所述中间电介质层上开设有贯穿所述中间电介质层上下表面并与所述第一导电孔相连通的第二导电孔，以及贯穿所述中间电介质层上表面并与所述有源层分别相连通的第三导电孔和第四导电孔；
    设置于所述中间电介质层上的源极、漏极和金属连线；其中，所述源极通过所述第三导电孔与所述有源层实现电相连和所述漏极通过所述第四导电孔与所述有源层实现电相连；或所述源极通过所述第四导电孔与所述有源层实现电相连和所述漏极通过所述第三导电孔与所述有源层实现电相连；所述金属连线依次通过所述第二导电孔及所述第一导电孔与所述辅助电极实现电相连；
    覆盖于所述源极、漏极和金属连线上的平坦层；其中，所述平坦层上开设有贯穿所述平坦层上表面并与所述源极或所述漏极相连通的第五导电孔，以及与所述金属连线相连通的所述凹孔；以及
    设置于所述平坦层上，通过所述第五导电孔与所述源极或所述漏极实现电相连的所述像素电极，以及通过所述凹孔与所述金属连线连通后再与所述辅助电极实现电相连的所述金属连接电极；
    其中，所述OLED半导体层和所述阴极均通过所述凹孔与所述金属连线连通后再与所述辅助电极实现电相连。
  3. 如权利要求2所述的有机发光显示装置，其中，所述平坦层为由有机材料制备而成的单层结构；其中，所述第五导电孔、所述凹孔的第一空腔和第二空腔均设置于所述单层结构的平坦层上；或
    由无机材料制备出的无机钝化层和由有机材料制备出的有机平坦层二者叠加而成的叠层结构；其中，所述第五导电孔贯穿所述有机平坦层上下表面并穿入所述无机钝化层中，所述凹孔的第一空腔设置于所述无机钝化层上，所述凹孔的第二空腔设置于位于所述无机钝化层上方的有机平坦层上。
  4. 如权利要求3所述的有机发光显示装置，其中，所述无机材料为SiOx、SiNx、SiNO之中其一种；所述有机材料为聚甲基丙烯酸甲酯PMMA或硅氧烷。
  5. 如权利要求4所述的有机发光显示装置，其中，所述缓冲层为由SiOx、SiNx、SiNO之中其一种制备而成的单层结构；或由SiNx/SiOx制备而成的叠层结构。
  6. 如权利要求5所述的有机发光显示装置，其中，所述有源层采用铟 镓锌氧化物IGZO或低温多晶硅LTPS制备而成。
  7. 如权利要求6所述的有机发光显示装置，其中，所述像素电极和所述辅助电极均采用ITO/Ag/ITO、IZO/Ag/IZO、AZO/Ag/AZO之中其一种金属氧化物制作而成。
  8. 一种有机发光显示装置，其中，包括：
    阵列基板，所述阵列基板包括像素电极以及位于所述像素电极周围的金属连接电极和辅助电极；其中，所述金属连接电极通过所述阵列基板上开设的凹孔与所述辅助电极实现电连接；所述凹孔位于所述辅助电极的上方，并形成有相互连通的第一空腔和第二空腔，且所述第一空腔自所述第二空腔远离所述像素电极一侧的边缘线起沿远离所述像素电极的方向进行延伸；
    设置于所述阵列基板上的像素定义层；其中，所述像素定义层在所述阵列基板的凹孔和像素电极的上方分别预留有相应的凹槽；
    设置于所述阵列基板及所述像素定义层上的OLED半导体层；其中，所述OLED半导体层还覆盖于所述像素电极和所述金属连接电极上，并延伸至所述凹孔的第一空腔中与所述辅助电极实现电连接；以及
    设置于所述OLED半导体层上的阴极；其中，所述阴极还延伸至所述凹孔的第一空腔中与所述辅助电极实现电连接，并以所述凹孔为断点呈不连续连接状态；
    其中，所述阵列基板为顶栅结构的TFT阵列基板，包括：
    衬底基板；
    设置于所述衬底基板上的光挡层以及所述辅助电极；
    覆盖于所述衬底基板、光挡层以及辅助电极上的缓冲层；其中，所述缓冲层上开设有贯穿所述缓冲层上表面并与所述辅助电极相连通的第一导电孔；
    设置于所述缓冲层上的有源层；
    设置于所述有源层上的栅极绝缘层；
    设置于所述栅极绝缘层上的顶部栅极；
    覆盖于所述有源层、栅极绝缘层、顶部栅极及缓冲层上的中间电介质层；其中，所述中间电介质层上开设有贯穿所述中间电介质层上下表面并与所述第一导电孔相连通的第二导电孔，以及贯穿所述中间电介质层上表面并与所述有源层分别相连通的第三导电孔和第四导电孔；
    设置于所述中间电介质层上的源极、漏极和金属连线；其中，所述源极通过所述第三导电孔与所述有源层实现电相连和所述漏极通过所述第四导电孔与所述有源层实现电相连；或所述源极通过所述第四导电孔与所述有源层实现电相连和所述漏极通过所述第三导电孔与所述有源层实现电相连；所述金属连线依次通过所述第二导电孔及所述第一导电孔与所述辅助电极实现电相连；
    覆盖于所述源极、漏极和金属连线上的平坦层；其中，所述平坦层上开 设有贯穿所述平坦层上表面并与所述源极或所述漏极相连通的第五导电孔，以及与所述金属连线相连通的所述凹孔；以及
    设置于所述平坦层上，通过所述第五导电孔与所述源极或所述漏极实现电相连的所述像素电极，以及通过所述凹孔与所述金属连线连通后再与所述辅助电极实现电相连的所述金属连接电极；
    其中，所述OLED半导体层和所述阴极均通过所述凹孔与所述金属连线连通后再与所述辅助电极实现电相连。
  9. 如权利要求8所述的有机发光显示装置，其中，所述平坦层为由有机材料制备而成的单层结构；其中，所述第五导电孔、所述凹孔的第一空腔和第二空腔均设置于所述单层结构的平坦层上；或
    由无机材料制备出的无机钝化层和由有机材料制备出的有机平坦层二者叠加而成的叠层结构；其中，所述第五导电孔贯穿所述有机平坦层上下表面并穿入所述无机钝化层中，所述凹孔的第一空腔设置于所述无机钝化层上，所述凹孔的第二空腔设置于位于所述无机钝化层上方的有机平坦层上。
  10. 如权利要求9所述的有机发光显示装置，其中，所述无机材料为SiOx、SiNx、SiNO之中其一种；所述有机材料为聚甲基丙烯酸甲酯PMMA或硅氧烷。
  11. 如权利要求10所述的有机发光显示装置，其中，所述缓冲层为由SiOx、SiNx、SiNO之中其一种制备而成的单层结构；或由SiNx/SiOx制备 而成的叠层结构。
  12. 如权利要求11所述的有机发光显示装置，其中，所述有源层采用铟镓锌氧化物IGZO或低温多晶硅LTPS制备而成。
  13. 如权利要求12所述的有机发光显示装置，其中，所述像素电极和所述辅助电极均采用ITO/Ag/ITO、IZO/Ag/IZO、AZO/Ag/AZO之中其一种金属氧化物制作而成。
  14. 一种有机发光显示装置，其中，包括：
    阵列基板，所述阵列基板包括像素电极以及位于所述像素电极周围的金属连接电极和辅助电极；其中，所述金属连接电极通过所述阵列基板上开设的凹孔与所述辅助电极实现电连接；所述凹孔位于所述辅助电极的上方，并形成有相互连通的第一空腔和第二空腔，且所述第一空腔自所述第二空腔远离所述像素电极一侧的边缘线起沿远离所述像素电极的方向进行延伸；
    设置于所述阵列基板上的像素定义层；其中，所述像素定义层在所述阵列基板的凹孔和像素电极的上方分别预留有相应的凹槽；
    设置于所述阵列基板及所述像素定义层上的OLED半导体层；其中，所述OLED半导体层还覆盖于所述像素电极和所述金属连接电极上，并延伸至所述凹孔的第一空腔中与所述辅助电极实现电连接；以及
    设置于所述OLED半导体层上的阴极；其中，所述阴极还延伸至所述凹孔的第一空腔中与所述辅助电极实现电连接，并以所述凹孔为断点呈不连续 连接状态；
    其中，所述阵列基板为底栅结构的TFT阵列基板，包括：
    衬底基板；
    设置于所述衬底基板上的底部栅极以及所述辅助电极；
    覆盖于所述衬底基板、底部栅极以及辅助电极上的缓冲层；其中，所述缓冲层上开设有贯穿所述缓冲层上表面并与所述辅助电极相连通的第一导电孔；
    设置于所述缓冲层上的有源层；
    覆盖于所述有源层及所述缓冲层上的中间电介质层；其中，所述中间电介质层上开设有贯穿所述中间电介质层上下表面并与所述第一导电孔相连通的第二导电孔，以及贯穿所述中间电介质层上表面并与所述有源层分别相连通的第三导电孔和第四导电孔；
    设置于所述中间电介质层上的源极、漏极和金属连线；其中，所述源极通过所述第三导电孔与所述有源层实现电相连和所述漏极通过所述第四导电孔与所述有源层实现电相连；或所述源极通过所述第四导电孔与所述有源层实现电相连和所述漏极通过所述第三导电孔与所述有源层实现电相连；所述金属连线依次通过所述第二导电孔及所述第一导电孔与所述辅助电极实现电相连；
    覆盖于所述源极、漏极和金属连线上的平坦层；其中，所述平坦层上开 设有贯穿所述平坦层上表面并与所述源极或所述漏极相连通的第五导电孔，以及与所述金属连线相连通的所述凹孔；以及
    设置于所述平坦层上，通过所述第五导电孔与所述源极或所述漏极实现电相连的所述像素电极，以及通过所述凹孔与所述金属连线连通后再与所述辅助电极实现电相连的所述金属连接电极；
    其中，所述OLED半导体层和所述阴极均通过所述凹孔与所述金属连线连通后再与所述辅助电极实现电相连。
  15. 如权利要求14所述的有机发光显示装置，其中，所述平坦层为由有机材料制备而成的单层结构；其中，所述第五导电孔、所述凹孔的第一空腔和第二空腔均设置于所述单层结构的平坦层上；或
    由无机材料制备出的无机钝化层和由有机材料制备出的有机平坦层二者叠加而成的叠层结构；其中，所述第五导电孔贯穿所述有机平坦层上下表面并穿入所述无机钝化层中，所述凹孔的第一空腔设置于所述无机钝化层上，所述凹孔的第二空腔设置于位于所述无机钝化层上方的有机平坦层上。
  16. 如权利要求15所述的有机发光显示装置，其中，所述无机材料为SiOx、SiNx、SiNO之中其一种；所述有机材料为聚甲基丙烯酸甲酯PMMA或硅氧烷。
  17. 如权利要求16所述的有机发光显示装置，其中，所述缓冲层为由SiOx、SiNx、SiNO之中其一种制备而成的单层结构；或由SiNx/SiOx制备 而成的叠层结构。
  18. 如权利要求17所述的有机发光显示装置，其中，所述有源层采用铟镓锌氧化物IGZO或低温多晶硅LTPS制备而成。
  19. 如权利要求18所述的有机发光显示装置，其中，所述像素电极和所述辅助电极均采用ITO/Ag/ITO、IZO/Ag/IZO、AZO/Ag/AZO之中其一种金属氧化物制作而成。
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