WO2023142012A1 - 显示面板及其制作方法、显示装置 - Google Patents

显示面板及其制作方法、显示装置 Download PDF

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Publication number
WO2023142012A1
WO2023142012A1 PCT/CN2022/074875 CN2022074875W WO2023142012A1 WO 2023142012 A1 WO2023142012 A1 WO 2023142012A1 CN 2022074875 W CN2022074875 W CN 2022074875W WO 2023142012 A1 WO2023142012 A1 WO 2023142012A1
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WIPO (PCT)
Prior art keywords
electrode
pixel
connection
sub
base substrate
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PCT/CN2022/074875
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English (en)
French (fr)
Inventor
周斌
刘宁
张大成
闫梁臣
王玉
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/074875 priority Critical patent/WO2023142012A1/zh
Priority to CN202280000100.7A priority patent/CN117280896A/zh
Priority to PCT/CN2022/090218 priority patent/WO2023142287A1/en
Priority to CN202280001048.7A priority patent/CN116897311A/zh
Publication of WO2023142012A1 publication Critical patent/WO2023142012A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel, a display device including the display panel, and a method for manufacturing the display panel.
  • the transparent display device can be applied to vehicle-mounted display terminals such as automobiles and subways, and window display scenarios such as hotels, clothing stores, and exhibitions to achieve realistic display effects.
  • the light transmittance of the display device should be as high as possible, and the brightness of the picture in the display area should be as uniform as possible.
  • An embodiment of the present disclosure provides a display panel, the display panel includes a base substrate, the display area of the display panel includes a plurality of sub-pixel areas, and each sub-pixel area in the plurality of sub-pixel areas includes: A first pixel electrode on the substrate and a second pixel electrode located on a side of the first pixel electrode away from the base substrate.
  • the display panel further includes an auxiliary electrode connection area, the auxiliary electrode connection area includes an auxiliary electrode and an electrode connection structure on the base substrate, the second pixel electrode is connected to the auxiliary electrode via the electrode connection structure, And the orthographic projection of the auxiliary electrode connection area on the base substrate does not overlap with the orthographic projection of the sub-pixel area on the base substrate.
  • the electrode connection structure includes a first connection electrode on the auxiliary electrode, a second connection electrode on the side of the first connection electrode away from the base substrate, and a second connection electrode on the first connection electrode and the second connection electrode.
  • a third connection electrode between the connection electrodes, the third connection electrode includes an upper surface in contact with the second connection electrode, a lower surface in contact with the first connection electrode and opposite to the upper surface, and a A vertical longitudinal section of the upper surface or the lower surface, the longitudinal section includes a top edge located in the upper surface and a bottom edge located in the lower surface, the bottom edge is on the base substrate
  • the orthographic projection of the overlay the orthographic projection of the top edge on the substrate substrate.
  • the orthographic projection of the first connection electrode on the substrate covers the orthographic projection of the second connection electrode on the substrate, and the third connection electrode on the substrate The orthographic projection on the base substrate does not exceed the orthographic projection of the second connection electrode on the base substrate.
  • the third connection electrode includes a longitudinal section perpendicular to the lower surface, and the longitudinal section includes a top edge located in the upper surface, a bottom edge located in the lower surface, and a side edge connecting the top edge and the bottom edge, the side edge and the lower surface intersect at an intersection point in the lower surface, wherein any point on the side edge is connected to the intersection point
  • the line forms an included angle with the lower surface, and the opening of the included angle faces the third connecting electrode and is less than or equal to 90 degrees.
  • the included angle is greater than or equal to 45 degrees and less than or equal to 70 degrees.
  • the display panel further includes a pixel definition layer on the base substrate, the display region forms the plurality of sub-pixel regions through the pixel definition layer, and the second pixel electrode extends Contacting at least one of the first connection electrode and the third connection electrode beyond the pixel definition layer, the first pixel electrode and the electrode connection structure are separated from each other by the pixel definition layer.
  • the orthographic projection of the second connection electrode on the base substrate covers the orthographic projection of the third connection electrode on the base substrate, so that the first connection electrode, the second connection electrode and the first connection electrode
  • the three connection electrodes form a cavity with an opening facing the pixel definition layer, the second pixel electrode extends into the cavity through the opening and connects with the first connection electrode and the third pixel electrode. Connect the electrode contacts.
  • the cavity includes an upper wall, a lower wall and a side wall, and the part of the second connection electrode extending toward the pixel definition layer and passing over the third connection layer forms the upper wall, so The portion of the first connection electrode extending toward the pixel definition layer and beyond the third connection layer forms the lower wall, the third connection electrode forms the side wall, and the upper wall is parallel to the The length of the horizontal direction of the surface direction of the base substrate is smaller than the length of the lower wall along the horizontal direction.
  • the length of the lower wall along the horizontal direction is 4 to 10 times the length of the upper wall along the horizontal direction.
  • the length of the upper wall along the horizontal direction is 1 to 2 times the height of the third connection electrode in a second direction, and the second direction is perpendicular to the horizontal direction. Vertically.
  • the third connection electrode and the first pixel electrode are in the same layer and include the same material.
  • both the third connection electrode and the first pixel electrode include a light reflective material.
  • the light reflective material includes aluminum alloy.
  • the display panel further includes a pixel driving circuit configured to drive the sub-pixel region to emit light
  • the pixel driving circuit includes a transistor, wherein the auxiliary electrode is connected to the source or drain of the transistor Be in the same layer and consist of the same material.
  • each second pixel electrode in the plurality of sub-pixel regions is connected to each other to form an integral structure.
  • the display panel further includes a light-shielding layer located between the base substrate and the pixel driving circuit, and the orthographic projection of the light-shielding layer on the base substrate covers the active layer of the transistor. Orthographic projection on the substrate substrate.
  • the display panel includes a plurality of auxiliary electrode connection regions, at least a part of the auxiliary electrode connection regions in the plurality of auxiliary electrode connection regions are located in adjacent sub-pixel regions. between pixels.
  • the display area includes a plurality of pixel units, each pixel unit includes at least three sub-pixel areas in the plurality of sub-pixel areas, and the display panel includes a plurality of the auxiliary electrode connection areas , wherein at least a part of the plurality of auxiliary electrode connection regions is located between adjacent pixel units of the plurality of pixel units.
  • the display panel includes a non-display area outside the display area, and the display panel includes a plurality of auxiliary electrode connection areas, wherein at least one of the plurality of auxiliary electrode connection areas A part of the auxiliary electrode connection area is located in the non-display area.
  • Another embodiment of the present disclosure provides a display device, which includes the display panel as described in any one of the foregoing embodiments.
  • Yet another embodiment of the present disclosure provides a method for manufacturing a display panel, including: providing a base substrate, the base substrate includes a display area, and the display area includes a plurality of sub-pixel areas; making a first pixel electrode and a second pixel electrode for each sub-pixel region in the plurality of sub-pixel regions, the second pixel electrode is located on the side of the first pixel electrode away from the base substrate; An auxiliary electrode and an electrode connection structure are formed on the base substrate, so that the auxiliary electrode is connected to the second pixel electrode through the electrode connection structure, wherein the electrode connection structure is located in the auxiliary electrode connection area, the The orthographic projection of the auxiliary electrode connection area on the base substrate does not overlap with the orthographic projection of the sub-pixel area on the base substrate.
  • the electrode connection structure includes a first connection electrode on the auxiliary electrode, a second connection electrode on the side of the first connection electrode away from the base substrate, and a second connection electrode on the first connection electrode and the second connection electrode.
  • a third connection electrode between the connection electrodes, the third connection electrode includes an upper surface in contact with the second connection electrode, a lower surface in contact with the first connection electrode and opposite to the upper surface, and a A longitudinal section perpendicular to the upper surface or the lower surface, the longitudinal section including a top edge located in the upper surface and a bottom edge located in the lower surface, the bottom edge being on the base substrate
  • the orthographic projection of the overlays the orthographic projection of the top edge on the substrate substrate.
  • the method further includes: fabricating a pixel driving circuit on the base substrate, the pixel driving circuit including a transistor, and fabricating the transistor and the auxiliary electrode include: forming a source-drain metal layer on the base substrate, the source-drain metal layer extending to the auxiliary electrode connection region; and patterning the source-drain metal layer by a single patterning process to form the source, drain and the auxiliary electrode.
  • the sub-pixel region further includes a first sub-conductive layer and a second sub-conductive layer
  • the second sub-conductive layer is located between the first pixel electrode and the second pixel electrode
  • the first sub-conductive layer is located on the side of the first pixel electrode facing the base substrate, and the electrode connection structure, the first sub-conductive layer, the second sub-conductive layer and the
  • the first pixel electrode includes: forming a first conductive layer on the source electrode, the drain electrode and the auxiliary electrode; and patterning the first conductive layer by using a single patterning process to obtain the first sub-conductive layer.
  • the first sub-conductive layer and the first connection electrode are respectively connected to the source of the transistor and the auxiliary electrode; between the first sub-conduction layer and the first sub-conduction layer Forming a first pixel electrode layer and a second conductive layer sequentially on a connecting electrode; performing etching on the second conductive layer to form the second sub-conductive layer and the second connecting electrode, and performing an etching process on the second conductive layer
  • the first pixel electrode layer is subjected to over-etching treatment at the position where the second conductive layer is subjected to etching treatment, so as to form the first pixel electrode and the third connection electrode, and the second connection electrode is
  • the orthographic projection on the base substrate covers the orthographic projection of the third connection electrode on the base substrate.
  • the method further includes: forming a pixel definition layer on the base substrate, and the display area forms the plurality of sub-pixel regions through the pixel definition layer, wherein the sub-pixels The first sub-conductive layer, the first pixel electrode and the second sub-conductive layer in the area are isolated from the electrode connection structure in the auxiliary electrode connection area by the pixel definition layer; and in the second sub-conductive fabricating a light-emitting layer on the light-emitting layer, wherein fabricating the second pixel electrode includes: forming the second pixel electrode on the light-emitting layer and the pixel definition layer, the second pixel electrode extending beyond the pixel definition layer making contact with at least one of the first connection electrode and the third connection electrode.
  • FIG. 1 shows a partial schematic top view of a display panel provided by an embodiment of the present disclosure
  • FIG. 2 shows a partial longitudinal cross-sectional view of the display panel obtained along the line segment "B1-B2" shown in FIG. 1;
  • Fig. 3a shows a schematic partial vertical cross-sectional view of an electrode connection structure in an auxiliary electrode connection region in a display panel according to another embodiment of the present disclosure
  • Fig. 3b shows a schematic partial vertical cross-sectional view of an electrode connection structure in an auxiliary electrode connection region in a display panel according to yet another embodiment of the present disclosure
  • FIG. 4 shows a schematic partial vertical cross-sectional view of a display panel provided according to another embodiment of the present disclosure
  • FIG. 8 shows an overall flow chart of manufacturing a display panel according to an embodiment of the present disclosure
  • FIG. 9 shows a flow chart of manufacturing a display panel according to another embodiment of the present disclosure.
  • Fig. 10 schematically shows the steps involved in making an electrode connection structure of a display panel according to another embodiment of the present disclosure
  • 11 to 16 show schematic partial vertical cross-sectional views of a display panel at different stages in the process of manufacturing a display panel according to another embodiment of the present disclosure.
  • the pixel electrodes of the display device can be made thinner, but this will increase the voltage drop on the extension path of the pixel electrodes.
  • a technical solution for making an auxiliary electrode in the display device has been proposed.
  • the voltage drop on the extension path of the pixel electrode still does not meet the display performance requirements of the display device, and the process of making the auxiliary electrode is relatively complicated.
  • An embodiment of the present disclosure provides a display panel, the display panel includes a base substrate, the display area of the display panel includes a plurality of sub-pixel areas, each sub-pixel area includes a first pixel electrode located on the base substrate, and a first pixel electrode located on the base substrate. The first pixel electrode is away from the second pixel electrode on the side of the base substrate.
  • the display panel further includes an auxiliary electrode connection area, the auxiliary electrode connection area includes an auxiliary electrode and an electrode connection structure on the base substrate, the second pixel electrode is connected to the auxiliary electrode through the electrode connection structure, and the The orthographic projection of the auxiliary electrode connection area on the base substrate does not overlap with the orthographic projection of the sub-pixel area on the base substrate.
  • the electrode connection structure includes a first connection electrode located on the auxiliary electrode, a second connection electrode located on the side of the first connection electrode away from the base substrate, and a second connection electrode located on the first connection electrode and the second connection electrode. between the third connection electrodes.
  • the third connection electrode includes an upper surface in contact with the first connection electrode, a lower surface in contact with the second connection electrode and opposite to the upper surface, and a longitudinal direction perpendicular to the upper surface or the lower surface.
  • Cross-section, the longitudinal section includes a top edge located in the upper surface and a bottom edge located in the lower surface, the orthographic projection of the bottom edge on the base substrate covers the top edge on the base substrate Orthographic projection on .
  • the meaning of “covering” mentioned herein includes exceeding or exceeding.
  • the meaning of "object A covering object B” means that the area of object A is larger than the area of object B and the boundary of object B is completely within the boundary of object A.
  • the first pixel electrode and the second pixel electrode mentioned herein refer to an electrode structure for receiving an electrical signal to control the sub-pixel region to emit light.
  • the first pixel electrode may be one of the anode and cathode of the OLED
  • the second pixel electrode may be the other of the anode and cathode of the OLED.
  • the embodiment of the display panel of the present disclosure is specifically described by taking the first pixel electrode as an anode of the OLED and the second pixel electrode as the cathode of the OLED as an example.
  • FIG. 1 illustrates a schematic partial top view of a display panel provided according to some embodiments of the present disclosure.
  • the display area AA of the display panel includes a plurality of sub-pixel areas, such as a red sub-pixel area r, a green sub-pixel area g, and a blue sub-pixel area b.
  • the display area AA also includes an auxiliary electrode connection area a.
  • the electrode connection area a may be distributed between adjacent sub-pixel areas.
  • a single red sub-pixel region r, a single green sub-pixel region g, and a single blue sub-pixel region b can be combined to form a pixel unit, and the auxiliary electrode connection region a is located between adjacent pixel units between.
  • the auxiliary electrode connection area includes the auxiliary electrode and the electrode connection structure on the base substrate, but this does not mean that the extension area of the auxiliary electrode above the base substrate is limited to the auxiliary electrode connection area.
  • the auxiliary electrodes can be distributed in the display area and the non-display area of the display panel, as long as they do not affect the normal light emission of the sub-pixel areas in the display area.
  • the auxiliary electrodes may be distributed along gaps between pixel units or sub-pixel regions.
  • FIG. 1 schematically shows the area where the auxiliary electrodes are located with a rectangular dotted line frame. It can be seen that the extension area of the auxiliary electrodes may be larger than the auxiliary electrode connection area.
  • FIG. 2 schematically shows a partial vertical cross-sectional view of the display panel shown in FIG. 1 taken along the horizontal line segment between arrow lines B1-B2.
  • the display panel includes a base substrate 100, a first pixel electrode E1, a second pixel electrode E2, and an auxiliary electrode 107c.
  • the electrode connection structure connecting the auxiliary electrode 107c and the second pixel electrode E2 includes a first connection electrode CE1, a second connection electrode CE2, and a third connection electrode CE3 located between the first connection electrode CE1 and the second connection electrode CE2.
  • the third connection electrode CE3 includes an upper surface in contact with the second connection electrode CE2, a lower surface in contact with the first connection electrode CE1 and opposite to the upper surface, and a contact with the upper surface or the lower surface.
  • the longitudinal section includes a top edge located in the upper surface and a bottom edge located in the lower surface, the orthographic projection of the bottom edge on the base substrate 100 covers the top edge on the Orthographic projection on the base substrate 100 described above.
  • the longitudinal section shown in FIG. 2 only represents an example of a certain longitudinal section of the third connecting electrode In other words, the present disclosure does not require that all longitudinal sections of the third connecting electrode have the characteristics of the top side and the bottom side of the longitudinal section described above.
  • the setting of the auxiliary electrode 107c can reduce the voltage drop on the extension path of the second pixel electrode when the display panel is running.
  • the second pixel electrode can be made relatively thinner, which is conducive to improving the light transmittance of the display panel.
  • the orthographic projection of the bottom edge of the longitudinal section of the third connection electrode on the base substrate exceeds to cover the orthographic projection of the top edge of the longitudinal section on the substrate substrate, which means that the third connection electrode has a and the slope structure between the lower surface, as further described below, this slope structure is beneficial to realize a larger contact area between the second pixel electrode and the electrode connection structure, and reduce the contact area between the second pixel electrode and the electrode connection structure.
  • the orthographic projection of the auxiliary electrode connection area on the base substrate does not overlap with the orthographic projection of the sub-pixel area on the base substrate, thereby reducing the normal effect of the auxiliary electrode connection area on the sub-pixel area as much as possible. Glowing effect.
  • This paper does not specifically limit the spatial position relationship between the electrode connection structure and the auxiliary electrode in the auxiliary electrode connection area.
  • Both the orthographic projection of the electrode connection structure on the substrate and the orthographic projection of the auxiliary electrode on the substrate can be at least partially Overlap, or not overlap. According to some embodiments of the present disclosure, as shown in FIG.
  • the electrode connection structure is located on the side of the auxiliary electrode 107c away from the base substrate 100 and directly above the auxiliary electrode 107c, so as to reduce the area of the auxiliary electrode connection area.
  • the auxiliary electrode 107c is located under the light emitting layer in the sub-pixel area, thereby preventing the light emitting layer in the sub-pixel area from being affected by the auxiliary electrode 107c.
  • the orthographic projection of the first connection electrode on the base substrate covers the orthographic projection of the second connection electrode on the base substrate, and the orthographic projection of the third connection electrode on the base substrate The orthographic projection of the second connection electrode on the base substrate is not exceeded.
  • the electrode connection structure including the first connection electrode, the second connection electrode and the third connection electrode can have a vertical cross-sectional structure similar to the Chinese character " ⁇ ".
  • This "I"-shaped vertical cross-sectional structure is very beneficial in A stable and effective connection between the second pixel electrode and the electrode connection structure is realized during the process of manufacturing the display panel.
  • the first connection electrode CE1 , the second connection electrode CE2 and the third connection electrode CE3 form a connection structure similar to the Chinese character " ⁇ ".
  • the third connection electrode includes a longitudinal section perpendicular to the lower surface, and the longitudinal section includes a top edge located in the upper surface, a bottom edge located in the lower surface, and a The side where the top edge and the bottom edge are connected, the side edge and the lower surface intersect at an intersection point in the lower surface, wherein the line connecting any point on the side edge to the intersection point is the same as The lower surface forms an included angle, and the opening of the included angle faces the third connecting electrode and is less than or equal to 90 degrees.
  • FIG. 3a alone shows a partial vertical cross-sectional view of an electrode connection structure in a display panel according to another embodiment of the present disclosure.
  • the third connection electrode CE3 has a longitudinal section perpendicular to its upper surface and lower surface, and the height of the longitudinal section is H in the vertical direction.
  • the longitudinal section of the third connection electrode CE3 includes a top edge located in the upper surface, a bottom edge located in the lower surface, and a side edge connecting the top edge and the bottom edge, and the side edge and the bottom edge are connected.
  • the bases intersect to form an acute angle ⁇ .
  • the acute angle ⁇ shown in Fig. 3a is an example of the aforementioned included angle.
  • this article does not make any indication of the shape of the side surface of the third connection electrode CE3, and the side surface of the third connection electrode CE3 can be flat or uneven and present any irregular shape. form.
  • Fig. 3b shows a partial vertical cross-sectional view of an electrode connection structure in a display panel according to yet another embodiment of the present disclosure.
  • Fig. 3b shows another example of the above-mentioned included angle ⁇ , and in the example of Fig. 3b, the third connection electrode CE3 includes a non-planar side surface.
  • the inventors of the present application have further learned through a large number of experiments that the size of the above-mentioned included angle also has an influence on the shape of the third connecting electrode itself.
  • the third connection electrode may be made of aluminum alloy or other metal materials. If the included angle is too small, it is easy to cause the third connection electrode to protrude during the subsequent manufacturing process of the display panel, which is not conducive to the connection between it and the second pixel electrode. effective contact. According to some embodiments of the present disclosure, the above included angle is greater than or equal to 45 degrees and less than or equal to 70 degrees, so as to achieve good contact between the third connection electrode and the second pixel electrode while preventing the third connection electrode from protruding. In the embodiment of FIG.
  • the display panel further includes a pixel definition layer on the base substrate, the display area forms a plurality of sub-pixel regions through the pixel definition layer, and the second pixel electrode extends beyond the pixel definition layer to connect with the first connection electrode.
  • the first pixel electrode is in contact with at least one of the third connection electrodes, and the first pixel electrode and the electrode connection structure are separated from each other by the pixel definition layer. This can be further understood by referring back to FIG. 2 .
  • the pixel definition layer PDL divides the display area of the display panel into a plurality of sub-pixel regions, and the second pixel electrode E2 in the sub-pixel region extends across the pixel definition layer PDL to be in contact with the first connection electrode CE1 and the third connection electrode CE3, and the first pixel
  • the electrode E1 and the electrode connection structure are isolated from each other by the pixel definition layer PDL.
  • the first pixel electrodes E1 in different sub-pixel regions are independent from each other through the pixel definition layer PDL, and the second pixel electrodes E2 in different sub-pixel regions (for example, the anode of OLED Cathodes) are connected to corresponding auxiliary electrodes, so that independent control of each sub-pixel area can be realized according to the image to be displayed.
  • thin film transistors for driving sub-pixels are also shown. In the example of FIG.
  • the thin film transistor is a top-gate structure, which includes a gate 105, a gate insulating layer 104, a drain 107a, a source 107b, an active layer (including a drain region 103b, a source region 103c and a trench Road area 103a).
  • FIG. 2 also shows a buffer layer 102 , a gate trace 105 a , an interlayer insulating layer 106 , a passivation layer 108 and a planarization layer 109 .
  • the auxiliary electrode 107c is connected to the second pixel electrode E2 via an electrode connection structure (including a first connection electrode CE1 , a second connection electrode CE2 and a third connection electrode CE3 ).
  • the source electrode 107b of the thin film transistor is connected to the first pixel electrode EC1.
  • the sub-pixel region further includes a light emitting layer EL located between the first pixel electrode E1 and the second pixel electrode E2 , as shown in FIG. 2 .
  • a partial cross-sectional view of the pixel definition layer PDL is shown in FIG.
  • the definition bars may be arranged along the row direction and the column direction of the sub-pixel region array formed by the multiple sub-pixel regions of the display region, so as to divide the display region of the display panel into a plurality of sub-pixel regions.
  • the orthographic projection of the first connection electrode CE1 on the base substrate 100 covers the orthographic projection of the second connection electrode CE2 on the base substrate 100, and the orthographic projection of the second connection electrode CE2 on the base substrate 100
  • the projection covers the orthographic projection of the third connection electrode CE3 on the base substrate 100, so that the first connection electrode CE1, the second connection electrode CE2 and the third connection electrode CE3 form a cavity with an opening, and the opening faces the pixel definition layer PDL,
  • the second pixel electrode E2 extends into the cavity through the opening and contacts the first connection electrode CE1 and the third connection electrode CE3 .
  • the structure of the cavity described above can also be understood more clearly with reference to the embodiment of FIG. 3a.
  • the cavity includes an upper wall, a lower wall and a side wall, the part of the second connecting electrode CE2 extending toward the pixel definition layer PDL and crossing the third connecting layer CE3 forms the upper wall of the cavity, and the first connecting electrode CE1
  • the portion extending toward the pixel definition layer PDL and beyond the third connection layer CE3 forms the lower wall
  • the third connection electrode forms the side wall
  • the upper wall is along a direction parallel to the surface of the base substrate.
  • the length in the horizontal direction is smaller than the length of the lower wall along the horizontal direction.
  • the length of the upper wall along the horizontal direction parallel to the surface direction of the base substrate is marked as D2
  • the length of the lower wall along the horizontal direction parallel to the surface direction of the base substrate is marked as D3.
  • Utilizing such a cavity structure can promote the material of the second pixel electrode E2 to extend into the cavity and fully contact the third connection electrode CE3 during the process of manufacturing the display panel, further reducing the voltage on the second pixel electrode when the display panel is in operation. drop.
  • the length D3 of the lower wall along the horizontal direction is 4 to 10 times the length D2 of the upper wall along the horizontal direction.
  • the size of D3 is about 5 microns
  • the size of D2 is between 0.5 microns and 1.2 microns.
  • the inside of the body and at the same time fully contact with the lower wall and side wall of the cavity, increasing the contact area between the second pixel electrode E2 and the first connection electrode CE1 and the third connection electrode CE3, which is beneficial to further reduce the operating time of the display panel.
  • the length of the second connection electrode CE2 in the horizontal direction parallel to the surface direction of the base substrate is identified as D1, which may be between 12 microns and 14 microns.
  • the light-emitting layer EL in at least a part of the sub-pixel area can extend beyond the pixel definition layer PDL to reach the auxiliary electrode connection area, and the height H of the third connection electrode in the second direction is equal to the height of the light-emitting layer in the second direction. 1.5 to 2 times the height d2 in both directions.
  • the third connection electrode CE3 in the electrode connection structure and the first pixel electrode E1 in the sub-pixel region are in the same layer and include the same material.
  • both the first pixel electrode E1 and the third connection electrode CE3 may include a light reflective material, and examples of the light reflective material include but are not limited to aluminum, molybdenum, silver or Alloy materials including the aforementioned metal elements.
  • both the first pixel electrode and the third connection electrode include aluminum alloy.
  • the first pixel electrode E1 and the third connection electrode CE3 may be formed simultaneously in a patterning process for the same aluminum alloy film layer. "Being in the same layer" mentioned in this article means that different structures are formed in the same patterning process for the same film layer, and these different structures are in the same layer.
  • the sub-pixel area of the display panel further includes a first sub-conductive layer EC1 and a second sub-conductive layer EC2, the second sub-conductive layer EC2 is located between the first pixel electrode E1 and the light emitting layer EL, the first The sub-conductive layer EC1 is located on the side of the first pixel electrode E1 facing the base substrate 100, the material of the first sub-conductive layer EC1 is in the same layer as the first connecting electrode CE1 and includes the same material, the second sub-conductive layer The material of the layer EC2 is in the same layer and includes the same material as the second connection electrode CE2, and the first sub-conductive layer EC1 and the second sub-conductive layer EC2 are separated from the electrode connection structure by the pixel definition layer PDL.
  • the first sub-conductive layer EC1 , the second sub-conductive layer EC2 , the first connection electrode CE1 and the second connection electrode CE2 all include a transparent conductive material, such as indium tin oxide ITO.
  • the first sub-conductive layer EC1 and the first connection electrode CE1 can be formed simultaneously in the patterning process for the same transparent conductive material layer. The layers are formed simultaneously in the patterning process.
  • the display panel includes a pixel driving circuit configured to drive each sub-pixel region to emit light.
  • the transistor shown in FIG. 2 is a part of the pixel driving circuit.
  • the material of the auxiliary electrode 107c and the source 107b or the drain 107a of the transistor are in the same layer and include the same material.
  • the auxiliary electrode 107c, the source 107b and the drain 107a of the transistor can be formed simultaneously in the patterning process for the same metal layer, so that the manufacturing process of the auxiliary electrode can be simplified and the cost of manufacturing the display panel can be saved.
  • the auxiliary electrode 107c is located under the light emitting layer of the sub-pixel area, thereby avoiding the influence of the auxiliary electrode on the performance of the light emitting layer of the sub-pixel area.
  • the second pixel electrodes in each sub-pixel region of the display panel are connected to each other to form an integral structure. Therefore, when the display panel is in operation, the second pixel electrode E2 in each sub-pixel area and the auxiliary electrode 107c in each auxiliary electrode connection area will have the same potential.
  • the second pixel electrodes in each sub-pixel region of the display panel can form an integral plate-shaped cathode (as the cathode of each OLED sub-pixel), and each auxiliary electrode is connected to the plate-shaped cathode through a corresponding electrode connection structure. In this way, the voltage drop on the cathode of the OLED sub-pixel can be further effectively reduced when the display panel is in operation, so that the cathode can be thinned and the light transmittance of the display device can be improved.
  • the display panel further includes a light-shielding layer 101 located between the base substrate 100 and the pixel driving circuit.
  • the orthographic projection of the light-shielding layer 101 on the base substrate 100 covers the active layer of the transistor (including the source region 103c, the drain region 103b and the channel region 103a) are orthographic projections on the base substrate.
  • the light-shielding layer 101 can reduce the amount of light irradiated to the active layer by the external ambient light passing through the base substrate 100 , which is beneficial to the stability of the operation performance of the transistor.
  • the transistor shown in FIG. 2 is a top-gate thin film transistor, this does not constitute a limitation to the embodiments of the present disclosure.
  • the pixel driving circuit may include a bottom-gate thin film transistor.
  • FIG. 4 shows a schematic partial vertical cross-sectional view of a display panel provided according to another embodiment of the present disclosure.
  • the structure of the display panel shown in Figure 4 is basically the same as that of the display panel shown in Figure 2, except that the main parts of the first connection electrode CE1, the second connection electrode CE2 and the third connection electrode CE3 in the electrode connection structure are all located on the insulating layer. (for example, including the passivation layer 108 and the planarization layer 109 ). Therefore, the embodiment of the display panel shown in FIG. 4 has the same advantages or technical effects as the embodiment shown in FIG. 2 , which will not be repeated here.
  • the display panel may further include other necessary layer structures located above the second pixel electrode E2 and covering the second pixel electrode E2 , which is not the focus of this disclosure and will not be described in detail here.
  • the display area of the display panel includes a plurality of pixel units, and each pixel unit includes at least three sub-pixel areas in the plurality of sub-pixel areas, for example, the red sub-pixel area r, the green sub-pixel area g and the blue sub-pixel area b. At least a part of the auxiliary electrode connection area of the display panel is located between adjacent pixel units among the plurality of pixel units.
  • the display panel includes a plurality of auxiliary electrode connection areas, and at least a part of the auxiliary electrode connection areas in the plurality of auxiliary electrode connection areas are located in adjacent sub-pixel areas. between sub-pixel regions. As shown in FIG.
  • the auxiliary electrode connection area a may be distributed between adjacent sub-pixel areas r, g, and b.
  • at least a part of the auxiliary electrode connection area of the display panel is located in its non-display area.
  • at least a part of the auxiliary electrode connection area a is located in the non-display area NA of the display panel, thereby reducing the number of auxiliary electrode connection areas a distributed in the display area AA or reducing the auxiliary electrode connection area a in the display area AA.
  • the purpose of the distribution of the electrode connection area a is to improve the aperture ratio of the display area AA. Or as shown in FIG.
  • all the auxiliary electrode connection areas a are located in the non-display area NA of the display panel, so that the influence of the auxiliary electrode connection area on the aperture ratio in the display area AA can be avoided, and at the same time, the second The voltage drop across the path where the pixel electrode extends.
  • the auxiliary electrodes are not shown in FIGS. 5 to 7 .
  • the display device may be any electronic device or a component in the electronic device with a display function. Examples of the display device include but are not limited to a vehicle display, a window display, a TV, a watch, and the like.
  • the method may include the following steps: S801. Provide a base substrate, the base substrate includes a display area, and the display area including a plurality of sub-pixel regions; S802, fabricating a first pixel electrode and a second pixel electrode for each sub-pixel region in the plurality of sub-pixel regions on the base substrate, the second pixel electrode being located in the first The side of the pixel electrode away from the base substrate; S803, fabricate an auxiliary electrode and an electrode connection structure on the base substrate, so that the auxiliary electrode is connected to the second pixel electrode through the electrode connection structure,
  • the electrode connection structure is located in the auxiliary electrode connection area, the orthographic projection of the auxiliary electrode connection area on the base substrate does not overlap with the orthographic projection of the sub-pixel area on the base substrate, the
  • the electrode connection structure includes a first connection electrode located on the auxiliary electrode, a second connection electrode located on the side of the first connection electrode away from the base substrate, and a
  • the third connection electrode includes an upper surface in contact with the second connection electrode, a lower surface in contact with the first connection electrode and opposite to the upper surface, and a lower surface in contact with the first connection electrode.
  • a thinner second pixel electrode can be realized to improve the light transmission of the display panel rate, and can better reduce the voltage drop on the second pixel electrode, further improving the brightness uniformity of the image displayed on the display panel.
  • the method for manufacturing a display panel further includes manufacturing a pixel driving circuit on the base substrate, and the pixel driving circuit includes a transistor.
  • the source and drain of the transistor and the above-mentioned auxiliary electrodes can be formed in the same patterning process, as shown in FIG. 9, the above-mentioned step S803 includes: S8031, forming a source-drain metal on the substrate layer, the source-drain metal layer extends to the auxiliary electrode connection region; S8032, pattern the source-drain metal layer using a single patterning process to form the source, drain and the auxiliary electrode of the transistor electrode.
  • the "single patterning process” mentioned in this article refers to the use of a single mask to form multiple desired structures (for example, the above-mentioned source, drain and auxiliary electrodes) in the patterning process, so these structures can be formed on the same It is formed in the patterning process, thereby simplifying the manufacturing process of the display panel and reducing the cost of manufacturing the display panel.
  • the sub-pixel area of the display panel further includes a first sub-conductive layer and a second sub-conductive layer, the second sub-conductive layer is located between the first pixel electrode and the second pixel electrode, and the first The sub-conductive layer is located on the side of the first pixel electrode facing the base substrate.
  • the first sub-conductive layer, the first pixel electrode and the second sub-conductive layer may be formed in the same process as the first connection electrode, the third connection electrode and the second connection electrode in the electrode connection structure respectively. In other words, as shown in FIG.
  • making the electrode connection structure, the first sub-conductive layer, the second sub-conductive layer and the first pixel electrode may include the following steps: making the electrode connection structure may include the following steps : S1001, forming a first conductive layer on the source electrode, the drain electrode and the auxiliary electrode; S1002, patterning the first conductive layer by using a single patterning process to obtain the The first sub-conductive layer and the first connection electrode located in the auxiliary electrode connection area, the first sub-conductive layer and the first connection electrode are respectively connected to the source of the transistor and the auxiliary electrode; S1003, sequentially forming a first pixel electrode layer and a second conductive layer on the first sub-conductive layer and the first connection electrode; S1004, performing etching on the second conductive layer to form a The second sub-conductive layer in the sub-pixel area and the second connection electrode located in the auxiliary electrode connection area; and S1005, etching the first pixel electrode at the position where the second conductive layer is etched The layer is etched to form the first pixel electrode located in the sub
  • the "over-etching process” mentioned here means that the etching degree of the first pixel electrode layer is larger than the etching degree of the second conductive layer, so that the first pixel electrode layer is etched at the etched position.
  • a larger indentation is used to form the above-mentioned second connection electrode, or in other words, make the second connection electrode extend a certain distance outward relative to the third connection electrode.
  • the method for manufacturing a display panel may further include: forming a pixel definition layer on the base substrate, the display region forms the plurality of sub-pixel regions through the pixel definition layer, the The first sub-conductive layer, the first pixel electrode and the second sub-conductive layer in the sub-pixel area are separated from the electrode connection structure in the auxiliary electrode connection area by the pixel definition layer; and in the second A light-emitting layer is formed on the sub-conductive layer.
  • fabricating the second pixel electrode includes: forming the second pixel electrode on the light-emitting layer and the pixel definition layer, the second pixel electrode extending beyond the pixel definition layer and connecting with the first pixel electrode A connection electrode is in contact with at least one of the third connection electrodes.
  • components such as an auxiliary electrode 107c and a pixel circuit for driving sub-pixels are fabricated on the base substrate 100 .
  • the transistor in the pixel circuit may include a gate 105, a gate insulating layer 104, a drain 107a, a source 107b, and an active layer (including a drain region 103b, a source region 103c and a channel region 103a).
  • other necessary auxiliary structures can also be fabricated on the base substrate 100 , for example, a light shielding layer 101 , a buffer layer 102 , a gate wiring 105 a , an interlayer insulating layer 106 , and a passivation layer 108 .
  • the auxiliary electrode 107c and the source 107b and the drain 107a of the transistor can be formed in a single patterning process, so as to simplify the process of making the auxiliary electrode.
  • a source-drain metal layer can be formed on the patterned interlayer insulating layer 106, and the source-drain metal layer is patterned to be patterned, and the auxiliary electrode 107c can be formed at the same time. and the source 107b and drain 107a of the transistor.
  • a flat layer 109 can be formed on the passivation layer 108 , and the material of the flat layer 109 includes but not limited to resin.
  • a first via hole h1 and a second via hole h2 are respectively formed at the position corresponding to the source electrode 107b of the transistor and the position corresponding to the auxiliary electrode 107c, and the first via hole h1 and the second via hole h2 Both pass through the passivation layer 108 and the planar layer 109 , thereby obtaining the patterned planar layer 109 and the passivation layer 108 .
  • FIG. 13 a first via hole h1 and a second via hole h2 are respectively formed at the position corresponding to the source electrode 107b of the transistor and the position corresponding to the auxiliary electrode 107c, and the first via hole h1 and the second via hole h2 Both pass through the passivation layer 108 and the planar layer 109 , thereby obtaining the patterned planar layer 109 and the passivation layer 108 .
  • the material of the first conductive layer (for example, indium tin oxide ITO) is deposited on the patterned flat layer 109, and the material of the first conductive layer fills the above-mentioned first via hole h1 and the second via hole h2, thereby forming a first conductive layer, and the first conductive layer is respectively connected to the source electrode 107b and the auxiliary electrode 107c via the first via hole h1 and the second via hole h2.
  • the first conductive layer is patterned to form the first sub-conductive layer EC1 in the sub-pixel region and the first connection electrode CE1 in the auxiliary electrode connection region.
  • the patterned first conductive layer includes an opening p such that the first A sub-conductive layer EC1 and the first connection electrode CE1 are independent and insulated from each other.
  • the second conductive layer can be etched with H 2 SO 4 -based dilute acid, and then the first pixel electrode layer can be over-etched with H 3 PO 4 -based concentrated acid, so that the second conductive layer and the first
  • the pixel electrode layer is patterned, the patterned second conductive layer and the opening in the first pixel electrode layer expose the opening p in the aforementioned patterned first conductive layer, and form the second sub-conductive layer EC2 and the second connection electrode CE2, the first pixel electrode E1 and the third connection electrode CE3 are shown in FIG. 15 .
  • the opening formed in the first pixel electrode layer is larger than the opening formed in the second conductive layer, and the formed third connecting electrode CE3 has a slope structure
  • the second The second connection electrode CE2 extends a certain distance outward relative to the third connection electrode CE3, or in other words, the orthographic projection of the second connection electrode CE2 on the substrate covers the orthographic projection of the third connection electrode CE3 on the substrate.
  • the formed third connection electrode CE3 has a trapezoidal longitudinal section, and the angle value of the bottom angle of the trapezoidal longitudinal section is greater than or equal to 45 degrees and less than or equal to 70 degrees.
  • the first connection electrode CE1 , the second connection electrode CE2 and the third connection electrode CE3 form an electrode connection structure similar to the Chinese character " ⁇ ".
  • the "I"-shaped electrode connection structure includes a cavity with openings formed by the first connection electrode, the second connection electrode and the third connection electrode.
  • the electrode connection structure is disconnected from the first sub-conductive layer EC1 , the first pixel electrode E1 and the second sub-conductive layer EC2 through the opening formed in the foregoing etching process.
  • the material is deposited on the second connecting electrode CE2, and the light emitting layer material on the second connecting electrode CE2 will not form a continuous structure with the light emitting layer on the pixel definition layer. This provides a basis for realizing good connection between the second pixel electrode and the electrode connection structure to be formed later.
  • the second pixel electrode E2 may be formed on the light emitting layer EL by a sputtering process.
  • indium zinc oxide (IZO) material can be sputtered on the light-emitting layer EL, thereby making the indium zinc oxide layer formed by sputtering have better diffusivity, and the indium zinc oxide material can bypass the cavity of the aforementioned electrode connection structure
  • the upper wall of the body is deposited onto the first connection electrode CE1.
  • the third connection electrode CE3 has a slope structure (for example, the third connection electrode CE3 has a trapezoidal vertical section, and the bottom angle of the trapezoidal vertical section is an acute angle), so in the process of sputtering to form the second pixel electrode E2 , the material of the second pixel electrode can easily climb along the third connection electrode CE3, so that there is a larger contact area between the second pixel electrode E2 and the third connection electrode CE3 and the first connection electrode CE1, which can further effectively The voltage drop on the second pixel electrode is reduced when the display panel is in operation.

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Abstract

一种显示面板，包括衬底基板(100)，显示面板的显示区(AA)包括多个子像素区，每个子像素区包括：位于衬底基板(100)上的第一像素电极(E1)和位于第一像素电极(E1)背离衬底基板(100)的一侧的第二像素电极(E2)。显示面板还包括辅助电极连接区，辅助电极连接区包括位于衬底基板(100)上的辅助电极(107c)和电极连接结构，第二像素电极(E2)经由电极连接结构连接至辅助电极(107c)，且辅助电极连接区在衬底基板(100)上的正投影与子像素区在衬底基板(100)上的正投影无交叠。电极连接结构包括位于辅助电极(107c)上的第一连接电极(CE1)、位于第一连接电极(CE1)背离衬底基板(100)一侧的第二连接电极(CE2)、以及位于第一连接电极(CE1)和第二连接电极(CE2)之间的第三连接电极(CE3)，第三连接电极(CE3)包括与第二连接电极(CE2)接触的上表面、与第一连接电极(CE1)接触并与上表面相对的下表面、以及与上表面或下表面垂直的纵截面，纵截面包括位于上表面内的顶边和位于下表面内的底边，底边在衬底基板(100)上的正投影覆盖顶边在衬底基板(100)上的正投影。

Description

显示面板及其制作方法、显示装置 技术领域
本申请涉及显示技术领域，具体地，涉及一种显示面板、包括该显示面板的显示装置和制作该显示面板的方法。
背景技术
随着半导体工艺和材料技术等方面的不断进步，电子显示产品也得到快速的升级和发展。目前，液晶显示器已经得到广泛的应用，诸如有机发光二极管显示装置的等新型显示装置也有长足的发展。甚至在一些场景中，出现了透明显示装置。例如，透明显示装置可应用于汽车、地铁等车载显示终端和酒店、服装店、展会等橱窗展示场景，以实现逼真的显示效果。
尽管如此，人们对显示装置的性能也有着越来越高的要求，例如，期望显示装置的透光率要尽可能地高、显示区域内的画面的亮度要尽可能均一等。
发明内容
本公开的实施例提供了一种显示面板，该显示面板包括衬底基板，显示面板的显示区包括多个子像素区，所述多个子像素区中的每个子像素区包括：位于所述衬底基板上的第一像素电极和位于所述第一像素电极背离所述衬底基板的一侧的第二像素电极。显示面板还包括辅助电极连接区，所述辅助电极连接区包括位于所述衬底基板上的辅助电极和电极连接结构，所述第二像素电极经由所述电极连接结构连接至所述辅助电极，且所述辅助电极连接区在所述衬底基板上的正投影与所述子像素区在所述衬底基板上的正投影无交叠。所述电极连接结构包括位于所述辅助电极上的第一连接电极、位于第一连接电极背离所述衬底基板一侧的第二连接电极、以及位于所述第一连接电极和所述第二连接电极之间的第三连接电极，所述第三连接电极包括与所述第二连接电极接触的上表面、与所述第一连接电极接触并与所述上表面相对的下表面、以及与所述上表面或所述下表面垂直的纵截面，所述纵截面包括位于所述上表面内的顶边和位于所述下表面内的底边， 所述底边在所述衬底基板上的正投影覆盖所述顶边在所述衬底基板上的正投影。
根据本公开的一些实施例，第一连接电极在所述衬底基板上的正投影覆盖所述第二连接电极在所述衬底基板上的正投影，所述第三连接电极在所述衬底基板上的正投影不超出所述第二连接电极在所述衬底基板上的正投影。
根据本公开的一些实施例，所述第三连接电极包括与所述下表面垂直的纵截面，所述纵截面包括位于所述上表面内的顶边、位于所述下表面内的底边、和将所述顶边和所述底边连接的侧边，所述侧边和所述下表面在所述下表面内相交于交点，其中所述侧边上的任意一点到所述交点的连线与所述下表面形成夹角，所述夹角的开口朝向所述第三连接电极且小于等于90度。
根据本公开的一些实施例，所述夹角大于等于45度而小于等于70度。
根据本公开的一些实施例，显示面板还包括位于所述衬底基板上的像素定义层，所述显示区通过所述像素定义层而形成所述多个子像素区，所述第二像素电极延伸越过所述像素定义层而与所述第一连接电极和所述第三连接电极中的至少一个接触，所述第一像素电极与所述电极连接结构通过所述像素定义层而彼此隔离。
根据本公开的一些实施例，第二连接电极在衬底基板上的正投影覆盖所述第三连接电极在衬底基板上的正投影，使得所述第一连接电极、第二连接电极和第三连接电极形成带有开口的腔体，所述开口面向所述像素定义层，所述第二像素电极经由所述开口延伸至所述腔体内并与所述第一连接电极和所述第三连接电极接触。
根据本公开的一些实施例，腔体包括上壁、下壁和侧壁，所述第二连接电极朝所述像素定义层延伸而越过所述第三连接层的部分形成所述上壁，所述第一连接电极朝所述像素定义层延伸而越过所述第三连接层的部分形成所述下壁，所述第三连接电极形成所述侧壁，且所述上壁沿平行于所述衬底基板的表面方向的水平方向的长度小于且所述下壁沿所述水平方向的长度。
根据本公开的一些实施例，所述下壁沿所述水平方向的长度是所述上壁沿所述水平方向的长度的4至10倍。
根据本公开的一些实施例，上壁沿所述水平方向的长度是所述第三连接电极在第二方向上的高度的1至2倍，所述第二方向为垂直于所述水平方向的竖直方向。
根据本公开的一些实施例，所述第三连接电极和所述第一像素电极处于同一层且包括相同的材料。
根据本公开的一些实施例，所述第三连接电极和所述第一像素电极均包括光反射材料。
根据本公开的一些实施例，所述光反射材料包括铝合金。
根据本公开的一些实施例，子像素区还包括第一子导电层和第二子导电层，其中所述第二子导电层位于所述第一像素电极和所述第二像素电极之间，所述第一子导电层位于所述第一像素电极面向所述衬底基板的一侧，其中第一子导电层的材料与所述第一连接电极处于同一层且包括相同的材料，第二子导电层的材料与所述第二连接电极处于同一层且包括相同的材料，所述第一子导电层和所述第二子导电层通过所述像素定义层而与所述电极连接结构隔离。
根据本公开的一些实施例，显示面板还包括被配置成驱动所述子像素区发光的像素驱动电路，所述像素驱动电路包括晶体管，其中所述辅助电极与所述晶体管的源极或漏极处于同一层且包括相同的材料。
根据本公开的一些实施例，所述多个子像素区内的各个第二像素电极彼此相连而成为一体结构。
根据本公开的一些实施例，显示面板还包括位于所述衬底基板和所述像素驱动电路之间的遮光层，所述遮光层在衬底基板上的正投影覆盖所述晶体管的有源层在所述衬底基板上的正投影。
根据本公开的一些实施例，显示面板包括多个所述辅助电极连接区，所述多个所述辅助电极连接区中的至少一部分辅助电极连接区位于所述多个子像素区中相邻的子像素区之间。
根据本公开的一些实施例，所述显示区包括多个像素单元，每个像素单元包括所述多个子像素区中的至少三个子像素区，所述显示面板包括多个所述辅助电极连接区，其中所述多个所述辅助电极连接区中的至少一部分辅助电极连接区位于所述多个像素单元中相邻的像素单元之间。
根据本公开的一些实施例，所述显示面板包括处于显示区外部的 非显示区，所述显示面板包括多个所述辅助电极连接区，其中所述多个所述辅助电极连接区中的至少一部分辅助电极连接区位于所述非显示区内。
本公开的另外的实施例提供了一种显示装置，其包括如前述实施例中任一实施例所述的显示面板。
本公开的又一实施例提供了一种制作显示面板的方法，包括：提供衬底基板，所述衬底基板包括显示区，所述显示区包括多个子像素区；在所述衬底基板上制作用于所述多个子像素区中的各个子像素区的第一像素电极和第二像素电极，所述第二像素电极位于所述第一像素电极背离所述衬底基板的一侧；在所述衬底基板上制作辅助电极和电极连接结构，使得所述辅助电极通过所述电极连接结构而与所述第二像素电极连接，其中所述电极连接结构位于辅助电极连接区内，所述辅助电极连接区在所述衬底基板上的正投影与所述子像素区在所述衬底基板上的正投影无交叠。所述电极连接结构包括位于所述辅助电极上的第一连接电极、位于第一连接电极背离所述衬底基板一侧的第二连接电极、以及位于所述第一连接电极和所述第二连接电极之间的第三连接电极，所述第三连接电极包括与所述第二连接电极接触的上表面、与所述第一连接电极接触并与所述上表面相对的下表面、以及与所述上表面或所述下表面垂直的纵截面，所述纵截面包括位于所述上表面内的顶边和位于所述下表面内的底边，所述底边在所述衬底基板上的正投影覆盖所述顶边在所述衬底基板上的正投影。
根据本公开的一些实施例，所述方法还包括：在所述衬底基板上制作像素驱动电路，所述像素驱动电路包括晶体管，制作所述晶体管和制作所述辅助电极包括：在所述衬底基板上形成源漏金属层，所述源漏金属层延伸至所述辅助电极连接区；和采用单次构图工艺对所述源漏金属层进行图案化，以形成所述晶体管的源极、漏极和所述辅助电极。
根据本公开的一些实施例，所述子像素区还包括第一子导电层和第二子导电层，所述第二子导电层位于所述第一像素电极和所述第二像素电极之间，所述第一子导电层位于所述第一像素电极面向所述衬底基板的一侧，制作所述电极连接结构、所述第一子导电层、所述第二子导电层和所述第一像素电极包括：在所述源极、漏极和所述辅助 电极上制作第一导电层；采用单次构图工艺对所述第一导电层进行图案化处理以获得所述第一子导电层和所述第一连接电极，所述第一子导电层和所述第一连接电极分别与所述晶体管的源极和所述辅助电极连接；在所述第一子导电层和所述第一连接电极上依次形成第一像素电极层和第二导电层；对所述第二导电层进行刻蚀处理，以形成所述第二子导电层和所述第二连接电极，以及在对所述第二导电层进行刻蚀处理的位置处对所述第一像素电极层进行过刻蚀处理，以形成所述第一像素电极和所述第三连接电极，且所述第二连接电极在所述衬底基板上的正投影覆盖所述第三连接电极在所述衬底基板上的正投影。
根据本公开的一些实施例，所述方法还包括：在所述衬底基板上形成像素定义层，所述显示区通过所述像素定义层而形成所述多个子像素区，其中所述子像素区内的第一子导电层、第一像素电极和第二子导电层通过所述像素定义层而与所述辅助电极连接区内的所述电极连接结构隔离；以及在所述第二子导电层上制作发光层，其中制作所述第二像素电极包括：在所述发光层和所述像素定义层上形成所述第二像素电极，所述第二像素电极延伸越过所述像素定义层而与所述第一连接电极和所述第三连接电极中的至少一个接触。
以上概述了本公开的一些实施例，这些实施例将通过下文中的具体描述进一步被阐述。通过对上述实施例中的一些特征或者不同实施例进行组合，可以获得与上述实施例不同的另外的实施例，这些不同的另外的实施例同样属于本公开的技术方案。
附图说明
在下面结合附图对于示例性实施例的描述中，本公开的技术方案更多细节、特征和优点被公开，在附图中：
图1示出了本公开实施例提供的显示面板的局部示意性俯视图；
图2示出了沿着图1中所示的线段“B1-B2”获得的显示面板的局部纵截面示意图；
图3a示出了根据本公开的另一实施例的显示面板中的辅助电极连接区中的电极连接结构的局部纵截面示意图；
图3b示出了根据本公开的又一实施例的显示面板中的辅助电极连接区中的电极连接结构的局部纵截面示意图；
图4示出根据本公开的另外的实施例提供的显示面板的局部纵截面示意图；
图5-图7分别示出了根据本公开的另外的实施例提供的显示面板的局部示意性俯视图；
图8示出了根据本公开的实施例提供的制作显示面板的总体流程图；
图9示出了根据本公开的另外的实施例提供的制作显示面板的流程图；
图10示意性地示出了根据本公开的另外实施例提供的制作显示面板的电极连接结构涉及的步骤；
图11-图16示出了根据本公开的另外的实施例提供的制作显示面板过程中处于不同步骤阶段的显示面板的示意性局部纵截面图。
具体实施方式
下面将参照附图更详细地描述本申请的若干个实施例以便使得本领域技术人员能够实现本申请的技术方案。本申请的技术方案可以体现为许多不同的形式和目的，并且不应局限于本文所阐述的实施例。提供这些实施例是为了使得本申请的技术方案清楚完整，但所述实施例并不限定本申请的保护范围。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本申请所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
为了提高显示装置的透光率，可以将显示装置的像素电极制作得较薄，但这会引起像素电极延伸路径上的电压降的增加。为了降低像素电极延伸路径上的电压降，已经提出在显示装置中制作辅助电极的技术方案，然而，已有的通过辅助电极降低像素电极延伸路径上的电压降的技术方案仍存在不少改进之处，例如，像素电极延伸路径上的电压降仍不满足显示装置显示性能的需要，制作辅助电极的工艺较为复杂等。
本公开实施例提供了一种显示面板，该显示面板包括衬底基板，显示面板的显示区包括多个子像素区，每个子像素区包括位于所述衬底基板上的第一像素电极、和位于所述第一像素电极背离所述衬底基板的一侧的第二像素电极。该显示面板还包括辅助电极连接区，辅助电极连接区包括位于所述衬底基板上的辅助电极和电极连接结构，第二像素电极经由所述电极连接结构连接至所述辅助电极，且所述辅助电极连接区在所述衬底基板上的正投影与所述子像素区在所述衬底基板上的正投影无交叠。电极连接结构包括位于所述辅助电极上的第一连接电极、位于第一连接电极背离所述衬底基板一侧的第二连接电极、以及位于所述第一连接电极和所述第二连接电极之间的第三连接电极。第三连接电极包括与所述第一连接电极接触的上表面、与所述第二连接电极接触并与所述上表面相对的下表面、以及与所述上表面或所述下表面垂直的纵截面，纵截面包括位于所述上表面内的顶边和位于所述下表面内的底边，所述底边在所述衬底基板上的正投影覆盖所述顶边在所述衬底基板上的正投影。
本文提到的“覆盖”的含义包括超过或超出，相应地，“对象A覆盖对象B”的含义是对象A的面积大于对象B的面积且对象B的边界完全位于对象A的边界之内。本文提到的第一像素电极和第二像素电极指的是用于接收电信号以控制子像素区发光的电极结构。例如，对于有机发光二极管(OLED)显示面板而言，第一像素电极可以是OLED的阳极和阴极中的一个，第二像素电极可以是OLED的阳极和阴极中的另一个。在下面的描述中，以第一像素电极为OLED的阳极、第二像素电极为OLED的阴极为例具体说明本公开的显示面板的实施例。
图1图示了根据本公开的一些实施例提供的显示面板的示意性局部俯视图。如图1所示，显示面板的显示区AA包括多个子像素区，例如红色子像素区r、绿色子像素区g和蓝色子像素区b，显示区AA还包括辅助电极连接区a，辅助电极连接区a可分布在相邻的子像素区之间。在图1的示例中，单个的红色子像素区r、单个的绿色子像素区g和单个的蓝色子像素区b可组合形成一个像素单元，辅助电极连接区a位于相邻的像素单元之间。当然，显示面板的子像素区不限于图1所示的示例，在其他实施例中，显示区还可以包括白色子像素区、黄色 子像素区等，显示区AA内子像素区的数量和具体排列不是本公开的技术方案的关键，本文对此也不作任何限制。
如前所述，辅助电极连接区包括位于衬底基板上的辅助电极和电极连接结构，但是这并不意味着辅助电极在衬底基板上方的延伸区域仅限于辅助电极连接区。辅助电极可以分布在显示面板的显示区和非显示区，只要不影响显示区内的子像素区的正常发光即可。在一些实施例中，辅助电极可以沿着像素单元之间或者子像素区之间的间隙分布。例如，图1中以矩形虚线框示意性地示出了辅助电极所在的区域，可以看出，辅助电极的延伸区域可大于辅助电极连接区。在其他的实施例中，辅助电极可以延伸分布至更多的区域，例如，辅助电极可以同时分布在相邻列的像素单元之间的间隙和相邻行的像素单元之间的间隙。在一些实施例中，分布在不同区域中的全部辅助电极可以彼此连接，形成一个图案化的一体结构。
图2示意性地示出了图1所示的显示面板沿着箭头线B1-B2之间的水平线段得到的显示面板的局部纵截面图。显示面板包括衬底基板100、第一像素电极E1、第二像素电极E2和辅助电极107c，将辅助电极107c和第二像素电极E2连接的电极连接结构包括第一连接电极CE1、第二连接电极CE2、以及位于第一连接电极CE1和第二连接电极CE2之间的第三连接电极CE3。如图2所示，第三连接电极CE3包括与第二连接电极CE2接触的上表面、与第一连接电极CE1接触并与上表面相对的下表面、以及与所述上表面或所述下表面垂直的纵截面，纵截面包括位于所述上表面内的顶边和位于所述下表面内的底边，所述底边在所述衬底基板100上的正投影覆盖所述顶边在所述衬底基板100上的正投影。这里并不对纵截面的顶边和底边分别在上述上表面和下表面内的具体位置作出限制，也就是说，图2所示的纵截面仅表示第三连接电极的某一纵截面的示例，换言之，本公开并不要求第三连接电极所有纵截面均具备以上描述的纵截面的顶边和底边的特性。
辅助电极107c的设置可降低显示面板运行时第二像素电极延伸路径上的电压降，在这种情况下，可以将第二像素电极制作得相对更薄，从而有利于提升显示面板的透光率。而且，第三连接电极的纵截面的底边在衬底基板上的正投影超出以覆盖该纵截面的顶边在衬底基板上的正投影，这意味着第三连接电极具有位于其上表面和下表面之间的 斜坡结构，如在下文中进一步描述的，这种斜坡结构有利于实现第二像素电极和电极连接结构之间更大的接触面积，降低第二像素电极和电极连接结构之间的接触电阻，进一步有效地降低显示面板运行时第二像素电极延伸路径上的电压降。因此，利用本公开实施例提供的技术方案，可以在通过薄化第二像素电极而提升显示面板的透光率的情况下进一步地避免第二像素电极上的电压降过大，进一步提升显示面板显示的图像的亮度均一性。
如前所述，辅助电极连接区在衬底基板上的正投影与子像素区在所述衬底基板上的正投影无交叠，由此尽可能降低辅助电极连接区对子像素区的正常发光的影响。本文不对辅助电极连接区内的电极连接结构和辅助电极的空间位置关系作具体的限定，电极连接结构在衬底基板上的正投影与辅助电极在衬底基板上的正投影二者可以至少部分交叠，也可以不交叠。根据本公开的一些实施例，如图2所示，电极连接结构位于辅助电极107c背离衬底基板100的一侧且位于辅助电极107c的正上方，以减小辅助电极连接区的面积。同时，辅助电极107c位于子像素区内的发光层的下方，由此避免子像素区内的发光层受到辅助电极107c的影响。
根据本公开的一些实施例，第一连接电极在所述衬底基板上的正投影覆盖第二连接电极在衬底基板上的正投影，第三连接电极在所述衬底基板上的正投影不超出所述第二连接电极在所述衬底基板上的正投影。由此，可以使得包括第一连接电极、第二连接电极和第三连接电极的电极连接结构具有类似于汉字“工”的纵截面结构，这种“工”字形的纵截面结构十分有利于在制作显示面板过程中实现第二像素电极与电极连接结构的稳定有效的连接。例如，在图2的截面图中，第一连接电极CE1、第二连接电极CE2和第三连接电极CE3形成类似于汉字“工”的连接结构。
根据本公开的一些实施例，第三连接电极包括与所述下表面垂直的纵截面，所述纵截面包括位于所述上表面内的顶边、位于所述下表面内的底边、和将所述顶边和所述底边连接的侧边，所述侧边和所述下表面在所述下表面内相交于交点，其中所述侧边上的任意一点到所述交点的连线与所述下表面形成夹角，所述夹角的开口朝向所述第三连接电极且小于等于90度。利用这样的夹角形成的第三连接电极的斜 坡结构，在制作显示面板的过程中，可以使得第二像素电极E2的材料容易地扩散到第三连接电极CE3的侧边，有利于实现第二像素电极与第三连接电极的之间较大的接触面积。例如，图3a单独示出了根据本公开的另一实施例的显示面板中的电极连接结构局部纵截面图。如图3a所示，第三连接电极CE3具有与其上表面和下表面垂直的纵截面，该纵截面在竖直方向上的高度为H。第三连接电极CE3的纵截面包括位于上述上表面内的顶边、位于所述下表面内的底边、和将所述顶边和所述底边连接的侧边，所述侧边和所述底边相交形成锐角α。图3a所示的锐角α即为前述的夹角的一个示例。此外，能够理解到的是，本文不对上述的第三连接电极CE3的侧表面的形态作出任何显示，第三连接电极CE3的侧表面可以是平坦的，也可以是凹凸不平而呈现任意不规则的形态。图3b示出了根据本公开的又一实施例的显示面板中的电极连接结构局部纵截面图。图3b示出了上述的夹角的另一示例β，且在图3b的示例中，第三连接电极CE3包括非平坦的侧表面。
本申请的发明人通过大量的实验进一步获知，上述夹角的大小对第三连接电极自身的形态也存在影响。第三连接电极可包括铝合金或其他的金属材料，如果夹角过小，容易引起第三连接电极在显示面板后续的制作工艺中发生凸起现象，不利于其与第二像素电极之间的有效接触。根据本公开的一些实施例，上述的夹角大于等于45度而小于等于70度，从而实现在预防第三连接电极发生凸起的情况下实现第三连接电极和第二像素电极的良好接触。在图3a的实施例中，第三连接电极CE3的纵截面呈梯形形状。当然，本公开实施例的显示面板中的第三连接电极CE3的纵截面的梯形形状并不受图3a所示的具体示例的限制。
根据本公开的一些实施例，显示面板还包括位于衬底基板上的像素定义层，显示区通过像素定义层而形成多个子像素区，第二像素电极延伸越过像素定义层而与第一连接电极和第三连接电极中的至少一个接触，第一像素电极与所述电极连接结构通过所述像素定义层而彼此隔离。这可返回参照图2得到进一步的理解。像素定义层PDL将显示面板的显示区分成多个子像素区，子像素区中的第二像素电极E2延伸越过像素定义层PDL而与第一连接电极CE1和第三连接电极CE3接触，第一像素电极E1与电极连接结构通过像素定义层PDL而彼此 隔离。在该实施例中，不同子像素区内的第一像素电极E1(例如，OLED的阳极)通过像素定义层PDL而彼此独立，而不同子像素区内的第二像素电极E2(例如，OLED的阴极)均连接至对应的辅助电极，由此可以根据要显示的图像实现对各子像素区的独立控制。在图2的示例中，还示出了用于驱动子像素的薄膜晶体管。在图2的示例中，薄膜晶体管为顶栅型结构，其包括栅极105、栅绝缘层104、漏极107a、源极107b、有源层(包括漏极区103b、源极区103c和沟道区103a)。图2还示出了缓冲层102、栅极走线105a、层间绝缘层106、钝化层108和平坦层109。辅助电极107c经由电极连接结构(包括第一连接电极CE1、第二连接电极CE2和第三连接电极CE3)与第二像素电极E2连接。薄膜晶体管的源极107b与第一像素电极EC1连接。在显示面板为OLED显示面板的情形中，子像素区还包括位于第一像素电极E1和第二像素电极E2之间的发光层EL，如图2所示。能够理解到的是，图2中仅示出了像素定义层PDL的局部截面图，像素定义层PDL可以包括多个像素定义条(像素定义条为由绝缘材料形成的条状结构)，这些像素定义条可沿着显示区的多个子像素区构成的子像素区阵列的行方向和列方向排列，从而将显示面板的显示区分成多个子像素区。
在图2的示例中，第一连接电极CE1在衬底基板上100的正投影覆盖第二连接电极CE2在衬底基板100上的正投影，第二连接电极CE2在衬底基板上100的正投影覆盖第三连接电极CE3在衬底基板100上的正投影，使得第一连接电极CE1、第二连接电极CE2和第三连接电极CE3形成带有开口的腔体，开口面向像素定义层PDL，第二像素电极E2经由上述开口延伸至所述腔体内并与第一连接电极CE1和第三连接电极CE3接触。关于上述的腔体的结构也可以参照图3a的实施例更加清楚地得到理解。如图3a所示，腔体包括上壁、下壁和侧壁，第二连接电极CE2朝像素定义层PDL延伸而越过第三连接层CE3的部分形成腔体的上壁，第一连接电极CE1朝像素定义层PDL延伸而越过所述第三连接层CE3的部分形成所述下壁，所述第三连接电极形成所述侧壁，且所述上壁沿平行于衬底基板的表面方向的水平方向的长度小于所述下壁沿所述水平方向的长度。在图3a中，上壁沿平行于所述衬底基板的表面方向的水平方向的长度被标识为D2，下壁沿平行于衬底基板的表面方向的水平方向的长度被标识为D3。利用这样的腔体结构， 在制作显示面板的过程中可以促进第二像素电极E2的材料延伸至腔体内并与第三连接电极CE3充分接触，进一步降低显示面板运行时第二像素电极上的电压降。根据本公开的一些实施例，所述下壁沿所述水平方向的长度D3是所述上壁沿所述水平方向的长度D2的4至10倍。例如，D3的大小约为5微米，而D2的大小在0.5微米至1.2微米之间，通过大量的实验测试验证，这可确保在制作第二像素电极E2的过程中使得其延伸至上述的腔体内部并同时与上述腔体的下壁和侧壁充分地接触，增加第二像素电极E2与第一连接电极CE1和第三连接电极CE3之间的接触面积，有利于进一步降低显示面板运行时第二像素电极延伸路径上的电压降。第二连接电极CE2在平行于衬底基板的表面方向的水平方向的长度被标识为D1，其可以在12微米至14微米之间。
根据本公开的一些实施例，所述上壁沿所述水平方向的长度D2是第三连接电极在第二方向上的高度的1至2倍，所述第二方向为垂直于所述水平方向的竖直方向。这可有利于在制作显示面板的过程中防止过多的发光层EL的材料进入上述腔体内。第三连接电极在第二方向上的高度即为前述的第三连接电极的纵截面在竖直方向上的高度H。根据本公开的一些实施例，上述的高度H为0.5微米至0.6微米之间，发光层EL在所述第二方向上的高度d2大约为3200埃米。如图3a所示，至少一部分子像素区中的发光层EL可延伸越过像素定义层PDL到达辅助电极连接区，第三连接电极在所述第二方向上的高度H是发光层在所述第二方向上的高度d2的1.5至2倍。
根据本公开的一些实施例，电极连接结构中的第三连接电极CE3和子像素区内的第一像素电极E1处于同一层且包括相同的材料。例如，在显示面板为顶发射式OLED显示面板的情形中，第一像素电极E1和第三连接电极CE3均可包括光反射性材料，光反射材料的示例包括但不限于铝、钼、银或包括前述金属元素的合金材料。在一些实施例中，第一像素电极和第三连接电极均包括铝合金。第一像素电极E1和第三连接电极CE3可以在针对同一铝合金膜层的图案化工艺中同时形成。本文提到的“处于同一层”意味着针对同一膜层在同一构图工艺中形成不同的结构，这些不同的结构即处于同一层。
返回参照图2，显示面板的子像素区还包括第一子导电层EC1和第二子导电层EC2，第二子导电层EC2位于第一像素电极E1和发光层 EL之间，所述第一子导电层EC1位于所述第一像素电极E1面向所述衬底基板100的一侧，第一子导电层EC1的材料与第一连接电极CE1处于同一层且包括相同的材料，第二子导电层EC2的材料与第二连接电极CE2处于同一层且包括相同的材料，所述第一子导电层EC1和所述第二子导电层EC2通过像素定义层PDL而与电极连接结构隔离。在一些实施例中，第一子导电层EC1、第二子导电层EC2、第一连接电极CE1和第二连接电极CE2均包括透明导电材料，例如铟锡氧化物ITO。第一子导电层EC1和第一连接电极CE1可以在针对同一透明导电材料层的构图工艺中同时形成，类似地，第二子导电层EC2和第二连接电极CE2可以在针对另一透明导电材料层的构图工艺中同时形成。
根据本公开的一些实施例，显示面板包括被配置成驱动各个子像素区发光的像素驱动电路。图2中所示的晶体管是像素驱动电路的一部分，如图2所示，辅助电极107c的材料和晶体管的源极107b或漏极107a处于同一层且包括相同的材料。例如，辅助电极107c、晶体管的源极107b和漏极107a可以在针对同一金属层的构图工艺中同时形成，如此，可以简化辅助电极的制作工艺，节约制作显示面板的成本。另外，与晶体管的源极107b和漏极107a一样，辅助电极107c处于子像素区的发光层的下方，由此避免辅助电极对子像素区的发光层的性能的影响。
根据本公开的实施例，显示面板的各个子像素区内的第二像素电极彼此相连而成为一体结构。因此，当显示面板运行时，各个子像素区域内的第二像素电极E2、各个辅助电极连接区内辅助电极107c将具有相同的电位。例如，显示面板的各个子像素区内的第二像素电极可以形成一个整体的板状阴极(作为各个OLED子像素的阴极)，各个辅助电极通过相应的电极连接结构与该板状阴极连接。这样，可进一步有效地降低显示面板运行时OLED子像素的阴极上的电压降，从而可以实现阴极的薄化，提升显示装置的透光率。
在图2实施例中，显示面板还包括位于衬底基板100和像素驱动电路之间的遮光层101，遮光层101在衬底基板100上的正投影覆盖晶体管的有源层(包括源极区103c、漏极区103b和沟道区103a)在衬底基板上的正投影。遮光层101可以减少透过衬底基板100的外部环境光照射到有源层的光的量，有利于晶体管的工作性能的稳定。虽然图2 中示出的晶体管是顶栅型薄膜晶体管，这并不构成对本公开实施例的限制，在本公开的其它实施例中，像素驱动电路可以包括底栅型薄膜晶体管。
图4示出根据本公开的另外的实施例提供的显示面板的局部纵截面示意图。图4所示的显示面板与图2所示的显示面板的结构基本相同，只是电极连接结构中的第一连接电极CE1、第二连接电极CE2和第三连接电极CE3的主要部分均位于绝缘层(例如包括钝化层108和平坦层109)的过孔内。因此，图4所示的显示面板的实施例具有与图2所示的实施例相同的优点或技术效果，在此不再重复。另外，显示面板还可包括位于第二像素电极E2上方覆盖第二像素电极E2的其它必要的层结构，这不是本公开的重点，在此也不再详述。
在图1的实施例中，显示面板的显示区包括多个像素单元，每个像素单元包括所述多个子像素区中的至少三个子像素区，例如，红色子像素区r、绿色子像素区g和蓝色子像素区b。显示面板的至少一部分辅助电极连接区位于所述多个像素单元中相邻的像素单元之间。替代性地，在另外的实施例中，显示面板包括多个辅助电极连接区，所述多个所述辅助电极连接区中的至少一部分辅助电极连接区位于所述多个子像素区中相邻的子像素区之间。如图5所示，辅助电极连接区a可分布于相邻的子像素区r、g、b之间。或者，在其它实施例中，显示面板的至少一部分辅助电极连接区位于其非显示区。如图6所示，至少一部分辅助电极连接区a位于显示面板的非显示区NA，由此可以减小分布在显示区AA中的辅助电极连接区a的数目或者降低在显示区AA中的辅助电极连接区a的分布目的，有利于提升显示区AA的开口率。再或者如图7所示，全部的辅助电极连接区a均位于显示面板的非显示区NA，从而可以避免辅助电极连接区对显示区AA内开口率的影响，同时降低显示面板运行时第二像素电极延伸路径上的电压降。为了简便起见，图5至图7没有示出辅助电极。
本公开的另外的实施例提供了一种显示装置，该显示装置包括如前述实施例中任一实施例所述的显示面板。显示装置可以是任何具备显示功能的电子设备或电子设备中的部件，显示装置的示例包括但不限于车载显示器、橱窗显示器、电视机、手表等。
本公开的另一实施例提供了一种制作显示面板的方法，如图8所 示，该方法可包括如下步骤：S801、提供衬底基板，所述衬底基板包括显示区，所述显示区包括多个子像素区；S802、在所述衬底基板上制作用于多个子像素区中的各个子像素区的第一像素电极和第二像素电极，所述第二像素电极位于所述第一像素电极背离所述衬底基板的一侧；S803、在所述衬底基板上制作辅助电极和电极连接结构，使得所述辅助电极通过所述电极连接结构而与所述第二像素电极连接，所述电极连接结构位于辅助电极连接区内，所述辅助电极连接区在所述衬底基板上的正投影与所述子像素区在所述衬底基板上的正投影无交叠，所述电极连接结构包括位于所述辅助电极上的第一连接电极、位于第一连接电极背离所述衬底基板一侧的第二连接电极、以及位于所述第一连接电极和所述第二连接电极之间的第三连接电极，所述第三连接电极包括与所述第二连接电极接触的上表面、与所述第一连接电极接触并与所述上表面相对的下表面、以及与所述上表面或所述下表面垂直的纵截面，所述纵截面包括位于所述上表面内的顶边和位于所述下表面内的底边，所述底边在所述衬底基板上的正投影覆盖所述顶边在衬底基板上的正投影。
利用本公开实施例提供的制作显示面板的方法来制作显示面板，可获得与前述的显示面板的实施例类似的技术效果，即，可以实现较薄的第二像素电极进而提升显示面板的透光率，同时能够更好地降低第二像素电极上的电压降，进一步提升显示面板显示的图像的亮度均一性。
根据本公开的一些实施例，制作显示面板的方法还包括在衬底基板上制作像素驱动电路，所述像素驱动电路包括晶体管。在该实施例中，晶体管的源极、漏极和上述辅助电极可以在同一构图工艺中形成，如图9所示，上述的步骤S803包括：S8031、在所述衬底基板上形成源漏金属层，所述源漏金属层延伸至所述辅助电极连接区；S8032、采用单次构图工艺对所述源漏金属层进行图案化，以形成所述晶体管的源极、漏极和所述辅助电极。本文提到的“单次构图工艺”指的是在构图工艺中采用单个的掩膜板形成期望的多个结构(例如，上述的源极、漏极和辅助电极)，因此这些结构可以在同一构图工艺中形成，由此简化了显示面板的制作工艺，降低了制作显示面板的成本。
根据本公开的一些实施例，显示面板的子像素区还包括第一子导 电层和第二子导电层，第二子导电层位于第一像素电极和所述第二像素电极之间，第一子导电层位于第一像素电极面向衬底基板的一侧。此时，第一子导电层、第一像素电极和第二子导电层可以分别与电极连接结构中第一连接电极、第三连接电极和第二连接电极在同一工艺中形成。换言之，如图10所示，制作所述电极连接结构、所述第一子导电层、所述第二子导电层和所述第一像素电极可包括如下步骤：制作电极连接结构可包括如下步骤：S1001、在所述源极、漏极和所述辅助电极上制作第一导电层；S1002、采用单次构图工艺对所述第一导电层进行图案化处理以获得位于所述子像素区的第一子导电层和位于所述辅助电极连接区的所述第一连接电极，所述第一子导电层和所述第一连接电极分别与所述晶体管的源极和所述辅助电极连接；S1003、在所述第一子导电层和所述第一连接电极上依次形成第一像素电极层和第二导电层；S1004、对所述第二导电层进行刻蚀处理，以形成位于所述子像素区的第二子导电层和位于所述辅助电极连接区的所述第二连接电极；以及S1005、在对所述第二导电层进行刻蚀处理的位置处对所述第一像素电极层进行过刻蚀处理，以形成位于所述子像素区的所述第一像素电极和位于所述辅助电极连接区的所述第三连接电极，且所述第二连接电极在所述衬底基板上的正投影覆盖所述第三连接电极在所述衬底基板上的正投影。这里提到的“过刻蚀处理”指的是对第一像素电极层的刻蚀程度相较于对第二导电层的刻蚀程度更大，使得第一像素电极层在刻蚀位置处发生更大的缩进量从而形成上述的第二连接电极，或者说，使得第二连接电极相对于第三连接电极向外延伸一定的距离。
根据本公开的一些实施例，制作显示面板的方法还可包括：在所述衬底基板上形成像素定义层，所述显示区通过所述像素定义层而形成所述多个子像素区，所述子像素区内的第一子导电层、第一像素电极和第二子导电层通过所述像素定义层而与所述辅助电极连接区内的所述电极连接结构隔离；以及在所述第二子导电层上制作发光层。相应地，制作所述第二像素电极包括：在所述发光层和所述像素定义层上形成所述第二像素电极，所述第二像素电极延伸越过所述像素定义层而与所述第一连接电极和所述第三连接电极中的至少一个接触。
下面，结合图11至图16通过示例的方式更详细地说明根据本公 开实施例的制作显示面板的方法的一些步骤。
如图11所示，在衬底基板100上制作辅助电极107c和用于驱动子像素的像素电路等部件。像素电路中的晶体管可包括栅极105、栅绝缘层104、漏极107a、源极107b、有源层(包括漏极区103b、源极区103c和沟道区103a)。此外，还可以在衬底基板100上制作其它必要的辅助性结构，例如，遮光层101、缓冲层102、栅极走线105a、层间绝缘层106、钝化层108。在此过程中，辅助电极107c和晶体管的源极107b、漏极107a可以在单次构图工艺中形成，以简化制作辅助电极的工艺。例如，在形成图案化的层间绝缘层106后，可以在图案化的层间绝缘层106上制作源漏金属层，并对源漏金属层进行构图工艺使得其图案化，同时形成辅助电极107c和晶体管的源极107b、漏极107a。如图12所示，在制作完成钝化层108后，可以在钝化层108上形成平坦层109，平坦层109的材料包括但不限于树脂。
接下来，如图13所示，在晶体管的源极107b对应的位置和辅助电极107c对应的位置分别形成第一过孔h1和第二过孔h2，第一过孔h1和第二过孔h2均穿透钝化层108和平坦层109，从而获得图案化的平坦层109和钝化层108。如图14所示，在图案化的平坦层109上沉积第一导电层的材料(例如，铟锡氧化物ITO)，第一导电层的材料填充上述的第一过孔h1和第二过孔h2，从而形成第一导电层，第一导电层经由第一过孔h1和第二过孔h2分别与源极107b和辅助电极107c连接。此后，对第一导电层进行图案化处理，形成子像素区内的第一子导电层EC1和辅助电极连接区中的第一连接电极CE1，图案化的第一导电层包括开口p而使得第一子导电层EC1和第一连接电极CE1彼此独立、相互绝缘。
接着，在图案化的第一导电层上依次形成第一像素电极层和第二导电层。第一像素电极层可包括反射性金属材料(包括但不限于铝合金等)，第二导电层可包括铟锡氧化物ITO等。然后，在前述的图案化的第一导电层中的开口p的位置处先后对第二导电层和第一像素电极层进行刻蚀处理。例如，可采用H 2SO 4系稀酸对第二导电层进行刻蚀，然后用H 3PO 4系浓酸对第一像素电极层进行过刻蚀处理，分别使得第二导电层和第一像素电极层图案化，图案化的第二导电层和第一像素电极层中的开口暴露前述的图案化的第一导电层中的开口p，并形 成第二子导电层EC2、第二连接电极CE2、第一像素电极E1和第三连接电极CE3，如图15所示。通过对第一像素电极层进行过刻蚀处理，使得第一像素电极层中形成的开口比第二导电层中形成的开口更大，并使得所形成的第三连接电极CE3具有斜坡结构，第二连接电极CE2相对于第三连接电极CE3向外延伸一定的距离，或者说，第二连接电极CE2在衬底基板上的正投影覆盖第三连接电极CE3在衬底基板上的正投影。在一些实施例中，通过上述的过刻蚀处理，使得形成的第三连接电极CE3具有梯形纵截面，梯形纵截面的底角的角度值大于等于45度而小于等于70度。例如，在一些实施例中，在对第一像素电极层进行图案化处理的过程中，可以控制刻蚀液(例如，H 3PO 4系浓酸)与第一像素电极层发生化学反应的过程的时间，以实现具有梯形纵截面的第三连接电极CE3。在一个实验性示例中，在对包括铝合金的0.6微米厚的第一像素电极层进行刻蚀时，从向第一像素电极层施加H 3PO 4系浓酸开始后的110秒，第一像素电极层因被H 3PO 4系浓酸刻蚀而出现过孔，从向第一像素电极层施加H 3PO 4系浓酸开始后的143-176秒的时间段内可以形成具有梯形纵截面的第三连接电极CE3。因此，通过控制刻蚀液与第一像素电极层发生化学反应的时间，可以制作形成期望的第三连接电极。第一连接电极CE1、第二连接电极CE2和第三连接电极CE3形成类似于汉字“工”的电极连接结构。该“工”字形电极连接结构包括由第一连接电极、第二连接电极和第三连接电极形成的带有开口的腔体。电极连接结构通过在前述刻蚀工艺中形成的开口而与第一子导电层EC1、第一像素电极E1和第二子导电层EC2断开。
如图16所示，在电极连接结构与第一子导电层EC1、第一像素电极E1和第二子导电层EC2之间的开口位置处形成像素定义层PDL，像素定义层PDL填充电极连接结构与第一子导电层EC1、第一像素电极E1和第二子导电层EC2之间的开口的一部分，但像素定义层PDL的材料并不延伸至第一连接电极、第二连接电极和第三连接电极形成的腔体内部。此后，可以在第二子导电层EC2上形成发光层。在一些实施例中，返回参照图2，可以通过蒸镀工艺形成有机电致发光层，发光层EL可延伸越过像素定义层PDL。采用蒸镀工艺形成发光层EL，这样可使得在形成发光层EL期间发光层EL的材料的扩散性较差，进而通过电极连接结构中的第二连接电极CE2朝像素定义层PDL延伸超 出第三连接电极CE3的部分(即，前述的显示面板实施例中描述的电极连接结构的腔体的上壁)可以阻止发光层的材料进入上述腔体的内部，即使在蒸镀工艺中，一部分发光层材料沉积在第二连接电极CE2的上方，第二连接电极CE2上的发光层材料也不会与像素定义层上的发光层形成连续的结构。这为实现之后要形成的第二像素电极与电极连接结构的良好连接提供了基础。继续参照图2，在一些实施例中，可通过溅射工艺在发光层EL上形成第二像素电极E2。例如，可以在发光层EL上喷溅氧化铟锌(IZO)材料，由此使得喷溅形成的氧化铟锌层具有较好的扩散性，氧化铟锌材料可以绕过前述的电极连接结构的腔体的上壁而沉积到第一连接电极CE1上。如前所述，由于第三连接电极CE3具有斜坡结构(例如，第三连接电极CE3具有梯形纵截面，梯形纵截面的底角为锐角)，所以在喷溅形成第二像素电极E2的过程中，第二像素电极的材料可以容易地沿着第三连接电极CE3爬升，使得第二像素电极E2与第三连接电极CE3和第一连接电极CE1之间存在较大的接触面积，能够进一步有效地降低显示面板运行时第二像素电极上的电压降。
以上结合一些实施例描述了本公开的技术方案，但是本公开的实施例并不被限于在本文中所阐述的特定形式。相反，本申请要求保护的范围仅由所附权利要求来限制。将理解的是，尽管第一、第二、等术语在本文中可以用来描述各种设备、元件、部件或部分，但是这些设备、元件、部件或部分不应当由这些术语限制。这些术语仅用来将一个设备、元件、部件或部分与另一个设备、元件、部件或部分相区分。本文提到的“连接”包括“直接连接”或“间接连接”。
此外，尽管单独的特征可以被包括在不同的权利要求中，但是这些可以可能地被有利地组合，并且包括在不同权利要求中不暗示特征的组合不是可行的和/或有利的。特征在权利要求中的次序不暗示特征必须以其工作的任何特定次序。此外，在权利要求中，词“包括”不排除其他元件，并且术语“一”或“一个”不排除多个。

Claims (24)

  1. 一种显示面板，包括衬底基板，所述显示面板的显示区包括多个子像素区，所述多个子像素区中的每个子像素区包括：位于所述衬底基板上的第一像素电极和位于所述第一像素电极背离所述衬底基板的一侧的第二像素电极，
    其中所述显示面板还包括辅助电极连接区，所述辅助电极连接区包括位于所述衬底基板上的辅助电极和电极连接结构，所述第二像素电极经由所述电极连接结构连接至所述辅助电极，且所述辅助电极连接区在所述衬底基板上的正投影与所述子像素区在所述衬底基板上的正投影无交叠，
    其中所述电极连接结构包括位于所述辅助电极上的第一连接电极、位于第一连接电极背离所述衬底基板一侧的第二连接电极、以及位于所述第一连接电极和所述第二连接电极之间的第三连接电极，
    其中所述第三连接电极包括与所述第二连接电极接触的上表面、与所述第一连接电极接触并与所述上表面相对的下表面、以及与所述上表面或所述下表面垂直的纵截面，所述纵截面包括位于所述上表面内的顶边和位于所述下表面内的底边，其中所述底边在所述衬底基板上的正投影覆盖所述顶边在所述衬底基板上的正投影。
  2. 根据权利要求1所述的显示面板，其中所述第一连接电极在所述衬底基板上的正投影覆盖所述第二连接电极在所述衬底基板上的正投影，所述第三连接电极在所述衬底基板上的正投影不超出所述第二连接电极在所述衬底基板上的正投影。
  3. 根据权利要求2所述的显示面板，其中所述纵截面包括将所述顶边和所述底边连接的侧边，所述侧边和所述下表面在所述下表面内相交于交点，其中所述侧边上的任意一点到所述交点的连线与所述下表面形成夹角，所述夹角的开口朝向所述第三连接电极且小于等于90度。
  4. 根据权利要求4所述的显示面板，其中所述夹角大于等于45度而小于等于70度。
  5. 根据权利要求1所述的显示面板，其中所述显示面板还包括位于所述衬底基板上的像素定义层，所述显示区通过所述像素定义层而 形成所述多个子像素区，所述第二像素电极延伸越过所述像素定义层而与所述第一连接电极和所述第三连接电极中的至少一个接触，所述第一像素电极与所述电极连接结构通过所述像素定义层而彼此隔离。
  6. 根据权利要求5所述的显示面板，其中所述第二连接电极在衬底基板上的正投影覆盖所述第三连接电极在衬底基板上的正投影，使得所述第一连接电极、第二连接电极和第三连接电极形成带有开口的腔体，所述开口面向所述像素定义层，所述第二像素电极经由所述开口延伸至所述腔体内并与所述第一连接电极和所述第三连接电极接触。
  7. 根据权利要求6所述的显示面板，其中所述腔体包括上壁、下壁和侧壁，其中所述第二连接电极朝所述像素定义层延伸而越过所述第三连接层的部分形成所述上壁，所述第一连接电极朝所述像素定义层延伸而越过所述第三连接层的部分形成所述下壁，所述第三连接电极形成所述侧壁，且所述上壁沿平行于所述衬底基板的表面方向的水平方向的长度小于且所述下壁沿所述水平方向的长度。
  8. 根据权利要求7所述的显示面板，其中所述下壁沿所述水平方向的长度是所述上壁沿所述水平方向的长度的4至10倍。
  9. 根据权利要求7所述的显示面板，其中所述第三连接电极在所述第二方向上的高度是所述第二像素电极在第二方向上的高度的1.5-6倍，所述第二方向为垂直于所述水平方向的竖直方向。
  10. 根据权利要求1所述的显示面板，其中所述第三连接电极和所述第一像素电极处于同一层且包括相同的材料。
  11. 根据权利要求10所述的显示面板，其中所述第三连接电极和所述第一像素电极均包括光反射材料。
  12. 根据权利要求11所述的显示面板，其中所述光反射材料包括铝合金。
  13. 根据权利要求5所述的显示面板，其中所述子像素区还包括第一子导电层和第二子导电层，其中所述第二子导电层位于所述第一像素电极和所述第二像素电极之间，所述第一子导电层位于所述第一像素电极面向所述衬底基板的一侧，其中第一子导电层的材料与所述第一连接电极处于同一层且包括相同的材料，第二子导电层的材料与所述第二连接电极处于同一层且包括相同的材料，所述第一子导电层和所述第二子导电层通过所述像素定义层而与所述电极连接结构隔离。
  14. 根据权利要求1所述的显示面板，其中显示面板还包括被配置成驱动所述子像素区发光的像素驱动电路，所述像素驱动电路包括晶体管，其中所述辅助电极与所述晶体管的源极或漏极处于同一层且包括相同的材料。
  15. 根据权利要求1所述的显示面板，其中所述多个子像素区内的各个第二像素电极彼此相连而成为一体结构。
  16. 根据权利要求14所述的显示面板，其中所述显示面板还包括位于所述衬底基板和所述像素驱动电路之间的遮光层，所述遮光层在衬底基板上的正投影覆盖所述晶体管的有源层在所述衬底基板上的正投影。
  17. 根据权利要求1所述的显示面板，其中所述显示面板包括多个所述辅助电极连接区，所述多个所述辅助电极连接区中的至少一部分辅助电极连接区位于所述多个子像素区中相邻的子像素区之间。
  18. 根据权利要求1所述的显示面板，其中所述显示区包括多个像素单元，每个像素单元包括所述多个子像素区中的至少三个子像素区，所述显示面板包括多个所述辅助电极连接区，其中所述多个所述辅助电极连接区中的至少一部分辅助电极连接区位于所述多个像素单元中相邻的像素单元之间。
  19. 根据权利要求1所述的显示面板，其中所述显示面板包括处于所述显示区外部的非显示区，所述显示面板包括多个所述辅助电极连接区，其中所述多个所述辅助电极连接区中的至少一部分辅助电极连接区位于所述非显示区内。
  20. 一种显示装置，包括如权利要求1-19中任一项所述的显示面板。
  21. 一种制作显示面板的方法，包括：
    提供衬底基板，所述衬底基板包括显示区，所述显示区包括多个子像素区；
    在所述衬底基板上制作用于所述多个子像素区中的各个子像素区的第一像素电极和第二像素电极，所述第二像素电极位于所述第一像素电极背离所述衬底基板的一侧；
    在所述衬底基板上制作辅助电极和电极连接结构，使得所述辅助电极通过所述电极连接结构而与所述第二像素电极连接，其中所述电 极连接结构位于辅助电极连接区内，所述辅助电极连接区在所述衬底基板上的正投影与所述子像素区在所述衬底基板上的正投影无交叠，
    其中所述电极连接结构包括位于所述辅助电极上的第一连接电极、位于第一连接电极背离所述衬底基板一侧的第二连接电极、以及位于所述第一连接电极和所述第二连接电极之间的第三连接电极，
    其中所述第三连接电极包括与所述第二连接电极接触的上表面、与所述第一连接电极接触并与所述上表面相对的下表面、以及与所述上表面或所述下表面垂直的纵截面，所述纵截面包括位于所述上表面内的顶边和位于所述下表面内的底边，其中所述底边在所述衬底基板上的正投影覆盖所述顶边在所述衬底基板上的正投影。
  22. 根据权利要求21所述的方法，其中所述方法还包括：
    在所述衬底基板上制作像素驱动电路，所述像素驱动电路包括晶体管，
    其中制作所述晶体管和制作所述辅助电极包括：
    在所述衬底基板上形成源漏金属层，所述源漏金属层延伸至所述辅助电极连接区；和
    采用单次构图工艺对所述源漏金属层进行图案化，以形成所述晶体管的源极、漏极和所述辅助电极。
  23. 根据权利要求22所述的方法，其中所述子像素区还包括第一子导电层和第二子导电层，所述第二子导电层位于所述第一像素电极和所述第二像素电极之间，所述第一子导电层位于所述第一像素电极面向所述衬底基板的一侧，
    其中制作所述电极连接结构、所述第一子导电层、所述第二子导电层和所述第一像素电极包括：
    在所述源极、漏极和所述辅助电极上制作第一导电层；
    采用单次构图工艺对所述第一导电层进行图案化处理以获得所述第一子导电层和所述第一连接电极，所述第一子导电层和所述第一连接电极分别与所述晶体管的源极和所述辅助电极连接；
    在所述第一子导电层和所述第一连接电极上依次形成第一像素电极层和第二导电层；
    对所述第二导电层进行刻蚀处理，以形成所述第二子导电层和所述第二连接电极，以及
    在对所述第二导电层进行刻蚀处理的位置处对所述第一像素电极层进行过刻蚀处理，以形成所述第一像素电极和所述第三连接电极，且所述第二连接电极在所述衬底基板上的正投影覆盖所述第三连接电极在所述衬底基板上的正投影。
  24. 根据权利要求23所述的方法，所述方法还包括：
    在所述衬底基板上形成像素定义层，所述显示区通过所述像素定义层而形成所述多个子像素区，其中所述子像素区内的第一子导电层、第一像素电极和第二子导电层通过所述像素定义层而与所述辅助电极连接区内的所述电极连接结构隔离；以及
    在所述第二子导电层上制作发光层，其中制作所述第二像素电极包括：
    在所述发光层和所述像素定义层上形成所述第二像素电极，所述第二像素电极延伸越过所述像素定义层而与所述第一连接电极和所述第三连接电极中的至少一个接触。
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