WO2019181373A1 - ワイヤボンディング構造 - Google Patents

ワイヤボンディング構造 Download PDF

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Publication number
WO2019181373A1
WO2019181373A1 PCT/JP2019/006961 JP2019006961W WO2019181373A1 WO 2019181373 A1 WO2019181373 A1 WO 2019181373A1 JP 2019006961 W JP2019006961 W JP 2019006961W WO 2019181373 A1 WO2019181373 A1 WO 2019181373A1
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Prior art keywords
wire
ground electrode
electrode
signal
ground
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PCT/JP2019/006961
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English (en)
French (fr)
Inventor
美和 武藤
松崎　秀昭
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日本電信電話株式会社
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Application filed by 日本電信電話株式会社 filed Critical 日本電信電話株式会社
Priority to US16/970,911 priority Critical patent/US11335661B2/en
Publication of WO2019181373A1 publication Critical patent/WO2019181373A1/ja

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Definitions

  • the present invention relates to a wire bonding structure in which electrodes are connected by a metal wire.
  • Wire bonding is a technique in which a metal wire is used between electrodes of an integrated circuit on a substrate and a chip or a semiconductor package.
  • a gold wire is bonded to an aluminum electrode or a gold terminal with heat, ultrasonic waves, and a load.
  • the wire bonding technique is used, for example, to electrically bond the inside and the outside of an integrated circuit chip. Further, the wire bonding technique may be used for connection between an integrated circuit and other electronic components, connection between printed circuit boards, and connection between integrated circuits.
  • first, a first signal electrode 202, a first ground electrode 203, and a second ground electrode 204 are formed on a first substrate 201.
  • the first ground electrode 203 and the second ground electrode 204 are formed with the first signal electrode 202 interposed therebetween.
  • a second signal electrode 206, a third ground electrode 207, and a fourth ground electrode 208 are formed on the second substrate 205.
  • the third ground electrode 207 and the fourth ground electrode 208 are formed with the second signal electrode 206 interposed therebetween.
  • first signal electrode 202 and the second signal electrode 206 are connected by the first wire 209
  • first ground electrode 203 and the third ground electrode 207 are connected by the second wire 210
  • second ground electrode 204 is connected.
  • fourth ground electrode 208 are connected by a third wire 211.
  • first signal electrode 202, the first ground electrode 203, and the second ground electrode 204 are connected to a first integrated circuit chip 212 mounted on the first substrate 201.
  • the first integrated circuit chip 212 is formed on the first substrate 201 via the ground plane 213.
  • the second signal electrode 206, the third ground electrode 207, and the fourth ground electrode 208 are connected to the second integrated circuit chip 214 mounted on the second substrate 205.
  • the second integrated circuit chip 214 is formed on the second substrate 205 via the ground plane 215.
  • the first substrate 201 is formed on the second substrate 205 via a ground plane 216.
  • the wire bonding described above is considered to be a low-cost and highly flexible connection technology, and most of the connection of semiconductor packages and integrated circuits is performed by wire bonding.
  • wire bonding in a high-frequency module that handles high-frequency signals, it is difficult to perform characteristic impedance matching at the connection portion by wire bonding, and there is a problem that transmission characteristics deteriorate due to a sudden impedance change in the high-frequency band.
  • the termination resistance of semiconductor packages and integrated circuits is often set to 50 ⁇ .
  • the characteristic impedance of the region connected by the wire is also 50 ⁇ . This is because when a traveling wave is applied to the transmission line, if a discontinuous surface of the characteristic impedance is encountered, a part (or all) of the traveling wave is reflected.
  • it is difficult to reduce the high characteristic impedance value of the wire portion which leads to deterioration of transmission characteristics.
  • the present invention has been made to solve the above problems, and aims to reduce characteristic impedance in a wire bonding structure for connecting high-frequency signals.
  • the wire bonding structure includes a first signal electrode formed on the main surface of the first substrate, a first ground electrode formed on the main surface of the first substrate with the first signal electrode sandwiched therebetween, Two ground electrodes, a second signal electrode formed on the main surface of the second substrate, a third ground electrode and a fourth ground electrode formed on the main surface of the second substrate with the second signal electrode interposed therebetween, A first wire connecting the first signal electrode and the second signal electrode, a second wire connecting the first ground electrode and the fourth ground electrode, and connecting the second ground electrode and the third ground electrode.
  • the second wire and the third wire intersect at only one point above the first wire.
  • the main surface of the first substrate and the main surface of the second substrate may be parallel to each other. Further, if the arrangement direction of the first signal electrode, the first ground electrode, and the second ground electrode and the arrangement direction of the second signal electrode, the third ground electrode, and the fourth ground electrode are parallel to each other, Good.
  • the characteristic impedance in the wire bonding structure for connecting the high frequency signal can be reduced. Effect.
  • FIG. 1 is a perspective view showing a configuration of a wire bonding structure according to an embodiment of the present invention.
  • FIG. 2A is a plan view showing the configuration of the wire bonding structure in the embodiment of the present invention.
  • FIG. 2B is a side view showing the configuration of the wire bonding structure in the embodiment of the present invention.
  • FIG. 3 is a perspective view showing a configuration of a conventional wire bonding structure.
  • FIG. 4 is a plan view showing a configuration of a conventional wire bonding structure.
  • a first signal electrode 102, a first ground electrode 103, and a second ground electrode 104 are formed on the main surface of the first substrate 101.
  • the first ground electrode 103 and the second ground electrode 104 are formed with the first signal electrode 102 interposed therebetween.
  • the second signal electrode 106, the third ground electrode 107, and the fourth ground electrode 108 are formed on the main surface of the second substrate 105.
  • the third ground electrode 107 and the fourth ground electrode 108 are formed with the second signal electrode 106 interposed therebetween.
  • first signal electrode 102 and the second signal electrode 106 are connected by a first wire 109.
  • the first ground electrode 103 and the fourth ground electrode 108 are connected by the second wire 110.
  • the second ground electrode 104 and the third ground electrode 107 are connected by a third wire 111.
  • the first wire 109 is a signal wire
  • the second wire 110 and the third wire 111 are ground wires.
  • Each wire is made of, for example, gold (Au) and is formed by a known wire bonding technique.
  • the second wire 110 and the third wire 111 intersect with each other only at one place above the first wire 109.
  • the 2nd wire 110 and the 3rd wire 111 may contact in the location which cross
  • the first ground electrode 103 and the third ground electrode 107 are arranged on one side of a virtual straight line connecting the first signal electrode 102 and the second signal electrode 106.
  • the second ground electrode 104 and the fourth ground electrode 108 are arranged on the other side of the virtual straight line connecting the first signal electrode 102 and the second signal electrode 106.
  • the main surface of the first substrate 101 and the main surface of the second substrate 105 are parallel to each other.
  • the arrangement direction of the first signal electrode 102, the first ground electrode 103, and the second ground electrode 104 and the arrangement direction of the second signal electrode 106, the third ground electrode 107, and the fourth ground electrode 108 are mutually different. Parallel.
  • the first signal electrode 102, the first ground electrode 103, and the second ground electrode 104 are connected to the first integrated circuit chip 112 formed (mounted) on the first substrate 101.
  • the first integrated circuit chip 112 is formed on the first substrate 101 via the ground plane 113.
  • the second signal electrode 106, the third ground electrode 107, and the fourth ground electrode 108 are connected to the second integrated circuit chip 114 formed (mounted) on the second substrate 105.
  • the second integrated circuit chip 114 is formed on the second substrate 105 via the ground plane 115.
  • the first substrate 101 is formed on the second substrate 105 via a ground plane 116.
  • the distance between the first wire 109, the second wire 110, and the third wire 111 can be made smaller than the conventional one described with reference to FIGS. Become.
  • the characteristic impedance of the first wire 109 serving as the signal line can be reduced.
  • the distance between the electrodes in the semiconductor package on which the integrated circuit chip is mounted is on the order of several mm, and the distance (interval) between the signal wire and the ground wire is the same value.
  • the distance (interval) between the signal wire and the ground wire is about tens of ⁇ m. It becomes possible to.
  • the distance between the signal wire and the ground wire gradually decreases as the distance from the intermediate point between the first signal electrode 102 and the second signal electrode 106 is approached. Therefore, a structure in which the characteristic impedance is hardly changed and the characteristic is hardly deteriorated is obtained.
  • the distance is minimum when the second wire 110 and the third wire 111 are directly above the first wire 109. Therefore, according to the embodiment, it is possible to suppress a rapid characteristic impedance change at the connection portion by the wire, and it is possible to connect the high frequency signal with low loss.
  • the so-called GSG structure in which the signal electrodes (S) and the ground electrodes (G) are alternately arranged has been described as an example, but the present invention is not limited thereto.
  • the present invention can be similarly applied even in the case of a multilane in which two signal lines or three or more signal lines are connected to one electrode.
  • the second wire and the third wire that are ground wires intersect each other above the first wire that is a signal wire.
  • the characteristic impedance in the structure can be reduced.
  • the signal wire is formed on a straight line as much as possible to shorten the distance, and the ground wire intersects on the upper side of the signal wire.
  • the wire bonding structure according to the present invention does not require the addition of a new configuration to the manufacturing worker of the conventional wire bonding structure, and only bonds the two ground wires crossing each other.
  • connection between the integrated circuits on the board is taken up.

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Abstract

高周波信号を接続するワイヤボンディング構造における特性インピーダンスを低減する。 第１シグナル電極１０２と第２シグナル電極１０６とが第１ワイヤ１０９で接続され、第１グランド電極１０３と第４グランド電極１０８とが、第２ワイヤ１１０で接続され、第２グランド電極１０４と第３グランド電極１０７とが、第３ワイヤ１１１で接続されている。第２ワイヤ１１０および第３ワイヤ１１１が、第１ワイヤ１０９の上方において１カ所のみで交差している。

Description

ワイヤボンディング構造
　本発明は、金属の線により電極間を接続するワイヤボンディング構造に関する。
　高周波モジュールに用いられる実装技術に、ワイヤボンディングによる接続がある。ワイヤボンディングは、基板上の集積回路とチップや半導体パッケージとの電極間を、金属ワイヤで実施する技術である。ワイヤボンディングでは、アルミ電極や金端子に、金ワイヤを熱と超音波と荷重で接合する。ワイヤボンディングの技術は、例えば、集積回路チップの内部と外部とを電気的に接合するために用いられる。また、ワイヤボンディングの技術は、集積回路と他の電子部品との接続や、プリント基板同士の接続、集積回路間の接続に用いられることもある。
　ワイヤボンディングによる接続例について、図３，図４を用いて説明する。このワイヤボンディング構造は、まず、第１基板２０１の上に、第１シグナル電極２０２、第１グランド電極２０３、および第２グランド電極２０４が形成されている。第１グランド電極２０３および第２グランド電極２０４は、第１シグナル電極２０２を挟んで形成されている。
　また、第２基板２０５の上に、第２シグナル電極２０６、第３グランド電極２０７、および第４グランド電極２０８が形成されている。第３グランド電極２０７および第４グランド電極２０８は、第２シグナル電極２０６を挟んで形成されている。
　また、第１シグナル電極２０２と第２シグナル電極２０６とが第１ワイヤ２０９で接続され、第１グランド電極２０３と第３グランド電極２０７とが、第２ワイヤ２１０で接続され、第２グランド電極２０４と第４グランド電極２０８とが、第３ワイヤ２１１で接続されている。
　なお、第１シグナル電極２０２、第１グランド電極２０３、および第２グランド電極２０４は、第１基板２０１の上に実装されている第１集積回路チップ２１２に接続されている。第１集積回路チップ２１２は、第１基板２０１の上に、グランドプレーン２１３を介して形成されている。
　また、第２シグナル電極２０６、第３グランド電極２０７、および第４グランド電極２０８は、第２基板２０５の上に実装されている第２集積回路チップ２１４に接続されている。第２集積回路チップ２１４は、第２基板２０５の上に、グランドプレーン２１５を介して形成さている。また、第１基板２０１は、第２基板２０５の上に、グランドプレーン２１６を介して形成されている。
特開平０７－０５８１３８号公報
　上述したワイヤボンディングは、コストが低く、自由度の高い接続技術であると考えられており、半導体パッケージや集積回路の接続の大部分がワイヤボンディングで行われている。しかし、高周波信号を扱う高周波モジュールにおいて、ワイヤボンディングによる接続部分で特性インピーダンスの整合を行うことは難しく、高周波帯での急激なインピーダンス変化による伝送特性の劣化をまねくという問題がある。
　通常、半導体パッケージや集積回路の終端抵抗は５０Ωに設定されていることが多い。このため、これらをワイヤボンディングにより接続する際、理想的にはワイヤで接続する領域の特性インピーダンスも５０Ωにすることが望ましい。これは、伝送線路に進行波を加えた時に、特性インピーダンスの不連続面に遭遇すると、進行波の一部（あるいは全部）が反射されるためである。しかし、ワイヤ部分の高い特性インピーダンス値を低減することは難しく、伝送特性の劣化をまねいている。
　このようなワイヤ部分（信号ワイヤ）の高い特性インピーダンス値を低減するワイヤボンディング技術としては、例えば特許文献１に記載のものが知られている。しかし、特許文献１に記載の構造では、接着剤を用いて信号ワイヤとグランドワイヤとを相互に固定し、これらワイヤ間の距離により特性インピーダンスを制御するため、正確性や再現性に疑問が生じる。また、信号ワイヤとグランドワイヤとを接着する工程が必要となるため、製造コストや製造時間が増大するという問題がある。
　本発明は、以上のような問題点を解消するためになされたものであり、高周波信号を接続するワイヤボンディング構造における特性インピーダンスの低減を目的とする。
　本発明に係るワイヤボンディング構造は、第１基板の主表面上に形成された第１シグナル電極と、 第１基板の主表面上で第１シグナル電極を挟んで形成された第１グランド電極および第２グランド電極と、第２基板の主表面上に形成された第２シグナル電極と、 第２基板の主表面上で第２シグナル電極を挟んで形成された第３グランド電極および第４グランド電極と、第１シグナル電極と第２シグナル電極とを接続する第１ワイヤと、第１グランド電極と第４グランド電極とを接続する第２ワイヤと、第２グランド電極と第３グランド電極とを接続する第３ワイヤとを備え、第２ワイヤおよび第３ワイヤは、第１ワイヤの上方において１カ所のみで交差する。
　上記ワイヤボンディング構造において、第１基板の主表面と第２基板の主表面とは、互いに平行とされていればよい。また、第１シグナル電極、第１グランド電極、および第２グランド電極の配列方向と、第２シグナル電極、第３グランド電極、および第４グランド電極の配列方向とは、互いに平行とされていればよい。
　以上説明したように、本発明によれば、第２ワイヤおよび第３ワイヤを、第１ワイヤの上方において交差させるようにしたので、高周波信号を接続するワイヤボンディング構造における特性インピーダンスが低減できるという優れた効果が得られる。
図１は、本発明の実施の形態におけるワイヤボンディング構造の構成を示す斜視図である。 図２Ａは、本発明の実施の形態におけるワイヤボンディング構造の構成を示す平面図である。 図２Ｂは、本発明の実施の形態におけるワイヤボンディング構造の構成を示す側面図である。 図３は、従来のワイヤボンディング構造の構成を示す斜視図である。 図４は、従来のワイヤボンディング構造の構成を示す平面図である。
　以下、本発明の実施の形態おけるワイヤボンディング構造ついて図１，図２Ａ，図２Ｂを参照して説明する。
　まず、第１基板１０１の主表面上に、第１シグナル電極１０２、第１グランド電極１０３、および第２グランド電極１０４が形成されている。第１グランド電極１０３および第２グランド電極１０４は、第１シグナル電極１０２を挟んで形成されている。
　また、第２基板１０５の主表面上に、第２シグナル電極１０６、第３グランド電極１０７、および第４グランド電極１０８が形成されている。第３グランド電極１０７および第４グランド電極１０８は、第２シグナル電極１０６を挟んで形成されている。
　また、第１シグナル電極１０２と第２シグナル電極１０６とが第１ワイヤ１０９で接続されている。また、第１グランド電極１０３と第４グランド電極１０８とが、第２ワイヤ１１０で接続されている。また、第２グランド電極１０４と第３グランド電極１０７とが、第３ワイヤ１１１で接続されている。第１ワイヤ１０９は、信号ワイヤであり、第２ワイヤ１１０，第３ワイヤ１１１が、グランドワイヤである。各ワイヤは、例えば、金（Ａｕ）から構成され、公知のワイヤボンディング技術により形成されている。
　上述した構成において、実施の形態では、第２ワイヤ１１０および第３ワイヤ１１１が、第１ワイヤ１０９の上方において１カ所のみで交差している。なお、第２ワイヤ１１０および第３ワイヤ１１１は、交差する箇所で接触してもよい。ただし、第１シグナル電極１０２と第２シグナル電極１０６とを結ぶ仮想の直線の、一方の側に、第１グランド電極１０３および第３グランド電極１０７が配置されている。また、第１シグナル電極１０２と第２シグナル電極１０６とを結ぶ仮想の直線の、他方の側に、第２グランド電極１０４および第４グランド電極１０８が配置されている。この状態で、第１グランド電極１０３と第４グランド電極１０８とを第２ワイヤ１１０で接続し、第２グランド電極１０４と第３グランド電極１０７とを第３ワイヤ１１１で接続すれば、第２ワイヤ１１０および第３ワイヤ１１１は、第１ワイヤ１０９の上方において１カ所のみで交差する状態となる。
　なお、実施の形態において、第１基板１０１の主表面と第２基板１０５の主表面とは、互いに平行とされている。また、第１シグナル電極１０２、第１グランド電極１０３、および第２グランド電極１０４の配列方向と、第２シグナル電極１０６、第３グランド電極１０７、および第４グランド電極１０８の配列方向とは、互いに平行とされている。
　ここで、実施の形態において、第１シグナル電極１０２、第１グランド電極１０３、および第２グランド電極１０４は、第１基板１０１の上に形成（実装）されている第１集積回路チップ１１２に接続されている。第１集積回路チップ１１２は、第１基板１０１の上に、グランドプレーン１１３を介して形成されている。
　また、第２シグナル電極１０６、第３グランド電極１０７、および第４グランド電極１０８は、第２基板１０５の上に形成（実装）されている第２集積回路チップ１１４に接続されている。第２集積回路チップ１１４は、第２基板１０５の上に、グランドプレーン１１５を介して形成さている。また、第１基板１０１は、第２基板１０５の上に、グランドプレーン１１６を介して形成されている。
　上述した実施の形態におけるワイヤボンディング構造によれば、第１ワイヤ１０９と第２ワイヤ１１０、第３ワイヤ１１１との距離を、図３，４を用いて説明した従来よりも小さくすることが可能となる。この結果、実施の形態によれば、信号線となる第１ワイヤ１０９の特性インピーダンスを低減することができるようになる。
　通常、集積回路チップを実装する半導体パッケージにおける電極間距離は、数ｍｍのオーダーであり、信号ワイヤとグランドワイヤの距離（間隔）も同程度の値になる。しかし、実施の形態によれば、第２ワイヤ１１０および第３ワイヤ１１１を、第１ワイヤ１０９の上方において交差させるので、信号ワイヤとグランドワイヤの距離（間隔）は、～数十μｍ程度の値にすることが可能となる。また、信号ワイヤとグランドワイヤの距離は、第１シグナル電極１０２と第２シグナル電極１０６との中間点に近づくほど徐々に小さくなる。従って、特性インピーダンスの急激な変化は起きにくく、特性劣化しにくい構造になっている。なお、上記距離は、第２ワイヤ１１０および第３ワイヤ１１１が、第１ワイヤ１０９の直上にある状態で最小になる。従って、実施の形態によれば、ワイヤによる接続部分での急激な特性インピーダンス変化を抑えることになり、高周波信号を低損失で接続することが可能となる。
　なお、上述では、シグナル電極（Ｓ）とグランド電極（Ｇ）が交互に配置されるいわゆるＧＳＧ構造を例に説明したが、これに限るものではない。例えば、ＧＳＧＳＧ構造において、１つの電極に２本の信号線あるいは３本以上の信号線を接続するマルチレーンの場合であっても同様に適用可能である。
　以上に説明したように、本発明によれば、グランドワイヤである第２ワイヤおよび第３ワイヤを、信号ワイヤである第１ワイヤの上方において交差させるようにしたので、高周波信号を接続するワイヤボンディング構造における特性インピーダンスが低減できるようになる。
　信号の流れる部分の周囲の金属、誘電体、磁性体全てが電磁エネルギーを蓄えるのに影響するため、これらすべてが特性インピーダンスに影響を与える。すなわち、信号ワイヤの周囲の物理的な配置が変化すれば信号ワイヤの特性インピーダンスは変化する。ワイヤの周辺に何もない場合、信号ワイヤの特性インピーダンスはグランドワイヤとの距離に依存性を持つ。
　本発明では、信号ワイヤを可能な範囲で直線上に形成して距離を短くし、グランドワイヤは信号ワイヤの上側で交差する構成とした。この構成とすることで、信号ワイヤとグランドワイヤとの距離を、従来技術よりも小さくすることが可能となり、信号ワイヤの特性インピーダンスを低減することが可能となる。
　本発明におけるワイヤボンディング構造は、従来のワイヤボンディング構造の製造工手に対し、新たな構成の追加は必要なく、２つのグランドワイヤを交差させてボンディングするのみである。
　なお、本発明は以上に説明した実施の形態に限定されるものではなく、本発明の技術的思想内で、当分野において通常の知識を有する者により、多くの変形および組み合わせが実施可能であることは明白である。例えば、上述した実施の形態では、基板上の集積回路同士の接続を取り上げているが、例えば集積回路とその他の電子部品との接続や、プリント基板同士の接続など、電気的に接合するための用途全般に適応可能である。
　１０１…第１基板、１０２…第１シグナル電極、１０３…第１グランド電極、１０４…第２グランド電極、１０５…第２基板、１０６…第２シグナル電極、１０７…第３グランド電極、１０８…第４グランド電極、１０９…第１ワイヤ、１１０…第２ワイヤ、１１１…第３ワイヤ、１１２…第１集積回路チップ、１１３…グランドプレーン、１１４…第２集積回路チップ、１１５…グランドプレーン、１１６…グランドプレーン。

Claims (3)

  1. 　第１基板の主表面上に形成された第１シグナル電極と、
    　前記第１基板の主表面上で前記第１シグナル電極を挟んで形成された第１グランド電極および第２グランド電極と、
    　第２基板の主表面上に形成された第２シグナル電極と、
    　前記第２基板の主表面上で前記第２シグナル電極を挟んで形成された第３グランド電極および第４グランド電極と、
    　前記第１シグナル電極と前記第２シグナル電極とを接続する第１ワイヤと、
    　前記第１グランド電極と前記第４グランド電極とを接続する第２ワイヤと、
    　前記第２グランド電極と前記第３グランド電極とを接続する第３ワイヤと
    　を備え、
    　前記第２ワイヤおよび前記第３ワイヤは、前記第１ワイヤの上方において１カ所のみで交差することを特徴とするワイヤボンディング構造。
  2. 　請求項１記載のワイヤボンディング構造において、
    　前記第１基板の主表面と前記第２基板の主表面とは、互いに平行とされていることを特徴とするワイヤボンディング構造。
  3. 　請求項１または２記載のワイヤボンディング構造において、
    　前記第１シグナル電極、前記第１グランド電極、および前記第２グランド電極の配列方向と、
    　前記第２シグナル電極、前記第３グランド電極、および前記第４グランド電極の配列方向とは、
    　互いに平行とされていることを特徴とするワイヤボンディング構造。
PCT/JP2019/006961 2018-03-22 2019-02-25 ワイヤボンディング構造 WO2019181373A1 (ja)

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11784146B1 (en) * 2020-04-07 2023-10-10 Scientific Components Corporation Method and apparatus for a ground wire bonding attachment in MMIC devices
CN115799199A (zh) * 2022-10-31 2023-03-14 华为数字能源技术有限公司 键合结构和功率器件

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007525842A (ja) * 2004-02-26 2007-09-06 フリースケール セミコンダクター インコーポレイテッド 交差導電体アセンブリを備えた半導体パッケージ及びその製造方法
JP2007312229A (ja) * 2006-05-19 2007-11-29 National Institute Of Advanced Industrial & Technology 基板間の接続方法
JP2010010492A (ja) * 2008-06-27 2010-01-14 Sony Corp 半導体装置および半導体集積回路
JP2011100871A (ja) * 2009-11-06 2011-05-19 Fujitsu Ltd 配線基板及び電子装置
JP2012069571A (ja) * 2010-09-21 2012-04-05 Panasonic Corp 半導体集積回路装置
JP2012164800A (ja) * 2011-02-07 2012-08-30 Tosaku Kojima ワイヤボンディング方法、回路装置及び回路装置パッケイジ方法
JP2016524338A (ja) * 2013-07-03 2016-08-12 ローゼンベルガー ホーフフレクベンツテクニーク ゲーエムベーハー ウント ツェーオー カーゲー 低電磁干渉配線を有するダイパッケージ
JP2017059650A (ja) * 2015-09-16 2017-03-23 三菱電機株式会社 増幅器

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0758138A (ja) 1993-08-16 1995-03-03 Nec Corp ワイヤボンディング構造およびそのボンディング方法
US5459284A (en) * 1993-08-31 1995-10-17 Motorola, Inc. Twisted-pair wire bond and method thereof
US5471010A (en) * 1993-08-31 1995-11-28 Motorola, Inc. Spatially separated uninsulated twisted wire pair
US7872325B2 (en) * 2009-02-24 2011-01-18 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Reduced-crosstalk wirebonding in an optical communication system
JP2013243209A (ja) * 2012-05-18 2013-12-05 Kyocera Corp 半導体装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007525842A (ja) * 2004-02-26 2007-09-06 フリースケール セミコンダクター インコーポレイテッド 交差導電体アセンブリを備えた半導体パッケージ及びその製造方法
JP2007312229A (ja) * 2006-05-19 2007-11-29 National Institute Of Advanced Industrial & Technology 基板間の接続方法
JP2010010492A (ja) * 2008-06-27 2010-01-14 Sony Corp 半導体装置および半導体集積回路
JP2011100871A (ja) * 2009-11-06 2011-05-19 Fujitsu Ltd 配線基板及び電子装置
JP2012069571A (ja) * 2010-09-21 2012-04-05 Panasonic Corp 半導体集積回路装置
JP2012164800A (ja) * 2011-02-07 2012-08-30 Tosaku Kojima ワイヤボンディング方法、回路装置及び回路装置パッケイジ方法
JP2016524338A (ja) * 2013-07-03 2016-08-12 ローゼンベルガー ホーフフレクベンツテクニーク ゲーエムベーハー ウント ツェーオー カーゲー 低電磁干渉配線を有するダイパッケージ
JP2017059650A (ja) * 2015-09-16 2017-03-23 三菱電機株式会社 増幅器

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