WO2019174297A1 - 阵列基板及其制作方法和显示装置 - Google Patents

阵列基板及其制作方法和显示装置 Download PDF

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Publication number
WO2019174297A1
WO2019174297A1 PCT/CN2018/116770 CN2018116770W WO2019174297A1 WO 2019174297 A1 WO2019174297 A1 WO 2019174297A1 CN 2018116770 W CN2018116770 W CN 2018116770W WO 2019174297 A1 WO2019174297 A1 WO 2019174297A1
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Prior art keywords
metal
metal layer
substrate
array substrate
insulating layer
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PCT/CN2018/116770
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English (en)
French (fr)
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马宏伟
张锴
肖云升
董向丹
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/466,531 priority Critical patent/US11316000B2/en
Priority to JP2019546891A priority patent/JP7239481B2/ja
Priority to EP18905908.2A priority patent/EP3767673A4/en
Publication of WO2019174297A1 publication Critical patent/WO2019174297A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements

Definitions

  • Embodiments of the present disclosure relate to an array substrate, a method of fabricating the same, and a display device.
  • LTPS-AMOLED low temperature polysilicon-active matrix light emitting diode
  • the backplane circuit of the low temperature polysilicon-active matrix light emitting diode display device includes a plurality of metal signal lines and an insulating layer, and the structure is relatively complicated.
  • At least one embodiment of the present disclosure provides an array substrate including: a base substrate; a first metal layer on the base substrate; and a first insulating layer located away from the base substrate a side of the second metal layer on a side of the first insulating layer away from the substrate; and a second insulating layer on a side of the second metal layer away from the substrate
  • the array substrate includes a display area and a peripheral area surrounding the display area
  • the first metal layer includes a plurality of signal lines in the peripheral area
  • the second insulating layer includes at least one of the peripheral area a groove in which at least two of the plurality of signal lines overlap
  • the second metal layer includes a metal strip in the peripheral region
  • the signal line is in a region where the groove overlaps the signal line
  • An orthographic projection on the substrate substrate falls within an orthographic projection of the metal strip on the substrate.
  • the metal strip includes a plurality of metal strips, and the plurality of metal strips are disposed in one-to-one correspondence with the plurality of signal lines, and the grooves and the An area where the signal lines overlap, and an orthographic projection of each of the signal lines on the base substrate falls within an orthographic projection of the corresponding metal strip on the base substrate.
  • a width of each of the metal strips is greater than a width of each of the signal lines.
  • the plurality of signal lines extend to the display area.
  • the second metal layer includes a conductive pattern in the display region, and each of the metal strips is insulated from the conductive pattern.
  • a material of the first insulating layer includes an inorganic insulating material
  • a material of the second insulating layer includes an inorganic insulating material
  • a region of the groove in which the metal strip is not disposed in the peripheral region penetrates the first insulating layer in a direction perpendicular to the substrate.
  • the first metal layer is a first gate metal layer
  • the second metal layer is a second gate metal layer
  • the second insulating layer includes an interlayer dielectric layer.
  • an array substrate further includes: a third metal layer located on a side of the second insulating layer away from the second metal layer; the third metal layer is located in the peripheral region The metal at the bottom corner of the groove remains.
  • the third metal layer includes at least one of a source, a drain, and a source/drain signal line in the display region.
  • an array substrate further includes: a passivation layer disposed on a side of the third metal layer away from the second insulating layer; and a pixel electrode located in the display area and in the The passivation layer is away from one side of the third metal layer.
  • At least one embodiment of the present disclosure provides a display device comprising the array substrate of any of the above.
  • At least one embodiment of the present disclosure provides a method of fabricating an array substrate, including: forming a first metal layer on a substrate; forming a first insulating layer on a side of the first metal layer away from the substrate Forming a second metal layer on a side of the first insulating layer away from the base substrate; forming a second insulating layer on a side of the second metal layer away from the base substrate; and etching the a second insulating layer to form at least one recess, the array substrate includes a display area and a peripheral area surrounding the display area, the first metal layer including a plurality of signal lines in the peripheral area, the groove and At least two of the plurality of signal lines overlap, the second metal layer includes a metal strip in the peripheral region, and the signal line is in a region where the groove overlaps with the signal line An orthographic projection on the substrate substrate falls within an orthographic projection of the metal strip on the substrate.
  • the metal strip includes a plurality of metal strips, and the plurality of metal strips are disposed in one-to-one correspondence with the plurality of signal lines.
  • an orthographic projection of each of the signal lines on the substrate substrate falls within an orthographic projection of the corresponding metal strip on the substrate.
  • a width of each of the metal strips is greater than a width of each of the signal lines.
  • the second metal layer includes a conductive pattern in the display region, and each of the metal strips is insulated from the conductive pattern, the metal strip and the The conductive patterns are fabricated by the same mask process.
  • 1 is a schematic cross-sectional view of an array substrate
  • FIG. 2 is a schematic view of a metal residue causing a short circuit
  • 3A-3F are step-by-step schematic diagrams of a method of fabricating an array substrate
  • 4A is a schematic plan view of another array substrate
  • FIG. 4B is a schematic view showing a metal residue in the array substrate shown in FIG. 4A causing a short circuit
  • 5A and 5B are schematic cross-sectional views of an array substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic plan view of an array substrate according to an embodiment of the present disclosure.
  • FIGS. 7A-7F are step-by-step schematic diagrams of a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • the edge of the array substrate usually forms at least one groove in the interlayer dielectric layer.
  • the metal layer for example, the third metal layer hereinafter
  • the concave process is performed. A residue of the metal layer appears at the bottom corner of the groove. The residual metal electrically connects the different metal signal lines, causing a short circuit, which causes display failure of the display device using the array substrate.
  • FIG. 1 is a schematic cross-sectional view of an array substrate.
  • Figure 1 shows only the peripheral area of the array substrate.
  • the array substrate includes a base substrate 01, a signal line 02 disposed on the base substrate 01, a first insulating layer 03 disposed on the signal line 02, and a first surface disposed on the first insulating layer 03.
  • the second insulating layer 04 is an interlayer dielectric layer.
  • at least one recess 30 is formed in the peripheral region of the array substrate. The groove 30 penetrates the first insulating layer 03 and the second insulating layer 04 and exposes the signal line 02.
  • the metal residue 40 of the third metal layer may appear at the bottom corner position of the groove 30.
  • Figure 2 shows a schematic diagram of a metal residue causing a short circuit.
  • the metal residue 40 at the bottom corner of the recess 30 electrically connects the different signal lines 02, thereby causing a short circuit, which causes display failure of the display device using the array substrate.
  • the above-mentioned signal line 02 can be obtained by patterning the first gate metal layer.
  • FIGS. 3A to 3F show a step-by-step schematic diagram of a method of fabricating an array substrate. Similarly, Figures 3A-3F show only the peripheral regions of the array substrate.
  • a signal line 02 is formed on the base substrate 01.
  • the signal line 02 can be formed by first forming a metal layer and then by a patterning process; as shown in FIG. 3B, on the substrate substrate 01 and the signal line.
  • a first insulating layer 03 is formed on the 02, the first insulating layer 03 covers the signal line 02; as shown in FIG.
  • a second insulating layer 04 is formed on the first insulating layer 03, for example, the first insulating layer 03 and the second insulating layer
  • the layer 04 may be an inorganic insulating layer; as shown in FIG. 3D, the second insulating layer 04 is etched to form at least one recess 30, since the second insulating layer 04 and the first insulating layer 03 are both inorganic insulating layers, During the etching of the second insulating layer 04, the etching liquid simultaneously etches away the first insulating layer 03 at the position of the recess 30, thereby exposing the signal line 02; as shown in FIG.
  • the fabrication method further included forming a second metal layer (eg, a second gate metal layer) that also retained a pattern only in the display region and required complete removal in the peripheral region.
  • a second metal layer eg, a second gate metal layer
  • FIG. 4A is a schematic plan view of another array substrate.
  • FIG. 4B is a schematic view showing a metal residue in the array substrate shown in FIG. 4A causing a short circuit.
  • FIG. 4A and 4B show only the peripheral region of the array substrate.
  • the array substrate includes a base substrate 01, a first insulating layer (not shown) disposed on the base substrate 01, and a second insulating layer 04 disposed on the first insulating layer.
  • the second insulating layer 04 is an interlayer dielectric layer.
  • At least one recess 30 is formed in the peripheral region of the array substrate.
  • the groove 30 penetrates through the first insulating layer 03 and the second insulating layer 04.
  • the metal residue 40 of the third metal layer appears at the bottom corner position of the groove 30.
  • the metal residue 40 at the bottom corner of the recess 30 electrically connects the different signal lines 02, thereby causing a short circuit, which causes display failure of the display device using the array substrate.
  • Embodiments of the present disclosure provide an array substrate, a method of fabricating the same, and a display device.
  • the array substrate includes a substrate; a first metal layer on the substrate; a first insulating layer on a side of the first metal layer away from the substrate; and a second metal layer on the first insulating layer away from the first a side of the metal layer; and a second insulating layer on a side of the second metal layer away from the first insulating layer, the array substrate includes a display area and a peripheral area surrounding the display area, the first metal layer including a plurality of signals in the peripheral area a second insulating layer includes at least one groove overlapping at least two of the plurality of signal lines in the peripheral region, the second metal layer including a metal strip in the peripheral region, where the groove overlaps the signal line
  • the signal line is projected onto the substrate substrate and falls into the orthographic projection of the metal strip on the substrate.
  • the array substrate can improve the product yield by adding an isolated metal strip on the signal line at the position of the
  • FIGS. 5A and 5B are schematic cross-sectional views of an array substrate according to an embodiment of the present disclosure.
  • FIG. 5A shows a peripheral region of the array substrate
  • FIG. 5B shows a display region of the array substrate.
  • the array substrate includes a base substrate 101; a first metal layer 110 on the base substrate 101; and a first insulating layer 103 on a side of the first metal layer 110 away from the base substrate 101.
  • a second metal layer 120 on a side of the first insulating layer 103 away from the first metal layer 110; and a second insulating layer 104 on a side of the second metal layer 120 away from the first insulating layer 103.
  • the array substrate includes a display area 180 and a peripheral area 190 surrounding the display area 180.
  • the first metal layer 110 includes a plurality of signal lines 102 in the peripheral area 190
  • the second insulating layer 104 includes at least one and a plurality of signal lines 102 in the peripheral area 190.
  • the second metal layer 120 includes a metal strip 150 in the peripheral region 190, in the recess 130.
  • the orthographic projection of the metal strip 150 on the base substrate 101 covers the signal line 102 orthographically projected on the base substrate 101, that is, the signal line 102 is projected onto the base substrate 101.
  • the metal strip 150 is inserted into the orthographic projection on the base substrate 101. It should be noted that the groove 130 can function to prevent cracks from diffusing into the display area.
  • the second insulating layer 104 overlaps at least two adjacent signal lines 102 of the plurality of signal lines 102 in the groove 130 of the peripheral region 190.
  • the preparation process and patterning process of the third metal layer also faces the problem that the metal residue 140 in the recess 130 causes the signal line 102 to be short-circuited.
  • FIG. 1 shows that the metal residue 140 in the recess 130 causes the signal line 102 to be short-circuited.
  • the metal strip 150 blocks the etching liquid (etching liquid for the insulating layer) to etch the first insulating layer 103 covered by the metal strip 150, that is, the wire 102
  • the first insulating layer 103 between the metal strip 150 and the metal strip 150 is not etched by the etchant and is retained.
  • the metal residue 140 can only be connected to the metal strip 150. It is impossible to connect to the wire 102, so that the signal line short circuit caused by the metal residue can be avoided, thereby improving the product yield.
  • the orthographic projection of the metal strip 150 on the base substrate 101 covers the signal line 102 orthographically projected on the base substrate 101, in the preparation process and patterning process of subsequent electrodes (for example, pixel electrodes, anodes, etc.),
  • the etching liquid (the etching liquid for the electrode) can only etch the metal strip 150 at most, and the first insulating layer 103 between the wire 102 and the metal strip 150 can prevent the wire 102 from being etched; therefore, the metal strip 150 can also be
  • the signal line 102 serves as a protection.
  • the base substrate 101 may be a glass substrate, a quartz substrate, or a plastic substrate.
  • the first metal layer 110 may be a first gate metal layer; the second metal layer 120 may be a third metal layer.
  • the material of the first insulating layer includes an inorganic insulating material
  • the material of the second insulating layer includes an inorganic insulating material
  • the second insulating layer can be an interlayer dielectric layer.
  • the material of the first insulating layer 103 and the second insulating layer 104 may be one or more of silicon nitride, silicon oxide, and silicon oxynitride.
  • the second metal layer 120 includes a conductive pattern 106 in the display region 180, each metal strip 150 being insulated from the conductive pattern 106. That is, the metal strip 150 is isolated relative to the conductive pattern 106. Thus, when the metal residue 140 can only be connected to the metal strip 150, the conductive pattern 106 cannot be adversely affected.
  • the metal strip 150 is patterned by the second metal layer 120 for forming the conductive pattern 106, the array substrate provided by the embodiment of the present disclosure has a short circuit between the avoidable signal lines, and the metal line is very At the same time as good protection, no new masking process is added, thus saving costs.
  • the first metal layer may be a first gate metal layer
  • the first gate metal layer may include a first gate in the display region
  • the second metal layer may be a second gate metal layer; It is the second gate.
  • the array substrate further includes: a third metal layer 160 on a side of the second insulating layer 104 away from the second metal layer 120; and a third metal layer 160 in the periphery Zone 190 includes a metal residue 140 at the bottom corner of the groove.
  • the third metal layer 160 does not serve as a signal line, the third metal layer 160 only retains a pattern in the display region 180, and the peripheral region 190 needs to be completely removed by a patterning process, and the usual patterning process includes exposure, development, and etching.
  • the steps of the third metal layer 160 on the oblique side of the groove 130 due to the groove 130 forming the third metal layer 160 may cause the third metal layer 160 at the bottom corner position of the groove 130 to be completely removed, forming a metal residue 140. .
  • the third metal layer 160 includes one or more of the source 107, the drain 108, and the source and drain signal lines 109 in the display region 190.
  • the array substrate further includes an active layer 210 disposed on the base substrate 101 and an insulating layer 220 disposed between the active layer 210 and the first metal layer 110. .
  • the array substrate further includes: a passivation layer 171 disposed on a side of the source and drain metal 160 away from the second insulating layer 104; and a pixel electrode 172 located in the display region 180 and The passivation layer 171 is away from the side of the third metal layer 160.
  • the etching liquid (the etching liquid for the pixel electrode) At most, only the metal strip 150 is etched away, and the first insulating layer 103 between the wire 102 and the metal strip 150 can prevent the wire 102 from being etched; therefore, the metal strip 150 can also protect the signal line 102.
  • the array substrate can be an array substrate of an organic light emitting diode display device.
  • the pixel electrode may be an anode.
  • the array substrate can be an array substrate of an organic light emitting diode display device, as shown in FIG. 5B, the array substrate further includes an organic light emitting layer 173 on a side of the pixel electrode 172 away from the passivation layer 171.
  • FIG. 6 is a schematic plan view of an array substrate according to an embodiment of the present disclosure.
  • Figure 6 shows only the peripheral region of the array substrate.
  • the number of the metal strips 150 is plural, and the plurality of metal strips 150 are disposed in one-to-one correspondence with the plurality of signal lines 102.
  • the orthographic projection of each metal strip 150 on the base substrate 101 covers the correspondingly disposed signal line 102 orthographically projected on the base substrate 101, that is, each signal line 102.
  • the erected projection on the base substrate 101 falls within the orthographic projection of the correspondingly disposed metal strip 150 on the base substrate 101.
  • the metal strip 150 can block the etching solution (the etching liquid for the insulating layer) from etching the first insulating layer 103 covered by the metal strip 150, That is to say, the first insulating layer 103 between the metal strip 150 and the correspondingly disposed wire 102 is not etched by the etching liquid and is retained.
  • the metal residue 140 can only be connected to the metal strip 150.
  • the etching liquid (the etching liquid for the electrode) can only etch the metal strip 150 at most, and the first insulating layer 103 between the metal strip 150 and the correspondingly disposed wire 102 can prevent the wire 102 from being etched;
  • the metal strip 150 can also protect the correspondingly disposed signal line 102.
  • the plurality of metal strips 150 are disposed in one-to-one correspondence with the plurality of signal lines 102.
  • the array substrate does not need to be provided with a single piece of metal strip (metal block) to cover all the signal lines; on the one hand, a single piece of metal strip (metal block) with a large area is affected to affect the flexibility of the array substrate. On the other hand, it can avoid the problem of reflection caused by a whole piece of metal strip (metal block).
  • the number of metal strips 150 is plural, a plurality of metal strips 150 are disposed in one-to-one correspondence with the plurality of signal lines 102.
  • the groove 130 penetrates the first insulating layer 103 in a direction perpendicular to the base substrate 101 in a region where the metal strip 150 is not provided in the peripheral region 190. Therefore, a short circuit can be avoided between the signal lines, and the metal wire can be well protected, and at the same time, the crack of the first insulating layer can be prevented from diffusing to the display region.
  • each metal strip 150 is greater than the width of the signal line 102, so that the first insulating layer 103 between the wire 102 and the metal strip 150 is better ensured that it will not be engraved. Etch etching is retained. It should be noted that the above-described width means a dimension in a direction perpendicular to the extending direction of the signal line.
  • multiple signal lines may extend to the display area.
  • the signal line can be used as a scan drive line, a source/drain signal line, or a power line.
  • An embodiment of the present disclosure further provides a display device, including the array substrate provided by any of the above embodiments. Since the display device includes the array substrate provided by any of the above embodiments, the display device has the technical effect corresponding to the technical effect of the display panel included therein, and the metal in the groove formed in the second insulating layer can be circumvented The signal line is short-circuited by the residual, so that the product yield can be improved. For details, refer to the related description of the foregoing embodiment, and details are not described herein again.
  • the display device may be any electronic device having a display function such as a television, a computer, a mobile phone, a navigator, a display instrument, or the like.
  • An embodiment of the present disclosure also provides a method of fabricating an array substrate.
  • the production method includes the following steps:
  • Step S301 forming a first metal layer on the base substrate.
  • Step S302 forming a first insulating layer on a side of the first metal layer away from the substrate.
  • Step S303 forming a second metal layer on a side of the first insulating layer away from the substrate.
  • Step S304 forming a second insulating layer on a side of the second metal layer away from the first insulating layer.
  • Step S305 etching the second insulating layer to form at least one groove
  • the array substrate comprises a display area and a peripheral area surrounding the display area
  • the first metal layer includes a plurality of signal lines, a groove and a plurality of signal lines in the peripheral area At least two signal lines overlap
  • the second metal layer includes a metal strip in the peripheral region. In a region where the groove overlaps the signal line, the signal line is projected onto the base substrate and falls into the metal strip on the base substrate. Inside the projection.
  • the subsequent third metal layer since the groove of the second insulating layer overlaps at least two adjacent signal lines of the plurality of signal lines in the peripheral region, the subsequent third metal layer The preparation process and the patterning process also face the problem that the metal residue in the groove causes the signal line to be short-circuited.
  • the metal The strip can block the etching liquid etching (the etching liquid for the insulating layer) to etch the first insulating layer covered by the metal strip, that is, the first insulating layer between the wire and the metal strip is not etched by the etching liquid , get reserved.
  • the metal residue can only be connected to the metal strip and cannot be connected to the wire.
  • the signal line short circuit caused by the metal residue can be avoided, thereby improving the product yield.
  • the etching solution ( The etching solution for the electrode can only etch the metal strip at most, and the first insulating layer between the wire and the metal strip can prevent the wire from being etched; therefore, the metal strip can also protect the signal line.
  • the base substrate may be a glass substrate, a quartz substrate, or a plastic substrate.
  • the first metal layer can be a first gate metal layer; the second metal layer can be a third metal layer.
  • the material of the first insulating layer includes an inorganic insulating material
  • the material of the second insulating layer includes an inorganic insulating material
  • the second insulating layer can be an interlayer dielectric layer.
  • the material of the first insulating layer and the second insulating layer may be one or more of silicon nitride, silicon oxide, and silicon oxynitride.
  • FIG. 7A-7F are step-by-step schematic diagrams of a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • Figures 7A-7F show only the peripheral regions of the array substrate.
  • a first metal layer 110 is formed on a base substrate 101, and the first metal layer 110 includes a plurality of signal lines 102 in a peripheral region.
  • a first insulating layer 103 is formed on a side of the first metal layer 110 away from the substrate 101.
  • FIG. 7C a second metal layer 120 is formed on a side of the first insulating layer 103 away from the substrate 101, and the second metal layer 120 includes a metal strip 150 in the peripheral region.
  • FIG. 7A a first metal layer 110 is formed on a base substrate 101, and the first metal layer 110 includes a plurality of signal lines 102 in a peripheral region.
  • a first insulating layer 103 is formed on a side of the first metal layer 110 away from the substrate 101.
  • a second metal layer 120 is formed on
  • a second insulating layer 104 is formed on a side of the second metal layer 120 away from the first insulating layer 103; the second insulating layer 104 is etched to form at least one recess 130, the recess 130 and the plurality of signals At least two adjacent signal lines 102 in the line 102 overlap.
  • the orthographic projection of the metal strip 150 on the base substrate 101 covers the signal line 102 on the base substrate 101. Orthographic projection.
  • the first insulating layer 103 between the wire 102 and the metal strip 050 is not etched by the etching liquid and is retained.
  • a third metal layer 160 is deposited on the substrate, and a third metal layer 160 is also deposited in the recess 130; as shown in FIG. 7F, the third metal layer 160 is etched and the peripheral region is removed.
  • FIG. 7F in the region where the groove 130 overlaps the signal line 102, even if there is a metal residue 140, the metal residue 140 can only be connected to the metal strip 150 and cannot be connected to the wire 102, thereby avoiding metal residue.
  • the signal line is short-circuited, which in turn increases product yield.
  • the number of metal strips 150 is plural, and the plurality of metal strips 150 are disposed in one-to-one correspondence with the plurality of signal lines 102.
  • the orthographic projection of each metal strip 150 on the base substrate 101 covers the correspondingly disposed signal line 102 orthographically projected on the base substrate 101, that is, each signal line is on the base substrate.
  • the upper positron projection falls within the orthographic projection of the correspondingly disposed metal strip on the base substrate.
  • each metal strip 150 is greater than the width of the signal line 102, so that the first insulating layer 103 between the wire 102 and the metal strip 150 is better ensured that it will not be engraved. Etch etching is retained. It should be noted that the above-described width means a dimension in a direction perpendicular to the extending direction of the signal line.
  • the second metal layer includes a conductive pattern in the display region, each metal strip is insulated from the conductive pattern, and the metal strip and the conductive pattern are fabricated by the same mask process. Therefore, the method for fabricating the array substrate provided by the embodiment of the present disclosure can avoid short circuit between the signal lines, and has a good protection effect on the metal line, and does not add a new mask process, thereby saving cost.

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Abstract

一种阵列基板及其制作方法和显示装置。该阵列基板包括衬底基板（101）；第一金属层（110），位于衬底基板（101）上；第一绝缘层（103），位于第一金属层（110）远离衬底基板（101）的一侧；第二金属层（120），位于第一绝缘层（103）远离衬底基板（101）的一侧；以及第二绝缘层（104），位于第二金属层（120）远离衬底基板（101）的一侧，阵列基板包括显示区（180）和围绕显示区（180）的周边区（190），第一金属层（110）在周边区包括多条信号线（102），第二绝缘层（104）在周边区（190）包括至少一个与多条信号线（102）中至少两条信号线（102）交叠的凹槽（130），第二金属层（120）在周边区（190）包括金属条（150），在凹槽（130）与信号线（102）交叠的区域，信号线（102）在衬底基板（101）上正投影落入金属条（150）在衬底基板（101）上的正投影内。该阵列基板可规避绝缘层中形成的凹槽中的金属残留而导致的信号线短路问题，从而可提高产品良率。

Description

阵列基板及其制作方法和显示装置
本申请要求于2018年03月14日递交的中国专利申请第201810208808.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种阵列基板及其制作方法和显示装置。
背景技术
随着显示技术的不断发展，低温多晶硅-有源矩阵发光二极管(LTPS-AMOLED)显示装置由于其具有广色域、高对比度、低功耗、轻薄、柔性可弯折等优点成为研究热点，并被视为新一代的显示技术。另一方面，随着智能手机、智能电视的不断发展，窄边框和超窄边框设计成为了市场上的主流和竞争的方向。
通常，低温多晶硅-有源矩阵发光二极管显示装置的背板电路包括多层金属信号线和绝缘层，并且结构较为复杂。
发明内容
本公开至少一个实施例提供一种阵列基板，其包括：衬底基板；第一金属层，位于所述衬底基板上；第一绝缘层，位于所述第一金属层远离所述衬底基板的一侧；第二金属层，位于所述第一绝缘层远离所述衬底基板的一侧；以及第二绝缘层，位于所述第二金属层远离所述衬底基板的一侧，所述阵列基板包括显示区和围绕所述显示区的周边区，所述第一金属层在所述周边区包括多条信号线，所述第二绝缘层在所述周边区包括至少一个与所述多条信号线中至少两条信号线交叠的凹槽，所述第二金属层在所述周边区包括金属条，在所述凹槽与所述信号线交叠的区域，所述信号线在所述衬底基板上的正投影落入所述金属条在所述衬底基板上的正投影内。
例如，在本公开一实施例提供的阵列基板中，所述金属条包括多个金属条，所述多个金属条与所述多条信号线一一对应设置，在所述凹槽与所述信号线交叠的区域，各所述信号线在所述衬底基板上的正投影落入对应设置的所述金属 条在所述衬底基板上的正投影内。
例如，在本公开一实施例提供的阵列基板中，在所述凹槽与所述信号线交叠的区域，各所述金属条的宽度大于各所述信号线的宽度。
例如，在本公开一实施例提供的阵列基板中，所述多条信号线延伸至所述显示区。
例如，在本公开一实施例提供的阵列基板中，所述第二金属层在所述显示区包括导电图案，各所述金属条与所述导电图案绝缘。
例如，在本公开一实施例提供的阵列基板中，所述第一绝缘层的材料包括无机绝缘材料，所述第二绝缘层的材料包括无机绝缘材料。
例如，在本公开一实施例提供的阵列基板中，所述凹槽在所述周边区没有设置所述金属条的区域沿垂直于所述衬底基板的方向贯穿所述第一绝缘层。
例如，在本公开一实施例提供的阵列基板中，所述第一金属层为第一栅极金属层，所述第二金属层为第二栅极金属层。
例如，在本公开一实施例提供的阵列基板中，所述第二绝缘层包括层间介电层。
例如，本公开一实施例提供的阵列基板还包括：第三金属层，位于所述第二绝缘层远离所述第二金属层的一侧；所述第三金属层在所述周边区包括位于所述凹槽的底角的金属残留。
例如，在本公开一实施例提供的阵列基板中，所述第三金属层在所述显示区包括源极、漏极和源漏信号线中的至少之一。
例如，本公开一实施例提供的阵列基板还包括：钝化层，设置在所述第三金属层远离所述第二绝缘层的一侧；以及像素电极，位于所述显示区且在所述钝化层远离所述第三金属层的一侧。
本公开至少一个实施例提供一种显示装置，包括上述任一项所述的阵列基板。
本公开至少一个实施例提供一种阵列基板的制作方法，其包括：在衬底基板上形成第一金属层；在所述第一金属层远离所述衬底基板的一侧形成第一绝缘层；在所述第一绝缘层远离所述衬底基板的一侧形成第二金属层；在所述第二金属层远离所述衬底基板的一侧形成第二绝缘层；以及刻蚀所述第二绝缘层以形成至少一个凹槽，所述阵列基板包括显示区和围绕所述显示区的周边区，所述第一金属层在所述周边区包括多条信号线，所述凹槽与所述多条信号线中 至少两条信号线交叠，所述第二金属层在所述周边区包括金属条，在所述凹槽与所述信号线交叠的区域，所述信号线在所述衬底基板上的正投影落入所述金属条在所述衬底基板上的正投影内。
例如，在本公开一实施例提供的阵列基板的制作方法中，所述金属条包括多个金属条，所述多个金属条与所述多条信号线一一对应设置，在所述凹槽与所述信号线交叠的区域，各所述信号线在所述衬底基板上的正投影落入对应设置的所述金属条在所述衬底基板上的正投影内。
例如，在本公开一实施例提供的阵列基板的制作方法中，在所述凹槽与所述信号线交叠的区域，各所述金属条的宽度大于各所述信号线的宽度。
例如，在本公开一实施例提供的阵列基板的制作方法中，所述第二金属层在所述显示区包括导电图案，各所述金属条与所述导电图案绝缘，所述金属条与所述导电图案通过同一掩模工艺制作。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种阵列基板的截面示意图；
图2为一种金属残留导致短路的示意图；
图3A-图3F为一种阵列基板的制作方法的分步示意图；
图4A为另一种阵列基板的平面示意图；
图4B为图4A所示的阵列基板中金属残留导致短路的示意图；
图5A和5B为根据本公开一实施例提供的一种阵列基板的截面示意图；
图6为根据本公开一实施例提供的一种阵列基板的平面示意图；以及
图7A-7F为根据本公开一实施例提供的一种阵列基板的制作方法的分步示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的 本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
在研究中，本申请的发明人发现：为了防止裂纹向显示区扩散，阵列基板的边缘通常会在层间介电层(Interlayer Dielectric Layer)中形成至少一个凹槽。然而，在制作上述阵列基板的过程中，在已经形成有凹槽的层间介电层的上方进行金属层(例如，下文中的第三金属层)的制备工艺和图案化工艺的时候，凹槽的底角位置出现金属层的残留。残留的金属会将不同的金属信号线电连接，从而造成短路，进而使得采用该阵列基板的显示装置出现显示不良。
图1为一种阵列基板的截面示意图。图1仅示出了该阵列基板的周边区域。如图1所示，该阵列基板包括衬底基板01、设置在衬底基板01上的信号线02、设置在信号线02上的第一绝缘层03以及设置在第一绝缘层03上的第二绝缘层04。例如，第二绝缘层04为层间介电层。为了防止裂纹向显示区扩散，该阵列基板的周边区会形成至少一个凹槽30。凹槽30贯穿第一绝缘层03和第二绝缘层04，并暴露出信号线02。然而，在进行后续的第三金属层的制备工艺和图案化工艺的时候，凹槽30的底角位置会出现第三金属层的金属残留40。图2示出了一种金属残留导致短路的示意图。如图2所示，在凹槽30的底角位置的金属残留40会将不同的信号线02电连接，从而造成短路，进而使得采用该阵列基板的显示装置出现显示不良。需要说明的是，上述的信号线02可由第一栅极金属层图案化得到。
为了更清楚地说明上述的金属残留导致的信号线短路问题，图3A-图3F示出了一种阵列基板的制作方法的分步示意图。同样地，图3A-3F仅示出了该阵列基板的周边区域。如图3A所示，在衬底基板01上形成信号线02，信号线02可通过先形成一层金属层，然后通过图案化工艺得到；如图3B所示，在衬底基板01和信号线02上形成第一绝缘层03，第一绝缘层03覆盖信号线02； 如图3C所示，在第一绝缘层03上形成第二绝缘层04，例如，第一绝缘层03和第二绝缘层04都可为无机绝缘层；如图3D所示，刻蚀第二绝缘层04以形成至少一个凹槽30，由于第二绝缘层04和第一绝缘层03均为无机绝缘层，因此在刻蚀第二绝缘层04的过程中，刻蚀液同时将凹槽30所在位置处的第一绝缘层03刻蚀掉，从而暴露出信号线02；如图3E所示，在上述的基板上沉积第三金属层05，此时第三金属层05也沉积在凹槽30中；如图3F所示，刻蚀第三金属层05并去除周边区的第三金属层05；由于第三金属层05也沉积在凹槽30中，在刻蚀第三金属层05的过程中，容易在凹槽30的底角位置形成金属残留40。如图3F所示，在凹槽30的底角位置的金属残留40会将不同的信号线02电连接，从而造成短路，进而使得采用该阵列基板的显示装置出现显示不良。需要说明的是，由于第三金属层不作为信号线时，第三金属层仅在显示区保留有图案，在周边区需要完全去除；另外，在形成第一绝缘层之后，形成第二绝缘层之前，该制作方法还包括形成第二金属层(例如，第二栅极金属层)，第二金属层同样仅在显示区保留有图案，在周边区需要完全去除。
另一方面，如果上述的信号线02通过图案化第三金属层05得到，同样也会产生信号线短路的问题。图4A为另一种阵列基板的平面示意图。图4B为图4A所示的阵列基板中金属残留导致短路的示意图。图4A和4B仅示出了该阵列基板的周边区域。如图4A和4B所示，该阵列基板包括衬底基板01、设置在衬底基板01上的第一绝缘层(未示出)以及设置在第一绝缘层上的第二绝缘层04。例如，第二绝缘层04为层间介电层。为了防止裂纹向显示区扩散，该阵列基板的周边区会形成至少一个凹槽30。凹槽30贯穿第一绝缘层03和第二绝缘层04。在进行后续的第三金属层的制备工艺和图案化第三金属层并形成信号线02的时候，凹槽30的底角位置会出现第三金属层的金属残留40。在凹槽30的底角位置的金属残留40会将不同的信号线02电连接，从而造成短路，进而使得采用该阵列基板的显示装置出现显示不良。
本公开实施例提供一种阵列基板及其制作方法和显示装置。该阵列基板包括衬底基板；第一金属层，位于衬底基板上；第一绝缘层，位于第一金属层远离衬底基板的一侧；第二金属层，位于第一绝缘层远离第一金属层的一侧；以及第二绝缘层，位于第二金属层远离第一绝缘层的一侧，阵列基板包括显示区和围绕显示区的周边区，第一金属层在周边区包括多条信号线，第二绝缘层在周边区包括至少一个与多条信号线中至少两条信号线交叠的凹槽，第二金属层 在周边区包括金属条，在凹槽与信号线交叠的区域，信号线在衬底基板上正投影落入金属条在衬底基板上的正投影内。该阵列基板可通过在凹槽所在位置处在信号线上增加孤立的金属条，从而规避绝缘层中形成的凹槽中的金属残留而导致的信号线短路问题，从而可提高产品良率。
下面结合附图对本公开实施例提供的阵列基板及其制作方法和显示装置进行详细的说明。
本公开一实施例提供一种阵列基板。图5A和5B为根据本公开一实施例提供的一种阵列基板的截面示意图。图5A示出了该阵列基板的周边区，图5B示出了该阵列基板的显示区。如图5A和5B所示，该阵列基板包括衬底基板101；位于衬底基板101上的第一金属层110；位于第一金属层110远离衬底基板101的一侧的第一绝缘层103；位于第一绝缘层103远离第一金属层110的一侧的第二金属层120；以及位于第二金属层120远离第一绝缘层103的一侧的第二绝缘层104。阵列基板包括显示区180和围绕显示区180的周边区190，第一金属层110在周边区190包括多条信号线102，第二绝缘层104在周边区190包括至少一个与多条信号线102中至少两条信号线102交叠的凹槽130，也就是说，凹槽130会与至少两条信号线102交叠，第二金属层120在周边区190包括金属条150，在凹槽130与信号线102交叠的区域，金属条150在衬底基板101上的正投影覆盖信号线102在衬底基板101上正投影，也就是说，信号线102在衬底基板101上正投影落入金属条150在衬底基板101上的正投影内。需要说明的是，凹槽130可起到防止裂纹向显示区扩散的作用。
在本公开实施例提供的阵列基板的制作过程中，由于第二绝缘层104在周边区190的凹槽130与多条信号线102中至少两条相邻的信号线102交叠，因此在后续的第三金属层的制备工艺和图案化工艺中也会面临凹槽130中的金属残留140导致信号线102短路的问题。然而，如图5A所示，由于在凹槽130与信号线102交叠的区域，金属条150在衬底基板101上的正投影覆盖信号线102在衬底基板101上正投影，在第二绝缘层104中形成凹槽130的工艺步骤中，金属条150可阻挡刻蚀液刻(针对绝缘层的刻蚀液)蚀刻被金属条150覆盖的第一绝缘层103，也就是说，导线102和金属条150之间的第一绝缘层103不会被刻蚀液刻蚀，得到保留。由此，在凹槽130与信号线102交叠的区域，在后续的第三金属层的制备工艺和图案化工艺中，即使存在金属残留140，金属残留140也只能和金属条150相连，无法与导线102相连，从而可避免金属 残留导致的信号线短路问题，进而可提高产品良率。另外，由于金属条150在衬底基板101上的正投影覆盖信号线102在衬底基板101上正投影，在后续的电极(例如，像素电极、阳极等)的制备工艺和图案化工艺中，刻蚀液(针对电极的刻蚀液)最多只会刻蚀掉金属条150，导线102和金属条150之间的第一绝缘层103可避免导线102被刻蚀；因此金属条150还可对信号线102起到保护作用。
例如，衬底基板101可采用玻璃基板、石英基板或塑料基板。
例如，第一金属层110可为第一栅极金属层；第二金属层120可为第三金属层。
例如，在一些示例中，第一绝缘层的材料包括无机绝缘材料，第二绝缘层的材料包括无机绝缘材料。
例如，在一些示例中，第二绝缘层可为层间介电层。
例如，第一绝缘层103和第二绝缘层104的材料可为氮化硅、氧化硅和氮氧化硅中的一种或多种。
例如，在一些示例中，如图5A和5B所示，第二金属层120在显示区180包括导电图案106，各金属条150与导电图案106绝缘。也就是说，金属条150相对于导电图案106是孤立的。由此，当金属残留140也只能和金属条150相连时，无法对导电图案106造成不利影响。另一方面，由于金属条150通过用于形成导电图案106第二金属层120图案化形成，因此，本公开实施例提供的阵列基板在可避免信号线之间发生短路，对金属线起到很好的保护作用的同时，没有增加新的掩模工艺，因此节约了成本。
例如，第一金属层可为第一栅极金属层，第一栅极金属层在显示区可包括第一栅极；第二金属层可为第二栅极金属层；此时，导电图案可为第二栅极。
例如，在一些示例中，如图5A和5B所示，该阵列基板还包括：第三金属层160，位于第二绝缘层104远离第二金属层120的一侧；第三金属层160在周边区190包括位于凹槽的底角的金属残留140。由于第三金属层160不作为信号线时，第三金属层160仅在显示区180保留有图案，在周边区190需要通过图案化工艺完全去除，通常的图案化工艺包括曝光、显影、刻蚀等步骤；由于凹槽130形成第三金属层160在凹槽130的斜边上有爬坡现象，容易导致凹槽130的底角位置的第三金属层160无法被完全去除，形成金属残留140。
例如，在一些示例中，第三金属层160在显示区190包括源极107、漏极 108、源漏信号线109中的一个或多个。
例如，在一些示例中，如图5B所示，该阵列基板还包括：设置在衬底基板101上的有源层210以及设置在有源层210和第一金属层110之间的绝缘层220。
例如，在一些示例中，如图5B所示，该阵列基板还包括：钝化层171，设置在源漏金属160远离第二绝缘层104的一侧；以及像素电极172，位于显示区180且在钝化层171远离第三金属层160的一侧。在像素电极172的制备工艺和图案化工艺中，由于金属条150在衬底基板101上的正投影覆盖信号线102在衬底基板101上正投影，刻蚀液(针对像素电极的刻蚀液)最多只会刻蚀掉金属条150，导线102和金属条150之间的第一绝缘层103可避免导线102被刻蚀；因此金属条150还可对信号线102起到保护作用。
例如，在一些示例中，该阵列基板可为有机发光二极管显示装置的阵列基板。此时，像素电极可为阳极。
例如，当该阵列基板可为有机发光二极管显示装置的阵列基板时，如图5B所示，该阵列基板还包括位于像素电极172远离钝化层171的一侧的有机发光层173。
图6为根据本公开一实施例提供的一种阵列基板的平面示意图。图6仅示出了该阵列基板的周边区。如图6所示，金属条150的数量为多个，多个金属条150与多条信号线102一一对应设置。在凹槽130与信号线102交叠的区域，各金属条150在衬底基板101上的正投影覆盖对应设置的信号线102在衬底基板101上正投影，也就是说，各信号线102在衬底基板101上正投影落入对应设置的金属条150在衬底基板101上的正投影内。由此，在第二绝缘层104中形成凹槽130的工艺步骤中，金属条150可阻挡刻蚀液刻(针对绝缘层的刻蚀液)蚀被金属条150覆盖的第一绝缘层103，也就是说，金属条150与对应设置的导线102之间的第一绝缘层103不会被刻蚀液刻蚀，得到保留。由此，在凹槽130与信号线102交叠的区域，在后续的第三金属层的制备工艺和图案化工艺中，即使存在金属残留140，金属残留140也只能和金属条150相连，无法与导线102相连，从而可避免金属残留导致的信号线短路问题，进而可提高产品良率。另外，由于金属条150在衬底基板101上的正投影覆盖对应设置的信号线102在衬底基板101上正投影，在后续的电极(例如，像素电极、阳极等)的制备工艺和图案化工艺中，刻蚀液(针对电极的刻蚀液)最多只会刻蚀 掉金属条150，金属条150与对应设置的导线102之间的第一绝缘层103可避免导线102被刻蚀；因此金属条150还可对对应设置的信号线102起到保护作用。
值得注意的是，由于金属条150的数量为多个，且多个金属条150与多条信号线102一一对应设置。该阵列基板不用设置一整块、面积较大的金属条(金属块)去覆盖所有的信号线；一方面可避免一整块、面积较大的金属条(金属块)影响该阵列基板的柔性，另一方面还可避免一整块、面积较大的金属条(金属块)造成的反光问题。
例如，在一些示例中，如图6所示，由于金属条150的数量为多个，多个金属条150与多条信号线102一一对应设置。凹槽130在周边区190没有设置金属条150的区域沿垂直于衬底基板101的方向贯穿第一绝缘层103。从而可在可避免信号线之间发生短路，对金属线起到很好的保护作用的同时，最大限度地起到阻挡第一绝缘层的裂纹向显示区扩散的作用。
例如，在一些示例中，如图6所示，各金属条150的宽度大于信号线102的宽度，从而可更好地保证导线102和金属条150之间的第一绝缘层103不会被刻蚀液刻蚀，得到保留。需要说明的是，上述的宽度是指沿与信号线的延伸方向垂直的方向上的尺寸。
例如，在一些示例中，多条信号线可延伸至显示区。例如，信号线可作为扫描驱动线、源漏信号线、或电源线等。
本公开一实施例还提供一种显示装置，包括上述实施例中任一示例所提供的阵列基板。由于该显示装置包括上述实施例中任一示例所提供的阵列基板，该显示装置具有与其包括的显示面板的技术效果对应的技术效果，即可规避第二绝缘层中形成的凹槽中的金属残留而导致的信号线短路问题，从而可提高产品良率，具体可参见上述实施例的相关描述，在此不再赘述。
例如，该显示装置可为电视、电脑、手机、导航仪、显示仪表等任意具有显示功能的电子设备。
本公开一实施例还提供一种阵列基板的制作方法。该制作方法包括以下步骤：
步骤S301：在衬底基板上形成第一金属层。
步骤S302：在第一金属层远离衬底基板的一侧形成第一绝缘层。
步骤S303：在第一绝缘层远离衬底基板的一侧形成第二金属层。
步骤S304：在第二金属层远离第一绝缘层的一侧形成第二绝缘层。
步骤S305：刻蚀第二绝缘层以形成至少一个凹槽，阵列基板包括显示区和围绕显示区的周边区，第一金属层在周边区包括多条信号线，凹槽与多条信号线中至少两条信号线交叠，第二金属层在周边区包括金属条，在凹槽与信号线交叠的区域，信号线在衬底基板上正投影落入金属条在衬底基板上的正投影内。
在本公开实施例提供的阵列基板的制作方法中，由于第二绝缘层在周边区的凹槽与多条信号线中至少两条相邻的信号线交叠，因此在后续的第三金属层的制备工艺和图案化工艺中也会面临凹槽中的金属残留导致信号线短路的问题。然而，由于在凹槽与信号线交叠的区域，金属条在衬底基板上的正投影覆盖信号线在衬底基板上正投影，在第二绝缘层中形成凹槽的工艺步骤中，金属条可阻挡刻蚀液刻(针对绝缘层的刻蚀液)蚀被金属条覆盖的第一绝缘层，也就是说，导线和金属条之间的第一绝缘层不会被刻蚀液刻蚀，得到保留。由此，在凹槽与信号线交叠的区域，在后续的第三金属层的制备工艺和图案化工艺中，即使存在金属残留，金属残留也只能和金属条相连，无法与导线相连，从而可避免金属残留导致的信号线短路问题，进而可提高产品良率。另外，由于金属条在衬底基板上的正投影覆盖信号线在衬底基板上正投影，在后续的电极(例如，像素电极、阳极等)的制备工艺和图案化工艺中，刻蚀液(针对电极的刻蚀液)最多只会刻蚀掉金属条，导线和金属条之间的第一绝缘层可避免导线被刻蚀；因此金属条还可对信号线起到保护作用。
例如，衬底基板可采用玻璃基板、石英基板或塑料基板。
例如，第一金属层可为第一栅极金属层；第二金属层可为第三金属层。
例如，在一些示例中，第一绝缘层的材料包括无机绝缘材料，第二绝缘层的材料包括无机绝缘材料。
例如，在一些示例中，第二绝缘层可为层间介电层。
例如，第一绝缘层和第二绝缘层的材料可为氮化硅、氧化硅和氮氧化硅中的一种或多种。
图7A-7F为根据本公开一实施例提供的一种阵列基板的制作方法的分步示意图。图7A-7F仅示出了该阵列基板的周边区。如图7A所示，在衬底基板101上形成第一金属层110，第一金属层110在周边区包括多条信号线102。如图7B所示，在第一金属层110远离衬底基板101的一侧形成第一绝缘层103。 如图7C所示，在第一绝缘层103远离衬底基板101的一侧形成第二金属层120，第二金属层120在周边区包括金属条150。如图7D所示，在第二金属层120远离第一绝缘层103的一侧形成第二绝缘层104；刻蚀第二绝缘层104以形成至少一个凹槽130，凹槽130与多条信号线102中至少两条相邻的信号线102交叠，在凹槽130与信号线102交叠的区域，金属条150在衬底基板101上的正投影覆盖信号线102在衬底基板101上的正投影。在凹槽130与信号线102交叠的区域，导线102和金属条050之间的第一绝缘层103不会被刻蚀液刻蚀，得到保留。
如图7E所示，在上述的基板上沉积第三金属层160，此时第三金属层160也沉积在凹槽130中；如图7F所示，刻蚀第三金属层160并去除周边区190的第三金属层160；由于第三金属层160也沉积在凹槽30中，在刻蚀第三金属层160的过程中，容易在凹槽130的底角位置形成金属残留140。如图7F所示，在凹槽130与信号线102交叠的区域，即使存在金属残留140，金属残留140也只能和金属条150相连，无法与导线102相连，从而可避免金属残留导致的信号线短路问题，进而可提高产品良率。
例如，在一些示例中，金属条150的数量为多个，多个金属条150与多条信号线102一一对应设置。在凹槽130与信号线102交叠的区域，各金属条150在衬底基板101上的正投影覆盖对应设置的信号线102在衬底基板101上正投影，即各信号线在衬底基板上正投影落入对应设置的金属条在衬底基板上的正投影内。
例如，在一些示例中，如图6所示，各金属条150的宽度大于信号线102的宽度，从而可更好地保证导线102和金属条150之间的第一绝缘层103不会被刻蚀液刻蚀，得到保留。需要说明的是，上述的宽度是指沿与信号线的延伸方向垂直的方向上的尺寸。
例如，在一些示例中，第二金属层在显示区包括导电图案，各金属条与导电图案绝缘，金属条与导电图案通过同一掩模工艺制作。因此，本公开实施例提供的阵列基板的制作方法在可避免信号线之间发生短路，对金属线起到很好的保护作用的同时，没有增加新的掩模工艺，因此节约了成本。
有以下几点需要说明：
(1)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开同一实施例及不同实施例中的特征可以相互组合。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (17)

  1. 一种阵列基板，包括：
    衬底基板；
    第一金属层，位于所述衬底基板上；
    第一绝缘层，位于所述第一金属层远离所述衬底基板的一侧；
    第二金属层，位于所述第一绝缘层远离所述衬底基板的一侧；以及
    第二绝缘层，位于所述第二金属层远离所述衬底基板的一侧，
    其中，所述阵列基板包括显示区和围绕所述显示区的周边区，所述第一金属层在所述周边区包括多条信号线，所述第二绝缘层在所述周边区包括至少一个与所述多条信号线中至少两条信号线交叠的凹槽，所述第二金属层在所述周边区包括金属条，
    在所述凹槽与所述信号线交叠的区域，所述信号线在所述衬底基板上的正投影落入所述金属条在所述衬底基板上的正投影内。
  2. 根据权利要求1所述的阵列基板，其中，所述金属条包括多个金属条，所述多个金属条与所述多条信号线一一对应设置，在所述凹槽与所述信号线交叠的区域，各所述信号线在所述衬底基板上的正投影落入对应设置的所述金属条在所述衬底基板上的正投影内。
  3. 根据权利要求1或2所述的阵列基板，其中，在所述凹槽与所述信号线交叠的区域，各所述金属条的宽度大于各所述信号线的宽度。
  4. 根据权利要求1-3中任一项所述的阵列基板，其中，所述多条信号线延伸至所述显示区。
  5. 根据权利要求1-4中任一项所述的阵列基板，其中，所述第二金属层在所述显示区包括导电图案，各所述金属条与所述导电图案绝缘。
  6. 根据权利要求1-5中任一项所述的阵列基板，其中，所述第一绝缘层的材料包括无机绝缘材料，所述第二绝缘层的材料包括无机绝缘材料。
  7. 根据权利要求1-6中任一项所述的阵列基板，其中，所述凹槽在所述周边区没有设置所述金属条的区域沿垂直于所述衬底基板的方向贯穿所述第一绝缘层。
  8. 根据权利要求1-7中任一项所述的阵列基板，其中，所述第一金属层为第一栅极金属层，所述第二金属层为第二栅极金属层。
  9. 根据权利要求1-8中任一项所述的阵列基板，其中，所述第二绝缘层包括层间介电层。
  10. 根据权利要求1-9中任一项所述的阵列基板，还包括：
    第三金属层，位于所述第二绝缘层远离所述第二金属层的一侧；
    其中，所述第三金属层在所述周边区包括位于所述凹槽的底角的金属残留。
  11. 根据权利要求10所述的阵列基板，其中，所述第三金属层在所述显示区包括源极、漏极和源漏信号线中的至少之一。
  12. 根据权利要求11所述的阵列基板，还包括：
    钝化层，设置在所述第三金属层远离所述第二绝缘层的一侧；以及
    像素电极，位于所述显示区且在所述钝化层远离所述第三金属层的一侧。
  13. 一种显示装置，包括根据权利要求1-12中任一项所述的阵列基板。
  14. 一种阵列基板的制作方法，包括：
    在衬底基板上形成第一金属层；
    在所述第一金属层远离所述衬底基板的一侧形成第一绝缘层；
    在所述第一绝缘层远离所述衬底基板的一侧形成第二金属层；
    在所述第二金属层远离所述衬底基板的一侧形成第二绝缘层；以及
    刻蚀所述第二绝缘层以形成至少一个凹槽，
    其中，所述阵列基板包括显示区和围绕所述显示区的周边区，所述第一金属层在所述周边区包括多条信号线，所述凹槽与所述多条信号线中至少两条信号线交叠，所述第二金属层在所述周边区包括金属条，在所述凹槽与所述信号线交叠的区域，所述信号线在所述衬底基板上的正投影落入所述金属条在所述衬底基板上的正投影内。
  15. 根据权利要求14所述的阵列基板的制作方法，其中，所述金属条包括多个金属条，所述多个金属条与所述多条信号线一一对应设置，在所述凹槽与所述信号线交叠的区域，各所述信号线在所述衬底基板上的正投影落入对应设置的所述金属条在所述衬底基板上的正投影内。
  16. 根据权利要求14所述的阵列基板的制作方法，其中，在所述凹槽与所述信号线交叠的区域，各所述金属条的宽度大于各所述信号线的宽度。
  17. 根据权利要求14所述的阵列基板的制作方法，其中，所述第二金属层在所述显示区包括导电图案，各所述金属条与所述导电图案绝缘，所述金属 条与所述导电图案通过同一掩模工艺制作。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7515520B2 (ja) 2020-03-23 2024-07-12 京東方科技集團股▲ふん▼有限公司 表示基板及びその製造方法、表示マザーボード並びに表示装置

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108447872B (zh) * 2018-03-14 2021-01-22 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
CN109637994B (zh) * 2018-11-26 2021-02-02 武汉华星光电半导体显示技术有限公司 一种柔性显示面板及柔性显示装置
CN109378320B (zh) * 2018-12-05 2021-01-26 合肥鑫晟光电科技有限公司 一种阵列基板及其制备方法
CN109599031B (zh) * 2018-12-13 2021-03-26 合肥鑫晟光电科技有限公司 一种显示基板及其制作方法、显示装置
CN111192910B (zh) * 2020-01-22 2022-10-14 京东方科技集团股份有限公司 阵列基板及制作方法、显示面板
WO2021174392A1 (zh) * 2020-03-02 2021-09-10 京东方科技集团股份有限公司 偏光片、电子装置及制备偏光片的方法
CN111524910A (zh) * 2020-04-29 2020-08-11 深圳市华星光电半导体显示技术有限公司 阵列基板及其制造方法、显示装置
CN113270460A (zh) * 2021-05-18 2021-08-17 京东方科技集团股份有限公司 一种显示面板及其制备方法、显示装置
CN113658974B (zh) * 2021-08-16 2024-05-03 京东方科技集团股份有限公司 一种发光基板及其制备方法、测试方法、显示装置
CN117322166A (zh) * 2021-12-02 2023-12-29 京东方科技集团股份有限公司 显示基板及电子设备
WO2023184374A1 (zh) * 2022-03-31 2023-10-05 京东方科技集团股份有限公司 显示面板、阵列基板及其制备方法
CN115509050B (zh) * 2022-10-09 2024-09-24 厦门天马微电子有限公司 显示面板和显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103715140A (zh) * 2013-10-12 2014-04-09 深圳市华星光电技术有限公司 一种避免oled显示设备中金属线路短路的方法
CN105161506A (zh) * 2015-10-29 2015-12-16 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
US20160306208A1 (en) * 2015-04-20 2016-10-20 Mitsubishi Electric Corporation Liquid crystal display device
CN108447872A (zh) * 2018-03-14 2018-08-24 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3306488B2 (ja) * 1996-07-02 2002-07-24 シャープ株式会社 アクティブマトリクス基板
JP4398601B2 (ja) * 2001-05-18 2010-01-13 エーユー オプトロニクス コーポレイション 薄膜トランジスタ・アレイ基板、薄膜トランジスタ・アレイ基板の製造方法および表示装置
JP2005183836A (ja) * 2003-12-22 2005-07-07 Hitachi Cable Ltd 半導体装置用テープキャリアおよびこれを用いた半導体装置
JP4739155B2 (ja) * 2006-09-12 2011-08-03 富士フイルム株式会社 表示媒体
JP5720222B2 (ja) * 2010-12-13 2015-05-20 ソニー株式会社 表示装置及び電子機器
KR101838736B1 (ko) * 2011-12-20 2018-03-15 삼성전자 주식회사 테이프 배선 기판 및 이를 포함하는 칩 온 필름 패키지
US9195108B2 (en) * 2012-08-21 2015-11-24 Apple Inc. Displays with bent signal lines
WO2015170369A1 (ja) 2014-05-09 2015-11-12 パナソニック液晶ディスプレイ株式会社 液晶表示装置
JP6289286B2 (ja) * 2014-06-25 2018-03-07 株式会社ジャパンディスプレイ 表示装置および表示装置の製造方法
US9450038B2 (en) * 2014-07-31 2016-09-20 Lg Display Co., Ltd. Flexible display
KR102311728B1 (ko) 2015-03-17 2021-10-12 삼성디스플레이 주식회사 표시 장치
KR102455318B1 (ko) * 2015-10-30 2022-10-18 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102513997B1 (ko) * 2016-02-04 2023-03-24 삼성디스플레이 주식회사 표시 장치
CN108701719A (zh) * 2016-02-22 2018-10-23 夏普株式会社 半导体装置和半导体装置的制造方法
TWI740908B (zh) * 2016-03-11 2021-10-01 南韓商三星顯示器有限公司 顯示設備
KR102505879B1 (ko) 2016-03-24 2023-03-06 삼성디스플레이 주식회사 디스플레이 장치
KR102696805B1 (ko) * 2016-08-12 2024-08-21 삼성디스플레이 주식회사 디스플레이 장치
CN107068695B (zh) * 2017-05-02 2020-02-21 京东方科技集团股份有限公司 一种柔性显示面板及其制备方法、柔性显示装置
CN107678196B (zh) * 2017-10-10 2021-04-27 京东方科技集团股份有限公司 连接器及显示屏

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103715140A (zh) * 2013-10-12 2014-04-09 深圳市华星光电技术有限公司 一种避免oled显示设备中金属线路短路的方法
US20160306208A1 (en) * 2015-04-20 2016-10-20 Mitsubishi Electric Corporation Liquid crystal display device
CN105161506A (zh) * 2015-10-29 2015-12-16 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN108447872A (zh) * 2018-03-14 2018-08-24 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3767673A4

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7515520B2 (ja) 2020-03-23 2024-07-12 京東方科技集團股▲ふん▼有限公司 表示基板及びその製造方法、表示マザーボード並びに表示装置

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