WO2019127634A1 - 一种igzo薄膜晶体管制备方法 - Google Patents

一种igzo薄膜晶体管制备方法 Download PDF

Info

Publication number
WO2019127634A1
WO2019127634A1 PCT/CN2018/071379 CN2018071379W WO2019127634A1 WO 2019127634 A1 WO2019127634 A1 WO 2019127634A1 CN 2018071379 W CN2018071379 W CN 2018071379W WO 2019127634 A1 WO2019127634 A1 WO 2019127634A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
metal layer
drain
pixel electrode
igzo semiconductor
Prior art date
Application number
PCT/CN2018/071379
Other languages
English (en)
French (fr)
Inventor
甘启明
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US15/749,492 priority Critical patent/US10861883B2/en
Publication of WO2019127634A1 publication Critical patent/WO2019127634A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to the field of screen display technologies, and in particular, to a method for fabricating an IGZO thin film transistor.
  • TFT The role that is crucial for pixel charging is TFT.
  • the characteristics of the TFT are largely determined by the active layer.
  • the conventional devices have AS (a-Si, amorphous silicon) as the active layer.
  • AS devices have been developed for a long time, and the device characteristics are stable, but the AS mobility is low, and the advantages are gradually lost at high resolution and high refresh rate.
  • IGZO Indium Gallium Zinc Oxide
  • IGZO has a higher mobility than AS, so it can have a faster charging rate, and can make the TFT smaller, further increase the pixel aperture ratio and reduce the backlight consumption.
  • the IGZO device itself has a small leakage current. The power consumption of the LCD panel itself is also a benefit.
  • the technical problem to be solved by the present invention is to provide a method for preparing an IGZO thin film transistor which can streamline the IGZO process and improve the process time.
  • the present invention provides a method for fabricating an IGZO thin film transistor, comprising:
  • Step S1 forming a gate electrode by the first metal layer through the first photomask, and sequentially forming a gate insulating layer, an IGZO semiconductor layer and a second metal layer on the gate;
  • Step S2 applying a photoresist layer on the second metal layer, exposing and developing the photoresist layer through a second mask, and simultaneously etching the second metal layer and the IGZO semiconductor layer by using a hydrogen peroxide etching solution.
  • the second metal layer is etched to form a source and a drain;
  • Step S3 forming a passivation layer on the source and the drain, and forming a contact hole over the drain through the third photomask;
  • Step S4 forming a pixel electrode on the passivation layer through a fourth photomask, and connecting the pixel electrode to the drain through the contact hole.
  • the etching rate of the second metal layer and the etching rate of the IGZO semiconductor layer are greater than 20.
  • the step S2 specifically includes:
  • the second metal layer located in the second channel region is etched to form a drain and a source, respectively.
  • the second reticle is a halftone reticle.
  • the photoresist of the first channel region is specifically removed by oxygen plasma ashing.
  • etching is performed until the IGZO semiconductor layer underlying the IGZO semiconductor layer is not covered.
  • the passivation layer is specifically deposited on the drain, the source, and the IGZO semiconductor layer not covered by the drain and the source.
  • the step S4 specifically includes:
  • the pixel electrode is connected to the drain through the contact hole.
  • the pixel electrode layer is specifically an indium tin oxide ITO layer.
  • the IGZO semiconductor layer is formed by physical vapor deposition.
  • the present invention adopts a hydrogen peroxide etching solution, which can etch the second metal layer and etch the IGZO semiconductor layer, and the etching rate of the second metal layer and the etching rate of the IGZO semiconductor layer are greater than 20,
  • the second metal layer and the IGZO semiconductor layer can be simultaneously subjected to a wet etching process, and the invention can shorten the process time and improve the production efficiency as compared with the prior art, which requires separate wet etching.
  • FIG. 1 is a schematic flow chart of a method for fabricating an IGZO thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a schematic view showing a gate insulating layer, an IGZO semiconductor layer, and a second metal layer sequentially formed on a gate electrode in an embodiment of the present invention.
  • FIG 3 is a schematic view showing a photoresist layer coated on a second metal layer in an embodiment of the present invention.
  • FIG. 4 is a schematic view showing exposure and development of the photoresist layer of FIG. 3 by a second mask in the embodiment of the present invention.
  • FIG. 5 is a schematic view showing etching of a second metal layer and an IGZO semiconductor layer simultaneously in an embodiment of the present invention.
  • Figure 6 is a schematic illustration of the removal of a photoresist layer in an embodiment of the present invention.
  • FIG. 7 is a schematic view showing etching of an annoying second metal layer in a channel region in an embodiment of the present invention.
  • FIG. 8 is a schematic view showing formation of a passivation layer on a source and a drain in an embodiment of the present invention.
  • Figure 9 is a schematic view showing the formation of a contact hole over the drain in the embodiment of the present invention.
  • Figure 10 is a schematic illustration of a deposition of a pixel electrode layer in an embodiment of the present invention.
  • FIG. 11 is a schematic view showing a pixel electrode connected to a drain through a contact hole in an embodiment of the present invention.
  • an embodiment of the present invention provides a method for fabricating an IGZO thin film transistor, including:
  • first metal layer by a first photomask, and sequentially forming a gate insulating layer, an IGZO semiconductor layer, and a second metal layer on the gate;
  • Coating a photoresist layer on the second metal layer exposing and developing the photoresist layer through a second mask, and simultaneously etching the second metal layer and the IGZO semiconductor layer by using a hydrogen peroxide etching solution.
  • a second metal layer is etched to form a source and a drain;
  • a pixel electrode layer is formed on the passivation layer, and the pixel electrode layer is exposed and developed by a fourth mask to form a pixel electrode, and the pixel electrode is connected to the drain through the contact hole.
  • FIG. 2 to FIG. 11 are schematic diagrams of respective steps of the method for fabricating the IGZO thin film transistor of the embodiment.
  • a first metal layer (not shown) is formed on a substrate (not shown).
  • the first metal layer is formed into a gate 1 by a first mask, and then sequentially on the gate 1.
  • a gate insulating layer 2, an IGZO semiconductor layer 3, and a second metal layer 4 are deposited.
  • the gate insulating layer 2 may be any one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, and the IGZO semiconductor layer 3 may be formed by physical vapor deposition.
  • the photoresist layer 5 is coated on the second metal layer 4. Then, as shown in FIG. 4, the photoresist layer 5 is exposed and developed by the second mask, and the photoresist is projected on the gate 1. Partially removed, a first channel region 51 is formed.
  • the second mask is specifically a Half Tone Mask (HTM).
  • the second metal layer 4 and the IGZO semiconductor layer 3 on both sides of the gate 1 are simultaneously etched by using a hydrogen peroxide (H 2 O 2 ) etching solution, wherein the etching rate of the second metal layer 4 and the IGZO semiconductor are The etch rate selection ratio of layer 3 is greater than 20.
  • the photoresist of the first channel region 51 is completely removed to form a second channel region 52.
  • the photoresist of the first channel region 51 is an oxygen plasma used in a dry etching process. Ashing is completely removed.
  • the second metal layer 4 located in the second channel region 52 after the photoresist is removed is etched to form the drain 6 and the source 7, respectively.
  • the IGZO semiconductor layer 3 is etched by monitoring the etching time and etching to the IGZO semiconductor layer 3 not covering the underside thereof. .
  • a passivation layer 8 is deposited on the drain 6 and the source 7 and the IGZO semiconductor layer 3 not covered by the drain 6 and the source 7, and as shown in FIG. A via hole 80 is formed over the drain electrode 6 through a third photomask.
  • the passivation layer 8 may be any one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.
  • a pixel electrode layer 9 preferably an indium tin oxide ITO layer, is deposited on the passivation layer 8 , and the pixel electrode layer 9 is exposed and developed through a fourth mask to form a pixel electrode 90 , and The pixel electrode 90 is connected to the drain electrode 6 through the contact hole 80.
  • the beneficial effects of the embodiments of the present invention are as follows: the present invention uses a hydrogen peroxide etching solution to etch the second metal layer and etch the IGZO semiconductor layer, the etching rate of the second metal layer and the etching rate of the IGZO semiconductor layer.
  • the selection ratio is greater than 20, so that the second metal layer and the IGZO semiconductor layer can be simultaneously subjected to a wet etching process.
  • the wet etching is separately performed, and the invention can shorten the processing time and improve the production efficiency.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种IGZO薄膜晶体管制备方法，包括：步骤S1，通过第一道光罩使第一金属层形成栅极，并在栅极上依次形成栅极绝缘层、IGZO半导体层和第二金属层；步骤S2，在第二金属层上涂布光阻层，通过第二道光罩对光阻层进行曝光显影，再采用双氧水蚀刻液同时蚀刻第二金属层和IGZO半导体层，第二金属层被蚀刻形成源极和漏极；步骤S3，在源极、漏极上形成钝化层，并通过第三道光罩在漏极上方形成接触孔；步骤S4，通过第四道光罩在钝化层上形成像素电极，并将像素电极通过接触孔与漏极连接。采用双氧水蚀刻液，既可以蚀刻第二金属层，又可以蚀刻IGZO半导体层，可以缩短制程时间，提高生产效率。

Description

一种IGZO薄膜晶体管制备方法
本申请要求于2017年12月27日提交中国专利局、申请号为201711444804.0、发明名称为“一种IGZO薄膜晶体管制备方法”的中国专利申请的优先权，上述专利的全部内容通过引用结合在本申请中。
技术领域
本发明涉及屏幕显示技术领域，尤其涉及一种IGZO薄膜晶体管制备方法。
背景技术
随着显示技术的发展，液晶显示屏逐渐往大尺寸高分辨率的方向发展。这就代表对像素的充电时间也越来越短。而对于像素充电起至关重要的作用是TFT。而TFT的特性又由有源层很大程度决定。而传统的器件均有AS(a-Si，非晶硅)作为有源层。AS器件由于发展已久，器件特性稳定，但是AS迁移率低下，在高分辨率及高刷新频率下，就逐渐失去了原有的优势。另一种氧化物半导体材料IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)为人们所推崇。IGZO有着比AS更大的迁移率，从而可以有更快的充电速率，而且可以将TFT做得更小，进一步提升像素开口率，降低背光消耗，另一方面，IGZO器件本身漏电流小，对于液晶面板本身的功耗也是一个益处。
IGZO发展之初是参考AS 5mask(光罩)制程制作TFT器件。但是，高品质、低成本一直是显示行业的发展趋势，有必要进一步精简IGZO制程工艺，提升制程时间。
发明内容
本发明所要解决的技术问题在于，提供一种能精简IGZO制程工艺，提升制程时间的IGZO薄膜晶体管制备方法。
为了解决上述技术问题，本发明提供一种IGZO薄膜晶体管制备方法，包括：
步骤S1，通过第一道光罩使第一金属层形成栅极，并在所述栅极上依 次形成栅极绝缘层、IGZO半导体层和第二金属层；
步骤S2，在所述第二金属层上涂布光阻层，通过第二道光罩对所述光阻层进行曝光显影，再采用双氧水蚀刻液同时蚀刻所述第二金属层和IGZO半导体层，所述第二金属层被蚀刻形成源极和漏极；
步骤S3，在所述源极、漏极上形成钝化层，并通过第三道光罩在所述漏极上方形成接触孔；
步骤S4，通过第四道光罩在所述钝化层上形成像素电极，并将像素电极通过接触孔与漏极连接。
其中，所述步骤S2中，所述第二金属层的蚀刻速率与所述IGZO半导体层的蚀刻速率选择比大于20。
其中，所述步骤S2具体包括：
在所述第二金属层上涂布光阻层；
通过第二道光罩对所述光阻层进行曝光显影，投影于所述栅极的光阻被部分去除，形成第一沟道区；
采用双氧水蚀刻液同时蚀刻位于所述栅极两侧的第二金属层和IGZO半导体层；
将第一沟道区的光阻全部去除，形成第二沟道区；
对位于第二沟道区的第二金属层进行蚀刻，分别形成漏极和源极。
其中，所述第二道光罩为半色调光罩。
其中，所述第一沟道区的光阻具体是用氧等离子灰化全部去除。
其中，所述对位于第二沟道区的第二金属层进行蚀刻时，蚀刻至不覆盖其下方的IGZO半导体层时止。
其中，所述步骤S3中，所述钝化层具体是在所述漏极、源极以及未被所述漏极和源极覆盖的IGZO半导体层上沉积形成。
其中，所述步骤S4具体包括：
在所述钝化层上沉积像素电极层；
通过第四道光罩对所述像素电极层进行曝光显影，形成像素电极；
将所述像素电极通过所述接触孔与所述漏极连接。
其中，所述像素电极层具体为氧化铟锡ITO层。
其中，所述IGZO半导体层采用物理气相沉积方式形成。
本发明实施例的有益效果在于：本发明采用双氧水蚀刻液，既可以蚀刻第二金属层，又可以蚀刻IGZO半导体层，第二金属层的蚀刻速率与IGZO半导体层的蚀刻速率选择比大于20，使得第二金属层和IGZO半导体层可以同时进行湿法蚀刻制程，相对于现有技术需要分别进行湿法蚀刻而言，本发明可以缩短制程时间，提高生产效率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例一种IGZO薄膜晶体管制备方法的流程示意图。
图2是本发明实施例中在栅极上依次形成栅极绝缘层、IGZO半导体层和第二金属层的示意图。
图3是本发明实施例中在第二金属层上涂布光阻层的示意图。
图4是本发明实施例中通过第二道光罩对图3中的光阻层进行曝光显影的示意图。
图5是本发明实施例中同时对第二金属层和IGZO半导体层进行蚀刻的示意图。
图6是本发明实施例中去除光阻层的示意图。
图7是本发明实施例中对沟道区烦人第二金属层进行蚀刻的示意图。
图8是本发明实施例中在源极、漏极上形成钝化层的示意图。
图9是本发明实施例中在漏极上方形成接触孔的示意图。
图10是本发明实施例中沉积像素电极层的示意图。
图11是本发明实施例中像素电极通过接触孔与漏极连接的示意图。
具体实施方式
以下各实施例的说明是参考附图，用以示例本发明可以用以实施的特定实施例。
请参照图1所示，本发明实施例提供一种IGZO薄膜晶体管制备方法， 包括：
通过第一道光罩使第一金属层形成栅极，并在所述栅极上依次形成栅极绝缘层、IGZO半导体层和第二金属层；
在所述第二金属层上涂布光阻层，通过第二道光罩对所述光阻层进行曝光显影，再采用双氧水蚀刻液同时蚀刻所述第二金属层和IGZO半导体层，所述第二金属层被蚀刻形成源极和漏极；
在所述源极、漏极上形成钝化层，并通过第三道光罩在所述漏极上方形成接触孔；
在所述钝化层上形成像素电极层，通过第四道光罩对像素电极层进行曝光显影，形成像素电极，并将像素电极通过接触孔与漏极连接。
具体地，请结合图2至图11所示，分别为本实施例IGZO薄膜晶体管制备方法的各步骤示意图。首先，在基板(未图示)上形成第一金属层(未图示)，如图2所示，通过第一道光罩使第一金属层形成栅极1，然后在栅极1上依次沉积形成栅极绝缘层2、IGZO半导体层3和第二金属层4。栅极绝缘层2可以是氧化硅层、氮化硅层、氮氧化硅层中的任一种，IGZO半导体层3可以采用物理气相沉积方式形成。
请参照图3所示，在第二金属层4上涂布光阻层5，然后如图4所示，通过第二道光罩对光阻层5进行曝光显影，投影于栅极1的光阻被部分去除，形成第一沟道区51。其中，第二道光罩具体为半色调光罩(Half Tone Mask，HTM)。
再请参照图5所示，采用双氧水(H 2O 2)蚀刻液同时蚀刻位于栅极1两侧的第二金属层4和IGZO半导体层3，其中第二金属层4的蚀刻速率与IGZO半导体层3的蚀刻速率选择比大于20。再如图6所示，将第一沟道区51的光阻全部去除，形成第二沟道区52，具体地，第一沟道区51的光阻是采用干刻工艺中的用氧等离子灰化全部去除。
然后如图7所示，对去除光阻后位于第二沟道区52的第二金属层4进行蚀刻，分别形成漏极6和源极7。需要说明的是，对位于第二沟道区的第二金属层进行蚀刻时，通过监控蚀刻时间，蚀刻至不覆盖其下方的IGZO半导体层3时止，避免此时对IGZO半导体层3进行蚀刻。
再请参照图8所示，在漏极6和源极7以及未被漏极6和源极7覆盖的IGZO半导体层3上沉积钝化层(Passivation Layer)8，并且如图9所示，通过第三道光罩在漏极6的上方形成接触孔(via hole)80。钝化层8可以是氧化硅层、氮化硅层、氮氧化硅层中的任一种。继续参照图10、图11所示，在钝化层8上沉积像素电极层9，优选为氧化铟锡ITO层，通过第四道光罩对像素电极层9进行曝光显影，形成像素电极90，并将像素电极90通过接触孔80与漏极6连接。
通过上述说明可知，本发明实施例的有益效果在于：本发明采用双氧水蚀刻液，既可以蚀刻第二金属层，又可以蚀刻IGZO半导体层，第二金属层的蚀刻速率与IGZO半导体层的蚀刻速率选择比大于20，使得第二金属层和IGZO半导体层可以同时进行湿法蚀刻制程，相对于现有技术需要分别进行湿法蚀刻而言，本发明可以缩短制程时间，提高生产效率。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (10)

  1. 一种IGZO薄膜晶体管制备方法，包括：
    步骤S1，通过第一道光罩使第一金属层形成栅极，并在所述栅极上依次形成栅极绝缘层、IGZO半导体层和第二金属层；
    步骤S2，在所述第二金属层上涂布光阻层，通过第二道光罩对所述光阻层进行曝光显影，再采用双氧水蚀刻液同时蚀刻所述第二金属层和IGZO半导体层，所述第二金属层被蚀刻形成源极和漏极；
    步骤S3，在所述源极、漏极上形成钝化层，并通过第三道光罩在所述漏极上方形成接触孔；
    步骤S4，通过第四道光罩在所述钝化层上形成像素电极，并将像素电极通过接触孔与漏极连接。
  2. 根据权利要求1所述的制备方法，其特征在于，所述步骤S2中，所述第二金属层的蚀刻速率与所述IGZO半导体层的蚀刻速率选择比大于20。
  3. 根据权利要求2所述的制备方法，其特征在于，所述步骤S2具体包括：
    在所述第二金属层上涂布光阻层；
    通过第二道光罩对所述光阻层进行曝光显影，投影于所述栅极的光阻被部分去除，形成第一沟道区；
    采用双氧水蚀刻液同时蚀刻位于所述栅极两侧的第二金属层和IGZO半导体层；
    将第一沟道区的光阻全部去除，形成第二沟道区；
    对位于第二沟道区的第二金属层进行蚀刻，分别形成漏极和源极。
  4. 根据权利要求3所述的制备方法，其特征在于，所述第二道光罩为半色调光罩。
  5. 根据权利要求3所述的制备方法，其特征在于，所述第一沟道区的光阻具体是用氧等离子灰化全部去除。
  6. 根据权利要求3所述的制备方法，其特征在于，所述对位于第二沟道区的第二金属层进行蚀刻时，蚀刻至不覆盖其下方的IGZO半导体层时止。
  7. 根据权利要求1所述的制备方法，其特征在于，所述步骤S3中，所 述钝化层具体是在所述漏极、源极以及未被所述漏极和源极覆盖的IGZO半导体层上沉积形成。
  8. 根据权利要求1所述的制备方法，其特征在于，所述步骤S4具体包括：
    在所述钝化层上沉积像素电极层；
    通过第四道光罩对所述像素电极层进行曝光显影，形成像素电极；
    将所述像素电极通过所述接触孔与所述漏极连接。
  9. 根据权利要求1所述的制备方法，其特征在于，所述像素电极层具体为氧化铟锡ITO层。
  10. 根据权利要求1所述的制备方法，其特征在于，所述IGZO半导体层采用物理气相沉积方式形成。
PCT/CN2018/071379 2017-12-27 2018-01-04 一种igzo薄膜晶体管制备方法 WO2019127634A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/749,492 US10861883B2 (en) 2017-12-27 2018-01-04 Method of preparing IGZO thin film transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201711444804.0 2017-12-27
CN201711444804.0A CN108183132A (zh) 2017-12-27 2017-12-27 一种igzo薄膜晶体管制备方法

Publications (1)

Publication Number Publication Date
WO2019127634A1 true WO2019127634A1 (zh) 2019-07-04

Family

ID=62547667

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/071379 WO2019127634A1 (zh) 2017-12-27 2018-01-04 一种igzo薄膜晶体管制备方法

Country Status (3)

Country Link
US (1) US10861883B2 (zh)
CN (1) CN108183132A (zh)
WO (1) WO2019127634A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111128876B (zh) * 2019-12-23 2023-11-28 Tcl华星光电技术有限公司 一种阵列基板的制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030107023A1 (en) * 2001-12-06 2003-06-12 Lg.Philips Lcd Co., Ltd. Etchant for etching metal wiring layers and method for forming thin film transistor by using the same
CN102629591A (zh) * 2012-02-28 2012-08-08 京东方科技集团股份有限公司 一种阵列基板的制造方法及阵列基板、显示器
CN102956676A (zh) * 2012-11-02 2013-03-06 京东方科技集团股份有限公司 Tft阵列基板、制备方法及量子点发光二极管显示器件
CN103094204A (zh) * 2011-11-01 2013-05-08 乐金显示有限公司 制造液晶显示装置的阵列基板的方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101325053B1 (ko) * 2007-04-18 2013-11-05 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 이의 제조 방법
KR20080094300A (ko) * 2007-04-19 2008-10-23 삼성전자주식회사 박막 트랜지스터 및 그 제조 방법과 박막 트랜지스터를포함하는 평판 디스플레이
KR101334181B1 (ko) * 2007-04-20 2013-11-28 삼성전자주식회사 선택적으로 결정화된 채널층을 갖는 박막 트랜지스터 및 그제조 방법
KR101345376B1 (ko) * 2007-05-29 2013-12-24 삼성전자주식회사 ＺｎＯ 계 박막 트랜지스터 및 그 제조방법
EP2256814B1 (en) * 2009-05-29 2019-01-16 Semiconductor Energy Laboratory Co, Ltd. Oxide semiconductor device and method for manufacturing the same
KR101213708B1 (ko) * 2009-06-03 2012-12-18 엘지디스플레이 주식회사 어레이 기판 및 이의 제조방법
EP2284891B1 (en) * 2009-08-07 2019-07-24 Semiconductor Energy Laboratory Co, Ltd. Semiconductor device and manufacturing method thereof
KR101624965B1 (ko) * 2009-10-12 2016-05-30 삼성디스플레이 주식회사 박막 트랜지스터 기판의 제조 방법
KR101281463B1 (ko) * 2010-07-06 2013-07-03 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 그를 이용한 액정표시장치
US20130215370A1 (en) * 2010-08-18 2013-08-22 Sharp Kabushiki Kaisha Display device substrate, method for producing the same, and display device
KR20140002616A (ko) * 2010-08-20 2014-01-08 어플라이드 머티어리얼스, 인코포레이티드 수소 미함유 실리콘 함유 유전체막을 형성하기 위한 방법들
KR20120063809A (ko) * 2010-12-08 2012-06-18 삼성전자주식회사 박막 트랜지스터 표시판
KR20120065521A (ko) * 2010-12-13 2012-06-21 삼성전자주식회사 표시 기판 및 이의 제조 방법
US9019440B2 (en) * 2011-01-21 2015-04-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
TWI575577B (zh) * 2011-11-15 2017-03-21 友達光電股份有限公司 畫素結構及畫素結構的製造方法
TWI459477B (zh) * 2011-11-16 2014-11-01 Chunghwa Picture Tubes Ltd 畫素結構及其製作方法
JP2014021170A (ja) * 2012-07-12 2014-02-03 Panasonic Liquid Crystal Display Co Ltd 液晶表示装置及びその製造方法
JP2014109589A (ja) * 2012-11-30 2014-06-12 Panasonic Liquid Crystal Display Co Ltd 表示装置の製造方法
KR102011274B1 (ko) * 2012-12-10 2019-08-19 삼성디스플레이 주식회사 표시 기판의 제조 방법
CN104460143B (zh) * 2013-09-17 2017-12-15 瀚宇彩晶股份有限公司 像素结构及其制造方法
KR102085099B1 (ko) * 2013-10-15 2020-03-05 삼성디스플레이 주식회사 박막 트랜지스터 기판, 표시 장치 및 표시 장치의 제조 방법
CN103715272A (zh) * 2014-01-16 2014-04-09 广州新视界光电科技有限公司 金属氧化物薄膜晶体管及其制备方法
US20160172562A1 (en) * 2014-01-31 2016-06-16 Sharp Laboratories Of America, Inc. Method for forming Circuit-on-Wire
KR20150142139A (ko) * 2014-06-10 2015-12-22 삼성디스플레이 주식회사 박막트랜지스터 어레이 기판 및 그 제조방법
CN104992947B (zh) * 2015-06-03 2018-01-12 合肥鑫晟光电科技有限公司 一种氧化物半导体tft阵列基板及其制备方法
CN105140131A (zh) * 2015-07-15 2015-12-09 京东方科技集团股份有限公司 氧化物薄膜晶体管的制备方法
CN105702586B (zh) * 2016-04-28 2019-06-07 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板、其制作方法及显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030107023A1 (en) * 2001-12-06 2003-06-12 Lg.Philips Lcd Co., Ltd. Etchant for etching metal wiring layers and method for forming thin film transistor by using the same
CN103094204A (zh) * 2011-11-01 2013-05-08 乐金显示有限公司 制造液晶显示装置的阵列基板的方法
CN102629591A (zh) * 2012-02-28 2012-08-08 京东方科技集团股份有限公司 一种阵列基板的制造方法及阵列基板、显示器
CN102956676A (zh) * 2012-11-02 2013-03-06 京东方科技集团股份有限公司 Tft阵列基板、制备方法及量子点发光二极管显示器件

Also Published As

Publication number Publication date
US20200295058A1 (en) 2020-09-17
US10861883B2 (en) 2020-12-08
CN108183132A (zh) 2018-06-19

Similar Documents

Publication Publication Date Title
WO2018170972A1 (zh) 优化4m制程的tft阵列制备方法
WO2018119927A1 (zh) 一种薄膜晶体管的制作方法
WO2017054384A1 (zh) 一种阵列基板及其制作方法、显示面板
US10115832B2 (en) Thin film transistor, method for manufacturing the same, array substrate and display device
WO2017219438A1 (zh) Tft基板的制造方法
US10241371B2 (en) Thin film transistor, method for manufacturing the same, array substrate and display device
US10050151B2 (en) Dual-gate TFT array substrate and manufacturing method thereof, and display device
WO2016070581A1 (zh) 阵列基板制备方法
WO2017133145A1 (zh) 金属氧化物薄膜晶体管及其制造方法
WO2017008333A1 (zh) Tft基板结构的制作方法
WO2018170973A1 (zh) 用于4m制程制备tft的光罩及4m制程tft阵列制备方法
WO2015143745A1 (zh) 一种阵列基板的制造方法
WO2015024350A1 (zh) 显示基板及其制造方法、显示装置
WO2020082623A1 (zh) 薄膜晶体管及其制造方法
WO2016026207A1 (zh) 阵列基板及其制作方法和显示装置
WO2016065780A1 (zh) 显示基板及其制作方法、显示装置
WO2018028304A1 (zh) 显示基板及其制备方法、显示面板
WO2016026177A1 (zh) Tft基板的制作方法及其结构
US11152403B2 (en) Method for manufacturing array substrate, array substrate and display panel
TW201523738A (zh) 薄膜電晶體基板及其製造方法
WO2019127634A1 (zh) 一种igzo薄膜晶体管制备方法
US10510857B2 (en) Thin film transistor, method for manufacturing the same and display device
US10529749B2 (en) Manufacturing method for thin film transistor array substrate
WO2019104849A1 (zh) 薄膜晶体管的制作方法及阵列基板的制作方法
KR20170028429A (ko) 공면형 산화물 반도체 tft 기판의 제작방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18896887

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18896887

Country of ref document: EP

Kind code of ref document: A1