WO2019019658A1 - Structure de transistor en couches minces et son procédé de fabrication, panneau d'affichage et dispositif d'affichage - Google Patents

Structure de transistor en couches minces et son procédé de fabrication, panneau d'affichage et dispositif d'affichage Download PDF

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WO2019019658A1
WO2019019658A1 PCT/CN2018/078869 CN2018078869W WO2019019658A1 WO 2019019658 A1 WO2019019658 A1 WO 2019019658A1 CN 2018078869 W CN2018078869 W CN 2018078869W WO 2019019658 A1 WO2019019658 A1 WO 2019019658A1
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Prior art keywords
thin film
film transistor
insulating layer
forming
isolation barrier
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PCT/CN2018/078869
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English (en)
Chinese (zh)
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胡合合
杨维
卢鑫泓
王珂
温钰
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京东方科技集团股份有限公司
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Priority to US16/302,850 priority Critical patent/US10553621B2/en
Publication of WO2019019658A1 publication Critical patent/WO2019019658A1/fr

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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a thin film transistor structure, a method of fabricating the same, a display panel, and a display device.
  • Thin film transistors as important switching control elements, play a key role in display devices.
  • a thin film transistor structure is generally disposed in a display panel of the display device, and the thin film transistor structure includes two types of thin film transistors, one of which has mobility
  • the advantages of high and fast charging, another thin film transistor has the advantage of low leakage current.
  • a thin film transistor structure is usually provided, and the thin film transistor structure includes a thin film transistor and a second thin film transistor, the first thin film transistor is a low temperature polysilicon thin film transistor, and the second thin film transistor is a metal oxide thin film transistor, and the migration of the first thin film transistor is performed when a display device of the display device of the OLED display panel is provided
  • the advantages of high rate, fast charging, and low leakage current of the second thin film transistor drive the OLED device in the OLED display panel to make the display device have good picture display quality.
  • the active layer of the first thin film transistor is usually doped with hydrogen (for example, low temperature polysilicon).
  • the second thin film transistor is usually a metal oxide thin film transistor, that is, the material of the active layer of the second thin film transistor is a metal oxide, and the metal oxide as an active layer of the second thin film transistor is very sensitive to hydrogen Therefore, when a first thin film transistor having a high mobility and a fast charging advantage and a second thin film transistor having a low leakage current are simultaneously disposed in the display panel, hydrogen in the active layer of the first thin film transistor may diffuse to the first The active layer of the second thin film transistor adversely affects the active layer of the second thin film transistor, thereby adversely affecting the performance of the second thin film transistor.
  • the present disclosure provides a thin film transistor structure including a substrate substrate, and a first thin film transistor and a second thin film transistor formed on the base substrate, wherein the first thin film transistor has a first The source layer is doped with hydrogen; the material of the second active layer of the second thin film transistor is a metal oxide; and the first isolation barrier surrounding the first thin film transistor is further disposed on the substrate. And a second isolation barrier surrounding the second thin film transistor.
  • the second gate insulating layer of the second thin film transistor covers the first thin film transistor, and the first via hole surrounding the second thin film transistor is disposed in the second gate insulating layer.
  • the second isolation barrier fills the first via.
  • the second isolation barrier includes a first portion and a second portion, wherein the first portion is on the base substrate, and the first portion covers the first thin film transistor An insulating layer surrounding an edge and a side of the second thin film transistor; a second gate insulating layer of the second thin film transistor covering the first thin film transistor and the first portion, the second gate insulating a region corresponding to the first portion of the layer is provided with a second via hole surrounding the second thin film transistor, the second portion fills the second via hole, and the second portion and the first portion contact.
  • the first isolation barrier includes a third portion and a fourth portion, wherein the third portion is on the base substrate, and the third portion covers the first thin film transistor An insulating layer surrounding an edge and a side of the first thin film transistor; a second gate insulating layer of the second thin film transistor covering the first thin film transistor and the third portion, the second gate insulating a region corresponding to the third portion is provided with a third via surrounding the first thin film transistor, the fourth portion filling the third via, and the fourth portion and the third portion contact.
  • the first thin film transistor is a low temperature polysilicon thin film transistor
  • the second thin film transistor is a bottom gate thin film transistor
  • the first thin film transistor includes a connection electrode on the second gate insulating layer, and the connection electrode passes through the first connection hole in the second gate insulating layer and the first film a drain of the first source and drain of the transistor is connected, or the connection electrode passes through the second connection hole in the second gate insulating layer and the first source and drain of the first thin film transistor The source is connected.
  • the first isolation retaining wall is an organic material barrier, an inorganic material barrier or a metal barrier
  • the second barrier is an organic material barrier, an inorganic material barrier or a metal Isolation of the retaining wall.
  • the first insulating layer includes a first gate insulating layer of the first thin film transistor and a first interlayer insulating layer covering the first gate of the first thin film transistor.
  • the third portion covering the first insulating layer of the first thin film transistor is formed on the substrate substrate in a region of the first thin film transistor and surrounds an edge of the first thin film transistor
  • the side surface includes: the third portion covering the first gate insulating layer of the first thin film transistor is disposed on the substrate substrate and is formed in a region of the first thin film transistor and surrounds the first thin film transistor a side surface and the third portion of the first interlayer insulating layer covering the first thin film transistor are formed on the base substrate and are formed in a region of the first thin film transistor and surround the first thin film transistor Edge and side.
  • the present disclosure provides a display panel comprising the thin film transistor structure of any of the first aspects.
  • the present disclosure provides a display device comprising the display panel of any of the second aspects.
  • the present disclosure provides a method of fabricating a thin film transistor structure, including:
  • first thin film transistor and a second thin film transistor Forming a first thin film transistor and a second thin film transistor, and a first isolation barrier or/and a second isolation barrier on the base substrate, wherein the first active layer of the first thin film transistor is doped with hydrogen;
  • the material of the second active layer of the second thin film transistor is a metal oxide; the first isolation barrier surrounds the first thin film transistor, and the second isolation barrier surrounds the second thin film transistor.
  • the first thin film transistor is a low temperature polysilicon thin film transistor
  • the second thin film transistor is a bottom gate thin film transistor
  • Forming a first thin film transistor, a second thin film transistor, and a second isolation barrier on the base substrate including:
  • forming the first thin film transistor on the base substrate comprises:
  • first source drain of the first thin film transistor and a second gate of the second thin film transistor, wherein the first source drain includes a first source and a first drain, the first a source is connected to the first active layer through the first connection hole, and the first drain is connected to the first active layer through the second connection hole; On the substrate substrate, in the exposed hole;
  • Forming the second thin film transistor and the second isolation barrier surrounding the second thin film transistor on the base substrate including:
  • the fourth connection hole connects the connection electrode of the first drain.
  • the first thin film transistor is a low temperature polysilicon thin film transistor
  • the second thin film transistor is a bottom gate thin film transistor
  • Forming a first thin film transistor, a second thin film transistor, and a second isolation barrier on the base substrate including:
  • the second portion is located on the first portion, and the second portion surrounds the second portion Thin film transistor.
  • forming the first portion of the first thin film transistor and the second isolation barrier on the base substrate comprises:
  • first source drain of the first thin film transistor, a second gate of the second thin film transistor, and a first portion of the second isolation barrier, wherein the first source drain includes a first source And a first drain, the first source is connected to the first active layer through the first connection hole, and the first drain passes through the second connection hole and the first active layer Connecting; the first portion covers an edge of the exposed hole and a hole wall; the second gate is located on the base substrate, in the exposed hole;
  • Forming the second thin film transistor and the second portion of the second isolation barrier on the base substrate including:
  • connection electrode of the first drain is connected to the pole or through the fourth connection hole.
  • the first thin film transistor is a low temperature polysilicon thin film transistor
  • the second thin film transistor is a bottom gate thin film transistor
  • Forming a first thin film transistor, a second thin film transistor, and a first isolation barrier on the base substrate including:
  • the fourth portion is located on the third portion, and the fourth portion surrounds the first portion Thin film transistor.
  • forming the first thin film transistor and the third portion of the first isolation barrier on the base substrate including:
  • first connection hole and the second connection hole both expose the first active layer
  • first source drain of the first thin film transistor, a second gate of the second thin film transistor, and a third portion of the first isolation barrier, wherein the first source drain includes a first source And a first drain, the first source is connected to the first active layer through the first connection hole, and the first drain passes through the second connection hole and the first active layer Connecting; the third portion covers an edge and a side of the first interlayer insulating layer, and a side of the first gate insulating layer; the second gate is located on the substrate;
  • Forming the second thin film transistor and the fourth portion of the first isolation barrier on the base substrate including:
  • connection electrode of the first drain is connected to the pole or through the fourth connection hole.
  • FIG. 1 is a schematic diagram of a structure of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of another thin film transistor structure according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of still another thin film transistor structure according to an embodiment of the present disclosure.
  • FIG. 4 is a flowchart of a method of fabricating a thin film transistor structure according to an embodiment of the present disclosure
  • FIG. 5 is a flow chart 1 of a specific method of the method for fabricating the thin film transistor structure of FIG. 4;
  • FIG. 6 is a flow chart showing a specific method of the method of fabricating the thin film transistor structure of FIG. 5;
  • FIG. 7 is a process flow diagram of step S100 in Figure 6;
  • step S200 in FIG. 6 is a process flow diagram of step S200 in FIG. 6;
  • FIG. 9 is a second flowchart of a specific method of the method for fabricating the thin film transistor structure of FIG. 4;
  • FIG. 10 is a flow chart showing a specific method of the method of fabricating the thin film transistor structure of FIG. 9;
  • FIG 11 is a process flow diagram of step S300 in Figure 10;
  • FIG 12 is a process flow diagram of step S400 in Figure 10;
  • FIG. 13 is a third flowchart of a specific method of the method for fabricating the thin film transistor structure of FIG. 4;
  • FIG. 14 is a flow chart showing a specific method of the method of fabricating the thin film transistor structure of FIG. 13;
  • FIG. 15 is a process flow diagram of step S500 of Figure 14.
  • FIG. 16 is a process flow diagram of step S600 in FIG.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” and “second” may include at least one of the features, either explicitly or implicitly.
  • the meaning of “a plurality” is two or more unless specifically and specifically defined otherwise.
  • the word “comprising” or “comprises” or the like means that the element or item preceding the word is intended to be in the
  • the words “connected” or “connected” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper”, “lower”, “left”, “right”, etc. are only used to indicate the relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may also change accordingly.
  • a thin film transistor structure provided by an embodiment of the present disclosure includes a base substrate 10 , and a first thin film transistor 20 and a second thin film transistor 30 formed on the base substrate 10 , wherein the first thin film transistor
  • the first active layer 21 of 20 is doped with hydrogen
  • the material of the second active layer 33 of the second thin film transistor 30 is a metal oxide
  • the first substrate 10 is further provided with at least a first surrounding the first thin film transistor 20
  • the first isolation barrier 50 of the active layer 21 and/or the second isolation barrier 40 surrounding the second active layer 33 of the second thin film transistor 30, the first isolation barrier 50 and the second isolation barrier 40 are parallel Provided in the direction of the base substrate 10 between the first active layer 21 and the second active layer 33, preventing hydrogen in the active layer of the first thin film transistor from diffusing to the active layer of the second thin film transistor.
  • the performance of the second thin film transistor causes an adverse effect.
  • the first isolation barrier and the second isolation barrier surround the first thin film transistor and the second, respectively a thin film transistor to space the first thin film transistor and the second thin film transistor in a direction parallel to the substrate, the first isolation barrier 50 and the second isolation barrier 40 being parallel to the lining
  • the direction of the base substrate is between the first and second thin film transistors.
  • the thin film transistor structure provided in the embodiment of the present disclosure includes a substrate substrate 10 , a first thin film transistor 20 , and a second thin film transistor 30 having a first region on the substrate substrate 10 . 11 and the second region 12, the first thin film transistor 20 is formed in the first region 11 on the base substrate 10, and the second thin film transistor 30 is formed in the second region 12 on the base substrate 10; the first thin film transistor 20
  • the first active layer 21 is doped with hydrogen.
  • the first thin film transistor 20 may be an amorphous silicon thin film transistor, a single crystal silicon thin film transistor, or a polycrystalline silicon thin film transistor (such as a low temperature polysilicon thin film transistor).
  • the second thin film transistor 30 is a metal oxide thin film transistor, that is, the material of the second active layer 33 of the second thin film transistor 30 is a metal oxide, for example, a material of the second active layer 33 of the second thin film transistor 30. It may be Indium Gallium Zinc Oxide (IGZO).
  • IGZO Indium Gallium Zinc Oxide
  • a first isolation barrier 50 or/and a second isolation barrier 40 are further disposed on the base substrate 10.
  • the base substrate 10 is provided with a second isolation barrier 40, and a second The isolation barrier 40 is disposed around the second thin film transistor 30.
  • the second isolation barrier 40 may be located on the edge of the second region 12 or the second region 12 on the base substrate 10 to surround the second thin film transistor 30 on the substrate. 10 in the second region 12, and the second thin film transistor 30 is isolated from the first thin film transistor 20; or, referring to FIG.
  • the substrate substrate 10 is provided with a first isolation barrier 50, the first isolation barrier 50 is disposed around the first thin film transistor 20, and the first isolation barrier 50 may be located on the edge of the first region 11 or the first region 11 on the base substrate 10 to surround the first thin film transistor 20 on the base substrate 10.
  • the second thin film transistor 30 is isolated from the first thin film transistor 20; or, in practical applications, the first isolation barrier 50 and the second isolation barrier 40 may be simultaneously disposed on the substrate 10 .
  • the first isolation barrier 50 is disposed around the first thin film transistor 20 to be first
  • the film transistor 20 is disposed in the first region 11 on the base substrate 10
  • the second isolation barrier 40 is disposed around the second thin film transistor 30 to surround the second thin film transistor 30 in the second region 12 on the base substrate 10.
  • the first isolation barrier 50 and the second isolation barrier 40 cooperate to isolate the second thin film transistor 30 from the first thin film transistor 20.
  • the second isolation barrier 40 surrounding the second thin film transistor 30 or/and the first isolation surrounding the first thin film transistor 20 are disposed on the base substrate 10.
  • the second insulating film 40 surrounds the second thin film transistor 30 in a region where the second thin film transistor 30 is disposed on the base substrate 10, and the first isolation barrier 50 surrounds the first thin film transistor 20 on the base substrate.
  • the second isolation barrier 40 or/and the first isolation barrier 50 may be disposed first Hydrogen isolation in the first active layer 21 of the thin film transistor 20 prevents hydrogen in the first active layer 21 of the first thin film transistor 20 from diffusing into the second thin film transistor 30, for example, preventing the first thin film transistor 20 Hydrogen in an active layer 21 diffuses into the second active layer 33 of the second thin film transistor 30, so that hydrogen in the first active layer 21 of the first thin film transistor 20 can be prevented from causing damage to the second thin film transistor 30.
  • Influence for example, prevention Hydrogen in the first active layer 21 of the first thin film transistor 20 adversely affects the second active layer 33 of the second thin film transistor 30, thereby preventing hydrogen in the first active layer 21 of the first thin film transistor 20
  • the performance of the second thin film transistor 30 causes an adverse effect.
  • the second isolation barrier 40 surrounding the second thin film transistor 30 or/and the first isolation barrier surrounding the first thin film transistor 20 are disposed on the base substrate 10 . 50.
  • the second isolation barrier 40 surrounds the second thin film transistor 30 in a region where the second thin film transistor 30 is disposed on the base substrate 10.
  • the first isolation barrier 50 surrounds the first thin film transistor 20 on the base substrate 10.
  • the region of the first thin film transistor 20 is disposed to isolate the second thin film transistor 30 from the first thin film transistor 20, and thus, the process of manufacturing the second thin film transistor 30 can be expanded when the thin film transistor structure provided by the embodiment of the present disclosure is fabricated.
  • the window reduces the difficulty of fabricating a thin film transistor structure.
  • the second isolation barrier 40 surrounding the second thin film transistor 30 or/and the first isolation barrier surrounding the first thin film transistor 20 are disposed on the base substrate 10.
  • the wall 50, the second isolation barrier 40 surrounds the second thin film transistor 30 in a region where the second thin film transistor 30 is disposed on the base substrate 10, and the first isolation barrier 50 surrounds the first thin film transistor 20 around the base substrate 10.
  • the region of the first thin film transistor 20 is disposed to isolate the second thin film transistor 30 from the first thin film transistor 20, preventing the hydrogen in the first active layer 21 of the first thin film transistor 20 from acting on the second thin film transistor 30.
  • the adverse effect is caused, and therefore, the characteristics and stability of the second thin film transistor 30 can be improved, thereby improving the picture display quality of the display device to which the thin film transistor structure provided by the embodiment of the present disclosure is applied.
  • first isolation barrier 50 may be disposed on the base substrate 10, or only the second isolation barrier 40 may be disposed on the base substrate 10, or the first substrate 10 may be simultaneously disposed on the base substrate 10.
  • the second gate of the second thin film transistor 30 covers the first thin film transistor 20, the first via hole surrounding the second thin film transistor 30 is disposed in the second gate insulating layer 32, and the second isolation barrier 40 fills the first via hole.
  • the first thin film transistor 20 is located in the first region 11 on the base substrate 10
  • the second thin film transistor 30 is located in the second region 12 on the base substrate 10
  • the second thin film transistor 30 includes
  • the second gate insulating layer 32 covers the first thin film transistor 20, and the second gate insulating layer 32 is provided with a first via surrounding the second thin film transistor 30, that is, the first via is annular
  • the first via hole may be located in the second region 12 or the edge of the second region 12, and the second isolation barrier wall 40 as a whole structure fills the first via hole, and the second isolation barrier wall 40 is in contact with the substrate substrate 10,
  • the second thin film transistor 30 is surrounded by the second thin film transistor 30 to isolate the second thin film transistor 30 from the first thin film transistor 20.
  • the second isolation retaining wall 40 can also be divided into multiple parts.
  • the second isolation retaining wall 40 can include a first portion 41 and a second portion 42, wherein the first portion 41 is located on the base substrate 10, and the first portion 41 covers the edge and the side of the first insulating layer of the first thin film transistor 20 surrounding the second thin film transistor 30; the second gate insulating layer 32 of the second thin film transistor 30 is covered
  • the first thin film transistor 20 and the first portion 41, the second gate insulating layer 32 is provided with a second via hole surrounding the second thin film transistor 30, and the second portion 42 is filled with the second via hole.
  • the second portion 42 is in contact with the first portion 41.
  • the first insulating layer of the first thin film transistor 20 and the second substrate 12 on the base substrate 10 corresponding to the second region 12 of the second thin film transistor 30 have exposed holes, and the exposed holes expose the lining.
  • the bottom substrate 10, the second thin film transistor 30 is located in the exposed hole of the base substrate 10, the first portion 41 of the second isolation retaining wall 40 is located on the base substrate 10, and the first portion 41 covers the edge of the exposed hole and the wall of the hole. That is, the first portion 41 covers the edge and the side of the first thin film transistor 30, and when the first thin film transistor 20 is a bottom gate thin film transistor or a top gate thin film transistor, the first thin film transistor 20 includes the first thin film.
  • the first insulating layer may include the first gate insulating layer of the first thin film transistor 20, or, please continue to refer to 2, when the first thin film transistor 20 is a low temperature polysilicon thin film transistor, the first thin film transistor 20 includes a first gate insulating layer 22 between the first active layer 21 and the first gate 23 of the first thin film transistor 20. And located at a first interlayer insulating layer 24 between the first gate 23 of the thin film transistor 20 and the first source drain (including the first source 25 and the first drain 26). At this time, the first insulating layer may include The first gate insulating layer 22 of the first thin film transistor 20 and the first interlayer insulating layer 24.
  • the second thin film transistor 30 includes a second gate insulating layer 32 covering the first thin film transistor 20 and the first portion 41, and the second gate insulating layer 32 is provided with a region corresponding to the first portion 41.
  • the second via Surrounding the second via of the second thin film transistor 30, the second via is annular, and the second portion 42 of the second isolation barrier 40 fills the second via and is in contact with the first portion 41, the first portion 41 and the second portion
  • the portions 42 collectively form a second isolation barrier 40 surrounding the second thin film transistor 30, surrounding the second thin film transistor 30, and isolating the second thin film transistor 30 from the first thin film transistor 20.
  • the second isolation barrier 40 is disposed as a first portion 41 and a second portion 42 , the first portion 41 is located on the base substrate 10 , and the first portion 41 covers the second insulating layer of the first thin film transistor 20 The edge and the side of the thin film transistor 30, therefore, the first portion 41 can isolate the first insulating layer of the first thin film transistor 20 from the second thin film transistor 30 to prevent the first thin film transistor 20 from being present in the first insulating layer The hydrogen diffuses into the second thin film transistor 30.
  • the first insulating layer includes the first gate insulating layer 22 and the first interlayer insulating layer 24, and the second isolation block
  • the first portion 41 of the wall 40 can separate the first gate insulating layer 22 and the first interlayer insulating layer 24 from the second thin film transistor 30, and may exist between the first gate insulating layer 22 and the first layer. Hydrogen in the insulating layer 24 diffuses to the second thin film transistor 30.
  • the arrangement of the first isolation barrier 50 can be set according to actual needs.
  • the first isolation barrier 50 includes a third portion 51 and a fourth portion 52, wherein The third portion 51 is disposed on the base substrate 10, and the third portion 51 covers the first insulating layer of the first thin film transistor 20 in the region of the base substrate 10 where the first thin film transistor 20 is formed, and surrounds the first thin film transistor 20.
  • the second gate insulating layer 32 of the second thin film transistor 30 covers the first thin film transistor 20 and the third portion 51, and the second gate insulating layer 32 is provided with a surrounding area corresponding to the third portion 51.
  • the third via of the thin film transistor 20, the fourth portion 52 fills the third via, and the fourth portion 52 is in contact with the third portion 51.
  • the first insulating layer of the first thin film transistor 20 is located on the base substrate 10 to form the first region 11 of the first thin film transistor 20, and the side of the first insulating layer is located in the first region. 11 , it should be noted that the side of the first insulating layer is located in the first region 11 .
  • the side of the first insulating layer is located at the edge or inside of the first region 11 , and the side of the first insulating layer surrounds the first The thin film transistor 20, the third portion 51 of the first isolation barrier 50 is located on the base substrate 10, and the third portion 51 covers the edge and the side of the first insulating layer, that is, the third portion 51 surrounds the first thin film transistor 20;
  • the first thin film transistor 20 is a bottom gate thin film transistor or a top gate thin film transistor
  • the first thin film transistor 20 includes a first gate insulating layer between the first gate of the first thin film transistor and the first active layer.
  • the first insulating layer may include the first gate insulating layer of the first thin film transistor 20; or, referring to FIG.
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor, and the first thin film transistor 20 includes the first thin film.
  • crystal a first gate insulating layer 22 between the first active layer 21 and the first gate 23 of the tube 20, and a first gate 23 and a first source drain (including the first source) of the first thin film transistor 20 a first interlayer insulating layer 24 between the pole 25 and the first drain 26).
  • the first insulating layer may include the first gate insulating layer 22 of the first thin film transistor 20 and the first interlayer insulating layer 24 .
  • the second thin film transistor 30 includes a second gate insulating layer 32 covering the first thin film transistor 20 and the third portion 51, and the second gate insulating layer 32 is provided with a region corresponding to the third portion 51.
  • the third via Surrounding the third via of the first thin film transistor 30, the third via is annular, and the fourth portion 52 of the first isolation barrier 50 fills the third via and contacts the third portion 51, the third portion 51 and the fourth portion
  • the portions 52 collectively form a first isolation barrier 50 surrounding the first thin film transistor 20, surrounding the first thin film transistor 20, and isolating the first thin film transistor 20 from the second thin film transistor 30.
  • the first isolation barrier 50 is disposed as a third portion 51 and a fourth portion 52, the third portion 51 is located on the base substrate 10, and the third portion 51 covers the first insulating layer of the first thin film transistor 20 at the first
  • the region 11 surrounds the edge and the side of the first thin film transistor 20, and therefore, the third portion 51 can isolate the first insulating layer of the first thin film transistor 20 from the second thin film transistor 30 to prevent possible in the first thin film transistor 20.
  • Hydrogen present in the first insulating layer diffuses into the second thin film transistor 30.
  • the first insulating layer includes the first gate insulating layer 22 and the first interlayer insulating layer.
  • the second portion 51 of the first isolation barrier 50 can isolate the first gate insulating layer 22 and the first interlayer insulating layer 24 from the second thin film transistor 30 to prevent possible presence of the first gate insulating layer.
  • the hydrogen in the layer 22 and the first interlayer insulating layer 24 is diffused to the second thin film transistor 30.
  • the first isolation barrier 50 when the first isolation barrier 50 and the second isolation barrier 40 are simultaneously disposed on the base substrate 10, the first isolation barrier 50 may adopt the third portion 51 and the fourth portion 52.
  • the second isolation barrier 40 can be disposed in an integrated manner, that is, the second isolation barrier 40 fills the first via formed in the second gate insulating layer 32 and surrounds the first via of the second thin film transistor 30.
  • the setting is made, that is, the first isolation retaining wall 50 can be disposed in the manner shown in FIG. 3, and the second insulating retaining wall 40 can be disposed in the manner shown in FIG.
  • the type of the first thin film transistor 20 can be selected according to actual needs.
  • the first thin film transistor 20 can be an amorphous silicon thin film transistor, a single crystal silicon thin film transistor, a polycrystalline silicon thin film transistor, etc., implemented in the present disclosure.
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor. Referring to FIG. 1 or FIG.
  • the first thin film transistor 20 includes a first active layer 21 , a first gate insulating layer 22 , a first gate 23 , a first interlayer insulating layer 24, a first source and a drain, wherein the first active layer 21 is on the base substrate 10; the first gate insulating layer 22 covers the base substrate 10, the first active layer 21, A gate insulating layer 22 and a region of the base substrate 10 corresponding to a region where the second thin film transistor 30 is formed have a first exposed hole exposing the base substrate 10; the first gate 23 is located on the first gate insulating layer 22.
  • the first gate 23 is located above the first active layer 21; the first interlayer insulating layer 24 covers the first gate 23 and the first gate insulating layer 22, the first interlayer insulating layer 24 and the first gate The area corresponding to the first exposed hole in the insulating layer 22 is exposed a second exposed hole of the base substrate 10; the first active layer 21 further has a first connection hole and a second connection hole penetrating the first interlayer insulating layer 24 and the first gate insulating layer 22, the first connection hole And the second connection hole exposing the first active layer 21; the first source drain is located on the first interlayer insulating layer 24, the first source drain comprises a first source 25 and a first drain 26, first The source electrode 25 is connected to the first active layer 21 through the first connection hole, and the first drain electrode 26 is connected to the first active layer 21 through the second connection hole; or, referring to FIG.
  • the first thin film transistor 20 includes a first active layer 21, a first gate insulating layer 22, a first gate 23, a first interlayer insulating layer 24, and a first source drain, wherein the first active layer 21 is located on the base substrate 10.
  • the first gate insulating layer 22 covers the first active layer 21 and the base substrate 10 located in the first region 11; the first gate 23 is located on the first gate insulating layer 22, and A gate electrode 23 is disposed above the first active layer 21; a first interlayer insulating layer 24 covers the first gate electrode 23 and the first gate insulating layer 22;
  • the first connection hole and the second connection hole of the interlayer insulating layer 24 and the first gate insulating layer 22, the first connection hole and the second connection hole both expose the first active layer 21;
  • the first source and drain electrodes are located at On the interlayer insulating layer 24, the first source drain includes a first source 25 and a first drain 26.
  • the first source 25 is connected to the first active layer 21 through the first connection hole, and the first drain 26
  • the type of the second thin film transistor 30 can be selected according to actual needs.
  • the second thin film transistor 30 can be a bottom gate thin film transistor, a top gate thin film transistor, etc., in the embodiment of the present disclosure, please continue to refer to 1 or 2, the second thin film transistor 30 is a bottom gate thin film transistor, and the second thin film transistor 30 includes a second gate 31, a second gate insulating layer 32, a second active layer 33, and a second source drain.
  • the second gate 31 is disposed on the base substrate 10; the second gate insulating layer 32 covers the second gate 31, the base substrate 10, and the first thin film transistor 20; the second active layer 33 is located at the second gate On the insulating layer 32, the second active layer 33 is located above the second gate 31, and the material of the second active layer 33 may be Indium Gallium Zinc Oxide (IGZO); the second source drain Located on the second active layer 33, the second source drain includes a second source 34 and a second drain 35, and the second source 34 and the second drain 35 are in contact with the second active layer 33, respectively.
  • IGZO Indium Gallium Zinc Oxide
  • the second thin film transistor 30 may be formed in the first exposed hole and the second exposed hole.
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor
  • the second thin film transistor 30 is a bottom gate thin film transistor
  • the first via hole surrounding the second thin film transistor 30 is formed in the second gate insulating layer 32.
  • the first via exposes the base substrate 10, and the second isolation barrier 40 is filled in the first via to isolate the second thin film transistor 30 from the first thin film transistor 20;
  • the first thin film transistor 20 further includes a connection electrode 27 a region of the second gate insulating layer 32 corresponding to the first source electrode 25 has a third connection hole.
  • the connection electrode 27 is connected to the first source electrode 25 through the third connection hole, or the second gate insulating layer
  • the region corresponding to the first drain 26 has a fourth connection hole.
  • the connection electrode 27 is connected to the first drain 26 through the fourth connection hole to facilitate the first source 25 or the first of the first thin film transistor 20.
  • a drain 26 is connected to other structures.
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor
  • the second thin film transistor 30 is a bottom gate thin film transistor
  • the second isolation barrier 40 includes a first portion 41 and a second portion 42 covered by the first portion 41.
  • the first thin film transistor 20 further includes a connection The electrode 27, the region corresponding to the first source electrode 25 of the second gate insulating layer 32 has a third connection hole, and at this time, the connection electrode 27 is connected to the first source 25 through the third connection hole, or the second gate
  • the insulating layer 32 corresponds to the first drain 26
  • the domain has a fourth connection hole. At this time, the connection electrode 27 is connected to the
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor
  • the second thin film transistor 30 is a bottom gate thin film transistor.
  • the first isolation barrier 50 includes a third portion 51 and a fourth portion 52, and the third portion 51 covers The first interlayer insulating layer 24 of the first thin film transistor 20 is located in the first region 11 , surrounds the edge and the side surface of the first thin film transistor 20 , and the first gate insulating layer 22 of the first thin film transistor 20 surrounds the first thin film a side surface of the transistor 20; a second via hole is disposed in a region corresponding to the third portion 51 of the second gate insulating layer 32, and the third via hole surrounds the first thin film transistor 20, and the fourth portion 52 of the first isolation barrier 50 is filled a third via hole is in contact with the third portion 51, and the third portion 51 and the fourth portion 52 collectively surround the first thin film transistor 20 to isolate the first thin film transistor 20 from the second thin film transistor 30; likewise, A thin film transistor 20 further includes a connection electrode
  • connection electrode 27 is connected to the first source 25 through the third connection hole.
  • the second gate insulating layer 32 and A region corresponding to the drain 26 has a fourth connection hole.
  • the connection electrode 27 is connected to the first drain 26 through the fourth connection hole to facilitate the first source 25 or the first drain of the first thin film transistor 20. 26 is connected to other structures.
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor
  • the second thin film transistor 30 is a bottom gate thin film transistor
  • the second thin film transistor 30 is a second gate insulating layer 32.
  • the first thin film transistor 20 is covered. Therefore, when the thin film transistor structure provided by the embodiment of the present disclosure is fabricated, the first thin film transistor 20 may be formed on the base substrate 10, and then the second thin film transistor 30 may be formed on the base substrate 10.
  • the second gate insulating layer 32 is formed before the second active layer 33, that is, the second gate insulating layer 32 is formed first, and the second gate insulating layer 32 is used to form the base substrate. 10.
  • the second gate electrode 31 and the first thin film transistor 20 are completely covered, and then the second active layer 33 is formed.
  • the second active layer 33 is formed in the process of forming the second active layer 33, for example, in forming the second active layer 33.
  • the second gate insulating layer 32 may block diffusion of hydrogen in the first active layer 21 of the first thin film transistor 20 toward the second active layer 33, thereby preventing the second thin film transistor 30 from being formed. Performance adversely affects .
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor
  • the second thin film transistor 30 is a bottom gate thin film transistor
  • the second gate insulating layer 32 of the second thin film transistor 30 covers the first thin film transistor 20, and thus, when manufacturing the present disclosure
  • the first thin film transistor 20 may be formed on the base substrate 10
  • the second thin film transistor 30 may be formed on the base substrate 10
  • the second The gate insulating layer 32 is formed prior to the second active layer 33, that is, the second gate insulating layer 32 is formed first
  • the second gate insulating layer 32 places the base substrate 10, the second gate 31, and the first thin film transistor 20.
  • the second active layer 33 is completely covered, and then the process of forming the first active layer 21 of the first thin film transistor 20 and the process of forming the second active layer 33 of the second thin film transistor 30 can be prevented from interfering with each other. .
  • the material of the first isolation retaining wall 50 and the material of the second insulating retaining wall 40 may be various, and the material of the first insulating retaining wall 50 and the material of the second insulating retaining wall 40 only need to have Better hydrogen resistance can be achieved.
  • the material of the first isolation barrier 50 may be an organic material, that is, the first isolation barrier 50 is an organic material first isolation barrier 50, for example, the organic material may be polyethylene (PE); or
  • the material of the first isolation barrier 50 may be an inorganic material, that is, the first isolation barrier 50 is an inorganic material first isolation barrier 50.
  • the inorganic material may be aluminum oxide (Al 2 O 3 ), silicon nitride (SiNx), or the like;
  • the material of the first isolation barrier 50 may be metal, that is, the first isolation barrier 50 is a metal first isolation barrier 50.
  • the first isolation barrier 50 includes a third portion 51.
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor
  • the second thin film transistor 30 is a bottom gate thin film transistor.
  • the first region 11 is first formed in the first region 11 on the substrate substrate 10.
  • the thin film transistor 20 can simultaneously form the third portion 51 of the first isolation barrier 50, that is, the first isolation, when forming the first source and the drain of the first thin film transistor 20, that is, the first source 25 and the first drain 26.
  • the third portion 51 of the retaining wall 50 and the first thin film transistor 2 The first source and drain electrodes of 0 are simultaneously formed.
  • the third portion 51 of the first isolation barrier 50 and the first source and drain of the first thin film transistor 20 are formed by one patterning process, and the first isolation barrier 50 is The material of the third portion 51 is the same as the material of the first source and drain of the first thin film transistor 20, and then the second thin film transistor 30 is formed in the second region 12 on the base substrate 10, and the second thin film transistor 30 is formed.
  • a third via surrounding the first thin film transistor 20 is formed in the second gate insulating layer 32 of the second thin film transistor 30, and a second via is formed.
  • the fourth portion 52 of the first isolation barrier 50 that is, the fourth portion 52 of the first isolation barrier 50 can be simultaneously formed.
  • the fourth portion 52 of the first isolation barrier 50 and the second source and drain of the second thin film transistor 30 are formed by one patterning process, first The material of the fourth portion 52 of the isolation barrier 50 and the second source and drain of the second thin film transistor 30 The same material.
  • the material of the second isolation retaining wall 40 may be an organic material, that is, the second insulating retaining wall 40 is a second insulating retaining wall 40 of organic material, for example, the organic material may be polyethylene (PE); or
  • the material of the second isolation retaining wall 40 may be an inorganic material, that is, the second insulating retaining wall 40 is a second insulating retaining wall 40 of inorganic material.
  • the inorganic material may be aluminum oxide (Al 2 O 3 ), silicon nitride (SiNx), or the like;
  • the material of the second isolation retaining wall 40 may be metal, that is, the second insulating retaining wall 40 is a metal second insulating retaining wall 40.
  • the structure of the second insulating retaining wall 40 is a whole.
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor
  • the second thin film transistor 30 is a bottom gate thin film transistor.
  • the first thin film transistor 20 is first formed in the first region 11 on the base substrate 10.
  • a second thin film transistor 30 in the second region 12 on the base substrate 10, wherein before forming the second source drain of the second thin film transistor 30, that is, the second source 34 and the second drain 35, Second thin film transistor 30 A first via surrounding the second thin film transistor 30 is formed in the gate insulating layer 32.
  • the first via can be simultaneously formed.
  • the second isolation barrier 40 that is, the second isolation barrier 40 is formed simultaneously with the second source and drain of the second thin film transistor 30, and can also be understood as the second isolation drain 40 and the second source and drain of the second thin film transistor 30.
  • the material of the second isolation barrier 40 is the same as the material of the second source and drain of the second thin film transistor 30; please continue to refer to FIG. 2, the structure of the second isolation barrier 40 includes the first portion 41 and In the second portion 42, the first thin film transistor 20 is a low temperature polysilicon thin film transistor, and the second thin film transistor 30 is a bottom gate thin film transistor.
  • a first thin film is first formed in the first region 11 on the base substrate 10.
  • the transistor 20 can simultaneously form the first portion 41 of the second isolation retaining wall 40, that is, the second isolation block, when the first source drain 25 and the first drain electrode 26 of the first thin film transistor 20 are formed.
  • the first portion 41 of the wall 40 and the first thin film transistor 2 The first source and drain electrodes of 0 are simultaneously formed. It can also be understood that the first portion 41 of the second isolation barrier 40 and the first source and drain of the first thin film transistor 20 are formed by one patterning process, and the second isolation barrier 40 is formed.
  • the material of the first portion 41 is the same as the material of the first source and drain of the first thin film transistor 20, and then the second thin film transistor 30 is formed in the second region 12 on the base substrate 10, and the second thin film transistor 30 is formed.
  • a second via surrounding the second thin film transistor 30 is formed in the second gate insulating layer 32 of the second thin film transistor 30, and a second via is formed.
  • the second portion 42 of the second isolation barrier 40 and the second source and drain of the second thin film transistor 30 are formed by one patterning process, and the second The material of the second portion 42 of the isolation barrier 40 and the second source and drain of the second thin film transistor 30 The same material.
  • the embodiment of the present disclosure further provides a display panel including the thin film transistor structure as described in the above embodiments.
  • the display panel may be a liquid crystal display panel or an organic light emitting diode display panel
  • the display panel includes a plurality of pixel units, each of which is provided with the above thin film transistor structure, by at least surrounding the first or second thin film transistor
  • An isolation barrier of the active layer for example, an isolation barrier surrounding the first and/or second thin film transistors, can prevent hydrogen in the first thin film transistor in the same pixel unit from being in the first thin film transistor to the second transistor influences.
  • An embodiment of the present disclosure further provides a display device including the display panel as described in the above embodiments.
  • an embodiment of the present disclosure further provides a method for fabricating a thin film transistor structure according to the above embodiments, including:
  • first thin film transistor and a second thin film transistor Forming a first thin film transistor and a second thin film transistor, and a first isolation barrier or/and a second isolation barrier on the base substrate, wherein the first active layer of the first thin film transistor is doped with hydrogen;
  • the material of the second active layer of the thin film transistor is a metal oxide;
  • the first isolation barrier surrounds at least the first active layer of the first thin film transistor, and the second isolation barrier surrounds at least the second thin film transistor Two active layers.
  • the manufacturing method includes: step S1, forming a first thin film transistor and a second thin film transistor on a base substrate, and a first isolation barrier or/and a second isolation barrier, wherein the first thin film transistor
  • the first active layer is doped with hydrogen
  • the second active layer of the second thin film transistor is made of a metal oxide
  • the first isolation barrier surrounds at least the first active layer of the first thin film transistor
  • the second isolation The retaining wall surrounds at least the second active layer of the second thin film transistor.
  • the first thin film transistor is a low temperature polysilicon thin film transistor
  • the second thin film transistor is a bottom gate thin film transistor
  • Step S100 forming a first thin film transistor on the base substrate.
  • Step S200 forming a second thin film transistor and a second isolation barrier surrounding the second thin film transistor on the base substrate.
  • step S100 forming a first thin film transistor on the substrate, may include:
  • Step S110 forming a first active layer of the first thin film transistor.
  • step S110 a polysilicon layer is deposited on the base substrate 10, the polysilicon layer is a low temperature polysilicon layer, and the low temperature polysilicon layer is doped with hydrogen; and then formed by a patterning process.
  • the first active layer 21 of the first thin film transistor 20, the first active layer 21 is located on the base substrate 10 to form the first region 11 of the first thin film transistor 20.
  • Step S120 forming a first gate insulating layer of the first thin film transistor.
  • a first gate insulating film layer is deposited on the base substrate 10 and the first active layer 21 to form a first gate insulating layer 22, first.
  • the gate insulating layer 22 covers the base substrate 10 and the first active layer 21.
  • Step S130 forming a first gate of the first thin film transistor.
  • step S130 a first metal layer is first deposited on the first gate insulating layer 22; then, a first gate of the first thin film transistor 20 is formed by a patterning process. 23, the first gate 23 is located in the first region 11 of the base substrate 10 above the first active layer 21.
  • Step S140 forming a first interlayer insulating layer of the first thin film transistor.
  • step S140 a first interlayer insulating film layer is deposited on the first gate insulating layer 22 and the first gate electrode 23 to form a first interlayer insulating layer 24.
  • the first interlayer insulating layer 24 covers the first gate insulating layer 22 and the first gate electrode 23.
  • Step S150 forming an exposed hole, a first connection hole and a second connection hole penetrating through the first interlayer insulating layer and the first gate insulating layer, the exposed hole exposing a region on the substrate substrate where the second thin film transistor is formed, first Both the connection hole and the second connection hole expose the first active layer.
  • step S150 the exposure hole 241, the first connection hole 242 and the second connection hole 243 are formed by a patterning process, wherein the exposure hole 241 penetrates the first interlayer insulation layer. And a first gate insulating layer 22, and exposing a region of the base substrate 10 on which the second thin film transistor 30 is formed to facilitate subsequent formation of the second thin film transistor 30 on the base substrate 10; the first connection hole 242 and the The two connection holes 243 respectively penetrate the first interlayer insulating layer 24 and the first gate insulating layer 22, and both expose the first active layer 21 to facilitate the formation of the first source and drain of the first source and the source 15 and The first drain 26 is connected to the first active layer 21, respectively.
  • Step S160 forming a first source drain of the first thin film transistor and a second gate of the second thin film transistor, wherein the first source drain includes a first source and a first drain, and the first source passes the first
  • the connection hole is connected to the first active layer
  • the first drain is connected to the first active layer through the second connection hole
  • the second gate is located on the substrate substrate and exposed in the hole.
  • step S160 a second metal layer is first deposited; then, a first source drain of the first thin film transistor 20 and a second thin film transistor 30 are simultaneously formed by a patterning process. a second gate 31, wherein the first source 25 of the first source and drain is connected to the first active layer 21 through the first connection hole 242, and the first drain 26 passes through the second connection hole 243 and the first active layer 21 is connected; the second gate 31 is located on the base substrate 10 and exposed in the hole 241.
  • the first source drain of the first thin film transistor 20 and the second gate 31 of the second thin film transistor 30 are formed by one patterning process, thereby reducing the number of process steps for fabricating the thin film transistor structure while reducing the fabrication of the thin film transistor The number of masks used in the structure, which in turn reduces the cost of fabricating the thin film transistor structure.
  • step S200 forming a second thin film transistor on the substrate and a second isolation barrier surrounding the second thin film transistor may include:
  • Step S210 forming a second gate insulating layer of the second thin film transistor.
  • step S210 a second gate insulating film layer is deposited to form a second gate insulating layer 32, and the second gate insulating layer 32 covers the first thin film transistor 20 and the lining.
  • Step S220 forming a second active layer of the second thin film transistor.
  • a metal oxide film layer may be deposited on the second gate insulating layer 32; then, a second thin film transistor 30 is formed by a patterning process.
  • the source layer 33 and the second active layer 33 are located above the second gate 31.
  • Step S230 forming a first via hole surrounding the second thin film transistor and exposing the base substrate in the second gate insulating layer, and a third connection hole corresponding to the first source of the first thin film transistor or corresponding to the first a fourth connection hole of the first drain of the thin film transistor.
  • a first via hole 321 is formed in the second gate insulating layer 32 by a patterning process, and the first via hole 321 surrounds the second thin film transistor 30, A via 321 exposes the base substrate 10 to subsequently form a second isolation barrier 40 surrounding the second thin film transistor 30.
  • a third connection hole is formed in the second gate insulating layer 32 by a patterning process, and the third connection hole corresponds to the first source of the first thin film transistor 20 .
  • a fourth connection hole may be formed in the second gate insulating layer 32 by a patterning process. 324.
  • the fourth connection hole 324 corresponds to the first drain electrode 26 of the first thin film transistor 20 to facilitate connecting the first drain electrode 26 and other structures through the subsequently formed connection electrode 27.
  • Step S240 forming a second source and drain of the second thin film transistor, filling a second isolation barrier in the first via hole, and connecting the first source through the third connection hole or connecting the first drain through the fourth connection hole
  • the pole is connected to the electrode.
  • a third metal layer is deposited first; then, a second isolation barrier 40, a second source drain of the second thin film transistor 30, and a second isolation gate are simultaneously formed by a patterning process.
  • the pole includes a second source 34 and a second drain 35.
  • the second source 34 and the second drain 35 are respectively in contact with the second active layer 33; the connection electrode 27 is located on the second gate insulating layer 32, and the connection electrode 27 is connected to the first source 25 through a third connection hole, or the connection electrode 27 is connected to the first drain 26 through the fourth connection hole 324. That is, the second isolation barrier 40, the second source drain, and the connection electrode 27 are formed by one patterning process, thereby reducing the number of process steps for fabricating the thin film transistor structure while reducing the mask used in fabricating the thin film transistor structure. The number of plates, which in turn reduces the cost of fabricating thin film transistor structures.
  • the first thin film transistor is a low temperature polysilicon thin film transistor
  • the second thin film transistor is a bottom gate thin film transistor
  • the second isolation barrier includes a plurality of portions, for example, the second isolation barrier includes a first portion and a second portion, that is, a second isolation barrier
  • Step S1 forming a first thin film transistor, a second thin film transistor, and a second isolation barrier on the substrate, which may include:
  • Step S300 forming a first portion of the first thin film transistor and the second isolation barrier on the base substrate, the first portion covering the edge and the side of the first thin film transistor surrounding the second thin film transistor.
  • Step S400 forming a second portion of the second thin film transistor and the second isolation barrier on the base substrate, the second portion being located on the first portion, the first portion and the second portion collectively surrounding the second thin film transistor.
  • step S300 forming the first portion of the first thin film transistor and the second isolation barrier on the base substrate may include:
  • Step S310 forming a first active layer of the first thin film transistor.
  • step S310 a polysilicon layer is deposited on the base substrate 10, the polysilicon layer is a low temperature polysilicon layer, and the low temperature polysilicon layer is doped with hydrogen; and then, through a patterning process, The first active layer 21 of the first thin film transistor 20 is formed, and the first active layer 21 is located on the base substrate 10 to form the first region 11 of the first thin film transistor 20.
  • Step S320 forming a first gate insulating layer of the first thin film transistor.
  • step S320 a first gate insulating film layer is deposited on the base substrate 10 and the first active layer 21 to form a first gate insulating layer 22, first.
  • the gate insulating layer 22 covers the base substrate 10 and the first active layer 21.
  • Step S330 forming a first gate of the first thin film transistor.
  • step S330 a first metal layer is first deposited on the first gate insulating layer 22; then, a first gate of the first thin film transistor 20 is formed by a patterning process. 23, the first gate 23 is located in the first region 11 of the base substrate 10 above the first active layer 21.
  • Step S340 forming a first interlayer insulating layer of the first thin film transistor.
  • a first interlayer insulating film layer is deposited on the first gate insulating layer 22 and the first gate 23 to form a first interlayer insulating layer 24,
  • the first interlayer insulating layer 24 covers the first gate insulating layer 22 and the first gate electrode 23.
  • Step S350 forming an exposure hole penetrating through the first interlayer insulating layer and the first gate insulating layer, a first connection hole and a second connection hole, the exposure hole exposing a region on the substrate substrate where the second thin film transistor is formed, first Both the connection hole and the second connection hole expose the first active layer.
  • an exposure hole 241 , a first connection hole 242 and a second connection hole 243 are formed through a patterning process, wherein the exposure hole 241 penetrates the first interlayer insulation layer And a first gate insulating layer 22, and exposing a region of the base substrate 10 on which the second thin film transistor 30 is formed to facilitate subsequent formation of the second thin film transistor 30 on the base substrate 10; the first connection hole 242 and the The two connection holes 243 respectively penetrate the first interlayer insulating layer 24 and the first gate insulating layer 22, and both expose the first active layer 21 to facilitate the formation of the first source and drain of the first source and the source 15 and The first drain 26 is connected to the first active layer 21, respectively.
  • Step S360 forming a first source drain of the first thin film transistor, a second gate of the second thin film transistor, and a first portion of the second isolation barrier, wherein the first source drain includes the first source and the first a drain, the first source is connected to the first active layer through the first connection hole, and the first drain is connected to the first active layer through the second connection hole; the first portion covers the edge of the exposed hole and the hole wall;
  • the second gate is on the substrate substrate and is exposed in the hole.
  • step S360 a second metal layer is first deposited; then, a first source and a drain of the first thin film transistor 20 and a second thin film transistor 30 are simultaneously formed by a patterning process.
  • the first portion 41 of the second gate 31 and the second isolation barrier 40 wherein, in the first source and drain, the first source 25 is connected to the first active layer 21 through the first connection hole 242, the first drain 26 is connected to the first active layer 21 through the second connection hole 243; the first portion 41 of the second isolation retaining wall 40 covers the edge of the exposed hole 241 and the hole wall, specifically, the first portion 41 covers the first interlayer insulation
  • the layer 24 corresponds to the edge of the exposure hole 241
  • the first interlayer insulating layer 24 corresponds to the side surface of the exposure hole 241
  • the first gate insulating layer 22 corresponds to the side surface of the exposure hole 241;
  • the second gate electrode 31 is located on the base substrate 10 Upper and exposed holes 241.
  • the first source and drain of the first thin film transistor 20, the second gate 31 of the second thin film transistor 30, and the first portion 41 of the second isolation barrier 40 are formed by one patterning process, thereby reducing the number of thin films.
  • the process steps of the transistor structure reduce the number of masks used in fabricating the thin film transistor structure, thereby reducing the cost of fabricating the thin film transistor structure.
  • step S400 forming a second portion of the second thin film transistor and the second isolation barrier on the base substrate may include:
  • Step S410 forming a second gate insulating layer of the second thin film transistor.
  • step S410 a second gate insulating film layer is deposited to form a second gate insulating layer 32, and the second gate insulating layer 32 covers the first thin film transistor 20 and the lining.
  • Step S420 forming a second active layer of the second thin film transistor.
  • a metal oxide film layer may be deposited on the second gate insulating layer 32; then, a second thin film transistor 30 is formed by a patterning process.
  • the source layer 33 and the second active layer 33 are located above the second gate 31.
  • Step S430 forming a second via hole surrounding the second thin film transistor and corresponding to the first portion in the second gate insulating layer, and a third connection hole corresponding to the first source of the first thin film transistor or corresponding to the first a fourth connection hole of the first drain of the thin film transistor.
  • a second via hole 322 is formed in the second gate insulating layer 32 by a patterning process, and the second via hole 322 surrounds the second thin film transistor 30,
  • the second via 322 exposes the first portion 41 of the first isolation barrier 40 to subsequently form the second portion 42 of the second isolation barrier 40 surrounding the second thin film transistor 30.
  • a third connection hole is further formed in the second gate insulating layer 32 by a patterning process, and the third connection hole corresponds to the first source electrode 25 of the first thin film transistor 20 to facilitate the connection formed through the subsequent formation.
  • the electrode 27 connects the first source 25 and other structures; or, by a patterning process, a fourth connection hole 324 is formed in the second gate insulating layer 32, and the fourth connection hole 324 corresponds to the first thin film transistor 20
  • a drain 26 is provided to facilitate connection of the first drain 26 to other structures through subsequently formed connection electrodes 27.
  • Step S440 forming a second source drain of the second thin film transistor, filling a second portion in the second via hole and contacting the first portion, and connecting the first source through the third connection hole or through the fourth connection hole A connection electrode that connects the first drain.
  • a third metal layer is first deposited; then, a second portion 42 of the second isolation barrier 40 and a second thin film transistor 30 are simultaneously formed by a patterning process.
  • a two-source drain and a connection electrode 27 of the first thin film transistor 20 wherein the second portion 42 is filled in the second via hole 322, and the second portion 42 is in contact with the first portion 41, the first portion 41 and the second portion 42
  • the second isolation barrier 40 is formed to surround the second thin film transistor 30 to isolate the second thin film transistor 30 from the first thin film transistor 20;
  • the second source and drain of the second thin film transistor 30 includes the second source 34 and The second drain 35, the second source 34 and the second drain 35 are respectively in contact with the second active layer 33;
  • the connection electrode 27 is located on the second gate insulating layer 32, and the connection electrode 27 is connected to the first through the third connection hole.
  • the source 25 or the connection electrode 27 is connected to the first drain 26 through the fourth connection hole 324. That is, the second portion 42, the second source drain, and the connection electrode 27 of the second isolation barrier 40 are formed by one patterning process, thereby reducing the number of process steps for fabricating the thin film transistor structure while reducing the fabrication of the thin film transistor structure. The number of masks used, which in turn reduces the cost of fabricating thin film transistor structures.
  • the first thin film transistor is a low temperature polysilicon thin film transistor
  • the second thin film transistor is a bottom gate thin film transistor
  • the first isolation barrier includes a plurality of portions, for example, the first isolation barrier includes a third portion and a fourth portion, that is, the first isolation barrier
  • Step S500 forming a first thin film transistor and a third portion of the first isolation barrier on the base substrate, and the third portion covering the first insulating layer of the first thin film transistor surrounds an edge and a side surface of the first thin film transistor.
  • Step S600 forming a second thin film transistor and a fourth portion of the first isolation barrier on the base substrate, the fourth portion is located on the third portion, and the third portion and the fourth portion collectively surround the first thin film transistor.
  • the step S500, forming the first thin film transistor and the third portion of the first isolation barrier on the base substrate may include:
  • Step S510 forming a first active layer of the first thin film transistor.
  • step S510 a polysilicon layer is deposited on the base substrate 10, the polysilicon layer is a low temperature polysilicon layer, and the low temperature polysilicon layer is doped with hydrogen; and then, through a patterning process, The first active layer 21 of the first thin film transistor 20 is formed, and the first active layer 21 is located on the base substrate 10 to form the first region 11 of the first thin film transistor 20.
  • Step S520 forming a first gate insulating layer of the first thin film transistor.
  • a first gate insulating film layer is deposited on the base substrate 10 and the first active layer 21 to form a first gate insulating layer 22, first The gate insulating layer 22 covers the base substrate 10 and the first active layer 21.
  • Step S530 forming a first gate of the first thin film transistor.
  • a first metal layer is first deposited on the first gate insulating layer 22; then, a first gate of the first thin film transistor 20 is formed by a patterning process. 23, the first gate 23 is located in the first region 11 of the base substrate 10 above the first active layer 21.
  • Step S540 forming a first interlayer insulating layer of the first thin film transistor.
  • step S540 a first interlayer insulating film layer is deposited on the first gate insulating layer 22 and the first gate electrode 23 to form a first interlayer insulating layer 24,
  • the first interlayer insulating layer 24 covers the first gate insulating layer 22 and the first gate electrode 23.
  • Step S550 removing the first gate insulating layer and the first interlayer insulating layer on a portion of the substrate other than the region where the first thin film transistor is formed, and forming the first interlayer insulating layer and the first gate insulating layer.
  • a first connection hole and a second connection hole wherein sides of the first gate insulating layer and the first interlayer insulating layer are located in a region where the base substrate forms the first thin film transistor; the first connection hole and the second connection hole are both The first active layer is exposed.
  • step S550 the first gate insulating layer 22 and the first interlayer insulating layer 24 are disposed on the base substrate 10 to form the first thin film transistor 20 by a patterning process.
  • the portion other than the first region 11 is removed, that is, the portion where the first gate insulating layer 22 and the first interlayer insulating layer 24 are located outside the first region 11 is removed, and the first connection hole 242 and the second connection hole 243 are formed.
  • the first gate insulating layer 22 covers only the first active layer 21 and the base substrate 10 located in the first region 11.
  • the first interlayer insulating layer 24 covers the first gate 23 and the first gate insulating layer.
  • the layer 22, the first gate insulating layer 22 and the first interlayer insulating layer 24 each have a side surrounding the first thin film transistor 20; the first connection hole 242 and the second connection hole 243 respectively penetrate the first interlayer insulating layer 24 and The first gate insulating layer 22 is exposed to the first active layer 21 to facilitate the formation of the first source drain and the first drain 26 of the first source drain and the first active layer 21 respectively.
  • the connection between the two is not limited to the two.
  • Step S560 forming a first source drain of the first thin film transistor, a second gate of the second thin film transistor, and a third portion of the first isolation barrier, wherein the first source drain includes the first source and the first a drain, the first source is connected to the first active layer through the first connection hole, the first drain is connected to the first active layer through the second connection hole; the third portion covers the edge of the first interlayer insulating layer and a side surface and a side surface of the first gate insulating layer; the second gate electrode is on the substrate substrate.
  • a second metal layer is deposited first; then, a first source and a drain of the first thin film transistor 20 and a second thin film transistor 30 are simultaneously formed by a patterning process.
  • the second gate 31 and the third portion 51 of the first isolation barrier 50 wherein, in the first source and drain, the first source 25 is connected to the first active layer 21 through the first connection hole 242, the first drain 26 is connected to the first active layer 21 through the second connection hole 243; the third portion 51 of the first isolation barrier 50 covers the edge and the side of the first interlayer insulating layer 24, and the side of the first gate insulating layer 22
  • the second gate 31 is located on the base substrate 10 in the second region 12.
  • the first source and drain of the first thin film transistor 20, the second gate 31 of the second thin film transistor 30, and the third portion 51 of the first isolation barrier 50 are formed by one patterning process, thereby reducing the number of thin films.
  • the process steps of the transistor structure reduce the number of masks used in fabricating the thin film transistor structure, thereby reducing the cost of fabricating the thin film transistor structure.
  • step S600 forming a second thin film transistor and a fourth portion of the first isolation barrier on the base substrate may include:
  • Step S610 forming a second gate insulating layer of the second thin film transistor.
  • a second gate insulating film layer is deposited to form a second gate insulating layer 32, and the second gate insulating layer 32 covers the first thin film transistor 20 and the lining.
  • Step S620 forming a second active layer of the second thin film transistor.
  • a metal oxide film layer may be deposited on the second gate insulating layer 32; then, a second thin film transistor 30 is formed by a patterning process.
  • the source layer 33 and the second active layer 33 are located above the second gate 31.
  • Step S630 forming a third via hole surrounding the first thin film transistor and corresponding to the third portion in the second gate insulating layer, and a third connection hole corresponding to the first source of the first thin film transistor or corresponding to the first a fourth connection hole of the first drain of the thin film transistor.
  • a third via 323 is formed in the second gate insulating layer 32 by a patterning process, and the third via 323 surrounds the first thin film transistor 20 ,
  • the three vias 323 expose the third portion 51 of the first isolation barrier 50 to subsequently form the fourth portion 52 of the first isolation barrier 50 surrounding the first thin film transistor 20.
  • a third connection hole is further formed in the second gate insulating layer 32 by a patterning process, and the third connection hole corresponds to the first source electrode 25 of the first thin film transistor 20 to facilitate the connection formed through the subsequent formation.
  • the electrode 27 connects the first source 25 and other structures; or, by a patterning process, a fourth connection hole 324 is formed in the second gate insulating layer 32, and the fourth connection hole 324 corresponds to the first thin film transistor 20
  • a drain 26 is provided to facilitate connection of the first drain 26 to other structures through subsequently formed connection electrodes 27.
  • Step S640 forming a second source drain of the second thin film transistor, filling a fourth portion in the third via hole and contacting the third portion, and connecting the first source through the third connection hole or through the fourth connection hole A connection electrode that connects the first drain.
  • a third metal layer is deposited first; then, a fourth portion 52 of the first isolation barrier 50 and a second thin film transistor 30 are simultaneously formed by a patterning process.
  • the two source drains and the connection electrode 27 of the first thin film transistor 20, wherein the fourth portion 52 is filled in the third via hole 323, the fourth portion 52 is in contact with the third portion 51, and the third portion 51 and the fourth portion 52 are
  • the first isolation barrier 50 is formed to surround the first thin film transistor 20 to isolate the second thin film transistor 30 from the first thin film transistor 20;
  • the second source and drain of the second thin film transistor 30 includes the second source 34 and The second drain 35, the second source 34 and the second drain 35 are respectively in contact with the second active layer 33;
  • the connection electrode 27 is located on the second gate insulating layer 32, and the connection electrode 27 is connected to the first through the third connection hole.
  • the source 25 or the connection electrode 27 is connected to the first drain 26 through the fourth connection hole 324. That is, the fourth portion 52 of the first isolation barrier 50, the second source drain, and the connection electrode 27 are formed by one patterning process, thereby reducing the number of process steps for fabricating the thin film transistor structure while reducing the fabrication of the thin film transistor structure. The number of masks used, which in turn reduces the cost of fabricating thin film transistor structures.
  • the manufacturing methods of the first isolation barrier 50 and the second isolation barrier 40 can be referred to the above embodiments, respectively.
  • the first isolation retaining wall 50 has the structure shown in FIG. 3 and the second insulating retaining wall 40 has the structure shown in FIG. 1, it can be formed in the manufacturing method with reference to FIGS. 15 and 16 and FIGS. 7 and 8.
  • the filling holes of the second isolation retaining wall 40 may be formed together when forming the second portion of the first insulating retaining wall 50.
  • the first isolation retaining wall 50 has the structure shown in FIG. 3 and the second insulating retaining wall 40 has the structure shown in FIG.
  • An isolation retaining wall 50 and a second insulating retaining wall 40 may share the opposing retaining wall at the junction of the two, or, at the junction of the two, the third portion of the first insulating retaining wall 50 may be in the second insulating retaining wall.
  • the first portion is formed later, or the third portion of the first isolation barrier 50 may be formed before the first portion of the second isolation barrier, and the third portion or the first portion formed thereafter may be perpendicular to the substrate Part or all of the first or third portion is covered in the direction, that is, overlapped in a direction perpendicular to the substrate.
  • the third portion or the first portion formed later may not cover the previously formed first portion or the third portion in a direction perpendicular to the substrate substrate, but only in a direction parallel to the substrate substrate Stack.
  • Embodiments of the present disclosure are not limited thereto.

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Abstract

La présente invention concerne une structure de transistor en couches minces et son procédé de fabrication, un panneau d'affichage et un dispositif d'affichage. La structure de transistor en couches minces comprend un substrat de base (10), ainsi qu'un premier transistor en couches minces (20) et un second transistor en couches minces (30) formés sur le substrat de base (10), une première couche active (21) du premier transistor en couches minces (20) étant dopée avec de l'hydrogène, une seconde couche active (33) du second transistor en couches minces (30) étant constituée d'un oxyde métallique, et une première barrière d'isolation (50) qui entoure le premier transistor en couches minces (20) et/ou une seconde barrière d'isolation (40) qui entoure le second transistor en couches minces (30) étant en outre disposées sur le substrat de base (10). La première barrière d'isolation (50) et/ou la seconde barrière d'isolation (40) isolent le second transistor en couches minces (30) du premier transistor en couches minces (20), de manière à isoler l'hydrogène dans la première couche active (21) du premier transistor en couches minces (20), évitant ainsi un impact négatif sur le second transistor en couches minces (30) causé par l'hydrogène dans la première couche active (21).
PCT/CN2018/078869 2017-07-28 2018-03-13 Structure de transistor en couches minces et son procédé de fabrication, panneau d'affichage et dispositif d'affichage WO2019019658A1 (fr)

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CN107452756A (zh) * 2017-07-28 2017-12-08 京东方科技集团股份有限公司 薄膜晶体管结构及其制造方法、显示面板、显示装置

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