WO2019019658A1 - 薄膜晶体管结构及其制造方法、显示面板、显示装置 - Google Patents

薄膜晶体管结构及其制造方法、显示面板、显示装置 Download PDF

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WO2019019658A1
WO2019019658A1 PCT/CN2018/078869 CN2018078869W WO2019019658A1 WO 2019019658 A1 WO2019019658 A1 WO 2019019658A1 CN 2018078869 W CN2018078869 W CN 2018078869W WO 2019019658 A1 WO2019019658 A1 WO 2019019658A1
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Prior art keywords
thin film
film transistor
insulating layer
forming
isolation barrier
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PCT/CN2018/078869
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English (en)
French (fr)
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胡合合
杨维
卢鑫泓
王珂
温钰
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京东方科技集团股份有限公司
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Priority to US16/302,850 priority Critical patent/US10553621B2/en
Publication of WO2019019658A1 publication Critical patent/WO2019019658A1/zh

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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a thin film transistor structure, a method of fabricating the same, a display panel, and a display device.
  • Thin film transistors as important switching control elements, play a key role in display devices.
  • a thin film transistor structure is generally disposed in a display panel of the display device, and the thin film transistor structure includes two types of thin film transistors, one of which has mobility
  • the advantages of high and fast charging, another thin film transistor has the advantage of low leakage current.
  • a thin film transistor structure is usually provided, and the thin film transistor structure includes a thin film transistor and a second thin film transistor, the first thin film transistor is a low temperature polysilicon thin film transistor, and the second thin film transistor is a metal oxide thin film transistor, and the migration of the first thin film transistor is performed when a display device of the display device of the OLED display panel is provided
  • the advantages of high rate, fast charging, and low leakage current of the second thin film transistor drive the OLED device in the OLED display panel to make the display device have good picture display quality.
  • the active layer of the first thin film transistor is usually doped with hydrogen (for example, low temperature polysilicon).
  • the second thin film transistor is usually a metal oxide thin film transistor, that is, the material of the active layer of the second thin film transistor is a metal oxide, and the metal oxide as an active layer of the second thin film transistor is very sensitive to hydrogen Therefore, when a first thin film transistor having a high mobility and a fast charging advantage and a second thin film transistor having a low leakage current are simultaneously disposed in the display panel, hydrogen in the active layer of the first thin film transistor may diffuse to the first The active layer of the second thin film transistor adversely affects the active layer of the second thin film transistor, thereby adversely affecting the performance of the second thin film transistor.
  • the present disclosure provides a thin film transistor structure including a substrate substrate, and a first thin film transistor and a second thin film transistor formed on the base substrate, wherein the first thin film transistor has a first The source layer is doped with hydrogen; the material of the second active layer of the second thin film transistor is a metal oxide; and the first isolation barrier surrounding the first thin film transistor is further disposed on the substrate. And a second isolation barrier surrounding the second thin film transistor.
  • the second gate insulating layer of the second thin film transistor covers the first thin film transistor, and the first via hole surrounding the second thin film transistor is disposed in the second gate insulating layer.
  • the second isolation barrier fills the first via.
  • the second isolation barrier includes a first portion and a second portion, wherein the first portion is on the base substrate, and the first portion covers the first thin film transistor An insulating layer surrounding an edge and a side of the second thin film transistor; a second gate insulating layer of the second thin film transistor covering the first thin film transistor and the first portion, the second gate insulating a region corresponding to the first portion of the layer is provided with a second via hole surrounding the second thin film transistor, the second portion fills the second via hole, and the second portion and the first portion contact.
  • the first isolation barrier includes a third portion and a fourth portion, wherein the third portion is on the base substrate, and the third portion covers the first thin film transistor An insulating layer surrounding an edge and a side of the first thin film transistor; a second gate insulating layer of the second thin film transistor covering the first thin film transistor and the third portion, the second gate insulating a region corresponding to the third portion is provided with a third via surrounding the first thin film transistor, the fourth portion filling the third via, and the fourth portion and the third portion contact.
  • the first thin film transistor is a low temperature polysilicon thin film transistor
  • the second thin film transistor is a bottom gate thin film transistor
  • the first thin film transistor includes a connection electrode on the second gate insulating layer, and the connection electrode passes through the first connection hole in the second gate insulating layer and the first film a drain of the first source and drain of the transistor is connected, or the connection electrode passes through the second connection hole in the second gate insulating layer and the first source and drain of the first thin film transistor The source is connected.
  • the first isolation retaining wall is an organic material barrier, an inorganic material barrier or a metal barrier
  • the second barrier is an organic material barrier, an inorganic material barrier or a metal Isolation of the retaining wall.
  • the first insulating layer includes a first gate insulating layer of the first thin film transistor and a first interlayer insulating layer covering the first gate of the first thin film transistor.
  • the third portion covering the first insulating layer of the first thin film transistor is formed on the substrate substrate in a region of the first thin film transistor and surrounds an edge of the first thin film transistor
  • the side surface includes: the third portion covering the first gate insulating layer of the first thin film transistor is disposed on the substrate substrate and is formed in a region of the first thin film transistor and surrounds the first thin film transistor a side surface and the third portion of the first interlayer insulating layer covering the first thin film transistor are formed on the base substrate and are formed in a region of the first thin film transistor and surround the first thin film transistor Edge and side.
  • the present disclosure provides a display panel comprising the thin film transistor structure of any of the first aspects.
  • the present disclosure provides a display device comprising the display panel of any of the second aspects.
  • the present disclosure provides a method of fabricating a thin film transistor structure, including:
  • first thin film transistor and a second thin film transistor Forming a first thin film transistor and a second thin film transistor, and a first isolation barrier or/and a second isolation barrier on the base substrate, wherein the first active layer of the first thin film transistor is doped with hydrogen;
  • the material of the second active layer of the second thin film transistor is a metal oxide; the first isolation barrier surrounds the first thin film transistor, and the second isolation barrier surrounds the second thin film transistor.
  • the first thin film transistor is a low temperature polysilicon thin film transistor
  • the second thin film transistor is a bottom gate thin film transistor
  • Forming a first thin film transistor, a second thin film transistor, and a second isolation barrier on the base substrate including:
  • forming the first thin film transistor on the base substrate comprises:
  • first source drain of the first thin film transistor and a second gate of the second thin film transistor, wherein the first source drain includes a first source and a first drain, the first a source is connected to the first active layer through the first connection hole, and the first drain is connected to the first active layer through the second connection hole; On the substrate substrate, in the exposed hole;
  • Forming the second thin film transistor and the second isolation barrier surrounding the second thin film transistor on the base substrate including:
  • the fourth connection hole connects the connection electrode of the first drain.
  • the first thin film transistor is a low temperature polysilicon thin film transistor
  • the second thin film transistor is a bottom gate thin film transistor
  • Forming a first thin film transistor, a second thin film transistor, and a second isolation barrier on the base substrate including:
  • the second portion is located on the first portion, and the second portion surrounds the second portion Thin film transistor.
  • forming the first portion of the first thin film transistor and the second isolation barrier on the base substrate comprises:
  • first source drain of the first thin film transistor, a second gate of the second thin film transistor, and a first portion of the second isolation barrier, wherein the first source drain includes a first source And a first drain, the first source is connected to the first active layer through the first connection hole, and the first drain passes through the second connection hole and the first active layer Connecting; the first portion covers an edge of the exposed hole and a hole wall; the second gate is located on the base substrate, in the exposed hole;
  • Forming the second thin film transistor and the second portion of the second isolation barrier on the base substrate including:
  • connection electrode of the first drain is connected to the pole or through the fourth connection hole.
  • the first thin film transistor is a low temperature polysilicon thin film transistor
  • the second thin film transistor is a bottom gate thin film transistor
  • Forming a first thin film transistor, a second thin film transistor, and a first isolation barrier on the base substrate including:
  • the fourth portion is located on the third portion, and the fourth portion surrounds the first portion Thin film transistor.
  • forming the first thin film transistor and the third portion of the first isolation barrier on the base substrate including:
  • first connection hole and the second connection hole both expose the first active layer
  • first source drain of the first thin film transistor, a second gate of the second thin film transistor, and a third portion of the first isolation barrier, wherein the first source drain includes a first source And a first drain, the first source is connected to the first active layer through the first connection hole, and the first drain passes through the second connection hole and the first active layer Connecting; the third portion covers an edge and a side of the first interlayer insulating layer, and a side of the first gate insulating layer; the second gate is located on the substrate;
  • Forming the second thin film transistor and the fourth portion of the first isolation barrier on the base substrate including:
  • connection electrode of the first drain is connected to the pole or through the fourth connection hole.
  • FIG. 1 is a schematic diagram of a structure of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of another thin film transistor structure according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of still another thin film transistor structure according to an embodiment of the present disclosure.
  • FIG. 4 is a flowchart of a method of fabricating a thin film transistor structure according to an embodiment of the present disclosure
  • FIG. 5 is a flow chart 1 of a specific method of the method for fabricating the thin film transistor structure of FIG. 4;
  • FIG. 6 is a flow chart showing a specific method of the method of fabricating the thin film transistor structure of FIG. 5;
  • FIG. 7 is a process flow diagram of step S100 in Figure 6;
  • step S200 in FIG. 6 is a process flow diagram of step S200 in FIG. 6;
  • FIG. 9 is a second flowchart of a specific method of the method for fabricating the thin film transistor structure of FIG. 4;
  • FIG. 10 is a flow chart showing a specific method of the method of fabricating the thin film transistor structure of FIG. 9;
  • FIG 11 is a process flow diagram of step S300 in Figure 10;
  • FIG 12 is a process flow diagram of step S400 in Figure 10;
  • FIG. 13 is a third flowchart of a specific method of the method for fabricating the thin film transistor structure of FIG. 4;
  • FIG. 14 is a flow chart showing a specific method of the method of fabricating the thin film transistor structure of FIG. 13;
  • FIG. 15 is a process flow diagram of step S500 of Figure 14.
  • FIG. 16 is a process flow diagram of step S600 in FIG.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” and “second” may include at least one of the features, either explicitly or implicitly.
  • the meaning of “a plurality” is two or more unless specifically and specifically defined otherwise.
  • the word “comprising” or “comprises” or the like means that the element or item preceding the word is intended to be in the
  • the words “connected” or “connected” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper”, “lower”, “left”, “right”, etc. are only used to indicate the relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may also change accordingly.
  • a thin film transistor structure provided by an embodiment of the present disclosure includes a base substrate 10 , and a first thin film transistor 20 and a second thin film transistor 30 formed on the base substrate 10 , wherein the first thin film transistor
  • the first active layer 21 of 20 is doped with hydrogen
  • the material of the second active layer 33 of the second thin film transistor 30 is a metal oxide
  • the first substrate 10 is further provided with at least a first surrounding the first thin film transistor 20
  • the first isolation barrier 50 of the active layer 21 and/or the second isolation barrier 40 surrounding the second active layer 33 of the second thin film transistor 30, the first isolation barrier 50 and the second isolation barrier 40 are parallel Provided in the direction of the base substrate 10 between the first active layer 21 and the second active layer 33, preventing hydrogen in the active layer of the first thin film transistor from diffusing to the active layer of the second thin film transistor.
  • the performance of the second thin film transistor causes an adverse effect.
  • the first isolation barrier and the second isolation barrier surround the first thin film transistor and the second, respectively a thin film transistor to space the first thin film transistor and the second thin film transistor in a direction parallel to the substrate, the first isolation barrier 50 and the second isolation barrier 40 being parallel to the lining
  • the direction of the base substrate is between the first and second thin film transistors.
  • the thin film transistor structure provided in the embodiment of the present disclosure includes a substrate substrate 10 , a first thin film transistor 20 , and a second thin film transistor 30 having a first region on the substrate substrate 10 . 11 and the second region 12, the first thin film transistor 20 is formed in the first region 11 on the base substrate 10, and the second thin film transistor 30 is formed in the second region 12 on the base substrate 10; the first thin film transistor 20
  • the first active layer 21 is doped with hydrogen.
  • the first thin film transistor 20 may be an amorphous silicon thin film transistor, a single crystal silicon thin film transistor, or a polycrystalline silicon thin film transistor (such as a low temperature polysilicon thin film transistor).
  • the second thin film transistor 30 is a metal oxide thin film transistor, that is, the material of the second active layer 33 of the second thin film transistor 30 is a metal oxide, for example, a material of the second active layer 33 of the second thin film transistor 30. It may be Indium Gallium Zinc Oxide (IGZO).
  • IGZO Indium Gallium Zinc Oxide
  • a first isolation barrier 50 or/and a second isolation barrier 40 are further disposed on the base substrate 10.
  • the base substrate 10 is provided with a second isolation barrier 40, and a second The isolation barrier 40 is disposed around the second thin film transistor 30.
  • the second isolation barrier 40 may be located on the edge of the second region 12 or the second region 12 on the base substrate 10 to surround the second thin film transistor 30 on the substrate. 10 in the second region 12, and the second thin film transistor 30 is isolated from the first thin film transistor 20; or, referring to FIG.
  • the substrate substrate 10 is provided with a first isolation barrier 50, the first isolation barrier 50 is disposed around the first thin film transistor 20, and the first isolation barrier 50 may be located on the edge of the first region 11 or the first region 11 on the base substrate 10 to surround the first thin film transistor 20 on the base substrate 10.
  • the second thin film transistor 30 is isolated from the first thin film transistor 20; or, in practical applications, the first isolation barrier 50 and the second isolation barrier 40 may be simultaneously disposed on the substrate 10 .
  • the first isolation barrier 50 is disposed around the first thin film transistor 20 to be first
  • the film transistor 20 is disposed in the first region 11 on the base substrate 10
  • the second isolation barrier 40 is disposed around the second thin film transistor 30 to surround the second thin film transistor 30 in the second region 12 on the base substrate 10.
  • the first isolation barrier 50 and the second isolation barrier 40 cooperate to isolate the second thin film transistor 30 from the first thin film transistor 20.
  • the second isolation barrier 40 surrounding the second thin film transistor 30 or/and the first isolation surrounding the first thin film transistor 20 are disposed on the base substrate 10.
  • the second insulating film 40 surrounds the second thin film transistor 30 in a region where the second thin film transistor 30 is disposed on the base substrate 10, and the first isolation barrier 50 surrounds the first thin film transistor 20 on the base substrate.
  • the second isolation barrier 40 or/and the first isolation barrier 50 may be disposed first Hydrogen isolation in the first active layer 21 of the thin film transistor 20 prevents hydrogen in the first active layer 21 of the first thin film transistor 20 from diffusing into the second thin film transistor 30, for example, preventing the first thin film transistor 20 Hydrogen in an active layer 21 diffuses into the second active layer 33 of the second thin film transistor 30, so that hydrogen in the first active layer 21 of the first thin film transistor 20 can be prevented from causing damage to the second thin film transistor 30.
  • Influence for example, prevention Hydrogen in the first active layer 21 of the first thin film transistor 20 adversely affects the second active layer 33 of the second thin film transistor 30, thereby preventing hydrogen in the first active layer 21 of the first thin film transistor 20
  • the performance of the second thin film transistor 30 causes an adverse effect.
  • the second isolation barrier 40 surrounding the second thin film transistor 30 or/and the first isolation barrier surrounding the first thin film transistor 20 are disposed on the base substrate 10 . 50.
  • the second isolation barrier 40 surrounds the second thin film transistor 30 in a region where the second thin film transistor 30 is disposed on the base substrate 10.
  • the first isolation barrier 50 surrounds the first thin film transistor 20 on the base substrate 10.
  • the region of the first thin film transistor 20 is disposed to isolate the second thin film transistor 30 from the first thin film transistor 20, and thus, the process of manufacturing the second thin film transistor 30 can be expanded when the thin film transistor structure provided by the embodiment of the present disclosure is fabricated.
  • the window reduces the difficulty of fabricating a thin film transistor structure.
  • the second isolation barrier 40 surrounding the second thin film transistor 30 or/and the first isolation barrier surrounding the first thin film transistor 20 are disposed on the base substrate 10.
  • the wall 50, the second isolation barrier 40 surrounds the second thin film transistor 30 in a region where the second thin film transistor 30 is disposed on the base substrate 10, and the first isolation barrier 50 surrounds the first thin film transistor 20 around the base substrate 10.
  • the region of the first thin film transistor 20 is disposed to isolate the second thin film transistor 30 from the first thin film transistor 20, preventing the hydrogen in the first active layer 21 of the first thin film transistor 20 from acting on the second thin film transistor 30.
  • the adverse effect is caused, and therefore, the characteristics and stability of the second thin film transistor 30 can be improved, thereby improving the picture display quality of the display device to which the thin film transistor structure provided by the embodiment of the present disclosure is applied.
  • first isolation barrier 50 may be disposed on the base substrate 10, or only the second isolation barrier 40 may be disposed on the base substrate 10, or the first substrate 10 may be simultaneously disposed on the base substrate 10.
  • the second gate of the second thin film transistor 30 covers the first thin film transistor 20, the first via hole surrounding the second thin film transistor 30 is disposed in the second gate insulating layer 32, and the second isolation barrier 40 fills the first via hole.
  • the first thin film transistor 20 is located in the first region 11 on the base substrate 10
  • the second thin film transistor 30 is located in the second region 12 on the base substrate 10
  • the second thin film transistor 30 includes
  • the second gate insulating layer 32 covers the first thin film transistor 20, and the second gate insulating layer 32 is provided with a first via surrounding the second thin film transistor 30, that is, the first via is annular
  • the first via hole may be located in the second region 12 or the edge of the second region 12, and the second isolation barrier wall 40 as a whole structure fills the first via hole, and the second isolation barrier wall 40 is in contact with the substrate substrate 10,
  • the second thin film transistor 30 is surrounded by the second thin film transistor 30 to isolate the second thin film transistor 30 from the first thin film transistor 20.
  • the second isolation retaining wall 40 can also be divided into multiple parts.
  • the second isolation retaining wall 40 can include a first portion 41 and a second portion 42, wherein the first portion 41 is located on the base substrate 10, and the first portion 41 covers the edge and the side of the first insulating layer of the first thin film transistor 20 surrounding the second thin film transistor 30; the second gate insulating layer 32 of the second thin film transistor 30 is covered
  • the first thin film transistor 20 and the first portion 41, the second gate insulating layer 32 is provided with a second via hole surrounding the second thin film transistor 30, and the second portion 42 is filled with the second via hole.
  • the second portion 42 is in contact with the first portion 41.
  • the first insulating layer of the first thin film transistor 20 and the second substrate 12 on the base substrate 10 corresponding to the second region 12 of the second thin film transistor 30 have exposed holes, and the exposed holes expose the lining.
  • the bottom substrate 10, the second thin film transistor 30 is located in the exposed hole of the base substrate 10, the first portion 41 of the second isolation retaining wall 40 is located on the base substrate 10, and the first portion 41 covers the edge of the exposed hole and the wall of the hole. That is, the first portion 41 covers the edge and the side of the first thin film transistor 30, and when the first thin film transistor 20 is a bottom gate thin film transistor or a top gate thin film transistor, the first thin film transistor 20 includes the first thin film.
  • the first insulating layer may include the first gate insulating layer of the first thin film transistor 20, or, please continue to refer to 2, when the first thin film transistor 20 is a low temperature polysilicon thin film transistor, the first thin film transistor 20 includes a first gate insulating layer 22 between the first active layer 21 and the first gate 23 of the first thin film transistor 20. And located at a first interlayer insulating layer 24 between the first gate 23 of the thin film transistor 20 and the first source drain (including the first source 25 and the first drain 26). At this time, the first insulating layer may include The first gate insulating layer 22 of the first thin film transistor 20 and the first interlayer insulating layer 24.
  • the second thin film transistor 30 includes a second gate insulating layer 32 covering the first thin film transistor 20 and the first portion 41, and the second gate insulating layer 32 is provided with a region corresponding to the first portion 41.
  • the second via Surrounding the second via of the second thin film transistor 30, the second via is annular, and the second portion 42 of the second isolation barrier 40 fills the second via and is in contact with the first portion 41, the first portion 41 and the second portion
  • the portions 42 collectively form a second isolation barrier 40 surrounding the second thin film transistor 30, surrounding the second thin film transistor 30, and isolating the second thin film transistor 30 from the first thin film transistor 20.
  • the second isolation barrier 40 is disposed as a first portion 41 and a second portion 42 , the first portion 41 is located on the base substrate 10 , and the first portion 41 covers the second insulating layer of the first thin film transistor 20 The edge and the side of the thin film transistor 30, therefore, the first portion 41 can isolate the first insulating layer of the first thin film transistor 20 from the second thin film transistor 30 to prevent the first thin film transistor 20 from being present in the first insulating layer The hydrogen diffuses into the second thin film transistor 30.
  • the first insulating layer includes the first gate insulating layer 22 and the first interlayer insulating layer 24, and the second isolation block
  • the first portion 41 of the wall 40 can separate the first gate insulating layer 22 and the first interlayer insulating layer 24 from the second thin film transistor 30, and may exist between the first gate insulating layer 22 and the first layer. Hydrogen in the insulating layer 24 diffuses to the second thin film transistor 30.
  • the arrangement of the first isolation barrier 50 can be set according to actual needs.
  • the first isolation barrier 50 includes a third portion 51 and a fourth portion 52, wherein The third portion 51 is disposed on the base substrate 10, and the third portion 51 covers the first insulating layer of the first thin film transistor 20 in the region of the base substrate 10 where the first thin film transistor 20 is formed, and surrounds the first thin film transistor 20.
  • the second gate insulating layer 32 of the second thin film transistor 30 covers the first thin film transistor 20 and the third portion 51, and the second gate insulating layer 32 is provided with a surrounding area corresponding to the third portion 51.
  • the third via of the thin film transistor 20, the fourth portion 52 fills the third via, and the fourth portion 52 is in contact with the third portion 51.
  • the first insulating layer of the first thin film transistor 20 is located on the base substrate 10 to form the first region 11 of the first thin film transistor 20, and the side of the first insulating layer is located in the first region. 11 , it should be noted that the side of the first insulating layer is located in the first region 11 .
  • the side of the first insulating layer is located at the edge or inside of the first region 11 , and the side of the first insulating layer surrounds the first The thin film transistor 20, the third portion 51 of the first isolation barrier 50 is located on the base substrate 10, and the third portion 51 covers the edge and the side of the first insulating layer, that is, the third portion 51 surrounds the first thin film transistor 20;
  • the first thin film transistor 20 is a bottom gate thin film transistor or a top gate thin film transistor
  • the first thin film transistor 20 includes a first gate insulating layer between the first gate of the first thin film transistor and the first active layer.
  • the first insulating layer may include the first gate insulating layer of the first thin film transistor 20; or, referring to FIG.
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor, and the first thin film transistor 20 includes the first thin film.
  • crystal a first gate insulating layer 22 between the first active layer 21 and the first gate 23 of the tube 20, and a first gate 23 and a first source drain (including the first source) of the first thin film transistor 20 a first interlayer insulating layer 24 between the pole 25 and the first drain 26).
  • the first insulating layer may include the first gate insulating layer 22 of the first thin film transistor 20 and the first interlayer insulating layer 24 .
  • the second thin film transistor 30 includes a second gate insulating layer 32 covering the first thin film transistor 20 and the third portion 51, and the second gate insulating layer 32 is provided with a region corresponding to the third portion 51.
  • the third via Surrounding the third via of the first thin film transistor 30, the third via is annular, and the fourth portion 52 of the first isolation barrier 50 fills the third via and contacts the third portion 51, the third portion 51 and the fourth portion
  • the portions 52 collectively form a first isolation barrier 50 surrounding the first thin film transistor 20, surrounding the first thin film transistor 20, and isolating the first thin film transistor 20 from the second thin film transistor 30.
  • the first isolation barrier 50 is disposed as a third portion 51 and a fourth portion 52, the third portion 51 is located on the base substrate 10, and the third portion 51 covers the first insulating layer of the first thin film transistor 20 at the first
  • the region 11 surrounds the edge and the side of the first thin film transistor 20, and therefore, the third portion 51 can isolate the first insulating layer of the first thin film transistor 20 from the second thin film transistor 30 to prevent possible in the first thin film transistor 20.
  • Hydrogen present in the first insulating layer diffuses into the second thin film transistor 30.
  • the first insulating layer includes the first gate insulating layer 22 and the first interlayer insulating layer.
  • the second portion 51 of the first isolation barrier 50 can isolate the first gate insulating layer 22 and the first interlayer insulating layer 24 from the second thin film transistor 30 to prevent possible presence of the first gate insulating layer.
  • the hydrogen in the layer 22 and the first interlayer insulating layer 24 is diffused to the second thin film transistor 30.
  • the first isolation barrier 50 when the first isolation barrier 50 and the second isolation barrier 40 are simultaneously disposed on the base substrate 10, the first isolation barrier 50 may adopt the third portion 51 and the fourth portion 52.
  • the second isolation barrier 40 can be disposed in an integrated manner, that is, the second isolation barrier 40 fills the first via formed in the second gate insulating layer 32 and surrounds the first via of the second thin film transistor 30.
  • the setting is made, that is, the first isolation retaining wall 50 can be disposed in the manner shown in FIG. 3, and the second insulating retaining wall 40 can be disposed in the manner shown in FIG.
  • the type of the first thin film transistor 20 can be selected according to actual needs.
  • the first thin film transistor 20 can be an amorphous silicon thin film transistor, a single crystal silicon thin film transistor, a polycrystalline silicon thin film transistor, etc., implemented in the present disclosure.
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor. Referring to FIG. 1 or FIG.
  • the first thin film transistor 20 includes a first active layer 21 , a first gate insulating layer 22 , a first gate 23 , a first interlayer insulating layer 24, a first source and a drain, wherein the first active layer 21 is on the base substrate 10; the first gate insulating layer 22 covers the base substrate 10, the first active layer 21, A gate insulating layer 22 and a region of the base substrate 10 corresponding to a region where the second thin film transistor 30 is formed have a first exposed hole exposing the base substrate 10; the first gate 23 is located on the first gate insulating layer 22.
  • the first gate 23 is located above the first active layer 21; the first interlayer insulating layer 24 covers the first gate 23 and the first gate insulating layer 22, the first interlayer insulating layer 24 and the first gate The area corresponding to the first exposed hole in the insulating layer 22 is exposed a second exposed hole of the base substrate 10; the first active layer 21 further has a first connection hole and a second connection hole penetrating the first interlayer insulating layer 24 and the first gate insulating layer 22, the first connection hole And the second connection hole exposing the first active layer 21; the first source drain is located on the first interlayer insulating layer 24, the first source drain comprises a first source 25 and a first drain 26, first The source electrode 25 is connected to the first active layer 21 through the first connection hole, and the first drain electrode 26 is connected to the first active layer 21 through the second connection hole; or, referring to FIG.
  • the first thin film transistor 20 includes a first active layer 21, a first gate insulating layer 22, a first gate 23, a first interlayer insulating layer 24, and a first source drain, wherein the first active layer 21 is located on the base substrate 10.
  • the first gate insulating layer 22 covers the first active layer 21 and the base substrate 10 located in the first region 11; the first gate 23 is located on the first gate insulating layer 22, and A gate electrode 23 is disposed above the first active layer 21; a first interlayer insulating layer 24 covers the first gate electrode 23 and the first gate insulating layer 22;
  • the first connection hole and the second connection hole of the interlayer insulating layer 24 and the first gate insulating layer 22, the first connection hole and the second connection hole both expose the first active layer 21;
  • the first source and drain electrodes are located at On the interlayer insulating layer 24, the first source drain includes a first source 25 and a first drain 26.
  • the first source 25 is connected to the first active layer 21 through the first connection hole, and the first drain 26
  • the type of the second thin film transistor 30 can be selected according to actual needs.
  • the second thin film transistor 30 can be a bottom gate thin film transistor, a top gate thin film transistor, etc., in the embodiment of the present disclosure, please continue to refer to 1 or 2, the second thin film transistor 30 is a bottom gate thin film transistor, and the second thin film transistor 30 includes a second gate 31, a second gate insulating layer 32, a second active layer 33, and a second source drain.
  • the second gate 31 is disposed on the base substrate 10; the second gate insulating layer 32 covers the second gate 31, the base substrate 10, and the first thin film transistor 20; the second active layer 33 is located at the second gate On the insulating layer 32, the second active layer 33 is located above the second gate 31, and the material of the second active layer 33 may be Indium Gallium Zinc Oxide (IGZO); the second source drain Located on the second active layer 33, the second source drain includes a second source 34 and a second drain 35, and the second source 34 and the second drain 35 are in contact with the second active layer 33, respectively.
  • IGZO Indium Gallium Zinc Oxide
  • the second thin film transistor 30 may be formed in the first exposed hole and the second exposed hole.
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor
  • the second thin film transistor 30 is a bottom gate thin film transistor
  • the first via hole surrounding the second thin film transistor 30 is formed in the second gate insulating layer 32.
  • the first via exposes the base substrate 10, and the second isolation barrier 40 is filled in the first via to isolate the second thin film transistor 30 from the first thin film transistor 20;
  • the first thin film transistor 20 further includes a connection electrode 27 a region of the second gate insulating layer 32 corresponding to the first source electrode 25 has a third connection hole.
  • the connection electrode 27 is connected to the first source electrode 25 through the third connection hole, or the second gate insulating layer
  • the region corresponding to the first drain 26 has a fourth connection hole.
  • the connection electrode 27 is connected to the first drain 26 through the fourth connection hole to facilitate the first source 25 or the first of the first thin film transistor 20.
  • a drain 26 is connected to other structures.
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor
  • the second thin film transistor 30 is a bottom gate thin film transistor
  • the second isolation barrier 40 includes a first portion 41 and a second portion 42 covered by the first portion 41.
  • the first thin film transistor 20 further includes a connection The electrode 27, the region corresponding to the first source electrode 25 of the second gate insulating layer 32 has a third connection hole, and at this time, the connection electrode 27 is connected to the first source 25 through the third connection hole, or the second gate
  • the insulating layer 32 corresponds to the first drain 26
  • the domain has a fourth connection hole. At this time, the connection electrode 27 is connected to the
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor
  • the second thin film transistor 30 is a bottom gate thin film transistor.
  • the first isolation barrier 50 includes a third portion 51 and a fourth portion 52, and the third portion 51 covers The first interlayer insulating layer 24 of the first thin film transistor 20 is located in the first region 11 , surrounds the edge and the side surface of the first thin film transistor 20 , and the first gate insulating layer 22 of the first thin film transistor 20 surrounds the first thin film a side surface of the transistor 20; a second via hole is disposed in a region corresponding to the third portion 51 of the second gate insulating layer 32, and the third via hole surrounds the first thin film transistor 20, and the fourth portion 52 of the first isolation barrier 50 is filled a third via hole is in contact with the third portion 51, and the third portion 51 and the fourth portion 52 collectively surround the first thin film transistor 20 to isolate the first thin film transistor 20 from the second thin film transistor 30; likewise, A thin film transistor 20 further includes a connection electrode
  • connection electrode 27 is connected to the first source 25 through the third connection hole.
  • the second gate insulating layer 32 and A region corresponding to the drain 26 has a fourth connection hole.
  • the connection electrode 27 is connected to the first drain 26 through the fourth connection hole to facilitate the first source 25 or the first drain of the first thin film transistor 20. 26 is connected to other structures.
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor
  • the second thin film transistor 30 is a bottom gate thin film transistor
  • the second thin film transistor 30 is a second gate insulating layer 32.
  • the first thin film transistor 20 is covered. Therefore, when the thin film transistor structure provided by the embodiment of the present disclosure is fabricated, the first thin film transistor 20 may be formed on the base substrate 10, and then the second thin film transistor 30 may be formed on the base substrate 10.
  • the second gate insulating layer 32 is formed before the second active layer 33, that is, the second gate insulating layer 32 is formed first, and the second gate insulating layer 32 is used to form the base substrate. 10.
  • the second gate electrode 31 and the first thin film transistor 20 are completely covered, and then the second active layer 33 is formed.
  • the second active layer 33 is formed in the process of forming the second active layer 33, for example, in forming the second active layer 33.
  • the second gate insulating layer 32 may block diffusion of hydrogen in the first active layer 21 of the first thin film transistor 20 toward the second active layer 33, thereby preventing the second thin film transistor 30 from being formed. Performance adversely affects .
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor
  • the second thin film transistor 30 is a bottom gate thin film transistor
  • the second gate insulating layer 32 of the second thin film transistor 30 covers the first thin film transistor 20, and thus, when manufacturing the present disclosure
  • the first thin film transistor 20 may be formed on the base substrate 10
  • the second thin film transistor 30 may be formed on the base substrate 10
  • the second The gate insulating layer 32 is formed prior to the second active layer 33, that is, the second gate insulating layer 32 is formed first
  • the second gate insulating layer 32 places the base substrate 10, the second gate 31, and the first thin film transistor 20.
  • the second active layer 33 is completely covered, and then the process of forming the first active layer 21 of the first thin film transistor 20 and the process of forming the second active layer 33 of the second thin film transistor 30 can be prevented from interfering with each other. .
  • the material of the first isolation retaining wall 50 and the material of the second insulating retaining wall 40 may be various, and the material of the first insulating retaining wall 50 and the material of the second insulating retaining wall 40 only need to have Better hydrogen resistance can be achieved.
  • the material of the first isolation barrier 50 may be an organic material, that is, the first isolation barrier 50 is an organic material first isolation barrier 50, for example, the organic material may be polyethylene (PE); or
  • the material of the first isolation barrier 50 may be an inorganic material, that is, the first isolation barrier 50 is an inorganic material first isolation barrier 50.
  • the inorganic material may be aluminum oxide (Al 2 O 3 ), silicon nitride (SiNx), or the like;
  • the material of the first isolation barrier 50 may be metal, that is, the first isolation barrier 50 is a metal first isolation barrier 50.
  • the first isolation barrier 50 includes a third portion 51.
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor
  • the second thin film transistor 30 is a bottom gate thin film transistor.
  • the first region 11 is first formed in the first region 11 on the substrate substrate 10.
  • the thin film transistor 20 can simultaneously form the third portion 51 of the first isolation barrier 50, that is, the first isolation, when forming the first source and the drain of the first thin film transistor 20, that is, the first source 25 and the first drain 26.
  • the third portion 51 of the retaining wall 50 and the first thin film transistor 2 The first source and drain electrodes of 0 are simultaneously formed.
  • the third portion 51 of the first isolation barrier 50 and the first source and drain of the first thin film transistor 20 are formed by one patterning process, and the first isolation barrier 50 is The material of the third portion 51 is the same as the material of the first source and drain of the first thin film transistor 20, and then the second thin film transistor 30 is formed in the second region 12 on the base substrate 10, and the second thin film transistor 30 is formed.
  • a third via surrounding the first thin film transistor 20 is formed in the second gate insulating layer 32 of the second thin film transistor 30, and a second via is formed.
  • the fourth portion 52 of the first isolation barrier 50 that is, the fourth portion 52 of the first isolation barrier 50 can be simultaneously formed.
  • the fourth portion 52 of the first isolation barrier 50 and the second source and drain of the second thin film transistor 30 are formed by one patterning process, first The material of the fourth portion 52 of the isolation barrier 50 and the second source and drain of the second thin film transistor 30 The same material.
  • the material of the second isolation retaining wall 40 may be an organic material, that is, the second insulating retaining wall 40 is a second insulating retaining wall 40 of organic material, for example, the organic material may be polyethylene (PE); or
  • the material of the second isolation retaining wall 40 may be an inorganic material, that is, the second insulating retaining wall 40 is a second insulating retaining wall 40 of inorganic material.
  • the inorganic material may be aluminum oxide (Al 2 O 3 ), silicon nitride (SiNx), or the like;
  • the material of the second isolation retaining wall 40 may be metal, that is, the second insulating retaining wall 40 is a metal second insulating retaining wall 40.
  • the structure of the second insulating retaining wall 40 is a whole.
  • the first thin film transistor 20 is a low temperature polysilicon thin film transistor
  • the second thin film transistor 30 is a bottom gate thin film transistor.
  • the first thin film transistor 20 is first formed in the first region 11 on the base substrate 10.
  • a second thin film transistor 30 in the second region 12 on the base substrate 10, wherein before forming the second source drain of the second thin film transistor 30, that is, the second source 34 and the second drain 35, Second thin film transistor 30 A first via surrounding the second thin film transistor 30 is formed in the gate insulating layer 32.
  • the first via can be simultaneously formed.
  • the second isolation barrier 40 that is, the second isolation barrier 40 is formed simultaneously with the second source and drain of the second thin film transistor 30, and can also be understood as the second isolation drain 40 and the second source and drain of the second thin film transistor 30.
  • the material of the second isolation barrier 40 is the same as the material of the second source and drain of the second thin film transistor 30; please continue to refer to FIG. 2, the structure of the second isolation barrier 40 includes the first portion 41 and In the second portion 42, the first thin film transistor 20 is a low temperature polysilicon thin film transistor, and the second thin film transistor 30 is a bottom gate thin film transistor.
  • a first thin film is first formed in the first region 11 on the base substrate 10.
  • the transistor 20 can simultaneously form the first portion 41 of the second isolation retaining wall 40, that is, the second isolation block, when the first source drain 25 and the first drain electrode 26 of the first thin film transistor 20 are formed.
  • the first portion 41 of the wall 40 and the first thin film transistor 2 The first source and drain electrodes of 0 are simultaneously formed. It can also be understood that the first portion 41 of the second isolation barrier 40 and the first source and drain of the first thin film transistor 20 are formed by one patterning process, and the second isolation barrier 40 is formed.
  • the material of the first portion 41 is the same as the material of the first source and drain of the first thin film transistor 20, and then the second thin film transistor 30 is formed in the second region 12 on the base substrate 10, and the second thin film transistor 30 is formed.
  • a second via surrounding the second thin film transistor 30 is formed in the second gate insulating layer 32 of the second thin film transistor 30, and a second via is formed.
  • the second portion 42 of the second isolation barrier 40 and the second source and drain of the second thin film transistor 30 are formed by one patterning process, and the second The material of the second portion 42 of the isolation barrier 40 and the second source and drain of the second thin film transistor 30 The same material.
  • the embodiment of the present disclosure further provides a display panel including the thin film transistor structure as described in the above embodiments.
  • the display panel may be a liquid crystal display panel or an organic light emitting diode display panel
  • the display panel includes a plurality of pixel units, each of which is provided with the above thin film transistor structure, by at least surrounding the first or second thin film transistor
  • An isolation barrier of the active layer for example, an isolation barrier surrounding the first and/or second thin film transistors, can prevent hydrogen in the first thin film transistor in the same pixel unit from being in the first thin film transistor to the second transistor influences.
  • An embodiment of the present disclosure further provides a display device including the display panel as described in the above embodiments.
  • an embodiment of the present disclosure further provides a method for fabricating a thin film transistor structure according to the above embodiments, including:
  • first thin film transistor and a second thin film transistor Forming a first thin film transistor and a second thin film transistor, and a first isolation barrier or/and a second isolation barrier on the base substrate, wherein the first active layer of the first thin film transistor is doped with hydrogen;
  • the material of the second active layer of the thin film transistor is a metal oxide;
  • the first isolation barrier surrounds at least the first active layer of the first thin film transistor, and the second isolation barrier surrounds at least the second thin film transistor Two active layers.
  • the manufacturing method includes: step S1, forming a first thin film transistor and a second thin film transistor on a base substrate, and a first isolation barrier or/and a second isolation barrier, wherein the first thin film transistor
  • the first active layer is doped with hydrogen
  • the second active layer of the second thin film transistor is made of a metal oxide
  • the first isolation barrier surrounds at least the first active layer of the first thin film transistor
  • the second isolation The retaining wall surrounds at least the second active layer of the second thin film transistor.
  • the first thin film transistor is a low temperature polysilicon thin film transistor
  • the second thin film transistor is a bottom gate thin film transistor
  • Step S100 forming a first thin film transistor on the base substrate.
  • Step S200 forming a second thin film transistor and a second isolation barrier surrounding the second thin film transistor on the base substrate.
  • step S100 forming a first thin film transistor on the substrate, may include:
  • Step S110 forming a first active layer of the first thin film transistor.
  • step S110 a polysilicon layer is deposited on the base substrate 10, the polysilicon layer is a low temperature polysilicon layer, and the low temperature polysilicon layer is doped with hydrogen; and then formed by a patterning process.
  • the first active layer 21 of the first thin film transistor 20, the first active layer 21 is located on the base substrate 10 to form the first region 11 of the first thin film transistor 20.
  • Step S120 forming a first gate insulating layer of the first thin film transistor.
  • a first gate insulating film layer is deposited on the base substrate 10 and the first active layer 21 to form a first gate insulating layer 22, first.
  • the gate insulating layer 22 covers the base substrate 10 and the first active layer 21.
  • Step S130 forming a first gate of the first thin film transistor.
  • step S130 a first metal layer is first deposited on the first gate insulating layer 22; then, a first gate of the first thin film transistor 20 is formed by a patterning process. 23, the first gate 23 is located in the first region 11 of the base substrate 10 above the first active layer 21.
  • Step S140 forming a first interlayer insulating layer of the first thin film transistor.
  • step S140 a first interlayer insulating film layer is deposited on the first gate insulating layer 22 and the first gate electrode 23 to form a first interlayer insulating layer 24.
  • the first interlayer insulating layer 24 covers the first gate insulating layer 22 and the first gate electrode 23.
  • Step S150 forming an exposed hole, a first connection hole and a second connection hole penetrating through the first interlayer insulating layer and the first gate insulating layer, the exposed hole exposing a region on the substrate substrate where the second thin film transistor is formed, first Both the connection hole and the second connection hole expose the first active layer.
  • step S150 the exposure hole 241, the first connection hole 242 and the second connection hole 243 are formed by a patterning process, wherein the exposure hole 241 penetrates the first interlayer insulation layer. And a first gate insulating layer 22, and exposing a region of the base substrate 10 on which the second thin film transistor 30 is formed to facilitate subsequent formation of the second thin film transistor 30 on the base substrate 10; the first connection hole 242 and the The two connection holes 243 respectively penetrate the first interlayer insulating layer 24 and the first gate insulating layer 22, and both expose the first active layer 21 to facilitate the formation of the first source and drain of the first source and the source 15 and The first drain 26 is connected to the first active layer 21, respectively.
  • Step S160 forming a first source drain of the first thin film transistor and a second gate of the second thin film transistor, wherein the first source drain includes a first source and a first drain, and the first source passes the first
  • the connection hole is connected to the first active layer
  • the first drain is connected to the first active layer through the second connection hole
  • the second gate is located on the substrate substrate and exposed in the hole.
  • step S160 a second metal layer is first deposited; then, a first source drain of the first thin film transistor 20 and a second thin film transistor 30 are simultaneously formed by a patterning process. a second gate 31, wherein the first source 25 of the first source and drain is connected to the first active layer 21 through the first connection hole 242, and the first drain 26 passes through the second connection hole 243 and the first active layer 21 is connected; the second gate 31 is located on the base substrate 10 and exposed in the hole 241.
  • the first source drain of the first thin film transistor 20 and the second gate 31 of the second thin film transistor 30 are formed by one patterning process, thereby reducing the number of process steps for fabricating the thin film transistor structure while reducing the fabrication of the thin film transistor The number of masks used in the structure, which in turn reduces the cost of fabricating the thin film transistor structure.
  • step S200 forming a second thin film transistor on the substrate and a second isolation barrier surrounding the second thin film transistor may include:
  • Step S210 forming a second gate insulating layer of the second thin film transistor.
  • step S210 a second gate insulating film layer is deposited to form a second gate insulating layer 32, and the second gate insulating layer 32 covers the first thin film transistor 20 and the lining.
  • Step S220 forming a second active layer of the second thin film transistor.
  • a metal oxide film layer may be deposited on the second gate insulating layer 32; then, a second thin film transistor 30 is formed by a patterning process.
  • the source layer 33 and the second active layer 33 are located above the second gate 31.
  • Step S230 forming a first via hole surrounding the second thin film transistor and exposing the base substrate in the second gate insulating layer, and a third connection hole corresponding to the first source of the first thin film transistor or corresponding to the first a fourth connection hole of the first drain of the thin film transistor.
  • a first via hole 321 is formed in the second gate insulating layer 32 by a patterning process, and the first via hole 321 surrounds the second thin film transistor 30, A via 321 exposes the base substrate 10 to subsequently form a second isolation barrier 40 surrounding the second thin film transistor 30.
  • a third connection hole is formed in the second gate insulating layer 32 by a patterning process, and the third connection hole corresponds to the first source of the first thin film transistor 20 .
  • a fourth connection hole may be formed in the second gate insulating layer 32 by a patterning process. 324.
  • the fourth connection hole 324 corresponds to the first drain electrode 26 of the first thin film transistor 20 to facilitate connecting the first drain electrode 26 and other structures through the subsequently formed connection electrode 27.
  • Step S240 forming a second source and drain of the second thin film transistor, filling a second isolation barrier in the first via hole, and connecting the first source through the third connection hole or connecting the first drain through the fourth connection hole
  • the pole is connected to the electrode.
  • a third metal layer is deposited first; then, a second isolation barrier 40, a second source drain of the second thin film transistor 30, and a second isolation gate are simultaneously formed by a patterning process.
  • the pole includes a second source 34 and a second drain 35.
  • the second source 34 and the second drain 35 are respectively in contact with the second active layer 33; the connection electrode 27 is located on the second gate insulating layer 32, and the connection electrode 27 is connected to the first source 25 through a third connection hole, or the connection electrode 27 is connected to the first drain 26 through the fourth connection hole 324. That is, the second isolation barrier 40, the second source drain, and the connection electrode 27 are formed by one patterning process, thereby reducing the number of process steps for fabricating the thin film transistor structure while reducing the mask used in fabricating the thin film transistor structure. The number of plates, which in turn reduces the cost of fabricating thin film transistor structures.
  • the first thin film transistor is a low temperature polysilicon thin film transistor
  • the second thin film transistor is a bottom gate thin film transistor
  • the second isolation barrier includes a plurality of portions, for example, the second isolation barrier includes a first portion and a second portion, that is, a second isolation barrier
  • Step S1 forming a first thin film transistor, a second thin film transistor, and a second isolation barrier on the substrate, which may include:
  • Step S300 forming a first portion of the first thin film transistor and the second isolation barrier on the base substrate, the first portion covering the edge and the side of the first thin film transistor surrounding the second thin film transistor.
  • Step S400 forming a second portion of the second thin film transistor and the second isolation barrier on the base substrate, the second portion being located on the first portion, the first portion and the second portion collectively surrounding the second thin film transistor.
  • step S300 forming the first portion of the first thin film transistor and the second isolation barrier on the base substrate may include:
  • Step S310 forming a first active layer of the first thin film transistor.
  • step S310 a polysilicon layer is deposited on the base substrate 10, the polysilicon layer is a low temperature polysilicon layer, and the low temperature polysilicon layer is doped with hydrogen; and then, through a patterning process, The first active layer 21 of the first thin film transistor 20 is formed, and the first active layer 21 is located on the base substrate 10 to form the first region 11 of the first thin film transistor 20.
  • Step S320 forming a first gate insulating layer of the first thin film transistor.
  • step S320 a first gate insulating film layer is deposited on the base substrate 10 and the first active layer 21 to form a first gate insulating layer 22, first.
  • the gate insulating layer 22 covers the base substrate 10 and the first active layer 21.
  • Step S330 forming a first gate of the first thin film transistor.
  • step S330 a first metal layer is first deposited on the first gate insulating layer 22; then, a first gate of the first thin film transistor 20 is formed by a patterning process. 23, the first gate 23 is located in the first region 11 of the base substrate 10 above the first active layer 21.
  • Step S340 forming a first interlayer insulating layer of the first thin film transistor.
  • a first interlayer insulating film layer is deposited on the first gate insulating layer 22 and the first gate 23 to form a first interlayer insulating layer 24,
  • the first interlayer insulating layer 24 covers the first gate insulating layer 22 and the first gate electrode 23.
  • Step S350 forming an exposure hole penetrating through the first interlayer insulating layer and the first gate insulating layer, a first connection hole and a second connection hole, the exposure hole exposing a region on the substrate substrate where the second thin film transistor is formed, first Both the connection hole and the second connection hole expose the first active layer.
  • an exposure hole 241 , a first connection hole 242 and a second connection hole 243 are formed through a patterning process, wherein the exposure hole 241 penetrates the first interlayer insulation layer And a first gate insulating layer 22, and exposing a region of the base substrate 10 on which the second thin film transistor 30 is formed to facilitate subsequent formation of the second thin film transistor 30 on the base substrate 10; the first connection hole 242 and the The two connection holes 243 respectively penetrate the first interlayer insulating layer 24 and the first gate insulating layer 22, and both expose the first active layer 21 to facilitate the formation of the first source and drain of the first source and the source 15 and The first drain 26 is connected to the first active layer 21, respectively.
  • Step S360 forming a first source drain of the first thin film transistor, a second gate of the second thin film transistor, and a first portion of the second isolation barrier, wherein the first source drain includes the first source and the first a drain, the first source is connected to the first active layer through the first connection hole, and the first drain is connected to the first active layer through the second connection hole; the first portion covers the edge of the exposed hole and the hole wall;
  • the second gate is on the substrate substrate and is exposed in the hole.
  • step S360 a second metal layer is first deposited; then, a first source and a drain of the first thin film transistor 20 and a second thin film transistor 30 are simultaneously formed by a patterning process.
  • the first portion 41 of the second gate 31 and the second isolation barrier 40 wherein, in the first source and drain, the first source 25 is connected to the first active layer 21 through the first connection hole 242, the first drain 26 is connected to the first active layer 21 through the second connection hole 243; the first portion 41 of the second isolation retaining wall 40 covers the edge of the exposed hole 241 and the hole wall, specifically, the first portion 41 covers the first interlayer insulation
  • the layer 24 corresponds to the edge of the exposure hole 241
  • the first interlayer insulating layer 24 corresponds to the side surface of the exposure hole 241
  • the first gate insulating layer 22 corresponds to the side surface of the exposure hole 241;
  • the second gate electrode 31 is located on the base substrate 10 Upper and exposed holes 241.
  • the first source and drain of the first thin film transistor 20, the second gate 31 of the second thin film transistor 30, and the first portion 41 of the second isolation barrier 40 are formed by one patterning process, thereby reducing the number of thin films.
  • the process steps of the transistor structure reduce the number of masks used in fabricating the thin film transistor structure, thereby reducing the cost of fabricating the thin film transistor structure.
  • step S400 forming a second portion of the second thin film transistor and the second isolation barrier on the base substrate may include:
  • Step S410 forming a second gate insulating layer of the second thin film transistor.
  • step S410 a second gate insulating film layer is deposited to form a second gate insulating layer 32, and the second gate insulating layer 32 covers the first thin film transistor 20 and the lining.
  • Step S420 forming a second active layer of the second thin film transistor.
  • a metal oxide film layer may be deposited on the second gate insulating layer 32; then, a second thin film transistor 30 is formed by a patterning process.
  • the source layer 33 and the second active layer 33 are located above the second gate 31.
  • Step S430 forming a second via hole surrounding the second thin film transistor and corresponding to the first portion in the second gate insulating layer, and a third connection hole corresponding to the first source of the first thin film transistor or corresponding to the first a fourth connection hole of the first drain of the thin film transistor.
  • a second via hole 322 is formed in the second gate insulating layer 32 by a patterning process, and the second via hole 322 surrounds the second thin film transistor 30,
  • the second via 322 exposes the first portion 41 of the first isolation barrier 40 to subsequently form the second portion 42 of the second isolation barrier 40 surrounding the second thin film transistor 30.
  • a third connection hole is further formed in the second gate insulating layer 32 by a patterning process, and the third connection hole corresponds to the first source electrode 25 of the first thin film transistor 20 to facilitate the connection formed through the subsequent formation.
  • the electrode 27 connects the first source 25 and other structures; or, by a patterning process, a fourth connection hole 324 is formed in the second gate insulating layer 32, and the fourth connection hole 324 corresponds to the first thin film transistor 20
  • a drain 26 is provided to facilitate connection of the first drain 26 to other structures through subsequently formed connection electrodes 27.
  • Step S440 forming a second source drain of the second thin film transistor, filling a second portion in the second via hole and contacting the first portion, and connecting the first source through the third connection hole or through the fourth connection hole A connection electrode that connects the first drain.
  • a third metal layer is first deposited; then, a second portion 42 of the second isolation barrier 40 and a second thin film transistor 30 are simultaneously formed by a patterning process.
  • a two-source drain and a connection electrode 27 of the first thin film transistor 20 wherein the second portion 42 is filled in the second via hole 322, and the second portion 42 is in contact with the first portion 41, the first portion 41 and the second portion 42
  • the second isolation barrier 40 is formed to surround the second thin film transistor 30 to isolate the second thin film transistor 30 from the first thin film transistor 20;
  • the second source and drain of the second thin film transistor 30 includes the second source 34 and The second drain 35, the second source 34 and the second drain 35 are respectively in contact with the second active layer 33;
  • the connection electrode 27 is located on the second gate insulating layer 32, and the connection electrode 27 is connected to the first through the third connection hole.
  • the source 25 or the connection electrode 27 is connected to the first drain 26 through the fourth connection hole 324. That is, the second portion 42, the second source drain, and the connection electrode 27 of the second isolation barrier 40 are formed by one patterning process, thereby reducing the number of process steps for fabricating the thin film transistor structure while reducing the fabrication of the thin film transistor structure. The number of masks used, which in turn reduces the cost of fabricating thin film transistor structures.
  • the first thin film transistor is a low temperature polysilicon thin film transistor
  • the second thin film transistor is a bottom gate thin film transistor
  • the first isolation barrier includes a plurality of portions, for example, the first isolation barrier includes a third portion and a fourth portion, that is, the first isolation barrier
  • Step S500 forming a first thin film transistor and a third portion of the first isolation barrier on the base substrate, and the third portion covering the first insulating layer of the first thin film transistor surrounds an edge and a side surface of the first thin film transistor.
  • Step S600 forming a second thin film transistor and a fourth portion of the first isolation barrier on the base substrate, the fourth portion is located on the third portion, and the third portion and the fourth portion collectively surround the first thin film transistor.
  • the step S500, forming the first thin film transistor and the third portion of the first isolation barrier on the base substrate may include:
  • Step S510 forming a first active layer of the first thin film transistor.
  • step S510 a polysilicon layer is deposited on the base substrate 10, the polysilicon layer is a low temperature polysilicon layer, and the low temperature polysilicon layer is doped with hydrogen; and then, through a patterning process, The first active layer 21 of the first thin film transistor 20 is formed, and the first active layer 21 is located on the base substrate 10 to form the first region 11 of the first thin film transistor 20.
  • Step S520 forming a first gate insulating layer of the first thin film transistor.
  • a first gate insulating film layer is deposited on the base substrate 10 and the first active layer 21 to form a first gate insulating layer 22, first The gate insulating layer 22 covers the base substrate 10 and the first active layer 21.
  • Step S530 forming a first gate of the first thin film transistor.
  • a first metal layer is first deposited on the first gate insulating layer 22; then, a first gate of the first thin film transistor 20 is formed by a patterning process. 23, the first gate 23 is located in the first region 11 of the base substrate 10 above the first active layer 21.
  • Step S540 forming a first interlayer insulating layer of the first thin film transistor.
  • step S540 a first interlayer insulating film layer is deposited on the first gate insulating layer 22 and the first gate electrode 23 to form a first interlayer insulating layer 24,
  • the first interlayer insulating layer 24 covers the first gate insulating layer 22 and the first gate electrode 23.
  • Step S550 removing the first gate insulating layer and the first interlayer insulating layer on a portion of the substrate other than the region where the first thin film transistor is formed, and forming the first interlayer insulating layer and the first gate insulating layer.
  • a first connection hole and a second connection hole wherein sides of the first gate insulating layer and the first interlayer insulating layer are located in a region where the base substrate forms the first thin film transistor; the first connection hole and the second connection hole are both The first active layer is exposed.
  • step S550 the first gate insulating layer 22 and the first interlayer insulating layer 24 are disposed on the base substrate 10 to form the first thin film transistor 20 by a patterning process.
  • the portion other than the first region 11 is removed, that is, the portion where the first gate insulating layer 22 and the first interlayer insulating layer 24 are located outside the first region 11 is removed, and the first connection hole 242 and the second connection hole 243 are formed.
  • the first gate insulating layer 22 covers only the first active layer 21 and the base substrate 10 located in the first region 11.
  • the first interlayer insulating layer 24 covers the first gate 23 and the first gate insulating layer.
  • the layer 22, the first gate insulating layer 22 and the first interlayer insulating layer 24 each have a side surrounding the first thin film transistor 20; the first connection hole 242 and the second connection hole 243 respectively penetrate the first interlayer insulating layer 24 and The first gate insulating layer 22 is exposed to the first active layer 21 to facilitate the formation of the first source drain and the first drain 26 of the first source drain and the first active layer 21 respectively.
  • the connection between the two is not limited to the two.
  • Step S560 forming a first source drain of the first thin film transistor, a second gate of the second thin film transistor, and a third portion of the first isolation barrier, wherein the first source drain includes the first source and the first a drain, the first source is connected to the first active layer through the first connection hole, the first drain is connected to the first active layer through the second connection hole; the third portion covers the edge of the first interlayer insulating layer and a side surface and a side surface of the first gate insulating layer; the second gate electrode is on the substrate substrate.
  • a second metal layer is deposited first; then, a first source and a drain of the first thin film transistor 20 and a second thin film transistor 30 are simultaneously formed by a patterning process.
  • the second gate 31 and the third portion 51 of the first isolation barrier 50 wherein, in the first source and drain, the first source 25 is connected to the first active layer 21 through the first connection hole 242, the first drain 26 is connected to the first active layer 21 through the second connection hole 243; the third portion 51 of the first isolation barrier 50 covers the edge and the side of the first interlayer insulating layer 24, and the side of the first gate insulating layer 22
  • the second gate 31 is located on the base substrate 10 in the second region 12.
  • the first source and drain of the first thin film transistor 20, the second gate 31 of the second thin film transistor 30, and the third portion 51 of the first isolation barrier 50 are formed by one patterning process, thereby reducing the number of thin films.
  • the process steps of the transistor structure reduce the number of masks used in fabricating the thin film transistor structure, thereby reducing the cost of fabricating the thin film transistor structure.
  • step S600 forming a second thin film transistor and a fourth portion of the first isolation barrier on the base substrate may include:
  • Step S610 forming a second gate insulating layer of the second thin film transistor.
  • a second gate insulating film layer is deposited to form a second gate insulating layer 32, and the second gate insulating layer 32 covers the first thin film transistor 20 and the lining.
  • Step S620 forming a second active layer of the second thin film transistor.
  • a metal oxide film layer may be deposited on the second gate insulating layer 32; then, a second thin film transistor 30 is formed by a patterning process.
  • the source layer 33 and the second active layer 33 are located above the second gate 31.
  • Step S630 forming a third via hole surrounding the first thin film transistor and corresponding to the third portion in the second gate insulating layer, and a third connection hole corresponding to the first source of the first thin film transistor or corresponding to the first a fourth connection hole of the first drain of the thin film transistor.
  • a third via 323 is formed in the second gate insulating layer 32 by a patterning process, and the third via 323 surrounds the first thin film transistor 20 ,
  • the three vias 323 expose the third portion 51 of the first isolation barrier 50 to subsequently form the fourth portion 52 of the first isolation barrier 50 surrounding the first thin film transistor 20.
  • a third connection hole is further formed in the second gate insulating layer 32 by a patterning process, and the third connection hole corresponds to the first source electrode 25 of the first thin film transistor 20 to facilitate the connection formed through the subsequent formation.
  • the electrode 27 connects the first source 25 and other structures; or, by a patterning process, a fourth connection hole 324 is formed in the second gate insulating layer 32, and the fourth connection hole 324 corresponds to the first thin film transistor 20
  • a drain 26 is provided to facilitate connection of the first drain 26 to other structures through subsequently formed connection electrodes 27.
  • Step S640 forming a second source drain of the second thin film transistor, filling a fourth portion in the third via hole and contacting the third portion, and connecting the first source through the third connection hole or through the fourth connection hole A connection electrode that connects the first drain.
  • a third metal layer is deposited first; then, a fourth portion 52 of the first isolation barrier 50 and a second thin film transistor 30 are simultaneously formed by a patterning process.
  • the two source drains and the connection electrode 27 of the first thin film transistor 20, wherein the fourth portion 52 is filled in the third via hole 323, the fourth portion 52 is in contact with the third portion 51, and the third portion 51 and the fourth portion 52 are
  • the first isolation barrier 50 is formed to surround the first thin film transistor 20 to isolate the second thin film transistor 30 from the first thin film transistor 20;
  • the second source and drain of the second thin film transistor 30 includes the second source 34 and The second drain 35, the second source 34 and the second drain 35 are respectively in contact with the second active layer 33;
  • the connection electrode 27 is located on the second gate insulating layer 32, and the connection electrode 27 is connected to the first through the third connection hole.
  • the source 25 or the connection electrode 27 is connected to the first drain 26 through the fourth connection hole 324. That is, the fourth portion 52 of the first isolation barrier 50, the second source drain, and the connection electrode 27 are formed by one patterning process, thereby reducing the number of process steps for fabricating the thin film transistor structure while reducing the fabrication of the thin film transistor structure. The number of masks used, which in turn reduces the cost of fabricating thin film transistor structures.
  • the manufacturing methods of the first isolation barrier 50 and the second isolation barrier 40 can be referred to the above embodiments, respectively.
  • the first isolation retaining wall 50 has the structure shown in FIG. 3 and the second insulating retaining wall 40 has the structure shown in FIG. 1, it can be formed in the manufacturing method with reference to FIGS. 15 and 16 and FIGS. 7 and 8.
  • the filling holes of the second isolation retaining wall 40 may be formed together when forming the second portion of the first insulating retaining wall 50.
  • the first isolation retaining wall 50 has the structure shown in FIG. 3 and the second insulating retaining wall 40 has the structure shown in FIG.
  • An isolation retaining wall 50 and a second insulating retaining wall 40 may share the opposing retaining wall at the junction of the two, or, at the junction of the two, the third portion of the first insulating retaining wall 50 may be in the second insulating retaining wall.
  • the first portion is formed later, or the third portion of the first isolation barrier 50 may be formed before the first portion of the second isolation barrier, and the third portion or the first portion formed thereafter may be perpendicular to the substrate Part or all of the first or third portion is covered in the direction, that is, overlapped in a direction perpendicular to the substrate.
  • the third portion or the first portion formed later may not cover the previously formed first portion or the third portion in a direction perpendicular to the substrate substrate, but only in a direction parallel to the substrate substrate Stack.
  • Embodiments of the present disclosure are not limited thereto.

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Abstract

本公开提供一种薄膜晶体管结构及其制造方法、显示面板、显示装置。该薄膜晶体管结构包括衬底基板 (10)，及形成在衬底基板 (10) 上的第一薄膜晶体管 (20) 和第二薄膜晶体管 (30)，第一薄膜晶体管 (20) 的第一有源层(21) 掺杂有氢；第二薄膜晶体管 (30) 的第二有源层 (33) 的材料为金属氧化物；衬底基板 (10) 上还设置有环绕第一薄膜晶体管 (20) 的第一隔离挡墙(50) 或/和环绕第二薄膜晶体管 (30) 的第二隔离挡墙 (40)。第一隔离挡墙(50) 或/和第二隔离挡墙 (40) 将第二薄膜晶体管 (30) 与第一薄膜晶体管 (20)隔离，以隔离第一薄膜晶体管 (20) 的第一有源层 (21) 中的氢，防止第一有源层 (21) 中的氢对第二薄膜晶体管 (30) 造成不良影响。

Description

薄膜晶体管结构及其制造方法、显示面板、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种薄膜晶体管结构及其制造方法、显示面板、显示装置。
背景技术
薄膜晶体管作为重要的开关控制元件，在显示装置中起着关键性作用。在现有技术中，为了使显示装置具有良好的画面显示质量，通常在显示装置的显示面板内设置薄膜晶体管结构，该薄膜晶体管结构包括两种类型的薄膜晶体管，其中一种薄膜晶体管具有迁移率高、充电快的优势，另一种薄膜晶体管具有漏电流低的优势，例如，在有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板中，通常会设置薄膜晶体管结构，薄膜晶体管结构包括第一薄膜晶体管和第二薄膜晶体管，第一薄膜晶体管为低温多晶硅薄膜晶体管，第二薄膜晶体管为金属氧化物薄膜晶体管，当设置有OLED显示面板的显示装置显示画面时，利用第一薄膜晶体管的迁移率高、充电快的优势，以及第二薄膜晶体管的漏电流低的优势，对OLED显示面板内的OLED器件进行驱动，以使显示装置具有良好的画面显示质量。
然而，在显示面板内同时设置具有迁移率高、充电快优势的第一薄膜晶体管和具有漏电流低的第二薄膜晶体管时，第一薄膜晶体管的有源层通常掺杂有氢(例如低温多晶硅薄膜晶体管)，第二薄膜晶体管通常为金属氧化物薄膜晶体管，即第二薄膜晶体管的有源层的材料为金属氧化物，而作为第二薄膜晶体管的有源层的金属氧化物对氢非常敏感，因此，当在显示面板内同时设置具有迁移率高、充电快优势的第一薄膜晶体管和具有漏电流低的第二薄膜晶体管时，第一薄膜晶体管的有源层中的氢可能扩散至第二薄膜晶体管的有源层，对第二薄膜晶体管的有源层造成不良影响，进而对第二薄膜晶体管的性能造成不良影响。
发明内容
本公开的目的在于提供一种薄膜晶体管结构，用于防止第一薄膜晶体管的有源层中的氢扩散至第二薄膜晶体管的有源层而对第二薄膜晶体管的性能 造成不良影响。
第一方面，本公开提供一种薄膜晶体管结构，包括衬底基板，以及形成在所述衬底基板上的第一薄膜晶体管和第二薄膜晶体管，其中，所述第一薄膜晶体管的第一有源层掺杂有氢；所述第二薄膜晶体管的第二有源层的材料为金属氧化物；所述衬底基板上还设置有环绕所述第一薄膜晶体管的第一隔离挡墙或/和环绕所述第二薄膜晶体管的第二隔离挡墙。
示例性地，所述第二薄膜晶体管的第二栅极绝缘层覆盖所述第一薄膜晶体管，所述第二栅极绝缘层内设置有环绕所述第二薄膜晶体管的第一过孔，所述第二隔离挡墙填充所述第一过孔。
示例性地，所述第二隔离挡墙包括第一部和第二部，其中，所述第一部位于所述衬底基板上，且所述第一部覆盖所述第一薄膜晶体管的第一绝缘层的环绕所述第二薄膜晶体管的边缘和侧面；所述第二薄膜晶体管的第二栅极绝缘层覆盖所述第一薄膜晶体管和所述第一部，所述第二栅极绝缘层与所述第一部对应的区域设置有环绕所述第二薄膜晶体管的第二过孔，所述第二部填充所述第二过孔，且所述第二部与所述第一部接触。
示例性地，所述第一隔离挡墙包括第三部和第四部，其中，所述第三部位于所述衬底基板上，且所述第三部覆盖所述第一薄膜晶体管的第一绝缘层的环绕所述第一薄膜晶体管的边缘和侧面；所述第二薄膜晶体管的第二栅极绝缘层覆盖所述第一薄膜晶体管和所述第三部，所述第二栅极绝缘层与所述第三部对应的区域设置有环绕所述第一薄膜晶体管的第三过孔，所述第四部填充所述第三过孔，且所述第四部与所述第三部接触。
示例性地，所述第一薄膜晶体管为低温多晶硅薄膜晶体管，所述第二薄膜晶体管为底栅薄膜晶体管。
示例性地，所述第一薄膜晶体管包括位于所述第二栅极绝缘层上的连接电极，所述连接电极通过所述第二栅极绝缘层内的第一连接孔与所述第一薄膜晶体管中所述第一源漏极的漏极连接，或者，所述连接电极通过所述第二栅极绝缘层内的第二连接孔与所述第一薄膜晶体管中所述第一源漏极的源极连接。
示例性地，所述第一隔离挡墙为有机材料隔离挡墙、无机材料隔离挡墙或金属隔离挡墙；所述第二隔离挡墙为有机材料隔离挡墙、无机材料隔离挡墙或金属隔离挡墙。
示例性地，所述第一绝缘层包括所述第一薄膜晶体管的第一栅极绝缘层和覆盖所述第一薄膜晶体管的第一栅极的第一层间绝缘层。
示例性地，所述第三部覆盖所述第一薄膜晶体管的第一绝缘层的位于所述衬底基板上形成在所述第一薄膜晶体管的区域内且环绕所述第一薄膜晶体管的边缘和侧面包括：所述第三部覆盖所述第一薄膜晶体管的第一栅极绝缘层的位于所述衬底基板上形成在所述第一薄膜晶体管的区域内且环绕所述第一薄膜晶体管的侧面以及所述第三部覆盖所述第一薄膜晶体管的第一层间绝缘层的位于所述衬底基板上形成在所述第一薄膜晶体管的区域内且环绕所述第一薄膜晶体管的边缘和侧面。
第二方面，本公开提供一种显示面板，所述显示面板包括第一方面中任意所述的薄膜晶体管结构。
第三方面，本公开提供一种显示装置，所述显示装置包括第二方面中任意所述的显示面板。
第四方面，本公开提供一种薄膜晶体管结构的制造方法，包括：
在衬底基板上形成第一薄膜晶体管和第二薄膜晶体管，以及第一隔离挡墙或/和第二隔离挡墙，其中，所述第一薄膜晶体管的第一有源层掺杂有氢；所述第二薄膜晶体管的第二有源层的材料为金属氧化物；所述第一隔离挡墙环绕所述第一薄膜晶体管，所述第二隔离挡墙环绕所述第二薄膜晶体管。
示例性地，所述第一薄膜晶体管为低温多晶硅薄膜晶体管，所述第二薄膜晶体管为底栅薄膜晶体管；
在衬底基板上形成第一薄膜晶体管、第二薄膜晶体管和第二隔离挡墙，包括：
在所述衬底基板上形成所述第一薄膜晶体管；
在所述衬底基板上形成所述第二薄膜晶体管和环绕所述第二薄膜晶体管的第二隔离挡墙。
示例性地，在所述衬底基板上形成所述第一薄膜晶体管，包括：
形成所述第一薄膜晶体管的第一有源层；
形成所述第一薄膜晶体管的第一栅极绝缘层；
形成所述第一薄膜晶体管的第一栅极；
形成所述第一薄膜晶体管的第一层间绝缘层；
形成贯穿所述第一层间绝缘层和所述第一栅极绝缘层的暴露孔、第一连 接孔和第二连接孔，所述暴露孔暴露出所述衬底基板上形成所述第二薄膜晶体管的区域，所述第一连接孔和所述第二连接孔均暴露出所述第一有源层；
形成所述第一薄膜晶体管的第一源漏极和所述第二薄膜晶体管的第二栅极，其中，所述第一源漏极包括第一源极和第一漏极，所述第一源极通过所述第一连接孔与所述第一有源层连接，所述第一漏极通过所述第二连接孔与所述第一有源层连接；所述第二栅极位于所述衬底基板上、所述暴露孔内；
在所述衬底基板上形成所述第二薄膜晶体管和环绕所述第二薄膜晶体管的所述第二隔离挡墙，包括：
形成所述第二薄膜晶体管的第二栅极绝缘层；
形成所述第二薄膜晶体管的第二有源层；
在所述第二栅极绝缘层内形成环绕所述第二薄膜晶体管且暴露出所述衬底基板的第一过孔，以及对应于所述第一薄膜晶体管的第一源极的第三连接孔或对应于所述第一薄膜晶体管的第一漏极的第四连接孔；
形成所述第二薄膜晶体管的第二源漏极、填充在所述第一过孔内的所述第二隔离挡墙、以及通过所述第三连接孔连接所述第一源极或通过所述第四连接孔连接所述第一漏极的连接电极。
示例性地，所述第一薄膜晶体管为低温多晶硅薄膜晶体管，所述第二薄膜晶体管为底栅薄膜晶体管；
在衬底基板上形成第一薄膜晶体管、第二薄膜晶体管和第二隔离挡墙，包括：
在所述衬底基板上形成所述第一薄膜晶体管和所述第二隔离挡墙的第一部，所述第一部覆盖所述第一薄膜晶体管的第一绝缘层环绕所述第二薄膜晶体管的边缘和侧面；
在所述衬底基板上形成所述第二薄膜晶体管和所述第二隔离挡墙的第二部，所述第二部位于所述第一部上，所述第二部环绕所述第二薄膜晶体管。
示例性地，在所述衬底基板上形成所述第一薄膜晶体管和所述第二隔离挡墙的第一部，包括：
形成所述第一薄膜晶体管的第一有源层；
形成所述第一薄膜晶体管的第一栅极绝缘层；
形成所述第一薄膜晶体管的第一栅极；
形成所述第一薄膜晶体管的第一层间绝缘层；
形成贯穿所述第一层间绝缘层和所述第一栅极绝缘层的暴露孔、第一连接孔和第二连接孔，所述暴露孔暴露出所述衬底基板上形成所述第二薄膜晶体管的区域，所述第一连接孔和所述第二连接孔均暴露出所述第一有源层；
形成第一薄膜晶体管的第一源漏极、所述第二薄膜晶体管的第二栅极和所述第二隔离挡墙的第一部，其中，所述第一源漏极包括第一源极和第一漏极，所述第一源极通过所述第一连接孔与所述第一有源层连接，所述第一漏极通过所述第二连接孔与所述第一有源层连接；所述第一部覆盖所述暴露孔的边缘和孔壁；所述第二栅极位于所述衬底基板上、所述暴露孔内；
在所述衬底基板上形成所述第二薄膜晶体管和所述第二隔离挡墙的第二部，包括：
形成所述第二薄膜晶体管的第二栅极绝缘层；
形成所述第二薄膜晶体管的第二有源层；
在所述第二栅极绝缘层内形成环绕所述第二薄膜晶体管且对应于所述第一部的第二过孔，以及对应于所述第一薄膜晶体管的第一源极的第三连接孔或对应于所述第一薄膜晶体管的第一漏极的第四连接孔；
形成所述第二薄膜晶体管的第二源漏极、填充在所述第二过孔内且与所述第一部接触的第二部、以及通过所述第三连接孔连接所述第一源极或通过所述第四连接孔连接所述第一漏极的连接电极。
示例性地，所述第一薄膜晶体管为低温多晶硅薄膜晶体管，所述第二薄膜晶体管为底栅薄膜晶体管；
在衬底基板上形成第一薄膜晶体管、第二薄膜晶体管和第一隔离挡墙，包括：
在所述衬底基板上形成所述第一薄膜晶体管和所述第一隔离挡墙的第三部，所述第三部覆盖所述第一薄膜晶体管的第一绝缘层的环绕所述第一薄膜晶体管的边缘和侧面；
在所述衬底基板上形成所述第二薄膜晶体管和所述第一隔离挡墙的第四部，所述第四部位于所述第三部上，所述第四部环绕所述第一薄膜晶体管。
示例性地，在所述衬底基板上形成所述第一薄膜晶体管和所述第一隔离挡墙的第三部，包括：
形成所述第一薄膜晶体管的第一有源层；
形成所述第一薄膜晶体管的第一栅极绝缘层；
形成所述第一薄膜晶体管的第一栅极；
形成所述第一薄膜晶体管的第一层间绝缘层；
在所述第一栅极绝缘层和所述第一层间绝缘层形成环绕所述第一薄膜晶体管的侧面，并形成贯穿所述第一层间绝缘层和所述第一栅极绝缘层的第一连接孔和第二连接孔，其中，所述第一栅极绝缘层和所述第一层间绝缘层的侧面位于所述衬底基板形成所述第一薄膜晶体管的区域内；所述第一连接孔和所述第二连接孔均暴露出所述第一有源层；
形成第一薄膜晶体管的第一源漏极、所述第二薄膜晶体管的第二栅极和所述第一隔离挡墙的第三部，其中，所述第一源漏极包括第一源极和第一漏极，所述第一源极通过所述第一连接孔与所述第一有源层连接，所述第一漏极通过所述第二连接孔与所述第一有源层连接；所述第三部覆盖所述第一层间绝缘层的边缘和侧面，以及所述第一栅极绝缘层的侧面；所述第二栅极位于所述衬底基板上；
在所述衬底基板上形成所述第二薄膜晶体管和所述第一隔离挡墙的第四部，包括：
形成所述第二薄膜晶体管的第二栅极绝缘层；
形成所述第二薄膜晶体管的第二有源层；
在所述第二栅极绝缘层内形成环绕所述第一薄膜晶体管且对应于所述第三部的第三过孔，以及对应于所述第一薄膜晶体管的第一源极的第三连接孔或对应于所述第一薄膜晶体管的第一漏极的第四连接孔；
形成所述第二薄膜晶体管的第二源漏极、填充在所述第三过孔内且与所述第三部接触的第四部、以及通过所述第三连接孔连接所述第一源极或通过所述第四连接孔连接所述第一漏极的连接电极。
附图说明
本公开的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1为本公开实施例提供的一种薄膜晶体管结构的示意图；
图2为本公开实施例提供的另一种薄膜晶体管结构的示意图；
图3为本公开实施例提供的又一种薄膜晶体管结构的示意图；
图4为本公开实施例提供的薄膜晶体管结构的制造方法的流程图；
图5为图4中薄膜晶体管结构的制造方法的具体方法的流程图一；
图6为图5中薄膜晶体管结构的制造方法的具体方法的流程图；
图7为图6中步骤S100的工艺流程图；
图8为图6中步骤S200的工艺流程图；
图9为图4中薄膜晶体管结构的制造方法的具体方法的流程图二；
图10为图9中薄膜晶体管结构的制造方法的具体方法的流程图；
图11为图10中步骤S300的工艺流程图；
图12为图10中步骤S400的工艺流程图；
图13为图4中薄膜晶体管结构的制造方法的具体方法的流程图三；
图14为图13中薄膜晶体管结构的制造方法的具体方法的流程图；
图15为图14中步骤S500的工艺流程图；
图16为图14中步骤S600的工艺流程图。
附图标记：
10-衬底基板，                        11-第一区，
12-第二区；
20-第一薄膜晶体管，                  21-第一有源层，
22-第一栅极绝缘层，                  23-第一栅极，
24-第一层间绝缘层，                  241-暴露孔，
242-第一连接孔，                     243-第二连接孔，
25-第一源极，                        26-第一漏极，
27-连接电极；
30-第二薄膜晶体管，                  31-第二栅极，
32-第二栅极绝缘层，                  321-第一过孔，
322-第二过孔，                       323-第三过孔，
324-第四连接孔，                     33-第二有源层，
34-第二源极，                        35-第二漏极；
40-第二隔离挡墙，                    41-第一部，
42-第二部；
50-第一隔离挡墙，                    51-第三部，
52-第四部。
具体实施方式
下面详细描述本公开的实施例，实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本公开，而不能理解为对本公开的限制。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本公开的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了进一步说明本公开实施例提供的薄膜晶体管结构及其制造方法、显示面板、显示装置，下面结合说明书附图进行详细描述。
请参阅图1至图3，本公开实施例提供的薄膜晶体管结构包括衬底基板10，以及形成在衬底基板10上的第一薄膜晶体管20和第二薄膜晶体管30，其中，第一薄膜晶体管20的第一有源层21掺杂有氢；第二薄膜晶体管30的第二有源层33的材料为金属氧化物；衬底基板10上还设置有至少环绕第一薄膜晶体管20的第一有源层21的第一隔离挡墙50和/或环绕第二薄膜晶体管30的第二有源层33的第二隔离挡墙40，第一隔离挡墙50和第二隔离挡 墙40在平行于衬底基板10的方向上设置在第一有源层21和第二有源层33之间，防止第一薄膜晶体管的有源层中的氢扩散至第二薄膜晶体管的有源层而对第二薄膜晶体管的性能造成不良影响。
示例性地，为了更好地防止第一薄膜晶体管的有源层中的氢扩散，所述第一隔离挡墙和所述第二隔离挡墙分别围绕所述第一薄膜晶体管和所述第二薄膜晶体管，以将所述第一薄膜晶体管和所述第二薄膜晶体管在平行于所述衬底基板的方向上间隔，第一隔离挡墙50和第二隔离挡墙40在平行于所述衬底基板的方向上位于第一和第二薄膜晶体管之间。
举例来说，请继续参阅图1或图2，在本公开实施例提供的薄膜晶体管结构包括衬底基板10、第一薄膜晶体管20和第二薄膜晶体管30，衬底基板10上具有第一区11和第二区12，第一薄膜晶体管20形成在衬底基板10上的第一区11内，第二薄膜晶体管30形成在衬底基板10上的第二区12内；第一薄膜晶体管20包括第一有源层21，第一有源层21掺杂有氢，例如，第一薄膜晶体管20可以为非晶硅薄膜晶体管、单晶硅薄膜晶体管、多晶硅薄膜晶体管(如低温多晶硅薄膜晶体管)等；第二薄膜晶体管30为金属氧化物薄膜晶体管，即第二薄膜晶体管30的第二有源层33的材料为金属氧化物，例如，第二薄膜晶体管30的第二有源层33的材料可以为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)。
衬底基板10上还设置有第一隔离挡墙50或/和第二隔离挡墙40，例如，请参阅图1或图2，衬底基板10上设置有第二隔离挡墙40，第二隔离挡墙40环绕第二薄膜晶体管30设置，第二隔离挡墙40可以位于衬底基板10上第二区12的边缘或者第二区12内，以将第二薄膜晶体管30围绕在衬底基板10上第二区12内，并将第二薄膜晶体管30与第一薄膜晶体管20进行隔离；或者，请参阅图3，衬底基板10上设置有第一隔离挡墙50，第一隔离挡墙50环绕第一薄膜晶体管20设置，第一隔离挡墙50可以位于衬底基板10上第一区11的边缘或者第一区11内，以将第一薄膜晶体管20围绕在衬底基板10上第一区11内，并将第二薄膜晶体管30与第一薄膜晶体管20进行隔离；或者，在实际应用中，衬底基板10上可以同时设置第一隔离挡墙50和第二隔离挡墙40，第一隔离挡墙50环绕第一薄膜晶体管20设置，以将第一薄膜晶体管20围绕在衬底基板10上第一区11内，第二隔离挡墙40环绕第二薄膜晶体管30设置，以将第二薄膜晶体管30围绕在衬底基板10上第二区12 内，第一隔离挡墙50和第二隔离挡墙40共同作用，将第二薄膜晶体管30与第一薄膜晶体管20进行隔离。
由上述可知，在本公开实施例提供的薄膜晶体管结构中，在衬底基板10上设置有环绕第二薄膜晶体管30的第二隔离挡墙40或/和环绕第一薄膜晶体管20的第一隔离挡墙50，第二隔离挡墙40将第二薄膜晶体管30围绕在衬底基板10上设置第二薄膜晶体管30的区域内，第一隔离挡墙50将第一薄膜晶体管20围绕在衬底基板10上设置第一薄膜晶体管20的区域内，以将第二薄膜晶体管30与第一薄膜晶体管20隔离，因而第二隔离挡墙40或/和第一隔离挡墙50的设置，可以将第一薄膜晶体管20的第一有源层21中的氢隔离，防止第一薄膜晶体管20的第一有源层21中的氢扩散至第二薄膜晶体管30中，例如，防止第一薄膜晶体管20的第一有源层21中的氢扩散至第二薄膜晶体管30的第二有源层33中，从而可以防止第一薄膜晶体管20的第一有源层21中的氢对第二薄膜晶体管30造成不良影响，例如，防止第一薄膜晶体管20的第一有源层21中的氢对第二薄膜晶体管30的第二有源层33造成不良影响，进而防止第一薄膜晶体管20的第一有源层21中的氢对第二薄膜晶体管30的性能造成不良影响。
另外，在本公开实施例提供的薄膜晶体管结构中，在衬底基板10上设置有环绕第二薄膜晶体管30的第二隔离挡墙40或/和环绕第一薄膜晶体管20的第一隔离挡墙50，第二隔离挡墙40将第二薄膜晶体管30围绕在衬底基板10上设置第二薄膜晶体管30的区域内，第一隔离挡墙50将第一薄膜晶体管20围绕在衬底基板10上设置第一薄膜晶体管20的区域内，以将第二薄膜晶体管30与第一薄膜晶体管20隔离，因而，在制造本公开实施例提供的薄膜晶体管结构时，可以扩大制造第二薄膜晶体管30的工艺窗口，降低制造薄膜晶体管结构的难度。
再者，在本公开实施例提供的薄膜晶体管结构中，通过设置在衬底基板10上环绕第二薄膜晶体管30的第二隔离挡墙40或/和环绕第一薄膜晶体管20的第一隔离挡墙50，第二隔离挡墙40将第二薄膜晶体管30围绕在衬底基板10上设置第二薄膜晶体管30的区域内，第一隔离挡墙50将第一薄膜晶体管20围绕在衬底基板10上设置第一薄膜晶体管20的区域内，以将第二薄膜晶体管30与第一薄膜晶体管20隔离，防止第一薄膜晶体管20的第一有源层21中的氢对第二薄膜晶体管30的性能造成不良影响，因此，可以改善第二 薄膜晶体管30的特性和稳定性，从而提高应用本公开实施例提供的薄膜晶体管结构的显示装置的画面显示质量。
在上述实施例中，可以在衬底基板10上只设置第一隔离挡墙50，或者，在衬底基板10上只设置第二隔离挡墙40，或者，在衬底基板10上同时设置第一隔离挡墙50和第二隔离挡墙40，其中，第二隔离挡墙40的设置形式可以根据实际需要进行设定，例如，请继续参阅图1，第二薄膜晶体管30的第二栅极绝缘层32覆盖第一薄膜晶体管20，第二栅极绝缘层32内设置有环绕第二薄膜晶体管30的第一过孔，第二隔离挡墙40填充第一过孔。示例性地，请继续参阅图1，第一薄膜晶体管20位于衬底基板10上第一区11内，第二薄膜晶体管30位于衬底基板10上第二区12内，第二薄膜晶体管30包括第二栅极绝缘层32，第二栅极绝缘层32覆盖第一薄膜晶体管20，第二栅极绝缘层32内设置有环绕第二薄膜晶体管30的第一过孔，即第一过孔呈环状，第一过孔可以位于第二区12内或第二区12的边缘，第二隔离挡墙40作为一个整体结构，填充第一过孔，第二隔离挡墙40与衬底基板10接触，以将第二薄膜晶体管30围绕起来，进而将第二薄膜晶体管30与第一薄膜晶体管20隔离。
在实际应用中，第二隔离挡墙40还可以分为多个部分，例如，请继续参阅图2，第二隔离挡墙40可以包括第一部41和第二部42，其中，第一部41位于衬底基板10上，且第一部41覆盖第一薄膜晶体管20的第一绝缘层的环绕第二薄膜晶体管30的边缘和侧面；第二薄膜晶体管30的第二栅极绝缘层32覆盖第一薄膜晶体管20和第一部41，第二栅极绝缘层32与第一部41对应的区域设置有环绕第二薄膜晶体管30的第二过孔，第二部42填充第二过孔，且第二部42与第一部41接触。
举例来说，请继续参阅图2，第一薄膜晶体管20的第一绝缘层与衬底基板10上设置第二薄膜晶体管30的第二区12对应的区域具有暴露孔，该暴露孔暴露出衬底基板10，第二薄膜晶体管30位于衬底基板10上暴露孔内，第二隔离挡墙40的第一部41位于衬底基板10上，第一部41覆盖暴露孔的边缘和孔壁，即第一部41覆盖第一绝缘层环绕第二薄膜晶体管30的边缘和侧面，其中，第一薄膜晶体管20为底栅薄膜晶体管或顶栅薄膜晶体管时，第一薄膜晶体管20包括位于第一薄膜晶体管20的第一栅极和第一有源层之间的第一栅极绝缘层，此时，第一绝缘层可以包括第一薄膜晶体管20的第一栅极 绝缘层，或者，请继续参阅图2，第一薄膜晶体管20为低温多晶硅薄膜晶体管时，第一薄膜晶体管20包括位于第一薄膜晶体管20的第一有源层21和第一栅极23之间的第一栅极绝缘层22，以及位于第一薄膜晶体管20的第一栅极23和第一源漏极(包括第一源极25和第一漏极26)之间的第一层间绝缘层24，此时，第一绝缘层可以包括第一薄膜晶体管20的第一栅极绝缘层22和第一层间绝缘层24。
第二薄膜晶体管30包括第二栅极绝缘层32，第二栅极绝缘层32覆盖第一薄膜晶体管20和第一部41，第二栅极绝缘层32与第一部41对应的区域设置有环绕第二薄膜晶体管30的第二过孔，第二过孔呈环状，第二隔离挡墙40的第二部42填充第二过孔，并与第一部41接触，第一部41和第二部42共同构成环绕第二薄膜晶体管30的第二隔离挡墙40，将第二薄膜晶体管30围绕，将第二薄膜晶体管30与第一薄膜晶体管20隔离。
将第二隔离挡墙40设置为第一部41和第二部42，第一部41位于衬底基板10上，且第一部41覆盖第一薄膜晶体管20的第一绝缘层的环绕第二薄膜晶体管30的边缘和侧面，因此，第一部41可以将第一薄膜晶体管20的第一绝缘层与第二薄膜晶体管30隔离，以防止第一薄膜晶体管20中可能存在于第一绝缘层中的氢扩散至第二薄膜晶体管30中，例如，第一薄膜晶体管20为低温多晶硅薄膜晶体管时，第一绝缘层包括第一栅极绝缘层22和第一层间绝缘层24，第二隔离挡墙40的第一部41则可以将第一栅极绝缘层22、第一层间绝缘层24均与第二薄膜晶体管30隔离，防止可能存在于第一栅极绝缘层22、第一层间绝缘层24中的氢扩散至第二薄膜晶体管30。
上述实施例中，第一隔离挡墙50的设置形式可以根据实际需要进行设定，例如，请继续参阅图3，第一隔离挡墙50包括第三部51和第四部52，其中，第三部51位于衬底基板10上，且第三部51覆盖第一薄膜晶体管20的第一绝缘层的位于衬底基板10上形成第一薄膜晶体管20的区域内、且环绕第一薄膜晶体管20的边缘和侧面；第二薄膜晶体管30的第二栅极绝缘层32覆盖第一薄膜晶体管20和第三部51，第二栅极绝缘层32与第三部51对应的区域设置有环绕第一薄膜晶体管20的第三过孔，第四部52填充第三过孔，且第四部52与第三部51接触。
举例来说，请继续参阅图3，第一薄膜晶体管20的第一绝缘层均位于衬底基板10上形成第一薄膜晶体管20的第一区11内，第一绝缘层的侧面位于 第一区11内，值得注意的是，此处第一绝缘层的侧面位于第一区11内可以理解为第一绝缘层的侧面位于第一区11的边缘或内部，第一绝缘层的侧面环绕第一薄膜晶体管20，第一隔离挡墙50的第三部51位于衬底基板10上，第三部51覆盖第一绝缘层的边缘和侧面，即第三部51环绕第一薄膜晶体管20；其中，第一薄膜晶体管20为底栅薄膜晶体管或顶栅薄膜晶体管时，第一薄膜晶体管20包括位于第一薄膜晶体管的第一栅极和第一有源层之间的第一栅极绝缘层，此时，第一绝缘层可以包括第一薄膜晶体管20的第一栅极绝缘层；或者，请继续参阅图3，第一薄膜晶体管20为低温多晶硅薄膜晶体管，第一薄膜晶体管20包括位于第一薄膜晶体管20的第一有源层21和第一栅极23之间的第一栅极绝缘层22，以及位于第一薄膜晶体管20的第一栅极23和第一源漏极(包括第一源极25和第一漏极26)之间的第一层间绝缘层24，此时，第一绝缘层可以包括第一薄膜晶体管20的第一栅极绝缘层22和第一层间绝缘层24。
第二薄膜晶体管30包括第二栅极绝缘层32，第二栅极绝缘层32覆盖第一薄膜晶体管20和第三部51，第二栅极绝缘层32与第三部51对应的区域设置有环绕第一薄膜晶体管30的第三过孔，第三过孔呈环状，第一隔离挡墙50的第四部52填充第三过孔，并与第三部51接触，第三部51和第四部52共同构成环绕第一薄膜晶体管20的第一隔离挡墙50，将第一薄膜晶体管20围绕，将第一薄膜晶体管20与第二薄膜晶体管30隔离。
将第一隔离挡墙50设置为第三部51和第四部52，第三部51位于衬底基板10上，且第三部51覆盖第一薄膜晶体管20的第一绝缘层的位于第一区11内、环绕第一薄膜晶体管20的边缘和侧面，因此，第三部51可以将第一薄膜晶体管20的第一绝缘层与第二薄膜晶体管30隔离，以防止第一薄膜晶体管20中可能存在于第一绝缘层中的氢扩散至第二薄膜晶体管30中，例如，第一薄膜晶体管20为低温多晶硅薄膜晶体管时，第一绝缘层包括第一栅极绝缘层22和第一层间绝缘层24，第一隔离挡墙50的第三部51则可以将第一栅极绝缘层22、第一层间绝缘层24均与第二薄膜晶体管30隔离，防止可能存在于第一栅极绝缘层22、第一层间绝缘层24中的氢扩散至第二薄膜晶体管30。
在上述实施例中，当在衬底基板10上同时设置第一隔离挡墙50和第二隔离挡墙40时，则第一隔离挡墙50可以采用包括第三部51和第四部52的 方式进行设置，第二隔离挡墙40可以采用整体的方式进行设置，即第二隔离挡墙40填充形成在第二栅极绝缘层32中、环绕第二薄膜晶体管30的第一过孔的方式进行设置，也就是说，第一隔离挡墙50可以采用图3所示的方式设置，第二隔离挡墙40可以采用图1所示的方式设置。
在上述实施例中，第一薄膜晶体管20的类型可以根据实际需要进行选择，例如，第一薄膜晶体管20可以为非晶硅薄膜晶体管、单晶硅薄膜晶体管、多晶硅薄膜晶体管等，在本公开实施例中，第一薄膜晶体管20为低温多晶硅薄膜晶体管，请继续参阅图1或图2，第一薄膜晶体管20包括第一有源层21、第一栅极绝缘层22、第一栅极23、第一层间绝缘层24、第一源漏极，其中，第一有源层21位于衬底基板10上；第一栅极绝缘层22覆盖衬底基板10、第一有源层21，第一栅极绝缘层22与衬底基板10上形成第二薄膜晶体管30的区域对应的区域具有暴露出衬底基板10的第一暴露孔；第一栅极23位于第一栅极绝缘层22上，且第一栅极23位于第一有源层21上方；第一层间绝缘层24覆盖第一栅极23和第一栅极绝缘层22，第一层间绝缘层24与第一栅极绝缘层22中第一暴露孔对应的区域具有暴露出衬底基板10的第二暴露孔；第一有源层21上方还具有贯穿第一层间绝缘层24和第一栅极绝缘层22的第一连接孔和第二连接孔，第一连接孔和第二连接孔均暴露出第一有源层21；第一源漏极位于第一层间绝缘层24上，第一源漏极包括第一源极25和第一漏极26，第一源极25通过第一连接孔与第一有源层21连接，第一漏极26通过第二连接孔与第一有源层21连接；或者，请继续参阅图3，第一薄膜晶体管20包括第一有源层21、第一栅极绝缘层22、第一栅极23、第一层间绝缘层24、第一源漏极，其中，第一有源层21位于衬底基板10上的第一区11内；第一栅极绝缘层22覆盖第一有源层21和位于第一区11内的衬底基板10；第一栅极23位于第一栅极绝缘层22上，且第一栅极23位于第一有源层21上方；第一层间绝缘层24覆盖第一栅极23和第一栅极绝缘层22；第一有源层21上方还具有贯穿第一层间绝缘层24和第一栅极绝缘层22的第一连接孔和第二连接孔，第一连接孔和第二连接孔均暴露出第一有源层21；第一源漏极位于第一层间绝缘层24上，第一源漏极包括第一源极25和第一漏极26，第一源极25通过第一连接孔与第一有源层21连接，第一漏极26通过第二连接孔与第一有源层21连接。
在上述实施例中，第二薄膜晶体管30的类型可以根据实际需要进行选 择，例如，第二薄膜晶体管30可以为底栅薄膜晶体管、顶栅薄膜晶体管等，在本公开实施例中，请继续参阅图1或图2，第二薄膜晶体管30为底栅薄膜晶体管，第二薄膜晶体管30包括第二栅极31、第二栅极绝缘层32、第二有源层33、第二源漏极，其中，第二栅极31位于衬底基板10上；第二栅极绝缘层32覆盖第二栅极31、衬底基板10和第一薄膜晶体管20；第二有源层33位于第二栅极绝缘层32上，且第二有源层33位于第二栅极31的上方，第二有源层33的材料可以为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)；第二源漏极位于第二有源层33上，第二源漏极包括第二源极34和第二漏极35，第二源极34和第二漏极35分别与第二有源层33接触。
示例性地，第二薄膜晶体管30可以形成在第一暴露孔和第二暴露孔中。
请继续参阅图1，第一薄膜晶体管20为低温多晶硅薄膜晶体管，第二薄膜晶体管30为底栅薄膜晶体管，第二栅极绝缘层32内形成有环绕第二薄膜晶体管30的第一过孔，第一过孔暴露出衬底基板10，第二隔离挡墙40填充在第一过孔内，以将第二薄膜晶体管30和第一薄膜晶体管20隔离；第一薄膜晶体管20还包括连接电极27，第二栅极绝缘层32与第一源极25对应的区域具有第三连接孔，此时，连接电极27通过第三连接孔与第一源极25连接，或者，第二栅极绝缘层32与第一漏极26对应的区域具有第四连接孔，此时，连接电极27通过第四连接孔与第一漏极26连接，以方便第一薄膜晶体管20的第一源极25或第一漏极26与其它结构进行连接。
请继续参阅图2，第一薄膜晶体管20为低温多晶硅薄膜晶体管，第二薄膜晶体管30为底栅薄膜晶体管，第二隔离挡墙40包括第一部41和第二部42，第一部41覆盖第一薄膜晶体管20的第一层间绝缘层24的环绕第二薄膜晶体管30的边缘和侧面，以及第一薄膜晶体管20的第一栅极绝缘层22环绕第二薄膜晶体管30的侧面；第二栅极绝缘层32与第一部41对应的区域设置有第二过孔，第二过孔环绕第二薄膜晶体管30，第二隔离挡墙40的第二部42填充第二过孔，并与第一部41接触，第一部41和第二部42共同将第二薄膜晶体管30围绕，以将第二薄膜晶体管30与第一薄膜晶体管20隔离；同样地，第一薄膜晶体管20还包括连接电极27，第二栅极绝缘层32与第一源极25对应的区域具有第三连接孔，此时，连接电极27通过第三连接孔与第一源极25连接，或者，第二栅极绝缘层32与第一漏极26对应的区域具有第四连接孔，此时，连接电极27通过第四连接孔与第一漏极26连接，以方便 第一薄膜晶体管20的第一源极25或第一漏极26与其它结构进行连接。
请继续参阅图3，第一薄膜晶体管20为低温多晶硅薄膜晶体管，第二薄膜晶体管30为底栅薄膜晶体管，第一隔离挡墙50包括第三部51和第四部52，第三部51覆盖第一薄膜晶体管20的第一层间绝缘层24的位于第一区11内、环绕第一薄膜晶体管20的边缘和侧面，以及第一薄膜晶体管20的第一栅极绝缘层22环绕第一薄膜晶体管20的侧面；第二栅极绝缘层32与第三部51对应的区域设置有第三过孔，第三过孔环绕第一薄膜晶体管20，第一隔离挡墙50的第四部52填充第三过孔，并与第三部51接触，第三部51和第四部52共同将第一薄膜晶体管20围绕，以将第一薄膜晶体管20与第二薄膜晶体管30隔离；同样地，第一薄膜晶体管20还包括连接电极27，第二栅极绝缘层32与第一源极25对应的区域具有第三连接孔，此时，连接电极27通过第三连接孔与第一源极25连接，或者，第二栅极绝缘层32与第一漏极26对应的区域具有第四连接孔，此时，连接电极27通过第四连接孔与第一漏极26连接，以方便第一薄膜晶体管20的第一源极25或第一漏极26与其它结构进行连接。
在本公开实施例中，请参阅图1至图3，第一薄膜晶体管20为低温多晶硅薄膜晶体管，第二薄膜晶体管30为底栅薄膜晶体管，第二薄膜晶体管30的第二栅极绝缘层32覆盖第一薄膜晶体管20，因此，当制造本公开实施例提供的薄膜晶体管结构时，可以先在衬底基板10上形成第一薄膜晶体管20，然后在衬底基板10上形成第二薄膜晶体管30，且在形成第二薄膜晶体管30时，第二栅极绝缘层32先于第二有源层33形成，即先形成第二栅极绝缘层32，第二栅极绝缘层32将衬底基板10、第二栅极31和第一薄膜晶体管20完全覆盖，然后再形成第二有源层33，在形成第二有源层33的过程中，例如是在对形成第二有源层33的金属氧化物膜层进行退火时，第二栅极绝缘层32可以阻挡第一薄膜晶体管20的第一有源层21中的氢向第二有源层33扩散，从而防止对第二薄膜晶体管30的性能造成不良影响。
另外，第一薄膜晶体管20为低温多晶硅薄膜晶体管，第二薄膜晶体管30为底栅薄膜晶体管，第二薄膜晶体管30的第二栅极绝缘层32覆盖第一薄膜晶体管20，因此，当制造本公开实施例提供的薄膜晶体管结构时，可以先在衬底基板10上形成第一薄膜晶体管20，然后在衬底基板10上形成第二薄膜晶体管30，且在形成第二薄膜晶体管30时，第二栅极绝缘层32先于第二 有源层33形成，即先形成第二栅极绝缘层32，第二栅极绝缘层32将衬底基板10、第二栅极31和第一薄膜晶体管20完全覆盖，然后再形成第二有源层33，因此，可以防止形成第一薄膜晶体管20的第一有源层21的工艺和形成第二薄膜晶体管30的第二有源层33的工艺相互干扰。
在上述实施例中，第一隔离挡墙50的材料和第二隔离挡墙40的材料均可以为多种，第一隔离挡墙50的材料和第二隔离挡墙40的材料均只需具有较好的阻氢性能即可。
举例来说，第一隔离挡墙50的材料可以为有机材料，即第一隔离挡墙50为有机材料第一隔离挡墙50，例如，有机材料可以为聚乙烯(Polyethylene，PE)；或者，第一隔离挡墙50的材料可以为无机材料，即第一隔离挡墙50为无机材料第一隔离挡墙50，例如，无机材料可以为氧化铝(Al2O3)、氮化硅(SiNx)等；或者，第一隔离挡墙50的材料可以为金属，即第一隔离挡墙50为金属第一隔离挡墙50，此时，请继续参阅图3，第一隔离挡墙50包括第三部51和第四部52，第一薄膜晶体管20为低温多晶硅薄膜晶体管，第二薄膜晶体管30为底栅薄膜晶体管，在制造薄膜晶体管结构时，先在衬底基板10上第一区11内形成第一薄膜晶体管20，在形成第一薄膜晶体管20的第一源漏极即第一源极25和第一漏极26时，可以同时形成第一隔离挡墙50的第三部51，即第一隔离挡墙50的第三部51与第一薄膜晶体管20的第一源漏极同时形成，也可以理解为第一隔离挡墙50的第三部51与第一薄膜晶体管20的第一源漏极通过一次构图工艺形成，第一隔离挡墙50的第三部51的材料与第一薄膜晶体管20的第一源漏极的材料相同，然后在衬底基板10上第二区12内形成第二薄膜晶体管30，在形成第二薄膜晶体管30的第二源漏极即第二源极34和第二漏极35之前，在第二薄膜晶体管30的第二栅极绝缘层32内形成环绕第一薄膜晶体管20的第三过孔，在形成第二薄膜晶体管30的第二源漏极即第二源极34和第二漏极35时，可以同时形成第一隔离挡墙50的第四部52，即第一隔离挡墙50的第四部52与第二薄膜晶体管30的第二源漏极同时形成，也可以理解为第一隔离挡墙50的第四部52与第二薄膜晶体管30的第二源漏极通过一次构图工艺形成，第一隔离挡墙50的第四部52的材料与第二薄膜晶体管30的第二源漏极的材料相同。
示例性地，第二隔离挡墙40的材料可以为有机材料，即第二隔离挡墙40为有机材料第二隔离挡墙40，例如，有机材料可以为聚乙烯(Polyethylene， PE)；或者，第二隔离挡墙40的材料可以为无机材料，即第二隔离挡墙40为无机材料第二隔离挡墙40，例如，无机材料可以为氧化铝(Al2O3)、氮化硅(SiNx)等；或者，第二隔离挡墙40的材料可以为金属，即第二隔离挡墙40为金属第二隔离挡墙40，此时，请继续参阅图1，第二隔离挡墙40的结构为一个整体结构，第一薄膜晶体管20为低温多晶硅薄膜晶体管，第二薄膜晶体管30为底栅薄膜晶体管，在制造薄膜晶体管结构时，先在衬底基板10上第一区11内形成第一薄膜晶体管20，然后在衬底基板10上第二区12内形成第二薄膜晶体管30，其中，在形成第二薄膜晶体管30的第二源漏极即第二源极34和第二漏极35之前，在第二薄膜晶体管30的第二栅极绝缘层32内形成环绕第二薄膜晶体管30的第一过孔，在形成第二薄膜晶体管30的第二源漏极即第二源极34和第二漏极35时，可以同时形成第二隔离挡墙40，即第二隔离挡墙40与第二薄膜晶体管30的第二源漏极同时形成，也可以理解为第二隔离挡墙40与第二薄膜晶体管30的第二源漏极通过一次构图工艺形成，第二隔离挡墙40的材料与第二薄膜晶体管30的第二源漏极的材料相同；请继续参阅图2，第二隔离挡墙40的结构包括第一部41和第二部42，第一薄膜晶体管20为低温多晶硅薄膜晶体管，第二薄膜晶体管30为底栅薄膜晶体管，在制造薄膜晶体管结构时，先在衬底基板10上第一区11内形成第一薄膜晶体管20，在形成第一薄膜晶体管20的第一源漏极即第一源极25和第一漏极26时，可以同时形成第二隔离挡墙40的第一部41，即第二隔离挡墙40的第一部41与第一薄膜晶体管20的第一源漏极同时形成，也可以理解为第二隔离挡墙40的第一部41与第一薄膜晶体管20的第一源漏极通过一次构图工艺形成，第二隔离挡墙40的第一部41的材料与第一薄膜晶体管20的第一源漏极的材料相同，然后在衬底基板10上第二区12内形成第二薄膜晶体管30，在形成第二薄膜晶体管30的第二源漏极即第二源极34和第二漏极35之前，在第二薄膜晶体管30的第二栅极绝缘层32内形成环绕第二薄膜晶体管30的第二过孔，在形成第二薄膜晶体管30的第二源漏极即第二源极34和第二漏极35时，可以同时形成第二隔离挡墙40的第二部42，即第二隔离挡墙40的第二部42与第二薄膜晶体管30的第二源漏极同时形成，也可以理解为第二隔离挡墙40的第二部42与第二薄膜晶体管30的第二源漏极通过一次构图工艺形成，第二隔离挡墙40的第二部42的材料与第二薄膜晶体管30的第二源漏极的材料相同。
本公开实施例还提供一种显示面板，所述显示面板包括如上述实施例所述的薄膜晶体管结构。
示例性地，该显示面板可以是液晶显示面板或者有机发光二极管显示面板，该显示面板包括多个像素单元，每个像素单元中设置有上述薄膜晶体管结构，通过至少环绕第一或第二薄膜晶体管的有源层的隔离挡墙，例如，环绕第一和/或第二薄膜晶体管的隔离挡墙，可以防止同一像素单元中、不同像素单元中的第一薄膜晶体管中的氢对第二晶体管的影响。
所述显示面板与上述薄膜晶体管结构相对于现有技术所具有的优势相同，在此不再赘述。
本公开实施例还提供一种显示装置，所述显示装置包括如上述实施例所述的显示面板。
所述显示装置与上述显示面板相对于现有技术所具有的优势相同，在此不再赘述。
请参阅图4，本公开实施例还提供一种上述实施例所述的薄膜晶体管结构的制造方法，包括：
在衬底基板上形成第一薄膜晶体管和第二薄膜晶体管，以及第一隔离挡墙或/和第二隔离挡墙，其中，第一薄膜晶体管的第一有源层掺杂有氢；第二薄膜晶体管的第二有源层的材料为金属氧化物；第一隔离挡墙至少环绕所述第一薄膜晶体管的第一有源层，第二隔离挡墙至少环绕所述第二薄膜晶体管的第二有源层。
示例性地，制造方法，包括：步骤S1、在衬底基板上形成第一薄膜晶体管和第二薄膜晶体管，以及第一隔离挡墙或/和第二隔离挡墙，其中，第一薄膜晶体管的第一有源层掺杂有氢；第二薄膜晶体管的第二有源层的材料为金属氧化物；第一隔离挡墙至少环绕所述第一薄膜晶体管的第一有源层，第二隔离挡墙至少环绕所述第二薄膜晶体管的第二有源层。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于结构实施例，所以描述得比较简单，相关之处参见结构实施例的部分说明即可。
第一薄膜晶体管为低温多晶硅薄膜晶体管，第二薄膜晶体管为底栅薄膜晶体管，第二隔离挡墙为整体结构即第二隔离挡墙不分为几个部分时，即第 二隔离挡墙采用图1所示的结构时，请参阅图5，步骤S1、在衬底基板上形成第一薄膜晶体管、第二薄膜晶体管和第二隔离挡墙，可以包括：
步骤S100、在衬底基板上形成第一薄膜晶体管。
步骤S200、在衬底基板上形成第二薄膜晶体管和环绕第二薄膜晶体管的第二隔离挡墙。
具体地，请参阅图6和图7，步骤S100、在衬底基板上形成第一薄膜晶体管，可以包括：
步骤S110、形成第一薄膜晶体管的第一有源层。
具体地，请参阅图6和图7，在步骤S110中，先在衬底基板10上沉积多晶硅层，该多晶硅层为低温多晶硅层，低温多晶硅层中掺杂有氢；然后通过构图工艺，形成第一薄膜晶体管20的第一有源层21，第一有源层21位于衬底基板10上形成第一薄膜晶体管20的第一区11内。
步骤S120、形成第一薄膜晶体管的第一栅极绝缘层。
具体地，请继续参阅图6和图7，在步骤S120中，在衬底基板10和第一有源层21上沉积第一栅极绝缘膜层，形成第一栅极绝缘层22，第一栅极绝缘层22覆盖衬底基板10和第一有源层21。
步骤S130、形成第一薄膜晶体管的第一栅极。
具体地，请继续参阅图6和图7，在步骤S130中，先在第一栅极绝缘层22上沉积第一金属层；然后，通过构图工艺，形成第一薄膜晶体管20的第一栅极23，第一栅极23位于衬底基板10的第一区11内、第一有源层21的上方。
步骤S140、形成第一薄膜晶体管的第一层间绝缘层。
具体地，请继续参阅图6和图7，在步骤S140中，在第一栅极绝缘层22和第一栅极23上沉积第一层间绝缘膜层，形成第一层间绝缘层24，第一层间绝缘层24覆盖第一栅极绝缘层22和第一栅极23。
步骤S150、形成贯穿第一层间绝缘层和第一栅极绝缘层的暴露孔、第一连接孔和第二连接孔，暴露孔暴露出衬底基板上形成第二薄膜晶体管的区域，第一连接孔和第二连接孔均暴露出第一有源层。
具体地，请继续参阅图6和图7，在步骤S150中，通过构图工艺，形成暴露孔241、第一连接孔242和第二连接孔243，其中，暴露孔241贯穿第一层间绝缘层24和第一栅极绝缘层22，并暴露出衬底基板10上形成第二薄膜 晶体管30的区域，以方便后续在衬底基板10上形成第二薄膜晶体管30；第一连接孔242和第二连接孔243分别贯穿第一层间绝缘层24和第一栅极绝缘层22，并均暴露出第一有源层21，以方便后续形成的第一源漏极中第一源极25和第一漏极26分别与第一有源层21之间的连接。
步骤S160、形成第一薄膜晶体管的第一源漏极和第二薄膜晶体管的第二栅极，其中，第一源漏极包括第一源极和第一漏极，第一源极通过第一连接孔与第一有源层连接，第一漏极通过第二连接孔与第一有源层连接；第二栅极位于衬底基板上、暴露孔内。
具体地，请继续参阅图6和图7，在步骤S160中，先沉积第二金属层；然后通过构图工艺，同时形成第一薄膜晶体管20的第一源漏极和第二薄膜晶体管30的第二栅极31，其中，第一源漏极中第一源极25通过第一连接孔242与第一有源层21连接，第一漏极26通过第二连接孔243与第一有源层21连接；第二栅极31位于衬底基板10上、暴露孔241内。也就是说，第一薄膜晶体管20的第一源漏极和第二薄膜晶体管30的第二栅极31通过一次构图工艺形成，从而可以减少制造薄膜晶体管结构的工艺步骤，同时，减少制造薄膜晶体管结构时所使用的掩膜版的数量，进而减低制造薄膜晶体管结构的成本。
请参阅图6和图8，步骤S200、在衬底基板上形成第二薄膜晶体管和环绕第二薄膜晶体管的第二隔离挡墙，可以包括：
步骤S210、形成第二薄膜晶体管的第二栅极绝缘层。
具体地，请继续参阅图6和图8，在步骤S210中，沉积第二栅极绝缘膜层，形成第二栅极绝缘层32，第二栅极绝缘层32覆盖第一薄膜晶体管20、衬底基板10和第二栅极31。
步骤S220、形成第二薄膜晶体管的第二有源层。
具体地，请继续参阅图6和图8，在步骤S220中，可以先在第二栅极绝缘层32上沉积金属氧化物膜层；然后通过构图工艺，形成第二薄膜晶体管30的第二有源层33，第二有源层33位于第二栅极31的上方。
步骤S230、在第二栅极绝缘层内形成环绕第二薄膜晶体管且暴露出衬底基板的第一过孔，以及对应于第一薄膜晶体管的第一源极的第三连接孔或对应于第一薄膜晶体管的第一漏极的第四连接孔。
具体地，请继续参阅图6和图8，在步骤S230中，通过构图工艺，在第 二栅极绝缘层32内形成第一过孔321，第一过孔321环绕第二薄膜晶体管30，第一过孔321暴露出衬底基板10，以便后续形成环绕第二薄膜晶体管30的第二隔离挡墙40。
在步骤S230中，请继续参阅图6和图8，通过构图工艺，在第二栅极绝缘层32内还形成第三连接孔，第三连接孔对应于第一薄膜晶体管20的第一源极25，以方便通过后续形成的连接电极27将第一源极25和其它结构连接；或者，在实际应用中，也可以通过构图工艺，在第二栅极绝缘层32内还形成第四连接孔324，第四连接孔324对应于第一薄膜晶体管20的第一漏极26，以方便通过后续形成的连接电极27将第一漏极26和其它结构连接。
步骤S240、形成第二薄膜晶体管的第二源漏极、填充在第一过孔内的第二隔离挡墙、以及通过第三连接孔连接第一源极或通过第四连接孔连接第一漏极的连接电极。
具体地，请继续参阅图6和图8，在步骤S240中，先沉积第三金属层；然后通过构图工艺，同时形成第二隔离挡墙40、第二薄膜晶体管30的第二源漏极和第一薄膜晶体管20的连接电极27，其中，第二隔离挡墙40填充在第一过孔321内，第二隔离挡墙40环绕第二薄膜晶体管30；第二薄膜晶体管30的第二源漏极包括第二源极34和第二漏极35，第二源极34和第二漏极35分别与第二有源层33接触；连接电极27位于第二栅极绝缘层32上，连接电极27通过第三连接孔连接第一源极25，或者，连接电极27通过第四连接孔324连接第一漏极26。也就是说，第二隔离挡墙40、第二源漏极和连接电极27通过一次构图工艺形成，从而可以减少制造薄膜晶体管结构的工艺步骤，同时，减少制造薄膜晶体管结构时所使用的掩膜版的数量，进而减低制造薄膜晶体管结构的成本。
第一薄膜晶体管为低温多晶硅薄膜晶体管，第二薄膜晶体管为底栅薄膜晶体管，第二隔离挡墙包括多个部分例如第二隔离挡墙包括第一部和第二部时，即第二隔离挡墙采用如2所示的结构时，请参阅图9，步骤S1、在衬底基板上形成第一薄膜晶体管、第二薄膜晶体管和第二隔离挡墙，可以包括：
步骤S300、在衬底基板上形成第一薄膜晶体管和第二隔离挡墙的第一部，第一部覆盖第一薄膜晶体管的第一绝缘层的环绕第二薄膜晶体管的边缘和侧面。
步骤S400、在衬底基板上形成第二薄膜晶体管和第二隔离挡墙的第二部， 第二部位于第一部上，第一部和第二部共同环绕第二薄膜晶体管。
具体地，请参阅图10和图11，步骤S300、在衬底基板上形成第一薄膜晶体管和第二隔离挡墙的第一部，可以包括：
步骤S310、形成第一薄膜晶体管的第一有源层。
具体地，请继续参阅图10和图11，在步骤S310中，先在衬底基板10上沉积多晶硅层，该多晶硅层为低温多晶硅层，低温多晶硅层中掺杂有氢；然后通过构图工艺，形成第一薄膜晶体管20的第一有源层21，第一有源层21位于衬底基板10上形成第一薄膜晶体管20的第一区11内。
步骤S320、形成第一薄膜晶体管的第一栅极绝缘层。
具体地，请继续参阅图10和图11，在步骤S320中，在衬底基板10和第一有源层21上沉积第一栅极绝缘膜层，形成第一栅极绝缘层22，第一栅极绝缘层22覆盖衬底基板10和第一有源层21。
步骤S330、形成第一薄膜晶体管的第一栅极。
具体地，请继续参阅图10和图11，在步骤S330中，先在第一栅极绝缘层22上沉积第一金属层；然后，通过构图工艺，形成第一薄膜晶体管20的第一栅极23，第一栅极23位于衬底基板10的第一区11内、第一有源层21的上方。
步骤S340、形成所述第一薄膜晶体管的第一层间绝缘层。
具体地，请继续参阅图10和图11，在步骤S340中，在第一栅极绝缘层22和第一栅极23上沉积第一层间绝缘膜层，形成第一层间绝缘层24，第一层间绝缘层24覆盖第一栅极绝缘层22和第一栅极23。
步骤S350、形成贯穿第一层间绝缘层和第一栅极绝缘层的暴露孔、第一连接孔和第二连接孔，暴露孔暴露出衬底基板上形成第二薄膜晶体管的区域，第一连接孔和第二连接孔均暴露出第一有源层。
具体地，请继续参阅图10和图11，在步骤S350中，通过构图工艺，形成暴露孔241、第一连接孔242和第二连接孔243，其中，暴露孔241贯穿第一层间绝缘层24和第一栅极绝缘层22，并暴露出衬底基板10上形成第二薄膜晶体管30的区域，以方便后续在衬底基板10上形成第二薄膜晶体管30；第一连接孔242和第二连接孔243分别贯穿第一层间绝缘层24和第一栅极绝缘层22，并均暴露出第一有源层21，以方便后续形成的第一源漏极中第一源极25和第一漏极26分别与第一有源层21之间的连接。
步骤S360、形成第一薄膜晶体管的第一源漏极、第二薄膜晶体管的第二栅极和第二隔离挡墙的第一部，其中，第一源漏极包括第一源极和第一漏极，第一源极通过第一连接孔与第一有源层连接，第一漏极通过第二连接孔与第一有源层连接；第一部覆盖暴露孔的边缘和孔壁；第二栅极位于衬底基板上、暴露孔内。
具体地，请继续参阅图10和图11，在步骤S360中，先沉积第二金属层；然后通过构图工艺，同时形成第一薄膜晶体管20的第一源漏极、第二薄膜晶体管30的第二栅极31和第二隔离挡墙40的第一部41，其中，第一源漏极中，第一源极25通过第一连接孔242与第一有源层21连接，第一漏极26通过第二连接孔243与第一有源层21连接；第二隔离挡墙40的第一部41覆盖暴露孔241的边缘和孔壁，具体地，第一部41覆盖第一层间绝缘层24对应于暴露孔241的边缘、第一层间绝缘层24对应于暴露孔241的侧面以及第一栅极绝缘层22对应于暴露孔241的侧面；第二栅极31位于衬底基板10上、暴露孔241内。也就是说，第一薄膜晶体管20的第一源漏极、第二薄膜晶体管30的第二栅极31和第二隔离挡墙40的第一部41通过一次构图工艺形成，从而可以减少制造薄膜晶体管结构的工艺步骤，同时，减少制造薄膜晶体管结构时所使用的掩膜版的数量，进而减低制造薄膜晶体管结构的成本。
请参阅图10和图12，步骤S400、在衬底基板上形成第二薄膜晶体管和第二隔离挡墙的第二部，可以包括：
步骤S410、形成第二薄膜晶体管的第二栅极绝缘层。
具体地，请继续参阅图10和图12，在步骤S410中，沉积第二栅极绝缘膜层，形成第二栅极绝缘层32，第二栅极绝缘层32覆盖第一薄膜晶体管20、衬底基板10、第一部41和第二薄膜晶体管30的第二栅极31。
步骤S420、形成第二薄膜晶体管的第二有源层。
具体地，请继续参阅图10和图12，在步骤S420中，可以先在第二栅极绝缘层32上沉积金属氧化物膜层；然后通过构图工艺，形成第二薄膜晶体管30的第二有源层33，第二有源层33位于第二栅极31的上方。
步骤S430、在第二栅极绝缘层内形成环绕第二薄膜晶体管且对应于第一部的第二过孔，以及对应于第一薄膜晶体管的第一源极的第三连接孔或对应于第一薄膜晶体管的第一漏极的第四连接孔。
具体地，请继续参阅图10和图12，在步骤S430中，通过构图工艺，在 第二栅极绝缘层32内形成第二过孔322，第二过孔322环绕第二薄膜晶体管30，第二过孔322暴露出第一隔离挡墙40的第一部41，以便后续形成环绕第二薄膜晶体管30的第二隔离挡墙40的第二部42。
在步骤S430中，通过构图工艺，在第二栅极绝缘层32内还形成第三连接孔，第三连接孔对应于第一薄膜晶体管20的第一源极25，以方便通过后续形成的连接电极27将第一源极25和其它结构连接；或者，通过构图工艺，在第二栅极绝缘层32内还形成第四连接孔324，第四连接孔324对应于第一薄膜晶体管20的第一漏极26，以方便通过后续形成的连接电极27将第一漏极26和其它结构连接。
步骤S440、形成第二薄膜晶体管的第二源漏极、填充在第二过孔内且与第一部接触的第二部、以及通过第三连接孔连接第一源极或通过第四连接孔连接第一漏极的连接电极。
具体地，请继续参阅图10和图12，在步骤S440中，先沉积第三金属层；然后通过构图工艺，同时形成第二隔离挡墙40的第二部42、第二薄膜晶体管30的第二源漏极和第一薄膜晶体管20的连接电极27，其中，第二部42填充在第二过孔322内，第二部42与第一部41接触，第一部41和第二部42共同构成第二隔离挡墙40，以环绕第二薄膜晶体管30，将第二薄膜晶体管30与第一薄膜晶体管20隔离；第二薄膜晶体管30的第二源漏极包括第二源极34和第二漏极35，第二源极34和第二漏极35分别与第二有源层33接触；连接电极27位于第二栅极绝缘层32上，连接电极27通过第三连接孔连接第一源极25，或者，连接电极27通过第四连接孔324连接第一漏极26。也就是说，第二隔离挡墙40的第二部42、第二源漏极和连接电极27通过一次构图工艺形成，从而可以减少制造薄膜晶体管结构的工艺步骤，同时，减少制造薄膜晶体管结构时所使用的掩膜版的数量，进而减低制造薄膜晶体管结构的成本。
第一薄膜晶体管为低温多晶硅薄膜晶体管，第二薄膜晶体管为底栅薄膜晶体管，第一隔离挡墙包括多个部分例如第一隔离挡墙包括第三部和第四部时，即第一隔离挡墙采用如3所示的结构时，请参阅图13，步骤S1、在衬底基板上形成第一薄膜晶体管、第二薄膜晶体管和第一隔离挡墙，可以包括：
步骤S500、在衬底基板上形成第一薄膜晶体管和第一隔离挡墙的第三部，第三部覆盖第一薄膜晶体管的第一绝缘层环绕第一薄膜晶体管的边缘和侧 面。
步骤S600、在衬底基板上形成第二薄膜晶体管和第一隔离挡墙的第四部，第四部位于第三部上，第三部和第四部共同环绕第一薄膜晶体管。
具体地，请继续参阅图14和图15，步骤S500、在衬底基板上形成第一薄膜晶体管和第一隔离挡墙的第三部，可以包括：
步骤S510、形成第一薄膜晶体管的第一有源层。
具体地，请继续参阅图14和图15，在步骤S510中，先在衬底基板10上沉积多晶硅层，该多晶硅层为低温多晶硅层，低温多晶硅层中掺杂有氢；然后通过构图工艺，形成第一薄膜晶体管20的第一有源层21，第一有源层21位于衬底基板10上形成第一薄膜晶体管20的第一区11内。
步骤S520、形成第一薄膜晶体管的第一栅极绝缘层。
具体地，请继续参阅图14和图15，在步骤S520中，在衬底基板10和第一有源层21上沉积第一栅极绝缘膜层，形成第一栅极绝缘层22，第一栅极绝缘层22覆盖衬底基板10和第一有源层21。
步骤S530、形成第一薄膜晶体管的第一栅极。
具体地，请继续参阅图14和图15，在步骤S530中，先在第一栅极绝缘层22上沉积第一金属层；然后，通过构图工艺，形成第一薄膜晶体管20的第一栅极23，第一栅极23位于衬底基板10的第一区11内、第一有源层21的上方。
步骤S540、形成所述第一薄膜晶体管的第一层间绝缘层。
具体地，请继续参阅图14和图15，在步骤S540中，在第一栅极绝缘层22和第一栅极23上沉积第一层间绝缘膜层，形成第一层间绝缘层24，第一层间绝缘层24覆盖第一栅极绝缘层22和第一栅极23。
步骤S550、去除第一栅极绝缘层和第一层间绝缘层位于衬底基板上形成第一薄膜晶体管的区域以外的部分，并形成贯穿第一层间绝缘层和第一栅极绝缘层的第一连接孔和第二连接孔，其中，第一栅极绝缘层和第一层间绝缘层的侧面位于衬底基板形成第一薄膜晶体管的区域内；第一连接孔和第二连接孔均暴露出第一有源层。
具体地，请继续参阅图14和图15，在步骤S550中，通过构图工艺，将第一栅极绝缘层22和第一层间绝缘层24除位于衬底基板10上形成第一薄膜晶体管20的第一区11之外的部分去除，即去除第一栅极绝缘层22和第一层 间绝缘层24位于第一区11以外的部分，并形成第一连接孔242和第二连接孔243，其中，第一栅极绝缘层22只覆盖第一有源层21和位于第一区11内的衬底基板10，第一层间绝缘层24覆盖第一栅极23和第一栅极绝缘层22，第一栅极绝缘层22和第一层间绝缘层24均具有环绕第一薄膜晶体管20的侧面；第一连接孔242和第二连接孔243分别贯穿第一层间绝缘层24和第一栅极绝缘层22，并均暴露出第一有源层21，以方便后续形成的第一源漏极中第一源极25和第一漏极26分别与第一有源层21之间的连接。
步骤S560、形成第一薄膜晶体管的第一源漏极、第二薄膜晶体管的第二栅极和第一隔离挡墙的第三部，其中，第一源漏极包括第一源极和第一漏极，第一源极通过第一连接孔与第一有源层连接，第一漏极通过第二连接孔与第一有源层连接；第三部覆盖第一层间绝缘层的边缘和侧面，以及第一栅极绝缘层的侧面；第二栅极位于衬底基板上。
具体地，请继续参阅图14和图15，在步骤S560中，先沉积第二金属层；然后通过构图工艺，同时形成第一薄膜晶体管20的第一源漏极、第二薄膜晶体管30的第二栅极31和第一隔离挡墙50的第三部51，其中，第一源漏极中，第一源极25通过第一连接孔242与第一有源层21连接，第一漏极26通过第二连接孔243与第一有源层21连接；第一隔离挡墙50的第三部51覆盖第一层间绝缘层24的边缘和侧面，以及第一栅极绝缘层22的侧面；第二栅极31位于衬底基板10上、第二区12内。也就是说，第一薄膜晶体管20的第一源漏极、第二薄膜晶体管30的第二栅极31和第一隔离挡墙50的第三部51通过一次构图工艺形成，从而可以减少制造薄膜晶体管结构的工艺步骤，同时，减少制造薄膜晶体管结构时所使用的掩膜版的数量，进而减低制造薄膜晶体管结构的成本。
请参阅图14和图16，步骤S600、在衬底基板上形成第二薄膜晶体管和第一隔离挡墙的第四部，可以包括：
步骤S610、形成第二薄膜晶体管的第二栅极绝缘层。
具体地，请继续参阅图14和图16，在步骤S610中，沉积第二栅极绝缘膜层，形成第二栅极绝缘层32，第二栅极绝缘层32覆盖第一薄膜晶体管20、衬底基板10、第三部51和第二薄膜晶体管30的第二栅极31。
步骤S620、形成第二薄膜晶体管的第二有源层。
具体地，请继续参阅图14和图16，在步骤S620中，可以先在第二栅极 绝缘层32上沉积金属氧化物膜层；然后通过构图工艺，形成第二薄膜晶体管30的第二有源层33，第二有源层33位于第二栅极31的上方。
步骤S630、在第二栅极绝缘层内形成环绕第一薄膜晶体管且对应于第三部的第三过孔，以及对应于第一薄膜晶体管的第一源极的第三连接孔或对应于第一薄膜晶体管的第一漏极的第四连接孔。
具体地，请继续参阅图14和图16，在步骤S630中，通过构图工艺，在第二栅极绝缘层32内形成第三过孔323，第三过孔323环绕第一薄膜晶体管20，第三过孔323暴露出第一隔离挡墙50的第三部51，以便后续形成环绕第一薄膜晶体管20的第一隔离挡墙50的第四部52。
在步骤S630中，通过构图工艺，在第二栅极绝缘层32内还形成第三连接孔，第三连接孔对应于第一薄膜晶体管20的第一源极25，以方便通过后续形成的连接电极27将第一源极25和其它结构连接；或者，通过构图工艺，在第二栅极绝缘层32内还形成第四连接孔324，第四连接孔324对应于第一薄膜晶体管20的第一漏极26，以方便通过后续形成的连接电极27将第一漏极26和其它结构连接。
步骤S640、形成第二薄膜晶体管的第二源漏极、填充在第三过孔内且与第三部接触的第四部、以及通过第三连接孔连接第一源极或通过第四连接孔连接第一漏极的连接电极。
具体地，请继续参阅图14和图16，在步骤S640中，先沉积第三金属层；然后通过构图工艺，同时形成第一隔离挡墙50的第四部52、第二薄膜晶体管30的第二源漏极和第一薄膜晶体管20的连接电极27，其中，第四部52填充在第三过孔323内，第四部52与第三部51接触，第三部51和第四部52共同构成第一隔离挡墙50，以环绕第一薄膜晶体管20，将第二薄膜晶体管30与第一薄膜晶体管20隔离；第二薄膜晶体管30的第二源漏极包括第二源极34和第二漏极35，第二源极34和第二漏极35分别与第二有源层33接触；连接电极27位于第二栅极绝缘层32上，连接电极27通过第三连接孔连接第一源极25，或者，连接电极27通过第四连接孔324连接第一漏极26。也就是说，第一隔离挡墙50的第四部52、第二源漏极和连接电极27通过一次构图工艺形成，从而可以减少制造薄膜晶体管结构的工艺步骤，同时，减少制造薄膜晶体管结构时所使用的掩膜版的数量，进而减低制造薄膜晶体管结构的成本。
对于存在第一隔离挡墙50和第二隔离挡墙40二者的薄膜晶体管结构的制造方法，第一隔离挡墙50和第二隔离挡墙40的制造方法可以分别参照以上的实施例。例如，第一隔离挡墙50具有图3所示的结构且第二隔离挡墙40具有图1所示的结构时，可以在参照图15和16以及图7和图8的制造方法来形成二者，其中，第二隔离挡墙40的填充孔可以在形成第一隔离挡墙50的第二部时一起形成。例如。第一隔离挡墙50具有图3所示的结构且第二隔离挡墙40具有图2所示的结构时，可以参照图11和12以及图15和16来形成二者，示例性地，第一隔离挡墙50和第二隔离挡墙40可以共用二者交界处的隔离挡墙，或者，在二者的交界处，第一隔离挡墙50的第三部可以在第二隔离挡墙的第一部之后形成，或者，第一隔离挡墙50的第三部可以在第二隔离挡墙的第一部之前形成，之后形成的第三部或第一部可以在垂直于衬底基板的方向上覆盖第一部或第三部的部分或全部，也就是，在垂直于衬底基板的方向具有交叠。备选地，之后形成的第三部或第一部可以在垂直于衬底基板的方向上可以不覆盖之前形成的第一部或第三部，而只是在平行于衬底基板的方向上交叠。本公开的实施例并不对此进行限制。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2017年7月28日递交的中国专利申请第201710629740.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (18)

  1. 一种薄膜晶体管结构，包括：
    衬底基板；以及
    第一薄膜晶体管和第二薄膜晶体管，形成在所述衬底基板上，
    其中，所述第一薄膜晶体管的第一有源层掺杂有氢；所述第二薄膜晶体管的第二有源层的材料为金属氧化物；所述衬底基板上还设置有环绕所述第一薄膜晶体管的第一隔离挡墙或/和环绕所述第二薄膜晶体管的第二隔离挡墙。
  2. 根据权利要求1所述的薄膜晶体管结构，其特征在于，所述第二薄膜晶体管的第二栅极绝缘层覆盖所述第一薄膜晶体管，所述第二栅极绝缘层内设置有环绕所述第二薄膜晶体管的第一过孔，所述第二隔离挡墙填充所述第一过孔。
  3. 根据权利要求1所述的薄膜晶体管结构，所述第二隔离挡墙包括第一部和第二部，其中，
    所述第一部位于所述衬底基板上，且所述第一部覆盖所述第一薄膜晶体管的第一绝缘层的环绕所述第二薄膜晶体管的边缘和侧面；
    所述第二薄膜晶体管的第二栅极绝缘层覆盖所述第一薄膜晶体管和所述第一部，所述第二栅极绝缘层与所述第一部对应的区域设置有环绕所述第二薄膜晶体管的第二过孔，所述第二部填充所述第二过孔，且所述第二部与所述第一部接触。
  4. 根据权利要求1所述的薄膜晶体管结构，其中所述第一隔离挡墙包括第三部和第四部，其中，
    所述第三部位于所述衬底基板上，且所述第三部覆盖所述第一薄膜晶体管的第一绝缘层的位于所述衬底基板上形成在所述第一薄膜晶体管的区域内且环绕所述第一薄膜晶体管的边缘和侧面；
    所述第二薄膜晶体管的第二栅极绝缘层覆盖所述第一薄膜晶体管和所述第三部，所述第二栅极绝缘层与所述第三部对应的区域设置有环绕所述第一薄膜晶体管的第三过孔，所述第四部填充所述第三过孔，且所述第四部与所述第三部接触。
  5. 根据权利要求2～4任一所述的薄膜晶体管结构，其中，所述第一薄膜晶体管为低温多晶硅薄膜晶体管，所述第二薄膜晶体管为底栅薄膜晶体管。
  6. 根据权利要求5所述的薄膜晶体管结构，其中所述第一薄膜晶体管包括位于所述第二栅极绝缘层上的连接电极，所述连接电极通过所述第二栅极绝缘层内的第一连接孔与所述第一薄膜晶体管中所述第一源漏极的漏极连接，或者，所述连接电极通过所述第二栅极绝缘层内的第二连接孔与所述第一薄膜晶体管中所述第一源漏极的源极连接。
  7. 根据权利要求1-6中任一项所述的薄膜晶体管结构，其中所述第一隔离挡墙为有机材料隔离挡墙、无机材料隔离挡墙或金属隔离挡墙；
    所述第二隔离挡墙为有机材料隔离挡墙、无机材料隔离挡墙或金属隔离挡墙。
  8. 根据权利要求4所述的薄膜晶体管结构，其中所述第一绝缘层包括所述第一薄膜晶体管的第一栅极绝缘层和覆盖所述第一薄膜晶体管的第一栅极的第一层间绝缘层。
  9. 根据权利要求8所述的薄膜晶体管结构，其中所述第三部覆盖所述第一薄膜晶体管的第一绝缘层的位于所述衬底基板上形成在所述第一薄膜晶体管的区域内且环绕所述第一薄膜晶体管的边缘和侧面包括：
    所述第三部覆盖所述第一薄膜晶体管的第一栅极绝缘层的位于所述衬底基板上形成在所述第一薄膜晶体管的区域内且环绕所述第一薄膜晶体管的侧面以及所述第三部覆盖所述第一薄膜晶体管的第一层间绝缘层的位于所述衬底基板上形成在所述第一薄膜晶体管的区域内且环绕所述第一薄膜晶体管的边缘和侧面。
  10. 一种显示面板，所述显示面板包括如权利要求1～9中任一所述的薄膜晶体管结构。
  11. 一种显示装置，所述显示装置包括如权利要求10所述的显示面板。
  12. 一种如权利要求1-9中任一项所述的薄膜晶体管结构的制造方法，其中，包括：
    在衬底基板上形成第一薄膜晶体管和第二薄膜晶体管，以及第一隔离挡墙或/和第二隔离挡墙，其中，所述第一薄膜晶体管的第一有源层掺杂有氢；所述第二薄膜晶体管的第二有源层的材料为金属氧化物；所述第一隔离挡墙 环绕所述第一薄膜晶体管，所述第二隔离挡墙环绕所述第二薄膜晶体管。
  13. 根据权利要求12所述的薄膜晶体管结构的制造方法，其中，所述第一薄膜晶体管为低温多晶硅薄膜晶体管，所述第二薄膜晶体管为底栅薄膜晶体管；
    在衬底基板上形成第一薄膜晶体管、第二薄膜晶体管和第二隔离挡墙，包括：
    在所述衬底基板上形成所述第一薄膜晶体管；
    在所述衬底基板上形成所述第二薄膜晶体管和环绕所述第二薄膜晶体管的第二隔离挡墙。
  14. 根据权利要求13所述的薄膜晶体管结构的制造方法，其中，
    在所述衬底基板上形成所述第一薄膜晶体管，包括：
    形成所述第一薄膜晶体管的第一有源层；
    形成所述第一薄膜晶体管的第一栅极绝缘层；
    形成所述第一薄膜晶体管的第一栅极；
    形成所述第一薄膜晶体管的第一层间绝缘层；
    形成贯穿所述第一层间绝缘层和所述第一栅极绝缘层的暴露孔、第一连接孔和第二连接孔，所述暴露孔暴露出所述衬底基板上形成所述第二薄膜晶体管的区域，所述第一连接孔和所述第二连接孔均暴露出所述第一有源层；
    形成所述第一薄膜晶体管的第一源漏极和所述第二薄膜晶体管的第二栅极，其中，所述第一源漏极包括第一源极和第一漏极，所述第一源极通过所述第一连接孔与所述第一有源层连接，所述第一漏极通过所述第二连接孔与所述第一有源层连接；所述第二栅极位于所述衬底基板上、所述暴露孔内；
    在所述衬底基板上形成所述第二薄膜晶体管和环绕所述第二薄膜晶体管的所述第二隔离挡墙，包括：
    形成所述第二薄膜晶体管的第二栅极绝缘层；
    形成所述第二薄膜晶体管的第二有源层；
    在所述第二栅极绝缘层内形成环绕所述第二薄膜晶体管且暴露出所述衬底基板的第一过孔，以及对应于所述第一薄膜晶体管的第一源极的第三连接孔或对应于所述第一薄膜晶体管的第一漏极的第四连接孔；
    形成所述第二薄膜晶体管的第二源漏极、填充在所述第一过孔内的所述第二隔离挡墙、以及通过所述第三连接孔连接所述第一源极或通过所述第四 连接孔连接所述第一漏极的连接电极。
  15. 根据权利要求12所述的薄膜晶体管结构的制造方法，其特征在于，所述第一薄膜晶体管为低温多晶硅薄膜晶体管，所述第二薄膜晶体管为底栅薄膜晶体管；
    在衬底基板上形成第一薄膜晶体管、第二薄膜晶体管和第二隔离挡墙，包括：
    在所述衬底基板上形成所述第一薄膜晶体管和所述第二隔离挡墙的第一部，所述第一部覆盖所述第一薄膜晶体管的第一绝缘层的环绕所述第二薄膜晶体管的边缘和侧面；
    在所述衬底基板上形成所述第二薄膜晶体管和所述第二隔离挡墙的第二部，所述第二部位于所述第一部上，所述第一部和所述第二部共同环绕所述第二薄膜晶体管。
  16. 根据权利要求15所述的薄膜晶体管结构的制造方法，其特征在于，
    在所述衬底基板上形成所述第一薄膜晶体管和所述第二隔离挡墙的第一部，包括：
    形成所述第一薄膜晶体管的第一有源层；
    形成所述第一薄膜晶体管的第一栅极绝缘层；
    形成所述第一薄膜晶体管的第一栅极；
    形成所述第一薄膜晶体管的第一层间绝缘层；
    形成贯穿所述第一层间绝缘层和所述第一栅极绝缘层的暴露孔、第一连接孔和第二连接孔，所述暴露孔暴露出所述衬底基板上形成所述第二薄膜晶体管的区域，所述第一连接孔和所述第二连接孔均暴露出所述第一有源层；
    形成第一薄膜晶体管的第一源漏极、所述第二薄膜晶体管的第二栅极和所述第二隔离挡墙的第一部，其中，所述第一源漏极包括第一源极和第一漏极，所述第一源极通过所述第一连接孔与所述第一有源层连接，所述第一漏极通过所述第二连接孔与所述第一有源层连接；所述第一部覆盖所述暴露孔的边缘和孔壁；所述第二栅极位于所述衬底基板上、所述暴露孔内；
    在所述衬底基板上形成所述第二薄膜晶体管和所述第二隔离挡墙的第二部，包括：
    形成所述第二薄膜晶体管的第二栅极绝缘层；
    形成所述第二薄膜晶体管的第二有源层；
    在所述第二栅极绝缘层内形成环绕所述第二薄膜晶体管且对应于所述第一部的第二过孔，以及对应于所述第一薄膜晶体管的第一源极的第三连接孔或对应于所述第一薄膜晶体管的第一漏极的第四连接孔；
    形成所述第二薄膜晶体管的第二源漏极、填充在所述第二过孔内且与所述第一部接触的第二部、以及通过所述第三连接孔连接所述第一源极或通过所述第四连接孔连接所述第一漏极的连接电极。
  17. 根据权利要求12所述的薄膜晶体管结构的制造方法，其特征在于，所述第一薄膜晶体管为低温多晶硅薄膜晶体管，所述第二薄膜晶体管为底栅薄膜晶体管；
    在衬底基板上形成第一薄膜晶体管、第二薄膜晶体管和第一隔离挡墙，包括：
    在所述衬底基板上形成所述第一薄膜晶体管和所述第一隔离挡墙的第三部，所述第三部覆盖所述第一薄膜晶体管的第一绝缘层环绕所述第一薄膜晶体管的边缘和侧面；
    在所述衬底基板上形成所述第二薄膜晶体管和所述第一隔离挡墙的第四部，所述第四部位于所述第三部上，所述第三部和第四部共同环绕所述第一薄膜晶体管。
  18. 根据权利要求17所述的薄膜晶体管结构的制造方法，其特征在于，
    在所述衬底基板上形成所述第一薄膜晶体管和所述隔离挡墙的第三部，包括：
    形成所述第一薄膜晶体管的第一有源层；
    形成所述第一薄膜晶体管的第一栅极绝缘层；
    形成所述第一薄膜晶体管的第一栅极；
    形成所述第一薄膜晶体管的第一层间绝缘层；
    去除所述第一栅极绝缘层和所述第一层间绝缘层位于所述衬底基板上形成所述第一薄膜晶体管的区域以外的部分，并形成贯穿所述第一层间绝缘层和所述第一栅极绝缘层的第一连接孔和第二连接孔，其中，所述第一栅极绝缘层和所述第一层间绝缘层的侧面位于所述衬底基板形成所述第一薄膜晶体管的区域内；所述第一连接孔和所述第二连接孔均暴露出所述第一有源层；
    形成第一薄膜晶体管的第一源漏极、所述第二薄膜晶体管的第二栅极和 所述第一隔离挡墙的第三部，其中，所述第一源漏极包括第一源极和第一漏极，所述第一源极通过所述第一连接孔与所述第一有源层连接，所述第一漏极通过所述第二连接孔与所述第一有源层连接；所述第三部覆盖所述第一层间绝缘层的边缘和侧面，以及所述第一栅极绝缘层的侧面；所述第二栅极位于所述衬底基板上；
    在所述衬底基板上形成所述第二薄膜晶体管和所述第一隔离挡墙的第四部，包括：
    形成所述第二薄膜晶体管的第二栅极绝缘层；
    形成所述第二薄膜晶体管的第二有源层；
    在所述第二栅极绝缘层内形成环绕所述第一薄膜晶体管且对应于所述第三部的第三过孔，以及对应于所述第一薄膜晶体管的第一源极的第三连接孔或对应于所述第一薄膜晶体管的第一漏极的第四连接孔；
    形成所述第二薄膜晶体管的第二源漏极、填充在所述第三过孔内且与所述第三部接触的第四部、以及通过所述第三连接孔连接所述第一源极或通过所述第四连接孔连接所述第一漏极的连接电极。
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107452756B (zh) * 2017-07-28 2020-05-19 京东方科技集团股份有限公司 薄膜晶体管结构及其制造方法、显示面板、显示装置
CN107393934B (zh) 2017-08-14 2020-02-21 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
CN107507841B (zh) * 2017-09-22 2021-01-22 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN108321159B (zh) * 2018-02-01 2021-01-26 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN109003991A (zh) * 2018-08-01 2018-12-14 京东方科技集团股份有限公司 阵列基板及其制作方法和显示面板
WO2020211087A1 (zh) * 2019-04-19 2020-10-22 京东方科技集团股份有限公司 阵列基板、其制备方法及显示装置
CN110148600A (zh) * 2019-05-05 2019-08-20 深圳市华星光电半导体显示技术有限公司 阵列基板及制备方法
US11121263B2 (en) * 2019-08-27 2021-09-14 Apple Inc. Hydrogen trap layer for display device and the same
EP4064361A4 (en) * 2019-12-13 2023-02-08 Huawei Technologies Co., Ltd. DISPLAY SCREEN AND ELECTRONIC DEVICE
CN113066818B (zh) * 2019-12-13 2022-10-04 华为技术有限公司 一种显示屏和电子设备
US20230139734A1 (en) * 2020-11-20 2023-05-04 Mianyang BOE Optoelectronics Technology Co.,Ltd. Display Substrate and Manufacturing Method Thereof, and Display Apparatus
CN112510069B (zh) * 2020-11-27 2022-07-01 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN112736092B (zh) * 2020-12-30 2024-03-08 武汉华星光电半导体显示技术有限公司 阵列基板及其制备方法、显示面板
CN115298823A (zh) * 2021-02-01 2022-11-04 京东方科技集团股份有限公司 驱动背板及其制备方法、显示装置
CN113113424B (zh) * 2021-03-17 2024-02-02 武汉华星光电半导体显示技术有限公司 显示面板
CN113113428B (zh) * 2021-03-25 2023-04-07 武汉华星光电技术有限公司 一种阵列基板及其制备方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1303128A (zh) * 2000-01-03 2001-07-11 因芬尼昂技术股份公司 铁电半导体存储器的制法
CN101322241A (zh) * 2005-11-29 2008-12-10 富士通株式会社 半导体器件及其制造方法
CN101339924A (zh) * 2007-07-04 2009-01-07 冲电气工业株式会社 半导体器件
US20110024774A1 (en) * 2009-07-29 2011-02-03 Tredwell Timothy J Digital radiographic flat-panel imaging array with dual height semiconductor and method of making same
CN104025269A (zh) * 2012-11-12 2014-09-03 深圳市柔宇科技有限公司 一种自对准金属氧化物薄膜晶体管器件及制造方法
KR20170049666A (ko) * 2015-10-27 2017-05-11 엘지디스플레이 주식회사 박막 트랜지스터 기판
CN107452756A (zh) * 2017-07-28 2017-12-08 京东方科技集团股份有限公司 薄膜晶体管结构及其制造方法、显示面板、显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102162885B1 (ko) * 2013-11-25 2020-10-08 엘지디스플레이 주식회사 어레이기판 및 이의 제조방법
CN106876412A (zh) * 2017-03-15 2017-06-20 厦门天马微电子有限公司 一种阵列基板以及制作方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1303128A (zh) * 2000-01-03 2001-07-11 因芬尼昂技术股份公司 铁电半导体存储器的制法
CN101322241A (zh) * 2005-11-29 2008-12-10 富士通株式会社 半导体器件及其制造方法
CN101339924A (zh) * 2007-07-04 2009-01-07 冲电气工业株式会社 半导体器件
US20110024774A1 (en) * 2009-07-29 2011-02-03 Tredwell Timothy J Digital radiographic flat-panel imaging array with dual height semiconductor and method of making same
CN104025269A (zh) * 2012-11-12 2014-09-03 深圳市柔宇科技有限公司 一种自对准金属氧化物薄膜晶体管器件及制造方法
KR20170049666A (ko) * 2015-10-27 2017-05-11 엘지디스플레이 주식회사 박막 트랜지스터 기판
CN107452756A (zh) * 2017-07-28 2017-12-08 京东方科技集团股份有限公司 薄膜晶体管结构及其制造方法、显示面板、显示装置

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