WO2018233672A1 - 一种芯片封装结构 - Google Patents

一种芯片封装结构 Download PDF

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Publication number
WO2018233672A1
WO2018233672A1 PCT/CN2018/092246 CN2018092246W WO2018233672A1 WO 2018233672 A1 WO2018233672 A1 WO 2018233672A1 CN 2018092246 W CN2018092246 W CN 2018092246W WO 2018233672 A1 WO2018233672 A1 WO 2018233672A1
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Prior art keywords
chip
package structure
thin film
heat pipe
chip package
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PCT/CN2018/092246
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English (en)
French (fr)
Inventor
符会利
林志荣
张相雄
蔡树杰
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2018233672A1 publication Critical patent/WO2018233672A1/zh
Priority to US16/723,269 priority Critical patent/US20200135615A1/en

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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal

Definitions

  • the present application relates to the field of information technology, and in particular, to a chip package structure.
  • FIG. 1 shows a heat dissipation method in the prior art, in which a chip 2 is fixed on a substrate 1 by a solder ball 4, through a thermal interface material layer 3 and a planar heat pipe 5 having an ultrahigh thermal conductivity. connection.
  • the transfer of heat from the chip 2 to the package surface 6 is enhanced by replacing the conventional heat sink cover (copper) with a planar heat pipe 5.
  • the above-mentioned conventional thermal interface material layer 3 has a high thermal resistance, which severely limits the benefits of using a planar heat pipe and becomes a major bottleneck on the chip heat dissipation channel.
  • the traditional package structure uses only passive heat dissipation, which limits the control of the chip temperature to some extent.
  • the present application provides a chip package structure for solving the problem of heat dissipation of the chip package structure in the prior art.
  • a chip package structure includes: a substrate, and a chip, further comprising: a heat dissipation ring fixed on the substrate; and a planar heat pipe heat sink covering the heat dissipation ring, and The substrate, the heat dissipation ring and the planar heat pipe heat sink enclose a space for accommodating the chip, the chip is located in the space and is fixedly connected to the substrate, and the planar heat pipe heat sink faces one side of the chip A first metal thin film layer is disposed, and the chip is thermally coupled to the first metal thin film layer through a sintered metal layer.
  • the heat dissipation of the chip is performed by using a planar heat pipe heat sink, and the first metal film layer is disposed on one side of the planar heat pipe heat sink for the heat dissipation capability between the strong chip and the planar heat pipe heat sink, and the first metal is
  • the thin film layer is connected to the chip through the sintered metal layer, and the sintered metal layer has a good heat transfer effect, and the heat can be quickly transferred to the planar heat pipe heat sink, thereby effectively improving the heat dissipation effect of the chip.
  • a side of the chip facing the planar heat pipe heat sink is provided with a second metal thin film layer, and the sintered metal layer is thermally coupled to the second metal thin film layer.
  • the heat dissipation effect of the chip is further improved by providing a second metal thin film layer on the chip.
  • the sintered metal layer includes a plurality of metal particles and a filled layer encasing the plurality of metal particles.
  • the metal particles may be silver particles, aluminum particles, copper particles, magnesium particles or gold particles or the like.
  • the metal particles are sintered with the first metal thin film layer and the second metal thin film layer to form an atomic continuous phase structure. Further improve the heat dissipation effect.
  • the fill layer is an air layer or a glue layer.
  • the filling layer is formed by different materials.
  • the first metal thin film layer is disposed on the planar heat pipe heat sink by sputtering or electroplating; the second metal thin film layer is disposed on the chip by sputtering or electroplating .
  • the first metal thin film layer and the second metal thin film layer are formed by different processes.
  • the number of the chips is m
  • a thermoelectric cooling sheet is disposed between the n chips and the planar heat pipe heat sink, and one side of the thermoelectric cooling sheet and the plane The heat pipe heat sink is connected, and the other side is thermally coupled to the chip through the sintered metal layer; wherein m and n are integers, and m ⁇ 1, m ⁇ n. The heat-dissipating effect is further improved by the thermoelectric cooling sheet.
  • thermoelectric cooling fin is a thermoelectrically cooled thermostat. Therefore, the power of the thermoelectric cooling sheet can be adjusted according to different heat dissipation requirements.
  • thermoelectric cooling sheet is provided with a third metal thin film layer toward one side of the chip. Further improve the heat dissipation effect.
  • the third metal thin film layer is disposed on the thermoelectric cooling sheet by sputtering or electroplating.
  • a third metal thin film layer is formed by a different process.
  • the heat dissipation ring is adhesively connected to the substrate and the planar heat pipe heat sink, respectively.
  • the heat sink ring and the planar heat pipe heat sink adopt a split structure.
  • the heat dissipation ring is integrally formed with the planar heat pipe heat sink, and the heat dissipation ring is adhesively coupled to the substrate.
  • the heat ring and the planar heat sink adopt an integrated structure.
  • FIG. 1 is a schematic structural view of a chip package structure in the prior art
  • FIG. 2 is a schematic structural diagram of a chip package structure provided by the present application.
  • FIG. 3 is a schematic structural diagram of another chip package structure provided by the present application.
  • FIG. 4 is a schematic structural view of a chip and a planar heat pipe heat sink provided by the present application.
  • FIG. 5 is a schematic structural diagram of another chip package structure provided by the present application.
  • FIG. 6 is a schematic structural diagram of another chip package structure provided by the present application.
  • the present application provides a chip package structure including a substrate and a chip including, but not limited to, a wire bond chip and a flip chip.
  • the number of the chips may be one or more, and when a plurality of chips are used, the chips may be different types of chips.
  • the substrate 101 may be bonded to the other by the solder balls 100.
  • the number of chips is two, and the two chips are a logic chip 104 and a memory chip 105, respectively.
  • the chip can also be other types of chips, and the above logic chip 104 and memory chip 105 are merely examples.
  • the heat dissipation ring 103 is a frame-shaped structure, and the heat dissipation ring 103 is covered with a planar heat pipe heat sink 107, thereby The substrate 101 and the heat-dissipating ring 103 planar heat pipe heat sink 107 are enclosed to accommodate the space of the chip, and the chip is wrapped.
  • the logic chip 104 and the memory chip 105 are fixed on the substrate 101.
  • the chip can be fixedly connected to the substrate 101 by the solder balls 109.
  • the logic chip 104 and the memory chip 105 are soldered to the substrate 101 by solder balls 109, respectively. Thereby, the logic chip 104 and the memory chip 105 can be stably fixed on the substrate 101.
  • the chip package structure provided in this embodiment uses different methods to dissipate heat from the chip. The following describes the specific embodiment.
  • the chip package structure includes a substrate 101, and two chips, which are a logic chip 104 and a memory chip 105, respectively.
  • the chip is fixed on the substrate 101, and the heat dissipation ring 103 is fixed on the substrate 101.
  • the heat dissipation ring 103 is a frame-shaped structure, and the heat dissipation ring 103 is covered with a planar heat pipe heat sink 107, thereby making the substrate 101 and heat dissipation.
  • the ring 103 planar heat pipe heat sink 107 encloses a space for accommodating the chip and wraps the chip.
  • the logic chip 104 and the memory chip 105 are fixed on the substrate 101.
  • the chip can be fixedly connected to the substrate 101 by the solder balls 109.
  • the logic chip 104 and the memory chip 105 are soldered to the substrate 101 by solder balls 109, respectively. Thereby, the logic chip 104 and the memory chip 105 can be stably fixed on the substrate 101.
  • the heat-dissipating ring 103 and the planar heat pipe heat sink 107 may be disposed separately or in an integrated manner. As shown in FIG. 2, in the structure shown in FIG. 2, the heat dissipation ring 103 and the planar heat pipe heat sink 107 are in a split design manner. At this time, the heat dissipation ring 103 is bonded to the substrate 101 and the planar heat pipe heat sink 107, respectively. .
  • one surface of the heat dissipation ring 103 is bonded to the substrate 101 by the adhesive 102, and the other surface is connected to the planar heat pipe heat sink 107 by the adhesive 102.
  • the heat dissipation ring 103 and the planar heat pipe heat sink 107 are integrally formed.
  • the heat dissipation ring 103 and the planar heat pipe heat sink 107 are integrally formed by a mold to form a cover body.
  • the structure, and after the chip is fixed on the substrate 101, the cover is covered on the substrate 101 to wrap the chip.
  • the heat-dissipating ring 103 and the substrate 101 are connected by bonding, for example, the heat-dissipating ring 103 and the substrate 101 are bonded and bonded by the adhesive 102.
  • the chip package structure is dissipated by the heat dissipation ring 103 and the planar heat pipe heat sink 107.
  • the planar heat pipe heat sink 107 serves as a heat dissipation cover.
  • the planar heat pipe radiator 107 can enhance the uniformity of heat on the heat dissipation cover to enhance the transfer of heat from the heat dissipation cover to the external environment (including the external heat sink), thereby effectively reducing the junction temperature of the chip.
  • a hollow cavity 108 is formed in the heat dissipation cover.
  • the heat dissipating ring 103 When the heat dissipating ring 103 is connected to the planar heat pipe heat sink 107, the heat dissipating ring 103 is adhesively connected to the heat dissipating cover.
  • the heat dissipating ring 103 and the heat dissipating cover form an integral structure.
  • the planar heat pipe heat sink 107 When the chip is connected to the planar heat pipe heat sink 107, in order to improve the heat dissipation effect, the planar heat pipe heat sink 107 provided in this embodiment is provided with a first metal film layer 110 facing one side of the chip, and the first metal film layer 110 is splashed.
  • the method of spraying or plating is formed on the metal thin film layer of the chip, but it should be understood that the manner of forming the first metal thin film layer 110 includes, but is not limited to, sputtering and plating, and may be other preparation methods.
  • the chip is thermally coupled to the first metal thin film layer 110 through the sintered metal layer 106. Specifically, as shown in FIG.
  • the logic chip 104 and the memory chip 105 face the planar heat pipe heat sink 107 through the sintered metal layer 106 and the first.
  • the metal thin film layer 110 is connected.
  • the sintered metal layer 106 includes a plurality of metal particles 113 and a filling layer 112 enclosing a plurality of metal particles 113.
  • the filling layer 112 is an air layer or a glue layer, or a filling layer 112 formed of other materials.
  • the first metal thin film layer 110 forms an atomic-level continuous phase structure with the metal particles 113, thereby reducing the thermal resistance of the connection structure between the chip and the planar heat pipe heat sink 107, thereby improving the heat dissipation effect.
  • the metal particles 113 may be metal particles such as silver particles, aluminum particles, copper particles, magnesium particles or gold particles.
  • the second metal thin film layer 111 is disposed on one side of the chip facing the planar heat pipe heat sink 107, and the sintered metal layer 106 is thermally coupled with the second metal thin film layer 111 to further reduce the chip and the plane.
  • the heat resistance of the connection structure between the heat pipe radiators 107 improves the heat dissipation effect.
  • the second metal thin film layer 111 is formed on the chip by electroplating or sputtering, but it should be understood that the manner of forming the second metal thin film layer 111 includes, but is not limited to, sputtering and electroplating. Other preparation methods are also possible; in the structure shown in FIG.
  • the memory chip 105 and the logic chip 104 are formed on one side of the planar heat pipe heat sink 107 by electroplating or sputtering to form one or more layers of the second metal film.
  • Layer 111 When the second metal thin film layer 111 is connected to the sintered metal layer 106, the second metal thin film layer 111 and the metal particles 113 in the sintered metal layer 106 form an atomic-level continuous phase structure.
  • the heat dissipation channel formed between the chip and the planar heat pipe heat sink 107 includes: a first metal film layer 110, a sintered metal layer 106, a second metal film layer 111, and when disposed, the sintered metal layer 106 and the first
  • the metal thin film layer 110 and the second metal thin film layer 111 are sintered to form an atomic-level continuous phase structure, so that the thermal resistance of the first metal thin film layer 110, the sintered metal layer 106, and the second metal thin film layer 111 can be effectively reduced.
  • the heat on the chip can be quickly transferred to the planar heat pipe radiator 107.
  • the present application provides a chip package structure that can improve the heat dissipation effect, and the chip package structure can improve the heat dissipation capability of the package structure in the case of system-level multi-chip sealing, and can effectively control the chip temperature.
  • the chip package structure provided in the present application can quickly transfer heat generated by different chips to the planar heat pipe heat sink 107 through the sintered metal layer 106, compared with the thermal interface material layer used in the chip package structure of the prior art.
  • the thermal conductivity of the thermal interface material is on the order of 4 W/mK, and the thermal conductivity of the sintered metal layer 106 in the present application is on the order of 100 W/mK.
  • the use of the sintered metal layer 106 enables the chip to be planar.
  • the heat resistance of the heat pipe radiator 107 is reduced by about 25 times, which can effectively lower the junction temperature of the chip, so that heat is transferred to the planar heat pipe radiator 107 as soon as possible, and the planar heat pipe radiator 107 can quickly heat the heat, which strengthens the heat.
  • the ability to transfer from the planar heat pipe radiator 107 to the environment, thereby effectively reducing the junction temperature of the chip, will be particularly significant for high power chips.
  • the substrate 101, the chip, the planar heat pipe heat sink 107, and the heat dissipation ring 103 of the chip package structure provided in this embodiment can adopt the structure in the first embodiment.
  • the heat dissipation ring 103 and the planar heat pipe heat sink 107 are in a split design. At this time, the heat dissipation ring 103 is bonded to the substrate 101 and the planar heat pipe heat sink 107, respectively. That is, one surface of the heat dissipation ring 103 is bonded to the substrate 101 by the adhesive 102, and the other surface is connected to the planar heat pipe heat sink 107 by the adhesive 102. As shown in FIG. 5, in the structure shown in FIG. 5, the heat dissipation ring 103 and the planar heat pipe heat sink 107 adopt an integrated structure.
  • the heat dissipation ring 103 and the planar heat pipe heat sink 107 are integrally formed by a mold to form a cover body.
  • the heat-dissipating ring 103 and the substrate 101 are bonded by bonding.
  • the heat-dissipating ring 103 and the substrate 101 are bonded and bonded by the adhesive 102.
  • thermoelectric cooling sheet 114 is added, and when the number of chips is plural, the chip generates more heat during operation.
  • the thermoelectric cooling fins 114 may be provided correspondingly to all the chips.
  • the number of the chips is m
  • the thermoelectric cooling fins 114 are disposed between the n chips and the planar heat pipe radiator 107, and one surface of the thermoelectric cooling fins 114 is connected to the planar heat pipe radiator 107, and the other surface is passed through the sintered metal layer.
  • thermoelectric cooling fins 114 are adhesively connected to the planar heat pipe heat sink 107, and the thermoelectric cooling fins 114 are provided with a third metal thin film layer toward one side of the chip.
  • the third metal thin film layer is formed on the memory chip 105 by sputtering or electroplating, but it should be understood that the manner of forming the third metal thin film layer includes However, it is not limited to the manner of sputtering and electroplating, but may be other preparation methods.
  • the heat dissipation channels between the memory chip 105 and the planar heat pipe heat sink 107 are: a second metal thin film layer 111, a sintered metal layer 106, a third metal thin film layer, and a thermoelectric cooling sheet 114.
  • thermoelectric cooling fins 114 can effectively control the temperature of the chip.
  • the thermoelectric cooling fins 114 are thermoelectric cooling fins 114 of adjustable power. Therefore, the power of the thermoelectric cooling fins 114 can be adjusted according to different heat dissipation requirements.
  • thermoelectric cooling sheets 114 may be provided according to actual needs.
  • thermoelectric cooling fins 114 when the temperature of the chip needs to be controlled, the temperature of the chip is adjusted by the provided thermoelectric cooling fins 114, thereby further improving the heat dissipation effect and ensuring stable operation of the chip.
  • Embodiment 1 and Embodiment 2 only the heat dissipation structure of the specific chip package structure is shown.
  • the heat dissipation method can adopt Embodiment 1 and
  • the heat dissipation structure in Embodiment 2 can effectively reduce the thermal resistance between the chip and the planar heat pipe heat sink 107 by forming an atomic continuous phase structure between the sintered metal layer 106 and the metal thin film layer, thereby effectively improving the heat dissipation effect of the chip package structure. .

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

一种芯片封装结构，该芯片封装结构包括：基板（101），以及芯片（104，105），还包括：固定在基板（101）上的散热环（103）以及覆盖在散热环（103）上的平面热管散热器（107），且基板（101）、散热环（103）及平面热管散热器（107）围成容纳芯片（104，105）的空间，平面热管散热器（107）朝向芯片（104，105）的一面设置有第一金属薄膜层（110），芯片通过烧结金属层（106）与第一金属薄膜层（110）热耦合连接。采用平面热管散热器对芯片进行散热，并且为了增强芯片到平面热管散热器间的散热能力，采用在平面热管散热器的一面设置第一金属薄膜层，并将第一金属薄膜层通过烧结金属层与芯片连接，该烧结金属层具有良好的热传递效果，可以将热量快速传递到平面热管散热器上，从而可以有效的改善芯片的散热效果。

Description

一种芯片封装结构
本申请要求在2017年6月21日提交中国专利局、申请号为201710479072.2、发明名称为“一种芯片封装结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及信息技术领域，尤其涉及一种芯片封装结构。
背景技术
随着芯片工艺节点的不断下降，芯片的集成度不断上升。在系统级芯片封装中多个异质芯片(逻辑芯片、内存等)及被动元器件被封装集成在一个小尺寸的系统中，封装的整体功耗以及单个芯片的功耗都在不断增加。为了保证芯片能够长期，稳定的工作，需要将管芯的温度控制在一定范围内。这是目前系统级芯片封装所面临的一个重要难题。
目前，将芯片热量更快速传递到封装外部的核心思路是通过引入导热率更高的材料或者优化封装结构，减小热量传递路径上的热阻。图1所示，图1示出了现有技术中的一种散热方式，其中，芯片2通过焊球4固定在基板1上面，通过热界面材料层3与具有超高热导率的平面热管5连接。通过平面热管5来替代传统的散热盖(铜)来强化热量从芯片2向封装表面6的传递。
但是，上述传统热界面材料层3热阻很高，严重限制了使用平面热管所能带来的收益，成为芯片散热通道上的主要瓶颈。此外，传统封装结构仅采用被动散热的方案，这在一定程度上限制了对芯片温度的控制。
发明内容
本申请提供一种芯片封装结构，用以解决现有技术中芯片封装结构散热的问题。
第一方面，提供了一种芯片封装结构，该芯片封装结构包括：基板，以及芯片，还包括：固定在所述基板上的散热环以及覆盖在所述散热环上的平面热管散热器，且所述基板、散热环及所述平面热管散热器围成容纳所述芯片的空间，所述芯片位于所述空间内且与所述基板固定连接，所述平面热管散热器朝向所述芯片的一面设置有第一金属薄膜层，且所述芯片通过烧结金属层与所述第一金属薄膜层热耦合连接。
在上述实施例中，采用平面热管散热器对芯片进行散热，并且为了强芯片到平面热管散热器间的散热能力，采用在平面热管散热器的一面设置第一金属薄膜层，并将第一金属薄膜层通过烧结金属层与芯片连接，该烧结金属层具有良好的热传递效果，可以将热量快速的传递到平面热管散热器上，从而可以有效的改善芯片的散热效果。
在一个具体的实施方案中，所述芯片朝向所述平面热管散热器的一面设置有第二金属薄膜层，所述烧结金属层与所述第二金属薄膜层热耦合。通过在芯片上设置第二金属薄膜层进一步的提高芯片的散热效果。
在一个具体的实施方案中，所述烧结金属层包括多个金属颗粒以及包裹所述多个金属颗粒的填充层。该金属颗粒可以为银颗粒、铝颗粒、铜颗粒、镁颗粒或者金颗粒等。
在一个具体的实施方案中，所述金属颗粒与所述第一金属薄膜层及第二金属薄膜层烧结形成原子级连续相结构。进一步的提高散热的效果。
在一个具体的实施方案中，所述填充层为空气层或胶层。通过不同的材质形成填充层。
在一个具体的实施方案中，所述第一金属薄膜层通过溅射或电镀的方式设置在所述平面热管散热器；所述第二金属薄膜层通过溅射或电镀的方式设置在所述芯片。采用不同的工艺形成第一金属薄膜层及第二金属薄膜层。
在一个具体的实施方案中，所述芯片的个数为m个，且其中n个芯片与所述平面热管散热器之间设置有热电制冷片，且所述热电制冷片的一面与所述平面热管散热器连接，另一面通过所述烧结金属层与所述芯片热耦合连接；其中，m、n均为整数，且m≥1，m≥n。通过热电制冷片进一步的提高散热的效果。
在一个具体的实施方案中，所述热电制冷片为功率可调的热电制冷片。从而可以根据不同的散热要求调整热电制冷片的功率。
在一个具体的实施方案中，所述热电制冷片朝向所述芯片的一面设置有第三金属薄膜层。进一步的提高散热效果。
在一个具体的实施方案中，所述第三金属薄膜层通过溅射或电镀的方式设置在所述热电制冷片。采用不同的工艺形成第三金属薄膜层。
在一个具体的实施方案中，所述散热环分别与所述基板及所述平面热管散热器粘接连接。散热环与平面热管散热器采用分体的结构。
在一个具体的实施方案中，所述散热环与所述平面热管散热器为一体结构，且所述散热环与所述基板粘接连接。散热环与平面散热器采用一体的结构。
附图说明
图1为现有技术中的芯片封装结构的结构示意图；
图2为本申请提供的芯片封装结构的结构示意图；
图3为本申请提供的另一种芯片封装结构的结构示意图；
图4为本申请提供的芯片与平面热管散热器的结构示意图；
图5为本申请提供的另一种芯片封装结构的结构示意图；
图6为本申请提供的另一种芯片封装结构的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
本申请提供了一种芯片封装结构，该芯片封装结构包括一个基板，以及芯片，该芯片包括但不限于引线键合芯片和倒装芯片。
该芯片的个数可以为一个或者多个，并且在采用多个芯片时，芯片可以为不同类 型的芯片，如图2所示的实施例中，该基板101通过焊球100可以粘接在其他的基板或者器件上。芯片的个数为两个，且两个芯片分别为逻辑芯片104和内存芯片105。该芯片还可以为其他类型的芯片，上述逻辑芯片104和内存芯片105仅仅作为一个示例。在芯片设置时，芯片固定在基板101上，并且基板101上还固定了散热环103，该散热环103为一个框形的结构，并且散热环103上还覆盖了一个平面热管散热器107，从而使得基板101、散热环103平面热管散热器107围成容纳芯片的空间，将芯片包裹起来。如图2中所示，逻辑芯片104及内存芯片105固定在基板101上。在具体连接时，芯片可以通过焊球109与基板101固定进行连接。如图2中所示，逻辑芯片104和内存芯片105分别通过焊球109与基板101焊接连接。从而使得逻辑芯片104和内存芯片105可以稳定的固定在基板101上。
为了提高芯片的散热效果，本实施例提供的芯片封装结构采用不同的方式对芯片进行散热，下面以具体的实施例进行说明。
实施例1
继续参考图2及图3，如图1所示，该芯片封装结构包括一个基板101，以及两个芯片，分别为逻辑芯片104和内存芯片105。芯片固定在基板101上，并且基板101上还固定了散热环103，该散热环103为一个框形的结构，并且散热环103上还覆盖了一个平面热管散热器107，从而使得基板101、散热环103平面热管散热器107围成容纳芯片的空间，将芯片包裹起来。如图2中所示，逻辑芯片104及内存芯片105固定在基板101上。在具体连接时，芯片可以通过焊球109与基板101固定进行连接。如图2中所示，逻辑芯片104和内存芯片105分别通过焊球109与基板101焊接连接。从而使得逻辑芯片104和内存芯片105可以稳定的固定在基板101上。
在散热环103及平面热管散热器107具体连接时，可以通过不同的方式，既可以散热环103与平面热管散热器107采用分体设置也可以采用一体设置。如图2所示，在图2所示的结构中，散热环103和平面热管散热器107采用分体设计的方式，此时，散热环103分别与基板101及平面热管散热器107粘接连接。即散热环103的一面通过粘接胶102与基板101粘接连接，另一面通过粘接胶102与平面热管散热器107连接。如图3所示，在图3所示的结构中，散热环103与平面热管散热器107采用一体结构的方式，此时，散热环103与平面热管散热器107通过模具一体制备形成一个罩体的结构，并且在芯片固定在基板101上后，该罩体盖合在基板101上，将芯片包裹起来。在采用此种结构时，散热环103与基板101之间通过粘接的方式进行连接，如散热环103与基板101之间通过粘接胶102粘接连接。
在上述实施例中，通过散热环103以及平面热管散热器107对芯片封装结构进行散热，如图2所示，该平面热管散热器107作为散热盖。平面热管散热器107能增强热量在散热盖上的均匀化，以强化热量从散热盖向外部环境(包括外置散热器)的传递，进而有效降低芯片的结温。在具体制作时，该散热盖内形成一个中空的腔体108。在散热环103与平面热管散热器107连接时，该散热环103与散热盖粘接连接，在平面热管散热器107与散热环103形成一体结构时，该散热环103与散热盖形成一体结构。
在芯片与平面热管散热器107连接时，为了提高散热的效果，本实施例提供的平面热管散热器107朝向芯片的一面设置了第一金属薄膜层110，该第一金属薄膜层110 为采用溅射或电镀的方式形成在芯片的金属薄膜层，但应当理解的是，形成第一金属薄膜层110的方式包括但不仅限定于溅射和电镀的方式，还可以是其他的制备方式。芯片通过烧结金属层106与第一金属薄膜层110热耦合连接，具体的，如图2所示，逻辑芯片104和内存芯片105朝向平面热管散热器107的一面分别通过烧结金属层106与第一金属薄膜层110连接。其中，如图4所示，该烧结金属层106包括多个金属颗粒113以及包裹多个金属颗粒113的填充层112。该填充层112为空气层或胶层，或者其他材料形成的填充层112。并且在第一金属薄膜层110与金属颗粒113形成原子级连续相结构，从而降低芯片与平面热管散热器107之间的连接结构的热阻，以提升散热的效果。其中，该金属颗粒113可以为银颗粒、铝颗粒、铜颗粒、镁颗粒或者金颗粒等金属颗粒。
为了更进一步的提升散热效果，在芯片朝向平面热管散热器107的一面设置了第二金属薄膜层111，并且烧结金属层106与第二金属薄膜层111热耦合，以更进一步的降低芯片与平面热管散热器107之间连接结构的热阻，提升散热效果。在具体设置时，该第二金属薄膜层111采用电镀或者溅射的方式形成在芯片，但应当理解的是，形成第二金属薄膜层111的方式包括但不仅限定于溅射和电镀的方式，还可以是其他的制备方式；在图2所示的结构中，内存芯片105及逻辑芯片104朝向平面热管散热器107的一面采用电镀或者溅射的方式形成一层或多层的第二金属薄膜层111。在第二金属薄膜层111与烧结金属层106连接时，第二金属薄膜层111与烧结金属层106中的金属颗粒113形成原子级连续相结构。此时，在芯片与平面热管散热器107之间形成的散热通道包括：第一金属薄膜层110、烧结金属层106、第二金属薄膜层111，并且在设置时，烧结金属层106与第一金属薄膜层110及第二金属薄膜层111之间均烧结形成原子级连续相结构，从而可以有效的降低第一金属薄膜层110、烧结金属层106及第二金属薄膜层111的热阻，使得芯片上的热量可以快速的传递到平面热管散热器107上。
通过上述描述可以看出，本申请提供了一种可提高散热效果的芯片封装结构，该芯片封装结构能提高系统级多芯片合封情况下封装结构的散热能力，能够实现对芯片温度的有效控制。本申请中提供的芯片封装结构可将不同芯片产生的热量通过烧结金属层106快速的传递至平面热管散热器107，与现有技术中的芯片封装结构中采用的热界面材料层进行导热相比，热界面材料的热导率为4W/mK的量级，而本申请中的烧结金属层106的热导率达到了100W/mK的量级，因此，采用烧结金属层106能够令芯片到平面热管散热器107的热阻减小25倍左右，能够有效降低芯片结温，使得热量尽快的传递到平面热管散热器107，平面热管散热器107能够快速的将热量均匀化，这就强化了热量从平面热管散热器107向环境传递的能力，进而有效减低芯片的结温，对大功率的芯片效果将尤为显著。
实施例2
如图4及图5所示，本实施例提供的芯片封装结构的基板101、芯片、平面热管散热器107、散热环103均可以采用上述实施例1中的结构。
如图4所示，散热环103和平面热管散热器107采用分体设计的方式，此时，散热环103分别与基板101及平面热管散热器107粘接连接。即散热环103的一面通过粘接胶102与基板101粘接连接，另一面通过粘接胶102与平面热管散热器107连接。 如图5所示，在图5所示的结构中，散热环103与平面热管散热器107采用一体结构的方式，此时，散热环103与平面热管散热器107通过模具一体制备形成一个罩体的结构，并且在芯片固定在基板101上后，该罩体盖合在基板101上，将芯片包裹起来。在采用此种结构时，散热环103与基板101之间通过粘接的方式进行连接，如图5所示，散热环103与基板101之间通过粘接胶102粘接连接。
在本申请实施例提供的芯片封装结构中，为了更进一步的提高芯片封装结构的散热效果，增加了热电制冷片114，并且在芯片的个数为多个时，工作时产生热量比较多的芯片对应设置热电制冷片114，也可以所有的芯片均对应设置热电制冷片114。如芯片的个数为m个，且其中n个芯片与平面热管散热器107之间设置有热电制冷片114，且热电制冷片114的一面与平面热管散热器107连接，另一面通过烧结金属层106与芯片热耦合连接；其中，m、n均为整数，且m≥1，m≥n。在图3及图4所示的结构中，芯片的个数为两个，分别为逻辑芯片104和内存芯片105，其中，内存芯片105对应一个热电制冷片114，此时，m＝2，n＝1。在具体设置时，热电制冷片114与平面热管散热器107粘接连接，并且热电制冷片114朝向所述芯片的一面设置有第三金属薄膜层。在图3所示的结构中，即在内存芯片105上通过溅射或者电镀的方式形成一层或多层的第三金属薄膜层，但应当理解的是，形成第三金属薄膜层的方式包括但不仅限定于溅射和电镀的方式，还可以是其他的制备方式。此时，内存芯片105到平面热管散热器107之间的散热通道为：第二金属薄膜层111、烧结金属层106、第三金属薄膜层、热电制冷片114。并且在具体设置时，第二金属薄膜层111、第三金属薄膜层均与烧结金属层106中的金属颗粒113采用原子级连续相结构，从而可以有效的降低通道的热阻，此外，通过设置的热电制冷片114可以有效的控制芯片的温度，在具体设置时，热电制冷片114为功率可调的热电制冷片114。从而可以根据不同的散热要求调整热电制冷片114的功率。
在图4及图5所示的结构中，仅仅示出了两个芯片的结构，应当理解的是，在采用多个芯片时，可以根据实际的需要设置不同个数的热电制冷片114。
通过上述描述可以看出，在需要控制芯片温度时，通过设置的热电制冷片114来调整芯片的温度，更进一步的提高散热的效果，保证芯片能够稳定的工作。
在上述实施例1及实施例2中仅仅示出了具体的芯片封装结构的散热结构，在本申请实施例的芯片封装结构中，无论采用多少个芯片，其散热方式均可采用实施例1及实施例2中的散热结构，通过烧结金属层106与金属薄膜层之间形成原子连续相结构可以有效的降低芯片与平面热管散热器107之间的热阻，有效的提高芯片封装结构的散热效果。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (13)

  1. 一种芯片封装结构，其特征在于，包括：基板，以及芯片，还包括：固定在所述基板上的散热环以及覆盖在所述散热环上的平面热管散热器，且所述基板、散热环及所述平面热管散热器围成容纳所述芯片的空间，所述芯片位于所述空间内且与所述基板固定连接，所述平面热管散热器朝向所述芯片的一面设置有第一金属薄膜层，且所述芯片通过烧结金属层与所述第一金属薄膜层热耦合连接。
  2. 如权利要求1所述的芯片封装结构，其特征在于，所述芯片朝向所述平面热管散热器的一面设置有第二金属薄膜层，所述烧结金属层与所述第二金属薄膜层热耦合。
  3. 如权利要求2所述的芯片封装结构，其特征在于，所述烧结金属层包括多个金属颗粒以及包裹所述多个金属颗粒的填充层。
  4. 如权利要求3所述的芯片封装结构，其特征在于，所述金属颗粒为银颗粒、铝颗粒、铜颗粒、镁颗粒或者金颗粒。
  5. 如权利要求3所述的芯片封装结构，其特征在于，所述金属颗粒与所述第一金属薄膜层及第二金属薄膜层烧结形成原子级连续相结构。
  6. 如权利要求3～5任一项所述的芯片封装结构，其特征在于，所述填充层为空气层或胶层。
  7. 如权利要求2～6任一项所述的芯片封装结构，其特征在于，所述第一金属薄膜层通过溅射或电镀的方式设置在所述平面热管散热器；所述第二金属薄膜层通过溅射或电镀的方式设置在所述芯片。
  8. 如权利要求1～7任一项所述的芯片封装结构，其特征在于，所述芯片的个数为m个，且其中n个芯片与所述平面热管散热器之间设置有热电制冷片，且所述热电制冷片的一面与所述平面热管散热器连接，另一面通过所述烧结金属层与所述芯片热耦合连接；其中，m、n均为整数，且m≥1，m≥n。
  9. 如权利要求8所述的芯片封装结构，其特征在于，所述热电制冷片为功率可调的热电制冷片。
  10. 如权利要求8所述的芯片封装结构，其特征在于，所述热电制冷片朝向所述芯片的一面设置有第三金属薄膜层。
  11. 如权利要求9所述的芯片封装结构，其特征在于，所述第三金属薄膜层通过溅射或电镀的方式设置在所述热电制冷片。
  12. 如权利要求1～11任一项所述的芯片封装结构，其特征在于，所述散热环分别与所述基板及所述平面热管散热器粘接连接。
  13. 如权利要求1～11任一项所述的芯片封装结构，其特征在于，所述散热环与所述平面热管散热器为一体结构，且所述散热环与所述基板粘接连接。
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