CN109103154A - 一种芯片封装结构 - Google Patents

一种芯片封装结构 Download PDF

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Publication number
CN109103154A
CN109103154A CN201710479072.2A CN201710479072A CN109103154A CN 109103154 A CN109103154 A CN 109103154A CN 201710479072 A CN201710479072 A CN 201710479072A CN 109103154 A CN109103154 A CN 109103154A
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CN
China
Prior art keywords
chip
film layer
pipe radiator
metal film
heat pipe
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Pending
Application number
CN201710479072.2A
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English (en)
Inventor
符会利
林志荣
张相雄
蔡树杰
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to CN201710479072.2A priority Critical patent/CN109103154A/zh
Priority to PCT/CN2018/092246 priority patent/WO2018233672A1/zh
Publication of CN109103154A publication Critical patent/CN109103154A/zh
Priority to US16/723,269 priority patent/US20200135615A1/en
Pending legal-status Critical Current

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Abstract

本申请公开了提供了一种芯片封装结构,该芯片封装结构包括:基板,以及芯片,还包括:固定在基板上的散热环以及覆盖在散热环上的平面热管散热器,且基板、散热环及平面热管散热器围成容纳芯片的空间,平面热管散热器朝向芯片的一面设置有第一金属薄膜层,芯片通过烧结金属层与第一金属薄膜层热耦合连接。在上述实施例中,采用平面热管散热器对芯片进行散热,并且为了强芯片到平面热管散热器间的散热能力,采用在平面热管散热器的一面设置第一金属薄膜层,并将第一金属薄膜层通过烧结金属层与芯片连接,该烧结金属层具有良好的热传递效果,可以将热量快速的传递到平面热管散热器上,从而可以有效的改善芯片的散热效果。

Description

一种芯片封装结构
技术领域
本申请涉及信息技术领域,尤其涉及一种芯片封装结构。
背景技术
随着芯片工艺节点的不断下降,芯片的集成度不断上升。在系统级芯片封装中多个异质芯片(逻辑芯片、内存等)及被动元器件被封装集成在一个小尺寸的系统中,封装的整体功耗以及单个芯片的功耗都在不断增加。为了保证芯片能够长期,稳定的工作,需要将管芯的温度控制在一定范围内。这是目前系统级芯片封装所面临的一个重要难题。
目前,将芯片热量更快速传递到封装外部的核心思路是通过引入导热率更高的材料或者优化封装结构,减小热量传递路径上的热阻。图1所示,图1示出了现有技术中的一种散热方式,其中,芯片2通过焊球4固定在基板1上面,通过热界面材料层3与具有超高热导率的平面热管5连接。通过平面热管5来替代传统的散热盖(铜)来强化热量从芯片2向封装表面6的传递。
但是,上述传统热界面材料层3热阻很高,严重限制了使用平面热管所能带来的收益,成为芯片散热通道上的主要瓶颈。此外,传统封装结构仅采用被动散热的方案,这在一定程度上限制了对芯片温度的控制。
发明内容
本申请提供一种芯片封装结构,用以解决现有技术中芯片封装结构散热的问题。
第一方面,提供了一种芯片封装结构,该芯片封装结构包括:基板,以及芯片,还包括:固定在所述基板上的散热环以及覆盖在所述散热环上的平面热管散热器,且所述基板、散热环及所述平面热管散热器围成容纳所述芯片的空间,所述芯片位于所述空间内且与所述基板固定连接,所述平面热管散热器朝向所述芯片的一面设置有第一金属薄膜层,且所述芯片通过烧结金属层与所述第一金属薄膜层热耦合连接。
在上述实施例中,采用平面热管散热器对芯片进行散热,并且为了强芯片到平面热管散热器间的散热能力,采用在平面热管散热器的一面设置第一金属薄膜层,并将第一金属薄膜层通过烧结金属层与芯片连接,该烧结金属层具有良好的热传递效果,可以将热量快速的传递到平面热管散热器上,从而可以有效的改善芯片的散热效果。
在一个具体的实施方案中,所述芯片朝向所述平面热管散热器的一面设置有第二金属薄膜层,所述烧结金属层与所述第二金属薄膜层热耦合。通过在芯片上设置第二金属薄膜层进一步的提高芯片的散热效果。
在一个具体的实施方案中,所述烧结金属层包括多个金属颗粒以及包裹所述多个金属颗粒的填充层。该金属颗粒可以为银颗粒、铝颗粒、铜颗粒、镁颗粒或者金颗粒等。
在一个具体的实施方案中,所述金属颗粒与所述第一金属薄膜层及第二金属薄膜层烧结形成原子级连续相结构。进一步的提高散热的效果。
在一个具体的实施方案中,所述填充层为空气层或胶层。通过不同的材质形成填充层。
在一个具体的实施方案中,所述第一金属薄膜层通过溅射或电镀的方式设置在所述平面热管散热器;所述第二金属薄膜层通过溅射或电镀的方式设置在所述芯片。采用不同的工艺形成第一金属薄膜层及第二金属薄膜层。
在一个具体的实施方案中,所述芯片的个数为m个,且其中n个芯片与所述平面热管散热器之间设置有热电制冷片,且所述热电制冷片的一面与所述平面热管散热器连接,另一面通过所述烧结金属层与所述芯片热耦合连接;其中,m、n均为整数,且m≥1,m≥n。通过热电制冷片进一步的提高散热的效果。
在一个具体的实施方案中,所述热电制冷片为功率可调的热电制冷片。从而可以根据不同的散热要求调整热电制冷片的功率。
在一个具体的实施方案中,所述热电制冷片朝向所述芯片的一面设置有第三金属薄膜层。进一步的提高散热效果。
在一个具体的实施方案中,所述第三金属薄膜层通过溅射或电镀的方式设置在所述热电制冷片。采用不同的工艺形成第三金属薄膜层。
在一个具体的实施方案中,所述散热环分别与所述基板及所述平面热管散热器粘接连接。散热环与平面热管散热器采用分体的结构。
在一个具体的实施方案中,所述散热环与所述平面热管散热器为一体结构,且所述散热环与所述基板粘接连接。散热环与平面散热器采用一体的结构。
附图说明
图1为现有技术中的芯片封装结构的结构示意图;
图2为本申请提供的芯片封装结构的结构示意图;
图3为本申请提供的另一种芯片封装结构的结构示意图;
图4为本申请提供的芯片与平面热管散热器的结构示意图;
图5为本申请提供的另一种芯片封装结构的结构示意图;
图6为本申请提供的另一种芯片封装结构的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚,下面将结合附图对本申请作进一步地详细描述。
本申请提供了一种芯片封装结构,该芯片封装结构包括一个基板,以及芯片,该芯片包括但不限于引线键合芯片和倒装芯片。
该芯片的个数可以为一个或者多个,并且在采用多个芯片时,芯片可以为不同类型的芯片,如图2所示的实施例中,该基板101通过焊球100可以粘接在其他的基板或者器件上。芯片的个数为两个,且两个芯片分别为逻辑芯片104和内存芯片105。该芯片还可以为其他类型的芯片,上述逻辑芯片104和内存芯片105仅仅作为一个示例。在芯片设置时,芯片固定在基板101上,并且基板101上还固定了散热环103,该散热环103为一个框形的结构,并且散热环103上还覆盖了一个平面热管散热器107,从而使得基板101、散热环103平面热管散热器107围成容纳芯片的空间,将芯片包裹起来。如图2中所示,逻辑芯片104及内存芯片105固定在基板101上。在具体连接时,芯片可以通过焊球109与基板101固定进行连接。如图2中所示,逻辑芯片104和内存芯片105分别通过焊球109与基板101焊接连接。从而使得逻辑芯片104和内存芯片105可以稳定的固定在基板101上。
为了提高芯片的散热效果,本实施例提供的芯片封装结构采用不同的方式对芯片进行散热,下面以具体的实施例进行说明。
实施例1
继续参考图2及图3,如图1所示,该芯片封装结构包括一个基板101,以及两个芯片,分别为逻辑芯片104和内存芯片105。芯片固定在基板101上,并且基板101上还固定了散热环103,该散热环103为一个框形的结构,并且散热环103上还覆盖了一个平面热管散热器107,从而使得基板101、散热环103平面热管散热器107围成容纳芯片的空间,将芯片包裹起来。如图2中所示,逻辑芯片104及内存芯片105固定在基板101上。在具体连接时,芯片可以通过焊球109与基板101固定进行连接。如图2中所示,逻辑芯片104和内存芯片105分别通过焊球109与基板101焊接连接。从而使得逻辑芯片104和内存芯片105可以稳定的固定在基板101上。
在散热环103及平面热管散热器107具体连接时,可以通过不同的方式,既可以散热环103与平面热管散热器107采用分体设置也可以采用一体设置。如图2所示,在图2所示的结构中,散热环103和平面热管散热器107采用分体设计的方式,此时,散热环103分别与基板101及平面热管散热器107粘接连接。即散热环103的一面通过粘接胶102与基板101粘接连接,另一面通过粘接胶102与平面热管散热器107连接。如图3所示,在图3所示的结构中,散热环103与平面热管散热器107采用一体结构的方式,此时,散热环103与平面热管散热器107通过模具一体制备形成一个罩体的结构,并且在芯片固定在基板101上后,该罩体盖合在基板101上,将芯片包裹起来。在采用此种结构时,散热环103与基板101之间通过粘接的方式进行连接,如散热环103与基板101之间通过粘接胶102粘接连接。
在上述实施例中,通过散热环103以及平面热管散热器107对芯片封装结构进行散热,如图2所示,该平面热管散热器107作为散热盖。平面热管散热器107能增强热量在散热盖上的均匀化,以强化热量从散热盖向外部环境(包括外置散热器)的传递,进而有效降低芯片的结温。在具体制作时,该散热盖内形成一个中空的腔体108。在散热环103与平面热管散热器107连接时,该散热环103与散热盖粘接连接,在平面热管散热器107与散热环103形成一体结构时,该散热环103与散热盖形成一体结构。
在芯片与平面热管散热器107连接时,为了提高散热的效果,本实施例提供的平面热管散热器107朝向芯片的一面设置了第一金属薄膜层110,该第一金属薄膜层110为采用溅射或电镀的方式形成在芯片的金属薄膜层,但应当理解的是,形成第一金属薄膜层110的方式包括但不仅限定于溅射和电镀的方式,还可以是其他的制备方式。芯片通过烧结金属层106与第一金属薄膜层110热耦合连接,具体的,如图2所示,逻辑芯片104和内存芯片105朝向平面热管散热器107的一面分别通过烧结金属层106与第一金属薄膜层110连接。其中,如图4所示,该烧结金属层106包括多个金属颗粒113以及包裹多个金属颗粒113的填充层112。该填充层112为空气层或胶层,或者其他材料形成的填充层112。并且在第一金属薄膜层110与金属颗粒113形成原子级连续相结构,从而降低芯片与平面热管散热器107之间的连接结构的热阻,以提升散热的效果。其中,该金属颗粒113可以为银颗粒、铝颗粒、铜颗粒、镁颗粒或者金颗粒等金属颗粒。
为了更进一步的提升散热效果,在芯片朝向平面热管散热器107的一面设置了第二金属薄膜层111,并且烧结金属层106与第二金属薄膜层111热耦合,以更进一步的降低芯片与平面热管散热器107之间连接结构的热阻,提升散热效果。在具体设置时,该第二金属薄膜层111采用电镀或者溅射的方式形成在芯片,但应当理解的是,形成第二金属薄膜层111的方式包括但不仅限定于溅射和电镀的方式,还可以是其他的制备方式;在图2所示的结构中,内存芯片105及逻辑芯片104朝向平面热管散热器107的一面采用电镀或者溅射的方式形成一层或多层的第二金属薄膜层111。在第二金属薄膜层111与烧结金属层106连接时,第二金属薄膜层111与烧结金属层106中的金属颗粒113形成原子级连续相结构。此时,在芯片与平面热管散热器107之间形成的散热通道包括:第一金属薄膜层110、烧结金属层106、第二金属薄膜层111,并且在设置时,烧结金属层106与第一金属薄膜层110及第二金属薄膜层111之间均烧结形成原子级连续相结构,从而可以有效的降低第一金属薄膜层110、烧结金属层106及第二金属薄膜层111的热阻,使得芯片上的热量可以快速的传递到平面热管散热器107上。
通过上述描述可以看出,本申请提供了一种可提高散热效果的芯片封装结构,该芯片封装结构能提高系统级多芯片合封情况下封装结构的散热能力,能够实现对芯片温度的有效控制。本申请中提供的芯片封装结构可将不同芯片产生的热量通过烧结金属层106快速的传递至平面热管散热器107,与现有技术中的芯片封装结构中采用的热界面材料层进行导热相比,热界面材料的热导率为4W/mK的量级,而本申请中的烧结金属层106的热导率达到了100W/mK的量级,因此,采用烧结金属层106能够令芯片到平面热管散热器107的热阻减小25倍左右,能够有效降低芯片结温,使得热量尽快的传递到平面热管散热器107,平面热管散热器107能够快速的将热量均匀化,这就强化了热量从平面热管散热器107向环境传递的能力,进而有效减低芯片的结温,对大功率的芯片效果将尤为显著。
实施例2
如图4及图5所示,本实施例提供的芯片封装结构的基板101、芯片、平面热管散热器107、散热环103均可以采用上述实施例1中的结构。
如图4所示,散热环103和平面热管散热器107采用分体设计的方式,此时,散热环103分别与基板101及平面热管散热器107粘接连接。即散热环103的一面通过粘接胶102与基板101粘接连接,另一面通过粘接胶102与平面热管散热器107连接。如图5所示,在图5所示的结构中,散热环103与平面热管散热器107采用一体结构的方式,此时,散热环103与平面热管散热器107通过模具一体制备形成一个罩体的结构,并且在芯片固定在基板101上后,该罩体盖合在基板101上,将芯片包裹起来。在采用此种结构时,散热环103与基板101之间通过粘接的方式进行连接,如图5所示,散热环103与基板101之间通过粘接胶102粘接连接。
在本申请实施例提供的芯片封装结构中,为了更进一步的提高芯片封装结构的散热效果,增加了热电制冷片114,并且在芯片的个数为多个时,工作时产生热量比较多的芯片对应设置热电制冷片114,也可以所有的芯片均对应设置热电制冷片114。如芯片的个数为m个,且其中n个芯片与平面热管散热器107之间设置有热电制冷片114,且热电制冷片114的一面与平面热管散热器107连接,另一面通过烧结金属层106与芯片热耦合连接;其中,m、n均为整数,且m≥1,m≥n。在图3及图4所示的结构中,芯片的个数为两个,分别为逻辑芯片104和内存芯片105,其中,内存芯片105对应一个热电制冷片114,此时,m=2,n=1。在具体设置时,热电制冷片114与平面热管散热器107粘接连接,并且热电制冷片114朝向所述芯片的一面设置有第三金属薄膜层。在图3所示的结构中,即在内存芯片105上通过溅射或者电镀的方式形成一层或多层的第三金属薄膜层,但应当理解的是,形成第三金属薄膜层的方式包括但不仅限定于溅射和电镀的方式,还可以是其他的制备方式。此时,内存芯片105到平面热管散热器107之间的散热通道为:第二金属薄膜层111、烧结金属层106、第三金属薄膜层、热电制冷片114。并且在具体设置时,第二金属薄膜层111、第三金属薄膜层均与烧结金属层106中的金属颗粒113采用原子级连续相结构,从而可以有效的降低通道的热阻,此外,通过设置的热电制冷片114可以有效的控制芯片的温度,在具体设置时,热电制冷片114为功率可调的热电制冷片114。从而可以根据不同的散热要求调整热电制冷片114的功率。
在图4及图5所示的结构中,仅仅示出了两个芯片的结构,应当理解的是,在采用多个芯片时,可以根据实际的需要设置不同个数的热电制冷片114。
通过上述描述可以看出,在需要控制芯片温度时,通过设置的热电制冷片114来调整芯片的温度,更进一步的提高散热的效果,保证芯片能够稳定的工作。
在上述实施例1及实施例2中仅仅示出了具体的芯片封装结构的散热结构,在本申请实施例的芯片封装结构中,无论采用多少个芯片,其散热方式均可采用实施例1及实施例2中的散热结构,通过烧结金属层106与金属薄膜层之间形成原子连续相结构可以有效的降低芯片与平面热管散热器107之间的热阻,有效的提高芯片封装结构的散热效果。
显然,本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样,倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内,则本申请也意图包含这些改动和变型在内。

Claims (13)

1.一种芯片封装结构,其特征在于,包括:基板,以及芯片,还包括:固定在所述基板上的散热环以及覆盖在所述散热环上的平面热管散热器,且所述基板、散热环及所述平面热管散热器围成容纳所述芯片的空间,所述芯片位于所述空间内且与所述基板固定连接,所述平面热管散热器朝向所述芯片的一面设置有第一金属薄膜层,且所述芯片通过烧结金属层与所述第一金属薄膜层热耦合连接。
2.如权利要求1所述的芯片封装结构,其特征在于,所述芯片朝向所述平面热管散热器的一面设置有第二金属薄膜层,所述烧结金属层与所述第二金属薄膜层热耦合。
3.如权利要求2所述的芯片封装结构,其特征在于,所述烧结金属层包括多个金属颗粒以及包裹所述多个金属颗粒的填充层。
4.如权利要求3所述的芯片封装结构,其特征在于,所述金属颗粒为银颗粒、铝颗粒、铜颗粒、镁颗粒或者金颗粒。
5.如权利要求3所述的芯片封装结构,其特征在于,所述金属颗粒与所述第一金属薄膜层及第二金属薄膜层烧结形成原子级连续相结构。
6.如权利要求3~5任一项所述的芯片封装结构,其特征在于,所述填充层为空气层或胶层。
7.如权利要求2~6任一项所述的芯片封装结构,其特征在于,所述第一金属薄膜层通过溅射或电镀的方式设置在所述平面热管散热器;所述第二金属薄膜层通过溅射或电镀的方式设置在所述芯片。
8.如权利要求1~7任一项所述的芯片封装结构,其特征在于,所述芯片的个数为m个,且其中n个芯片与所述平面热管散热器之间设置有热电制冷片,且所述热电制冷片的一面与所述平面热管散热器连接,另一面通过所述烧结金属层与所述芯片热耦合连接;其中,m、n均为整数,且m≥1,m≥n。
9.如权利要求8所述的芯片封装结构,其特征在于,所述热电制冷片为功率可调的热电制冷片。
10.如权利要求8所述的芯片封装结构,其特征在于,所述热电制冷片朝向所述芯片的一面设置有第三金属薄膜层。
11.如权利要求9所述的芯片封装结构,其特征在于,所述第三金属薄膜层通过溅射或电镀的方式设置在所述热电制冷片。
12.如权利要求1~11任一项所述的芯片封装结构,其特征在于,所述散热环分别与所述基板及所述平面热管散热器粘接连接。
13.如权利要求1~11任一项所述的芯片封装结构,其特征在于,所述散热环与所述平面热管散热器为一体结构,且所述散热环与所述基板粘接连接。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112018049A (zh) * 2019-05-31 2020-12-01 华为技术有限公司 一种芯片封装结构及一种电子设备
CN112382615A (zh) * 2020-11-05 2021-02-19 海光信息技术股份有限公司 功率器件封装结构、封装方法及封装系统

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114787990A (zh) * 2019-12-16 2022-07-22 华为技术有限公司 芯片封装及其制作方法
CN111627897A (zh) * 2020-05-28 2020-09-04 上海先方半导体有限公司 一种立体封装结构及其制备方法
CN112071814B (zh) * 2020-09-09 2022-09-27 深圳市同和光电科技有限公司 一种芯片封装系统及其芯片封装工艺
US11784061B2 (en) 2021-02-25 2023-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package structure and method for forming the same
CN114141730B (zh) * 2021-11-15 2022-09-09 绵阳惠科光电科技有限公司 覆晶薄膜、显示装置及覆晶薄膜制作方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040183188A1 (en) * 2002-12-25 2004-09-23 Denso Corporation Semiconductor module and semiconductor device
CN101159251A (zh) * 2006-09-26 2008-04-09 英特尔公司 用于微电子冷却组件的烧结金属热界面材料
CN101304017A (zh) * 2007-05-12 2008-11-12 塞米克朗电子有限及两合公司 烧结的功率半导体基片及其制造方法
CN102779808A (zh) * 2011-05-09 2012-11-14 英飞凌科技股份有限公司 集成电路封装和封装方法
CN102800636A (zh) * 2012-08-28 2012-11-28 中国科学院微电子研究所 电子元件封装体及其制造方法
CN102867793A (zh) * 2012-08-14 2013-01-09 日月光半导体制造股份有限公司 热界面材料及半导体封装结构
WO2016021561A1 (ja) * 2014-08-08 2016-02-11 日本発條株式会社 複合基板及びパワーモジュール

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0341950B1 (en) * 1988-05-09 1994-09-14 Nec Corporation Flat cooling structure of integrated circuit
JP4451752B2 (ja) * 2004-09-29 2010-04-14 株式会社ザナヴィ・インフォマティクス 放熱部材および半導体部品
DE102010044709B4 (de) * 2010-09-08 2015-07-02 Vincotech Holdings S.à.r.l. Leistungshalbleitermodul mit Metallsinterverbindungen sowie Herstellungsverfahren
JP6508193B2 (ja) * 2014-03-11 2019-05-08 富士電機株式会社 半導体装置の製造方法および半導体装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040183188A1 (en) * 2002-12-25 2004-09-23 Denso Corporation Semiconductor module and semiconductor device
CN101159251A (zh) * 2006-09-26 2008-04-09 英特尔公司 用于微电子冷却组件的烧结金属热界面材料
CN101304017A (zh) * 2007-05-12 2008-11-12 塞米克朗电子有限及两合公司 烧结的功率半导体基片及其制造方法
CN102779808A (zh) * 2011-05-09 2012-11-14 英飞凌科技股份有限公司 集成电路封装和封装方法
CN102867793A (zh) * 2012-08-14 2013-01-09 日月光半导体制造股份有限公司 热界面材料及半导体封装结构
CN102800636A (zh) * 2012-08-28 2012-11-28 中国科学院微电子研究所 电子元件封装体及其制造方法
WO2016021561A1 (ja) * 2014-08-08 2016-02-11 日本発條株式会社 複合基板及びパワーモジュール

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112018049A (zh) * 2019-05-31 2020-12-01 华为技术有限公司 一种芯片封装结构及一种电子设备
CN112382615A (zh) * 2020-11-05 2021-02-19 海光信息技术股份有限公司 功率器件封装结构、封装方法及封装系统
CN112382615B (zh) * 2020-11-05 2023-03-10 海光信息技术股份有限公司 功率器件封装结构、封装方法及封装系统

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WO2018233672A1 (zh) 2018-12-27

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Application publication date: 20181228