WO2018233280A1 - 阵列基板、其制作方法、显示面板及显示装置 - Google Patents

阵列基板、其制作方法、显示面板及显示装置 Download PDF

Info

Publication number
WO2018233280A1
WO2018233280A1 PCT/CN2018/072274 CN2018072274W WO2018233280A1 WO 2018233280 A1 WO2018233280 A1 WO 2018233280A1 CN 2018072274 W CN2018072274 W CN 2018072274W WO 2018233280 A1 WO2018233280 A1 WO 2018233280A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
layer
transistor
gate
pixel
Prior art date
Application number
PCT/CN2018/072274
Other languages
English (en)
French (fr)
Inventor
郭玉珍
董学
王海生
吴俊纬
曹学友
刘英明
丁小梁
郑智仁
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/310,052 priority Critical patent/US10802630B2/en
Publication of WO2018233280A1 publication Critical patent/WO2018233280A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0414—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using force sensing means to determine a position
    • G06F3/04144—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using force sensing means to determine a position using an array of force sensing means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/30—Piezoelectric or electrostrictive devices with mechanical input and electrical output, e.g. functioning as generators or sensors
    • H10N30/302—Sensors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04102—Flexible digitiser, i.e. constructional details for allowing the whole digitising part of a device to be flexed or rolled like a sheet of paper
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04105—Pressure sensors for measuring the pressure or force exerted on the touch surface without providing the touch position
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED

Definitions

  • the present disclosure relates to the field of display technologies, and more particularly to an array substrate, a method of fabricating the same, a display panel, and a display device.
  • a display with Three Dimension Touch (3D-Touch) function integrates a pressure sensor into the display, which introduces a third Z-axis dimension beyond the touch function, which can add some pressure to the touch function of the display.
  • the action of the control; wherein the pressure sensor integrated into the display can be realized by deformation capacitance or deformation by a pressure sensitive material, and is mainly composed of a simple three-layer structure, but a simple sandwich structure is difficult to achieve high-precision pressure detection. This makes the pressure detection resolution and sensitivity low.
  • Embodiments of the present disclosure provide an array substrate, a manufacturing method thereof, a display panel, and a display device.
  • the specific scheme is as follows:
  • An embodiment of the present disclosure provides an array substrate, including: a substrate substrate, a pressure sensitive structure, a plurality of double gate transistors, and a plurality of pixel transistors; wherein
  • the pressure sensitive structure includes a first electrode layer, a pressure sensitive layer and a second electrode layer which are sequentially disposed on the base substrate; the second electrode layer includes a plurality of ones and one corresponding to each of the double gate transistors Second electrodes;
  • the double gate transistor and the pixel transistor are disposed on the second electrode layer; and each of the second electrodes is electrically connected to a bottom gate electrode of the corresponding double gate transistor.
  • a source/drain electrode of the pixel transistor is disposed in the same layer as a source/drain electrode of the dual gate transistor, and an active layer and a transistor of the pixel transistor are disposed.
  • the active layer of the double gate transistor is disposed in the same layer, and the gate electrode of the pixel transistor is disposed in the same layer as the top gate electrode or the bottom gate electrode of the double gate transistor.
  • an orthographic projection of the second electrode on the substrate substrate and a source/drain electrode in the dual gate transistor on the substrate substrate do not overlap each other.
  • the pixel transistor is a top gate transistor, and a gate electrode of the pixel transistor is disposed in the same layer as a top gate electrode of the dual gate transistor.
  • the second electrode is disposed in the same layer as the electrically connected bottom gate electrode and has a unitary structure.
  • the pixel transistor is a bottom gate transistor, and a gate electrode of the pixel transistor is disposed in the same layer as a bottom gate electrode of the dual gate transistor.
  • the second electrode is electrically connected to the bottom gate electrode through a via hole.
  • the pixel transistor is a bottom gate transistor.
  • the first electrode layer is disposed in a whole layer.
  • the first electrode layer has a hollow structure in a region where an active layer of each of the pixel transistors is located.
  • the pressure sensitive layer is disposed in a whole layer.
  • the pressure sensitive layer has a hollow region, an orthographic projection of the hollow region on the substrate substrate and the second electrode on the substrate The orthographic projections on the substrate do not overlap each other.
  • the material of the pressure sensitive layer is a piezoelectric material
  • the first electrode layer is for loading a first constant potential; the second electrode is for applying a potential difference generated when the piezoelectric material is pressed to the bottom gate electrode; a top of the double gate transistor
  • the gate electrode and the source electrode are respectively used to load a second constant potential, and the drain electrode in the double gate transistor is used to output a first pressure sensing potential.
  • the material of the pressure sensitive layer is a piezoresistive material
  • the first electrode layer is for loading a first constant potential through a voltage dividing resistor; the second electrode is for applying a potential difference generated when the piezoresistive material is pressed to the bottom gate electrode;
  • the top gate electrode and the source electrode in the transistor are respectively used to load a third constant potential, and the drain electrode in the double gate transistor is used to output a second pressure sensing potential.
  • the embodiment of the present disclosure further provides a display panel comprising: the above array substrate provided by an embodiment of the present disclosure.
  • the display panel is a flexible organic electroluminescent display panel.
  • the embodiment of the present disclosure further provides a display device, including: the above display panel provided according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a method for fabricating the above array substrate according to an embodiment of the present disclosure, including:
  • first electrode layer Forming a first electrode layer, a pressure sensitive layer and a second electrode layer constituting the pressure sensitive structure on the base substrate; the second electrode layer comprising a plurality of second electrodes;
  • each of the double gate transistors is disposed in one-to-one correspondence with each of the second electrodes, and each of the second electrodes respectively corresponds to The bottom gate electrode of the dual gate transistor is electrically connected.
  • the second electrode layer is formed on the pressure sensitive layer, and specifically includes:
  • a bottom gate electrode and a second electrode layer of the dual gate transistor are separately formed on the pressure sensitive layer.
  • the plurality of pixel transistors and the plurality of double gate transistors are simultaneously formed on the second electrode layer, and specifically includes:
  • a source/drain electrode of the plurality of pixel transistors and a source/drain electrode of the plurality of double gate transistors are respectively formed on the interlayer insulating layer.
  • the gate transistor specifically includes:
  • a bottom gate electrode of the plurality of pixel transistors and a bottom gate electrode of the plurality of double gate transistors are respectively formed on the second electrode layer; a bottom gate electrode of the double gate transistor passes through a via Corresponding to the second electrode electrical connection;
  • a top gate electrode is formed on the source and drain electrodes in the double gate transistor.
  • FIG. 1 is a schematic structural view of a pressure sensor in the related art
  • FIGS. 2 to 4 are side views of an array substrate provided in an embodiment of the present disclosure.
  • 5a and 5b are top views of a dual gate transistor and a second electrode, respectively, provided in an embodiment of the present disclosure
  • FIG. 6 is a top plan view of a dual gate transistor, a pixel transistor, and a second electrode provided in an embodiment of the present disclosure
  • FIG. 7a and 7b are top plan views of a first electrode provided in an embodiment of the present disclosure.
  • FIG. 8 and FIG. 9 are respectively equivalent circuit diagrams of a pressure sensitive structure and a dual gate transistor provided in an embodiment of the present disclosure
  • 10 to 13 are flowcharts of a method for fabricating an array substrate provided in an embodiment of the present disclosure.
  • a pressure sensor combines a pressure sensitive structure of a sandwich structure with a double gate transistor.
  • a pressure sensitive structure 20 is disposed on a top gate electrode 11 of the double gate transistor 10 at a voltage.
  • the first structure 21, the pressure sensitive layer 22 and the second electrode 23 are included in the sensitive structure 20, and the second electrode 23 is shared with the top gate electrode 11 of the double gate transistor 10, and is subjected to pressure in the pressure sensitive structure 20 (black arrow indicates pressure)
  • a potential difference is generated and acts on the top gate electrode 11, so that the double gate transistor 10 generates a threshold drift, thereby outputting a pressure sensing potential, and sensing the potential through the pressure of the output.
  • the calculation process determines the magnitude of the pressure received; the pressure sensor of this structure can achieve high-precision pressure detection, which can greatly improve the accuracy and sensitivity of pressure detection.
  • the structure shown in FIG. 1 is integrated into the display, in order to not affect the display, when the pressure sensitive structure is fabricated, the pressure sensitive layer and the first electrode need to be patterned, so that when the display panel is produced, Significantly increasing the number of masks used makes the fabrication work complicated, resulting in a significant increase in manufacturing costs and a greater difficulty in the fabrication process.
  • an embodiment of the present disclosure provides an array substrate, a manufacturing method thereof, a display panel, and a display device, which realize a high detection precision of a pressure when a pressure sensitive structure and a dual gate transistor are integrated into a display. It can simplify the production process and reduce the production cost.
  • An embodiment of the present disclosure provides an array substrate, as shown in FIG. 2 to FIG. 4, which may include: a substrate substrate 1, a pressure sensitive structure 2, a plurality of double gate transistors 3, and a plurality of pixel transistors 4; 2 to Figure 4 shows only one dual gate transistor 3 and one pixel transistor 4;
  • the pressure sensitive structure 2 includes a first electrode layer 2-1, a pressure sensitive layer 2-2 and a second electrode layer which are sequentially disposed on the base substrate 1, and the second electrode layer includes a one-to-one correspondence with each of the double gate transistors 3. a plurality of second electrodes 2-3, wherein only one second electrode 2-3 is shown in Figures 2 to 4;
  • the double gate transistor 3 and the pixel transistor 4 are disposed on the second electrode layer; and each of the second electrodes 2-3 is electrically connected to the bottom gate electrode 3-1 of the corresponding double gate transistor 3, respectively.
  • the above array substrate integrates the pressure sensitive structure and the double gate transistor into the array substrate at the same time, which can greatly improve the accuracy of pressure detection; and, because the pressure sensitive layer in the pressure sensitive structure is disposed on the double gate Between the transistor and the substrate, the pressure sensitive layer does not need to be patterned, so that the fabrication process of the array substrate can be simplified; since the double gate transistor and the pixel transistor are both located on the second electrode layer, when the array substrate is fabricated, At the same time, it can effectively reduce the number of masks used, simplify the production process, and reduce the production cost.
  • the double gate transistor 3 has two gate electrodes, which are a top gate electrode 3-2 and a bottom gate electrode 3-1, respectively.
  • the source-drain electrode 4-3 of the pixel transistor 4 is disposed in the same layer as the source-drain electrode 3-3 of the double-gate transistor 3, and the active layer 4-2 of the pixel transistor 4 and the active layer 3-4 of the double-gate transistor 3
  • the gate electrode 4-1 of the pixel transistor 4 is disposed in the same layer as the top gate electrode 3-2 or the bottom gate electrode 3-1 of the double gate transistor 3. Therefore, the double gate transistor 3 and the pixel transistor 4 are simultaneously fabricated, which can effectively reduce the number of masks used, simplify the manufacturing process, and reduce the manufacturing cost.
  • the pixel transistor 4 may be a top gate transistor, or as shown in FIG. 3 and FIG. 4, the pixel transistor 4 may be a bottom gate transistor, which is not limited herein.
  • the gate electrode 4-1 of the pixel transistor 4 and the double gate transistor 3 is disposed in the same layer.
  • the gate electrode 4-1 and the double gate of the pixel transistor 4 are used.
  • the bottom gate electrode 3-2 of the transistor 3 is disposed in the same layer.
  • the second electrode 2-3 may be electrically connected to the bottom gate electrode 3-1 through a via (shown in a solid line frame).
  • the second electrode 2-3 and the electrically connected bottom gate electrode 3-1 may be The same layer is disposed and integrated, that is, the bottom gate electrode 3-1 in the dual gate transistor 3 is multiplexed into the second electrode 2-3 in the pressure sensitive structure 2.
  • the gate electrode 4-1 is located between the active layer 4-2 and the source/drain electrode 4-3, so that when the array substrate is fabricated, the double gate can be used.
  • the top gate electrode 3-2 in the transistor 3 is fabricated together with the gate electrode 4-1 in the pixel transistor 4, and the bottom gate electrode 3-1 in the double gate transistor 3 and the second electrode 2 in the pressure sensitive structure 2 3 is disposed in the same layer and has an integrated structure.
  • the bottom gate electrode 3-1 and the second electrode 2-3 in the double gate transistor 3 are in the same layer, and have an integrated structure to reduce the number of masks used.
  • the manufacturing process is simplified; of course, the shape of the second electrode 2-3 is not limited to that shown in FIG. 5a, and may be other structures (as shown in FIG. 5b) as long as the pixel transistor 4 is a top gate transistor.
  • the bottom gate electrode 3-1 and the second electrode 2-3 of the double gate transistor 3 are disposed in the same layer and are in an integrated structure, which is not limited herein.
  • the active layer of the pixel transistor and the double gate transistor is generally made of low temperature polysilicon, that is, low temperature poly-silicon (LTPS).
  • LTPS low temperature poly-silicon
  • the pixel transistor 4 when the pixel transistor is a bottom gate transistor, as shown in FIG. 3, the pixel transistor 4 is a bottom gate transistor, and the gate electrode 4-1 thereof. It is located between the active layer 4-2 and the base substrate 1, so that the bottom gate electrode 3-1 in the double gate transistor 3 and the gate electrode 4-1 in the pixel transistor 4 can be formed in the fabrication of the array substrate. Make it together.
  • the first insulating layer 6 is provided between the second electrode 2-3 and the gate electrode 4-1 of the pixel transistor 4, so that The second electrode 2-3 may be electrically connected to the bottom gate electrode 3-1 through a via (shown in a solid line frame), that is, the via penetrates through the first insulating layer 6.
  • the pixel transistor 4 is a bottom gate type transistor, as shown in FIG. 4, the second electrode 2-3, the bottom gate electrode 3-1 of the double gate transistor 3, and the pixel transistor 4 may be used.
  • the gate electrode 4-1 is disposed in the same layer, that is, the bottom gate electrode 3-1 in the double gate transistor 3 is multiplexed into the second electrode 2-3. As shown in the top view of FIG.
  • the gate electrode 4-1 in the pixel transistor 4 is insulated from the bottom gate electrode 3-1 and the second electrode 2-3 in the double gate transistor 3, respectively, and the double gate transistor 3 is
  • the bottom gate electrode 3-1 is electrically connected to the second electrode 2-3, and the bottom gate electrode 3-1 and the second electrode 2-3 of the double gate transistor 3 are integrated;
  • a via hole penetrating through the first insulating layer 6 (shown in the solid line frame) is connected to the pressure sensitive layer 2-2 so as to facilitate the potential difference generated when the pressure sensitive layer 2-2 is pressed through the second electrode 2-3 In the double gate transistor 3.
  • the gate electrode 4-1 of each pixel transistor 4 and the bottom gate electrode of the double gate transistor 3 are used. 3-1 is produced at the same time, so that when the source-drain electrodes 4-3 of the respective pixel transistors 4 and the source-drain electrodes 3-3 of the double-gate transistor 3 are completed, the source-drain electrodes 3 of the double-gate transistor 3 are required.
  • the top gate electrode 3-2 is formed on the third surface to complete the fabrication of the double gate transistor 3; and the gate insulating layer 7 and the interlayer insulating layer 5 may be disposed of the same material and have the same thickness to ensure the double gate transistor 3 Semiconductor performance, which in turn enables accurate detection of pressure.
  • the active layer of the pixel transistor and the double gate transistor is generally made of amorphous silicon (a-Si) or oxide to ensure a pixel transistor and a double gate.
  • Transistors have excellent semiconductor performance.
  • the double gate transistor and the pixel transistor are fabricated, a part of the film layers are simultaneously formed, and therefore, when the pixel transistor is provided as a top gate transistor or a bottom gate transistor, It is set as a double gate transistor, which is not limited herein.
  • the second The orthographic projection of the electrode 2-3 on the base substrate and the orthographic projection of the source-drain electrodes 3-3 on the base substrate in the double-gate transistor 3 do not overlap each other, as shown in Figs. 5a and 5b and Fig. 6.
  • the first electrode in order to simplify the fabrication process of the array substrate, the first electrode may be overlaid on the substrate substrate, that is, the first electrode layer is disposed as a whole layer; but in this structure, during the operation of the display panel The active layer in the first electrode and the pixel transistor generates parasitic capacitance, which adversely affects the semiconductor performance of the pixel transistor and affects the display function of the display panel. Therefore, in order to avoid this problem, the first electrode may be applied. Perform patterning.
  • the first electrode layer has a hollow structure in a region where the active layer of each pixel transistor is located; specifically, when viewed from one side of the substrate substrate toward the array substrate The positional relationship between the active layer of the first electrode layer and the pixel transistor and the active layer of the dual gate transistor is as shown in the top view of FIG. 7a and FIG.
  • 4-2 represents the active layer in the transistor for the pixel
  • 4- 3 denotes an active layer in a double gate transistor
  • 2-1 denotes a first electrode layer
  • the hollow region is disposed by using the corresponding region of the active layer 4-2 in the transistor 4 to prevent the first electrode 2-1 from forming a parasitic capacitance with the active layer 4-2 in the pixel transistor 4 to avoid the influence on the display screen;
  • the orthographic projection of the hollow structure on the base substrate can completely overlap with the orthographic projection of the pixel transistor 4 on the substrate, so that no hollow structure can be seen in the top view shown in FIG.
  • Transistor 4 on a substrate The projection falls into the orthographic projection of the hollow structure on the base substrate, as shown in FIG. 7b, wherein the white area represents the hollow structure; of course, it is found through experiments that if the first electrode and the active layer in the pixel transistor are formed When the parasitic capacitance has a small influence on the semiconductor performance of the pixel transistor, it is not necessary to perform patterning processing on the first electrode, and it is only necessary to provide the entire surface on the substrate.
  • the pressure sensitive layer may be overlaid on the first electrode, that is, the pressure sensitive layer is disposed in a whole layer; but in this structure, when the pressure sensitive structure is subjected to external pressure,
  • the pressure sensitive layer has a hollow region and a hollow region, because the stress concentration is likely to cause the pressure sensitive layer to fall off, thereby reducing the accuracy of detecting the pressure; therefore, in order to avoid the occurrence of the problem, in the above array substrate provided by the embodiment of the present disclosure, the pressure sensitive layer has a hollow region.
  • the orthographic projection on the substrate substrate and the orthographic projection of the second electrode on the substrate substrate do not overlap each other; that is, the orthographic projection of the second electrode on the substrate substrate needs to overlap with the orthographic projection of the pressure sensitive layer on the substrate substrate
  • the size of the hollowed out area is not limited, as long as it can satisfy the orthogonal projection of the hollow area on the base substrate and the orthogonal projection of the second electrode on the base substrate.
  • the pressure sensitive material may be a piezoelectric material or a pressure. a resisting material; wherein, when the material of the pressure sensitive layer is a piezoelectric material, due to the self-characteristics of the piezoelectric material, the positive and negative charge centers inside the piezoelectric material are separated when subjected to external pressure, thereby being at the first electrode and the second
  • the electrodes respectively concentrate a positive charge and a negative charge to generate a potential difference, and then apply a potential difference to the double gate transistor through the bottom gate electrode in the double gate transistor electrically connected to the second electrode.
  • the equivalent circuit diagram is as shown in FIG. 8.
  • the first electrode layer 2-1 is used to load the first constant potential; and the second electrode 2-3 is used to apply a potential difference generated when the piezoelectric material is pressed to the bottom gate.
  • Electrode 3-1; top gate electrode 3-2 and source electrode in double gate transistor 3 are respectively used to load a second constant potential, and drain electrode in double gate transistor 3 is used to output first pressure sensing potential Vout;
  • the first constant potential may be a zero potential, and may be other constant potentials, which is not limited herein.
  • the resistance of the piezoresistive material changes when subjected to an external pressure due to the self-characteristics of the piezoresistive material, thereby generating between the first electrode and the second electrode.
  • the potential difference is then applied to the double gate transistor by the bottom gate electrode in the double gate transistor electrically connected to the second electrode.
  • the equivalent circuit diagram is as shown in FIG. 9.
  • the first electrode layer 2-1 is used to load the first constant potential through the voltage dividing resistor R 0 ; and the second electrode 2-3 is used to generate the piezoresistive material under pressure.
  • the potential difference acts on the bottom gate electrode 3-1; the top gate electrode 3-2 and the source electrode in the double gate transistor 3 are respectively used to load the third constant potential, and the drain electrode in the double gate transistor 3 is used to output the second pressure sense Measuring potential Vout'.
  • the embodiment of the present disclosure further provides a method for fabricating the above array substrate, as shown in FIG. 10, which may include:
  • the second electrode layer includes a plurality of second electrodes
  • each double gate transistor is disposed in one-to-one correspondence with each of the second electrodes, and each of the second electrodes is respectively connected to a bottom of the corresponding double gate transistor
  • the gate electrode is electrically connected.
  • the second electrode layer is formed on the pressure sensitive layer, which may specifically include:
  • a bottom gate electrode and a second electrode layer of the double gate transistor are separately formed on the pressure sensitive layer.
  • the plurality of pixel transistors and the plurality of double gate transistors are simultaneously formed on the second electrode layer, which may specifically include:
  • An interlayer insulating layer is formed on the top gate electrode in the pixel transistor and the top gate electrode in the dual gate transistor;
  • Source/drain electrodes of the plurality of pixel transistors and source/drain electrodes of the plurality of double gate transistors are respectively formed on the interlayer insulating layer.
  • step S1002 in the above manufacturing method provided by the embodiment of the present disclosure when the pixel transistor is a bottom gate transistor, a plurality of pixel transistors and a plurality of double gate transistors are simultaneously formed on the second electrode layer.
  • the pixel transistor is a bottom gate transistor, a plurality of pixel transistors and a plurality of double gate transistors are simultaneously formed on the second electrode layer.
  • the bottom gate electrode of the double gate transistor is electrically connected to the corresponding second electrode through the via hole;
  • a top gate electrode is formed on the source and drain electrodes in the dual gate transistor.
  • the second electrode layer includes a plurality of second electrodes
  • a source/drain electrode in the pixel transistor and a source/drain electrode in the double gate transistor are respectively formed on the interlayer insulating layer.
  • the second electrode layer includes a plurality of second electrodes
  • a top gate electrode is formed on the source and drain electrodes in the dual gate transistor.
  • an embodiment of the present disclosure further provides a display panel, which may include the above array substrate provided by an embodiment of the present disclosure.
  • the display panel when the display panel is a liquid crystal display panel, the thickness of the liquid crystal display panel is large due to the need to provide a backlight, and it is difficult to achieve thinning, so that the pressure sensitive structure and the dual gate transistor are integrated into the liquid crystal display. In the panel, the sensitivity and accuracy of the detection of the pressure may decrease or even disappear as the thickness of the liquid crystal display panel increases. Therefore, in the above display panel provided by the embodiment of the present disclosure, the display panel is generally light and thin.
  • a light-emitting display panel preferably an organic electroluminescence display panel; further, preferably a flexible organic electroluminescence display panel, to maximize sensitivity and accuracy for pressure detection.
  • an embodiment of the present disclosure further provides a display device, which may include the above display panel provided according to an embodiment of the present disclosure.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • An embodiment of the present disclosure provides an array substrate, a manufacturing method thereof, a display panel, and a display device, including: a substrate substrate, a pressure sensitive structure, a plurality of double gate transistors, and a plurality of pixel transistors; and the pressure sensitive structure includes a first electrode layer, a pressure sensitive layer and a second electrode layer on the base substrate; the second electrode layer includes a plurality of second electrodes disposed in one-to-one correspondence with the respective double gate transistors; the double gate transistor and the pixel transistor are disposed in the first Above the two electrode layers; and each of the second electrodes is electrically connected to the bottom gate electrode of the corresponding double gate transistor.
  • the pressure sensitive structure and the dual gate transistor are simultaneously integrated into the array substrate, which can greatly improve the accuracy of pressure detection; and, because the pressure sensitive layer in the pressure sensitive structure is disposed on the double gate transistor and the base substrate Therefore, the pressure sensitive layer does not need to be patterned, so that the fabrication process of the array substrate can be simplified; since the double gate transistor and the pixel transistor are both located on the second electrode layer, they can be simultaneously fabricated when the array substrate is fabricated, thereby effectively It can reduce the number of masks used, simplify the production process, and reduce the production cost.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

提供了一种阵列基板、其制作方法、显示面板及显示装置，包括：衬底基板（1）、压敏结构（2）、多个双栅晶体管（3）和多个像素用晶体管（4）；压敏结构（2）包括依次设置在衬底基板（1）上的第一电极层（2-1）、压敏层（2-2）和第二电极层，第二电极层包括与各双栅晶体管（3）一一对应设置的多个第二电极（2-3），且双栅晶体管（3）和像素用晶体管（4）设置于第二电极层之上，各第二电极（2-3）分别与对应双栅晶体管（3）中的底栅电极（3-1）电连接，从而实现对压力的检测。

Description

阵列基板、其制作方法、显示面板及显示装置
本申请要求在2017年6月23日提交中国专利局、申请号为201710488335.6、发明名称为“一种阵列基板、其制作方法、显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤指一种阵列基板、其制作方法、显示面板及显示装置。
背景技术
具有三维触摸(Three Dimension Touch,3D-Touch)功能的显示器，是将压力传感器集成到显示器中，即在触摸功能之外引入第三个Z轴的维度，能够为显示器的触摸功能增加一些由压力控制的动作；其中，集成到显示器中的压力传感器可以通过形变电容或者通过压敏材料的形变来实现，并且以简单的三层结构为主，但是简单的三明治结构很难实现高精度的压力检测，使得压力检测的分辨率和灵敏度较低。
发明内容
本公开实施例提供了一种阵列基板、其制作方法、显示面板及显示装置，具体方案如下：
本公开实施例提供了一种阵列基板，包括：衬底基板、压敏结构、多个双栅晶体管和多个像素用晶体管；其中，
所述压敏结构包括依次设置在所述衬底基板上的第一电极层、压敏层和第二电极层；所述第二电极层包括与各所述双栅晶体管一一对应设置的多个第二电极；
所述双栅晶体管和所述像素用晶体管设置于所述第二电极层之上；且各 所述第二电极分别与对应的所述双栅晶体管中的底栅电极电连接。
可选地，在本公开实施例提供的上述阵列基板中，所述像素用晶体管的源漏电极与所述双栅晶体管的源漏电极同层设置，所述像素用晶体管的有源层与所述双栅晶体管的有源层同层设置，所述像素用晶体管的栅电极与所述双栅晶体管的顶栅电极或底栅电极同层设置。
可选地，在本公开实施例提供的上述阵列基板中，所述第二电极在所述衬底基板上的正投影与所述双栅晶体管中的源漏电极在所述衬底基板上的正投影互不重叠。
可选地，在本公开实施例提供的上述阵列基板中，所述像素用晶体管为顶栅型晶体管，且所述像素用晶体管的栅电极与所述双栅晶体管的顶栅电极同层设置。
可选地，在本公开实施例提供的上述阵列基板中，所述第二电极与电连接的底栅电极同层设置且为一体结构。
可选地，在本公开实施例提供的上述阵列基板中，所述像素用晶体管为底栅型晶体管，且所述像素用晶体管的栅电极与所述双栅晶体管的底栅电极同层设置。
可选地，在本公开实施例提供的上述阵列基板中，所述第二电极通过过孔与所述底栅电极电连接。
可选地，在本公开实施例提供的上述阵列基板中，所述像素用晶体管为底栅型晶体管。
可选地，在本公开实施例提供的上述阵列基板中，所述第一电极层为整层设置。
可选地，在本公开实施例提供的上述阵列基板中，所述第一电极层在各所述像素用晶体管的有源层所在区域具有镂空结构。
可选地，在本公开实施例提供的上述阵列基板中，所述压敏层为整层设置。
可选地，在本公开实施例提供的上述阵列基板中，所述压敏层具有镂空 区域，所述镂空区域在所述衬底基板上的正投影与所述第二电极在所述衬底基板上的正投影互不重叠。
可选地，在本公开实施例提供的上述阵列基板中，所述压敏层的材质为压电材料；
所述第一电极层用于加载第一恒定电位；所述第二电极用于将所述压电材料受压时产生的电位差作用于所述底栅电极；所述双栅晶体管中的顶栅电极和源电极分别用于加载第二恒定电位，所述双栅晶体管中的漏电极用于输出第一压力感测电位。
可选地，在本公开实施例提供的上述阵列基板中，所述压敏层的材质为压阻材料；
所述第一电极层用于通过分压电阻加载第一恒定电位；所述第二电极用于将所述压阻材料受压时产生的电位差作用于所述底栅电极；所述双栅晶体管中的顶栅电极和源电极分别用于加载第三恒定电位，所述双栅晶体管中的漏电极用于输出第二压力感测电位。
本公开实施例还提供了一种显示面板，包括：如本公开实施例提供的上述阵列基板。
可选地，在本公开实施例提供的上述显示面板中，所述显示面板为柔性有机电致发光显示面板。
本公开实施例还提供了一种显示装置，包括：如本公开实施例提供的上述显示面板。
本公开实施例还提供了一种如本公开实施例提供的上述阵列基板的制作方法，包括：
在衬底基板上依次制作构成压敏结构的第一电极层、压敏层和第二电极层；所述第二电极层包括多个第二电极；
在所述第二电极层上同时制作多个像素用晶体管和多个双栅晶体管；各所述双栅晶体管与各所述第二电极一一对应设置，且各所述第二电极分别与对应所述双栅晶体管中的底栅电极电连接。
可选地，在本公开实施例提供的上述制作方法中，在所述像素用晶体管为顶栅型晶体管时，在所述压敏层上制作第二电极层，具体包括：
在所述压敏层上分别制作所述双栅晶体管的底栅电极和所述第二电极层。
可选地，在本公开实施例提供的上述制作方法中，所述在所述第二电极层上同时制作多个像素用晶体管和多个双栅晶体管，具体包括：
在所述第二电极层上分别制作多个所述像素用晶体管中的有源层和多个所述双栅晶体管中的有源层；
在所述像素用晶体管中的有源层和所述双栅晶体管中的有源层上制作栅绝缘层；
在所述栅绝缘层上分别制作多个所述像素用晶体管中的顶栅电极和多个所述双栅晶体管中的顶栅电极；
在所述像素用晶体管中的顶栅电极和所述双栅晶体管中的顶栅电极上制作层间绝缘层；
在所述层间绝缘层上分别制作多个所述像素用晶体管中的源漏电极和多个所述双栅晶体管中的源漏电极。
可选地，在本公开实施例提供的上述制作方法中，在所述像素用晶体管为底栅型晶体管时，所述在所述第二电极层上同时制作多个像素用晶体管和多个双栅晶体管，具体包括：
在所述第二电极层上分别制作多个所述像素用晶体管中的底栅电极和多个所述双栅晶体管中的底栅电极；所述双栅晶体管中的底栅电极通过过孔与对应所述第二电极电连接；
在所述像素用晶体管中的底栅电极和所述双栅晶体管中的底栅电极上制作栅绝缘层；
在所述栅绝缘层上分别制作多个所述像素用晶体管中的有源层和多个所述双栅晶体管的有源层；
在所述像素用晶体管中的有源层和所述双栅晶体管中的有源层上制作层 间绝缘层；
在所述层间绝缘层上分别制作多个所述像素用晶体管中的源漏电极和多个所述双栅晶体管的源漏电极；
在所述双栅晶体管中的源漏电极上制作顶栅电极。
附图说明
图1为相关技术中的压力传感器的结构示意图；
图2至图4分别为本公开实施例中提供的阵列基板的侧视图；
图5a和图5b分别为本公开实施例中提供的双栅晶体管和第二电极的俯视图；
图6为本公开实施例中提供的双栅晶体管、像素用晶体管和第二电极的俯视图；
图7a和图7b分别为本公开实施例中提供的第一电极的俯视图；
图8和图9分别为本公开实施例中提供的压敏结构与双栅晶体管的等效电路图；
图10至图13分别为本公开实施例中提供的阵列基板的制作方法的流程图。
具体实施方式
相关技术中，一种压力传感器是将三明治结构的压敏结构与双栅晶体管相结合，如图1所示，在双栅晶体管10的顶栅电极11之上设置有压敏结构20，在压敏结构20中包括第一电极21、压敏层22和第二电极23，且第二电极23与双栅晶体管10的顶栅电极11共用，在压敏结构20受到压力(黑色箭头表示压力)时，在第一电极21与第二电极23处会产生电位差并作用于顶栅电极11中，使得双栅晶体管10产生阈值漂移，从而输出压力感测电位，通过对输出的压力感测电位的计算处理确定受到的压力大小；该种结构的压力传感器可以实现高精度的压力检测，可以大大提高压力检测的精确度和灵 敏度。
然而，若将如图1所示的结构集成到显示器中时，为了不影响显示，在制作压敏结构时，需要对压敏层和第一电极进行图案化处理，使得在制作显示面板时会明显增加掩模板(mask)的使用数量，使得制作工作变得复杂，导致制作成本大大增加，制作工艺的难度也大大增加。
基于此，本公开实施例提供了一种阵列基板、其制作方法、显示面板及显示装置，实现将压敏结构和双栅晶体管集成到显示器时，在保证对压力具有较高的检测精度的同时，可以简化制作工艺以及降低制作成本。
下面将结合附图，对本公开实施例提供的一种阵列基板、其制作方法、显示面板及显示装置的具体实施方式进行详细地说明。需要说明的是，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开实施例提供了一种阵列基板，如图2至图4所示，可以包括：衬底基板1、压敏结构2、多个双栅晶体管3和多个像素用晶体管4；其中，图2至图4中只示出了一个双栅晶体管3和一个像素用晶体管4；
压敏结构2包括依次设置在衬底基板1上的第一电极层2-1、压敏层2-2和第二电极层；第二电极层包括与各双栅晶体管3一一对应设置的多个第二电极2-3，其中，图2至图4中仅示出了一个第二电极2-3；
双栅晶体管3和像素用晶体管4设置于第二电极层之上；且各第二电极2-3分别与对应的双栅晶体管3中的底栅电极3-1电连接。
本公开实施例提供的上述阵列基板，将压敏结构和双栅晶体管同时集成到了阵列基板中，可以较大地提高压力检测的精确度；并且，因压敏结构中的压敏层设置于双栅晶体管与衬底基板之间，所以压敏层无需进行图案化处理，从而可以简化阵列基板的制作工艺；由于双栅晶体管与像素用晶体管均位于第二电极层之上，在制作阵列基板时可以同时制作，从而有效可以减少mask的使用数量，简化制作工艺，降低制作成本。
可选地，在本公开实施例提供的阵列基板中，如图2至图4所示，双栅晶体管3中具有两个栅电极，分别为顶栅电极3-2和底栅电极3-1。像素用晶体管4的源漏电极4-3与双栅晶体管3的源漏电极3-3同层设置，像素用晶体管4的有源层4-2与双栅晶体管3的有源层3-4同层设置，像素用晶体管4的栅电极4-1与双栅晶体管3的顶栅电极3-2或底栅电极3-1同层设置。从而使双栅晶体管3与像素用晶体管4同时制作，可以有效减少mask的使用数量，简化制作工艺，降低制作成本。
在具体实施时，如图2所示，像素用晶体管4可以为顶栅型晶体管，或者如图3和图4所示，像素用晶体管4也可以为底栅型晶体管，在此不作限定。
可选地，在本公开实施例提供的上述阵列基板中，如图2所示，当像素用晶体管4为顶栅型晶体管时，像素用晶体管4的栅电极4-1与双栅晶体管3的顶栅电极3-2同层设置。
可选地，在本公开实施例提供的上述阵列基板中，如图3和图4所示，当像素用晶体管4为底栅型晶体管时，像素用晶体管4的栅电极4-1与双栅晶体管3的底栅电极3-2同层设置。
可选地，在本公开实施例提供的上述阵列基板中，如图3所示，第二电极2-3可以通过过孔(实线框内所示)与底栅电极3-1电连接。
可选地，在本公开实施例提供的上述阵列基板中，如图2所示，当像素用晶体管4为顶栅型晶体管，第二电极2-3与电连接的底栅电极3-1可以同层设置且为一体结构，即双栅晶体管3中的底栅电极3-1复用为压敏结构2中的第二电极2-3。这是由于像素用晶体管4为顶栅型晶体管时，其栅电极4-1是位于有源层4-2和源漏电极4-3之间的，因此在制作阵列基板时，可以将双栅晶体管3中的顶栅电极3-2与像素用晶体管4中的栅电极4-1一起制作，将双栅晶体管3中的底栅电极3-1与压敏结构2中的第二电极2-3同层设置且为一体结构，如图5a所示，双栅晶体管3中的底栅电极3-1与第二电极2-3处于同一层中，且为一体结构，以减少mask的使用数量，简化制作工艺；当然， 第二电极2-3的形状并不限于图5a中所示，还可以是其他结构(如图5b所示)，只要能够在像素用晶体管4为顶栅型晶体管时，使得双栅晶体管3中的底栅电极3-1与第二电极2-3同层设置且为一体结构即可，在此不作限定。
具体地，在像素用晶体管为顶栅型晶体管时，像素用晶体管和双栅晶体管中的有源层的材质一般为低温多晶硅，即通过低温多晶硅技术(Low Temperature Poly-silicon,LTPS)制作而成，以保证像素用晶体管和双栅晶体管具有优异的半导体性能。
具体地，在本公开实施例提供的上述阵列基板中，当像素用晶体管为底栅型晶体管时，如图3所示，由于像素用晶体管4为底栅型晶体管，其中的栅电极4-1是位于有源层4-2和衬底基板1之间的，因此在制作阵列基板时，可以将双栅晶体管3中的底栅电极3-1与像素用晶体管4中的栅电极4-1一起制作。并且为了避免压敏层2-2与像素用晶体管4的栅电极4-1接触，在第二电极2-3与像素用晶体管4的栅电极4-1之间设置第一绝缘层6，这样第二电极2-3可以通过过孔(实线框内所示)与底栅电极3-1电连接，即过孔贯穿第一绝缘层6。
具体地，在像素用晶体管4为底栅型晶体管时，如图4所示，也可以将第二电极2-3、双栅晶体管3中的底栅电极3-1和像素用晶体管4中的栅电极4-1同层设置，即双栅晶体管3中的底栅电极3-1复用为第二电极2-3。如图6所示的俯视图，保证使像素用晶体管4中的栅电极4-1分别与双栅晶体管3中的底栅电极3-1和第二电极2-3绝缘，而双栅晶体管3中的底栅电极3-1与第二电极2-3电连接，双栅晶体管3中的底栅电极3-1与第二电极2-3为一体结构；此时第二电极2-3需要通过贯穿第一绝缘层6的过孔(实线框内所示)与压敏层2-2连接，以便于将压敏层2-2受压时产生的电位差通过第二电极2-3作用于双栅晶体管3中。
进一步地，在如图3和图4所示的阵列基板中，因像素用晶体管4为底栅型晶体管，所以各像素用晶体管4的栅电极4-1与双栅晶体管3中的底栅电极3-1是同时制作的，使得在制作完成各像素用晶体管4的源漏电极4-3和双 栅晶体管3的源漏电极3-3时，需要在双栅晶体管3的源漏电极3-3之上制作顶栅电极3-2，以完成双栅晶体管3的制作；并且，可以将栅绝缘层7与层间绝缘层5设置为同一材质，且厚度相同，以保证双栅晶体管3的半导体性能，进而实现对压力的精确检测。
具体地，在像素用晶体管为底栅型晶体管时，像素用晶体管和双栅晶体管中的有源层的材质一般为非晶硅(a-Si)或氧化物，以保证像素用晶体管和双栅晶体管具有优异的半导体性能。
可选地，由于双栅晶体管和像素用晶体管在制作时，其中部分膜层是同时制作的，所以，在将像素用晶体管设置为顶栅型晶体管或底栅型晶体管的同时，还可以将其设置为双栅晶体管，在此不作限定。
可选地，为了避免第二电极中的电位信号对双栅晶体管中的源漏电极的信号产生干扰，以减少对显示画面的影响，在本公开实施例提供的上述阵列基板中，使得第二电极2-3在衬底基板上的正投影与双栅晶体管3中的源漏电极3-3在衬底基板上的正投影互不重叠，如图5a和图5b以及图6所示。
在具体实施时，为了简化阵列基板的制作工艺，第一电极可以整面覆盖在衬底基板之上，即第一电极层为整层设置；但在此结构下，在显示面板的工作过程中，第一电极与像素用晶体管中的有源层会产生寄生电容，对像素用晶体管的半导体性能造成不良影响，影响显示面板的显示功能，所以为了避免这一问题的出现，可以对第一电极进行图案化处理。
可选地，在本公开实施例提供的上述阵列基板中，第一电极层在各像素用晶体管的有源层所在区域具有镂空结构；具体地，从衬底基板的一侧看向阵列基板时，第一电极层与像素用晶体管的有源层与双栅晶体管的有源层的位置关系如图7a和图7b所示的俯视图，4-2表示像素用晶体管中的有源层，4-3表示双栅晶体管中的有源层，2-1表示第一电极层，且图中仅示出了一个像素用晶体管的有源层和一个双栅晶体管的有源层；其中，只有在像素用晶体管4中的有源层4-2的对应区域进行镂空设置，避免第一电极2-1与像素用晶体管4中的有源层4-2形成寄生电容，以避免对显示画面的影响；并且，镂 空结构在衬底基板上的正投影可以与像素用晶体管4在衬底基板上的正投影完全重叠，所以在如图7a所示的俯视图中看不到镂空结构；还可以将像素用晶体管4在衬底基板上的正投影落入镂空结构在衬底基板上的正投影内，如图7b所示，其中白色区域表示镂空结构；当然，通过实验发现，若第一电极与像素用晶体管中的有源层之间形成的寄生电容，对像素用晶体管的半导体性能影响较小时，可以不需要对第一电极再进行图案化处理，只需整面设置在衬底基板上即可。
可选地，为了简化阵列基板的制作工艺，压敏层可以整面覆盖在第一电极之上，即压敏层为整层设置；但在此结构下，当压敏结构受到外压力时，因应力集中容易导致压敏层的脱落，从而降低对压力的检测精度；因此，为了避免这一问题的出现，在本公开实施例提供的上述阵列基板中，压敏层具有镂空区域，镂空区域在衬底基板上的正投影与第二电极在衬底基板上的正投影互不重叠；即第二电极在衬底基板上的正投影需要与压敏层在衬底基板上的正投影重叠，以保证对外压力进行有效的检测；当然，镂空区域的大小并不限定，只要能够满足镂空区域在衬底基板上的正投影与第二电极在衬底基板上的正投影互不重叠即可。
可选地，为了在压敏结构在受到外压力时，压敏层受到外压力的作用，在第一电极与第二电极之间产生电位差，所以，压敏材料可以为压电材料或压阻材料；其中，在压敏层的材质为压电材料时，因压电材料的自身特性，在受到外压力时压电材料内部的正负电荷中心发生分离，从而在第一电极和第二电极分别聚集正电荷和负电荷而产生电位差，然后，通过与第二电极电连接的双栅晶体管中的底栅电极，将电位差作用于双栅晶体管中。具体地，等效电路图如图8所示，第一电极层2-1用于加载第一恒定电位；第二电极2-3用于将压电材料受压时产生的电位差作用于底栅电极3-1；双栅晶体管3中的顶栅电极3-2和源电极分别用于加载第二恒定电位，双栅晶体管3中的漏电极用于输出第一压力感测电位Vout；并且，第一恒定电位可以是零电位，还可以是其他恒定电位，在此不作限定。
可选地，在压敏层的材质为压阻材料时，因压阻材料的自身特性，在受到外压力时压阻材料的电阻会发生变化，从而在第一电极和第二电极之间产生电位差，然后，通过与第二电极电连接的双栅晶体管中的底栅电极，将电位差作用于双栅晶体管中。具体地，等效电路图如图9所示，第一电极层2-1用于通过分压电阻R 0加载第一恒定电位；第二电极2-3用于将压阻材料受压时产生的电位差作用于底栅电极3-1；双栅晶体管3中的顶栅电极3-2和源电极分别用于加载第三恒定电位，双栅晶体管3中的漏电极用于输出第二压力感测电位Vout’。
基于同一发明构思，本公开实施例还提供了一种如本公开实施例提供的上述阵列基板的制作方法，如图10所示，可以包括：
S1001、在衬底基板上依次制作构成压敏结构的第一电极层、压敏层和第二电极层；第二电极层包括多个第二电极；
S1002、在第二电极层上同时制作多个像素用晶体管和多个双栅晶体管；各双栅晶体管与各第二电极一一对应设置，且各第二电极分别与对应双栅晶体管中的底栅电极电连接。
在具体实施时，在本公开实施例提供的上述制作方法中的步骤S1001，在像素用晶体管为顶栅型晶体管时，在压敏层上制作第二电极层，可以具体包括：
在压敏层上分别制作双栅晶体管的底栅电极和第二电极层。
可选地，在本公开实施例提供的上述制作方法中的步骤S1002在第二电极层上同时制作多个像素用晶体管和多个双栅晶体管，可以具体包括：
在第二电极层上分别制作多个像素用晶体管中的有源层和多个双栅晶体管中的有源层；
在像素用晶体管中的有源层和双栅晶体管中的有源层上制作栅绝缘层；
在栅绝缘层上分别制作多个像素用晶体管中的顶栅电极和多个双栅晶体管中的顶栅电极；
在像素用晶体管中的顶栅电极和双栅晶体管中的顶栅电极上制作层间绝 缘层；
在层间绝缘层上分别制作多个像素用晶体管中的源漏电极和多个双栅晶体管中的源漏电极。
在具体实施时，在本公开实施例提供的上述制作方法中的步骤S1002，在像素用晶体管为底栅型晶体管时，在第二电极层上同时制作多个像素用晶体管和多个双栅晶体管，可以具体包括：
在第二电极层上分别制作多个像素用晶体管中的底栅电极和多个双栅晶体管中的底栅电极；双栅晶体管中的底栅电极通过过孔与对应第二电极电连接；
在像素用晶体管中的底栅电极和双栅晶体管中的底栅电极上制作栅绝缘层；
在栅绝缘层上分别制作多个像素用晶体管中的有源层和多个双栅晶体管的有源层；
在像素用晶体管中的有源层和双栅晶体管中的有源层上制作层间绝缘层；
在层间绝缘层上分别制作多个像素用晶体管中的源漏电极和多个双栅晶体管的源漏电极；
在双栅晶体管中的源漏电极上制作顶栅电极。
下面将结合具体实施例对本公开实施例提供的上述制作方法进行详细描述。
可选地，根据图2所示的阵列基板的结构，结合图11所示的制作方法的流程图，对本公开实施例提供的上述制作方法的详细步骤如下：
S1101、在衬底基板上依次制作构成压敏结构的第一电极层和压敏层；
S1102、在压敏层上分别制作第二电极层和双栅晶体管的底栅电极；第二电极层包括多个第二电极；
S1103、在第二电极层上分别制作像素用晶体管中的有源层和双栅晶体管中的有源层；
S1104、在像素用晶体管中的有源层和双栅晶体管中的有源层上制作栅绝缘层；
S1105、在栅绝缘层上分别制作像素用晶体管中的顶栅电极和双栅晶体管中的顶栅电极；
S1106、在像素用晶体管中的顶栅电极和双栅晶体管中的顶栅电极上制作层间绝缘层；
S1107、在层间绝缘层上分别制作像素用晶体管中的源漏电极和双栅晶体管中的源漏电极。
可选地，根据图3所示的阵列基板的结构，结合图12所示的制作方法的流程图，对本公开实施例提供的上述制作方法的详细步骤如下：
S1201、在衬底基板上依次制作构成压敏结构的第一电极层、压敏层和第二电极层；第二电极层包括多个第二电极；
S1202、在第二电极层上分别制作像素用晶体管中的底栅电极和双栅晶体管中的底栅电极；双栅晶体管中的底栅电极通过过孔与对应第二电极电连接；
S1203、在像素用晶体管中的底栅电极和双栅晶体管中的底栅电极上制作栅绝缘层；
S1204、在栅绝缘层上分别制作像素用晶体管中的有源层和双栅晶体管的有源层；
S1205、在像素用晶体管中的有源层和双栅晶体管中的有源层上制作层间绝缘层；
S1206、在层间绝缘层上分别制作像素用晶体管中的源漏电极和双栅晶体管的源漏电极；
S1207、在双栅晶体管中的源漏电极上制作顶栅电极。
可选地，根据图4所示的阵列基板的结构，结合图13所示的制作方法的流程图，对本公开实施例提供的上述制作方法的详细步骤如下：
S1301、在衬底基板上依次制作构成压敏结构的第一电极层和压敏层；
S1302、在压敏层上分别制作第二电极层、双栅晶体管的底栅电极和像素 用晶体管的底栅电极；第二电极层包括多个第二电极；第二电极通过过孔与压敏层连接；
S1303、在像素用晶体管中的底栅电极和双栅晶体管中的底栅电极上制作栅绝缘层；
S1304、在栅绝缘层上分别制作像素用晶体管中的有源层和双栅晶体管的有源层；
S1305、在像素用晶体管中的有源层和双栅晶体管中的有源层上制作层间绝缘层；
S1306、在层间绝缘层上分别制作像素用晶体管中的源漏电极和双栅晶体管的源漏电极；
S1307、在双栅晶体管中的源漏电极上制作顶栅电极。
基于同一发明构思，本公开实施例还提供了一种显示面板，可以包括：如本公开实施例提供的上述阵列基板。
在具体实施时，在显示面板为液晶显示面板时，因其需要设置背光源而使得液晶显示面板的厚度较大而难以实现薄型化，所以，若将压敏结构和双栅晶体管集成至液晶显示面板中时，对压力的检测灵敏度和精确度会随着液晶显示面板的厚度的增加而降低甚至消失；因此，在本公开实施例提供的上述显示面板中，显示面板一般为轻薄化的电致发光显示面板，其中优选为有机电致发光显示面板；进一步地，优选为柔性有机电致发光显示面板，以最大程度地提高对压力检测的灵敏度和精确度。
基于同一发明构思，本公开实施例还提供了一种显示装置，可以包括：如本公开实施例提供的上述显示面板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
本公开实施例提供了一种阵列基板、其制作方法、显示面板及显示装置，包括：衬底基板、压敏结构、多个双栅晶体管和多个像素用晶体管；压敏结 构包括依次设置在衬底基板上的第一电极层、压敏层和第二电极层；第二电极层包括与各双栅晶体管一一对应设置的多个第二电极；双栅晶体管和像素用晶体管设置于第二电极层之上；且各第二电极分别与对应双栅晶体管中的底栅电极电连接。因此，本公开中将压敏结构和双栅晶体管同时集成到了阵列基板中，可以较大地提高压力检测的精确度；并且，因压敏结构中的压敏层设置于双栅晶体管与衬底基板之间，所以压敏层无需进行图案化处理，从而可以简化阵列基板的制作工艺；由于双栅晶体管与像素用晶体管均位于第二电极层之上，在制作阵列基板时可以同时制作，从而有效可以减少mask的使用数量，简化制作工艺，降低制作成本。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (20)

  1. 一种阵列基板，其中，包括：衬底基板、压敏结构、多个双栅晶体管和多个像素用晶体管；其中，
    所述压敏结构包括依次设置在所述衬底基板上的第一电极层、压敏层和第二电极层；所述第二电极层包括与各所述双栅晶体管一一对应设置的多个第二电极；
    所述双栅晶体管和所述像素用晶体管设置于所述第二电极层之上；且各所述第二电极分别与对应的所述双栅晶体管中的底栅电极电连接。
  2. 如权利要求1所述的阵列基板，其中，所述像素用晶体管的源漏电极与所述双栅晶体管的源漏电极同层设置，所述像素用晶体管的有源层与所述双栅晶体管的有源层同层设置，所述像素用晶体管的栅电极与所述双栅晶体管的顶栅电极或底栅电极同层设置。
  3. 如权利要求1所述的阵列基板，其中，所述第二电极在所述衬底基板上的正投影与所述双栅晶体管中的源漏电极在所述衬底基板上的正投影互不重叠。
  4. 如权利要求2所述的阵列基板，其中，所述像素用晶体管为顶栅型晶体管，且所述像素用晶体管的栅电极与所述双栅晶体管的顶栅电极同层设置。
  5. 如权利要求4所述的阵列基板，其中，所述第二电极与电连接的底栅电极同层设置且为一体结构。
  6. 如权利要求2所述的阵列基板，其中，所述像素用晶体管为底栅型晶体管，且所述像素用晶体管的栅电极与所述双栅晶体管的底栅电极同层设置。
  7. 如权利要求6所述的阵列基板，其中，所述第二电极通过过孔与所述底栅电极电连接。
  8. 如权利要求1所述的阵列基板，其中，所述第一电极层为整层设置。
  9. 如权利要求1所述的阵列基板，其中，所述第一电极层在各所述像素用晶体管的有源层所在区域具有镂空结构。
  10. 如权利要求1所述的阵列基板，其中，所述压敏层为整层设置。
  11. 如权利要求1所述的阵列基板，其中，所述压敏层具有镂空区域，所述镂空区域在所述衬底基板上的正投影与所述第二电极在所述衬底基板上的正投影互不重叠。
  12. 如权利要求1-11任一项所述的阵列基板，其中，所述压敏层的材质为压电材料；
    所述第一电极层用于加载第一恒定电位；所述第二电极用于将所述压电材料受压时产生的电位差作用于所述底栅电极；所述双栅晶体管中的顶栅电极和源电极分别用于加载第二恒定电位，所述双栅晶体管中的漏电极用于输出第一压力感测电位。
  13. 如权利要求1-11任一项所述的阵列基板，其中，所述压敏层的材质为压阻材料；
    所述第一电极层用于通过分压电阻加载第一恒定电位；所述第二电极用于将所述压阻材料受压时产生的电位差作用于所述底栅电极；所述双栅晶体管中的顶栅电极和源电极分别用于加载第三恒定电位，所述双栅晶体管中的漏电极用于输出第二压力感测电位。
  14. 一种显示面板，其中，包括：如权利要求1-13任一项所述的阵列基板。
  15. 如权利要求14所述的显示面板，其中，所述显示面板为柔性有机电致发光显示面板。
  16. 一种显示装置，其特征在于，包括：如权利要求14或15所述的显示面板。
  17. 一种如权利要求1-13任一项所述的阵列基板的制作方法，其中，包括：
    在衬底基板上依次制作构成压敏结构的第一电极层、压敏层和第二电极层；所述第二电极层包括多个第二电极；
    在所述第二电极层上同时制作多个像素用晶体管和多个双栅晶体管；各 所述双栅晶体管与各所述第二电极一一对应设置，且各所述第二电极分别与对应所述双栅晶体管中的底栅电极电连接。
  18. 如权利要求17所述的制作方法，其中，在所述像素用晶体管为顶栅型晶体管时，在所述压敏层上制作第二电极层，具体包括：
    在所述压敏层上分别制作所述双栅晶体管的底栅电极和所述第二电极层；
  19. 如权利要求18所述的制作方法，其中，所述在所述第二电极层上同时制作多个像素用晶体管和多个双栅晶体管，具体包括：
    在所述第二电极层上分别制作多个所述像素用晶体管中的有源层和多个所述双栅晶体管中的有源层；
    在所述像素用晶体管中的有源层和所述双栅晶体管中的有源层上制作栅绝缘层；
    在所述栅绝缘层上分别制作多个所述像素用晶体管中的顶栅电极和多个所述双栅晶体管中的顶栅电极；
    在所述像素用晶体管中的顶栅电极和所述双栅晶体管中的顶栅电极上制作层间绝缘层；
    在所述层间绝缘层上分别制作多个所述像素用晶体管中的源漏电极和多个所述双栅晶体管中的源漏电极。
  20. 如权利要求17所述的制作方法，其中，在所述像素用晶体管为底栅型晶体管时，所述在所述第二电极层上同时制作多个像素用晶体管和多个双栅晶体管，具体包括：
    在所述第二电极层上分别制作多个所述像素用晶体管中的底栅电极和多个所述双栅晶体管中的底栅电极；所述双栅晶体管中的底栅电极通过过孔与对应所述第二电极电连接；
    在所述像素用晶体管中的底栅电极和所述双栅晶体管中的底栅电极上制作栅绝缘层；
    在所述栅绝缘层上分别制作多个所述像素用晶体管中的有源层和多个所 述双栅晶体管的有源层；
    在所述像素用晶体管中的有源层和所述双栅晶体管中的有源层上制作层间绝缘层；
    在所述层间绝缘层上分别制作多个所述像素用晶体管中的源漏电极和多个所述双栅晶体管的源漏电极；
    在所述双栅晶体管中的源漏电极上制作顶栅电极。
PCT/CN2018/072274 2017-06-23 2018-01-11 阵列基板、其制作方法、显示面板及显示装置 WO2018233280A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/310,052 US10802630B2 (en) 2017-06-23 2018-01-11 Array substrate, method for fabricating the same, display panel, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710488335.6 2017-06-23
CN201710488335.6A CN107195665B (zh) 2017-06-23 2017-06-23 一种阵列基板、其制作方法、显示面板及显示装置

Publications (1)

Publication Number Publication Date
WO2018233280A1 true WO2018233280A1 (zh) 2018-12-27

Family

ID=59878843

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/072274 WO2018233280A1 (zh) 2017-06-23 2018-01-11 阵列基板、其制作方法、显示面板及显示装置

Country Status (3)

Country Link
US (1) US10802630B2 (zh)
CN (1) CN107195665B (zh)
WO (1) WO2018233280A1 (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107195665B (zh) 2017-06-23 2019-12-03 京东方科技集团股份有限公司 一种阵列基板、其制作方法、显示面板及显示装置
US20220123240A1 (en) * 2019-02-08 2022-04-21 Georgia Tech Research Corporation High Sensitivity Stable Sensors And Methods For Manufacturing Same
KR102472120B1 (ko) * 2019-05-03 2022-11-28 메이 선 테크놀로지 씨오 엘티디 의사-압전 d33 진동 장치 및 이를 통합하는 디스플레이
US11545612B2 (en) * 2019-05-03 2023-01-03 May Sun Technology Co., Ltd. Pseudo-piezoelectric D33 device and electronic device using the same
TWI699753B (zh) * 2019-05-21 2020-07-21 友達光電股份有限公司 主動元件基板及其驅動方法
CN110307777B (zh) * 2019-06-28 2021-03-05 上海天马微电子有限公司 一种压感面板及显示装置
KR20210035936A (ko) * 2019-09-24 2021-04-02 삼성디스플레이 주식회사 화소 회로 및 이를 포함하는 표시 장치
CN110718560B (zh) 2019-09-30 2021-05-07 武汉华星光电技术有限公司 阵列基板及其制备方法和显示面板
CN110910825B (zh) * 2019-12-10 2021-04-02 京东方科技集团股份有限公司 一种显示面板及显示装置
US11195859B2 (en) * 2019-12-10 2021-12-07 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Array substrate and flexible display panel
CN112435629B (zh) * 2020-11-24 2023-04-18 京东方科技集团股份有限公司 一种显示基板、显示装置
CN113571532B (zh) * 2021-07-14 2024-08-23 惠州华星光电显示有限公司 Tft背板与led显示面板及其制作方法
CN114023766B (zh) * 2021-10-25 2023-06-27 深圳市华星光电半导体显示技术有限公司 阵列基板及其制备方法和显示面板
CN117813940A (zh) * 2022-07-28 2024-04-02 京东方科技集团股份有限公司 显示基板及显示装置

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140008203A1 (en) * 2012-07-05 2014-01-09 Cambridge Touch Technologies, Ltd. Pressure sensing display device
CN105808001A (zh) * 2016-03-10 2016-07-27 京东方科技集团股份有限公司 一种压感触摸屏及显示装置
CN105867688A (zh) * 2016-03-29 2016-08-17 京东方科技集团股份有限公司 触控基板及其驱动方法、显示装置
CN205750751U (zh) * 2016-04-29 2016-11-30 芜湖伦丰电子科技有限公司 一种后置式电阻压感触摸屏结构
CN205788139U (zh) * 2016-06-03 2016-12-07 京东方科技集团股份有限公司 一种显示面板及显示装置
CN106328716A (zh) * 2016-08-26 2017-01-11 京东方科技集团股份有限公司 薄膜晶体管和利用其检测压力的方法、以及触控装置
CN106373977A (zh) * 2016-10-09 2017-02-01 中山大学 一种光增强的振动能量采集器件和阵列
CN106814912A (zh) * 2017-01-17 2017-06-09 京东方科技集团股份有限公司 一种压力触控传感器、显示装置及其驱动方法
CN107195665A (zh) * 2017-06-23 2017-09-22 京东方科技集团股份有限公司 一种阵列基板、其制作方法、显示面板及显示装置

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4562835B2 (ja) * 1999-11-05 2010-10-13 株式会社半導体エネルギー研究所 半導体装置の作製方法
TWI259409B (en) * 2005-01-07 2006-08-01 Au Optronics Corp Touch panel for recognizing fingerprint and method of making the same
JP5216204B2 (ja) * 2006-10-31 2013-06-19 株式会社半導体エネルギー研究所 液晶表示装置及びその作製方法
US20090115741A1 (en) * 2007-11-06 2009-05-07 Wintek Corporation Touch sensor and touch screen panel
JP2010140919A (ja) * 2008-12-09 2010-06-24 Hitachi Ltd 酸化物半導体装置及びその製造方法並びにアクティブマトリクス基板
JP4780204B2 (ja) * 2009-02-23 2011-09-28 カシオ計算機株式会社 圧力センサ及び圧力センサの圧力測定方法
WO2011045956A1 (ja) * 2009-10-16 2011-04-21 シャープ株式会社 半導体装置、それを備えた表示装置、および半導体装置の製造方法
JP2012119532A (ja) * 2010-12-01 2012-06-21 Seiko Epson Corp 薄膜トランジスタ形成用基板、半導体装置、電気装置
FR2979991B1 (fr) * 2011-09-14 2014-04-25 Commissariat Energie Atomique Capteur de pression piezoelectrique
KR20130037072A (ko) * 2011-10-05 2013-04-15 삼성전자주식회사 광터치 스크린 장치 및 그 제조 방법
CN103885223B (zh) * 2012-12-21 2017-04-19 上海天马微电子有限公司 一种触控显示面板、触控显示装置
TWI633668B (zh) * 2013-09-23 2018-08-21 半導體能源研究所股份有限公司 半導體裝置
KR102227474B1 (ko) * 2013-11-05 2021-03-15 삼성디스플레이 주식회사 박막트랜지스터 어레이 기판, 유기발광표시장치 및 박막트랜지스터 어레이 기판의 제조 방법
TWI679560B (zh) * 2014-03-13 2019-12-11 日商半導體能源研究所股份有限公司 觸控面板
CN104252276B (zh) * 2014-06-30 2018-04-27 上海天马有机发光显示技术有限公司 一种触控显示装置及其制造方法
KR20170068511A (ko) * 2014-10-06 2017-06-19 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 전자 기기
KR102287013B1 (ko) * 2014-11-25 2021-08-06 삼성디스플레이 주식회사 박막 트랜지스터, 이를 포함하는 유기 발광 표시 장치 및 그 제조 방법
JP6358081B2 (ja) * 2014-12-25 2018-07-18 大日本印刷株式会社 圧力センサ
CN104731405B (zh) * 2015-03-09 2018-01-19 上海天马微电子有限公司 一种触控显示装置及其制造方法
TWI765634B (zh) * 2015-03-27 2022-05-21 日商半導體能源研究所股份有限公司 觸控面板
WO2016181524A1 (ja) * 2015-05-13 2016-11-17 凸版印刷株式会社 液晶表示装置
KR102430575B1 (ko) * 2015-08-26 2022-08-08 엘지디스플레이 주식회사 유기 발광 표시 장치 및 이의 제조 방법
CN105136378B (zh) * 2015-09-24 2018-04-20 京东方科技集团股份有限公司 一种显示基板及显示装置
CN105573549B (zh) * 2015-12-08 2018-12-25 上海天马微电子有限公司 阵列基板、触控屏和触控显示装置及其制作方法
CN108292055B (zh) * 2015-12-28 2020-12-01 凸版印刷株式会社 液晶显示装置
JP6698486B2 (ja) * 2016-09-26 2020-05-27 株式会社ジャパンディスプレイ 表示装置
CN106531784A (zh) * 2016-10-20 2017-03-22 麦克思商务咨询(深圳)有限公司 薄膜晶体管、超声波传感器、阵列基板及显示装置
CN106886111A (zh) * 2017-03-31 2017-06-23 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
KR101832831B1 (ko) * 2017-06-14 2018-02-28 주식회사 에이코닉 표시 장치

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140008203A1 (en) * 2012-07-05 2014-01-09 Cambridge Touch Technologies, Ltd. Pressure sensing display device
CN105808001A (zh) * 2016-03-10 2016-07-27 京东方科技集团股份有限公司 一种压感触摸屏及显示装置
CN105867688A (zh) * 2016-03-29 2016-08-17 京东方科技集团股份有限公司 触控基板及其驱动方法、显示装置
CN205750751U (zh) * 2016-04-29 2016-11-30 芜湖伦丰电子科技有限公司 一种后置式电阻压感触摸屏结构
CN205788139U (zh) * 2016-06-03 2016-12-07 京东方科技集团股份有限公司 一种显示面板及显示装置
CN106328716A (zh) * 2016-08-26 2017-01-11 京东方科技集团股份有限公司 薄膜晶体管和利用其检测压力的方法、以及触控装置
CN106373977A (zh) * 2016-10-09 2017-02-01 中山大学 一种光增强的振动能量采集器件和阵列
CN106814912A (zh) * 2017-01-17 2017-06-09 京东方科技集团股份有限公司 一种压力触控传感器、显示装置及其驱动方法
CN107195665A (zh) * 2017-06-23 2017-09-22 京东方科技集团股份有限公司 一种阵列基板、其制作方法、显示面板及显示装置

Also Published As

Publication number Publication date
CN107195665B (zh) 2019-12-03
US10802630B2 (en) 2020-10-13
US20200012369A1 (en) 2020-01-09
CN107195665A (zh) 2017-09-22

Similar Documents

Publication Publication Date Title
WO2018233280A1 (zh) 阵列基板、其制作方法、显示面板及显示装置
US11393871B2 (en) Array substrate and display panel having force TFT
WO2016123985A1 (zh) 阵列基板及其制作方法和驱动方法、显示装置
TW201803128A (zh) 陣列基板結構與顯示裝置
US10643049B2 (en) Display substrate, manufacturing method thereof, display device and fingerprint identification method
WO2015180358A1 (zh) 阵列基板及其制作方法和显示装置
KR102418577B1 (ko) 터치 센서를 가지는 표시 장치 및 그 제조 방법
WO2018223689A1 (zh) 一种阵列基板、显示面板及显示装置
WO2016145771A1 (zh) 阵列基板及其制作方法以及显示装置
WO2018036190A1 (zh) 薄膜晶体管和利用其检测压力的方法、以及触控装置
US20140240362A1 (en) Method for Processing and Displaying Image Information, Program, and Information Processor
JP2007048279A (ja) ディスプレイにデジタイザ入力装置を統合するプロセス
CN108231595B (zh) 薄膜晶体管及其制备方法、阵列基板、显示装置
KR20130037072A (ko) 광터치 스크린 장치 및 그 제조 방법
US10324554B2 (en) Array substrate and manufacturing method thereof, touch display panel and touch display apparatus
CN107885400B (zh) 一种oled触控显示面板及其驱动方法
KR20120062284A (ko) 광센싱 회로, 상기 광센싱 회로의 제조 방법, 및 상기 광센싱 회로를 포함하는 광터치 패널
WO2016090725A1 (zh) 一种ltps阵列基板
US20230161428A1 (en) Display substrate and manufacturing method therefor, and display device
WO2019219081A1 (zh) 压力传感单元及压力传感器、压力传感装置
WO2017156872A1 (zh) 一种显示基板、触摸屏及显示装置
KR20170098382A (ko) 터치 부재 및 이의 제조 방법
WO2017213175A1 (ja) タッチパネル付き表示装置及びタッチパネル付き表示装置の製造方法
US20170357352A1 (en) Display substrate and driving method thereof, and display device
CN112925435A (zh) 触摸显示装置及其制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18820832

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 03/06/2020)

122 Ep: pct application non-entry in european phase

Ref document number: 18820832

Country of ref document: EP

Kind code of ref document: A1