WO2018036190A1 - 薄膜晶体管和利用其检测压力的方法、以及触控装置 - Google Patents

薄膜晶体管和利用其检测压力的方法、以及触控装置 Download PDF

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WO2018036190A1
WO2018036190A1 PCT/CN2017/082326 CN2017082326W WO2018036190A1 WO 2018036190 A1 WO2018036190 A1 WO 2018036190A1 CN 2017082326 W CN2017082326 W CN 2017082326W WO 2018036190 A1 WO2018036190 A1 WO 2018036190A1
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thin film
layer
film transistor
source
drain
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PCT/CN2017/082326
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English (en)
French (fr)
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张斌
王光兴
陈鹏名
解宇
张衎
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/566,526 priority Critical patent/US10297695B2/en
Publication of WO2018036190A1 publication Critical patent/WO2018036190A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0414—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using force sensing means to determine a position
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/84—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of applied mechanical force, e.g. of pressure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N39/00—Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N30/00 – H10N35/00
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04102—Flexible digitiser, i.e. constructional details for allowing the whole digitising part of a device to be flexed or rolled like a sheet of paper
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04105—Pressure sensors for measuring the pressure or force exerted on the touch surface without providing the touch position
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/85—Piezoelectric or electrostrictive active materials
    • H10N30/857—Macromolecular compositions

Definitions

  • Embodiments of the present invention relate to a thin film transistor and a method of detecting pressure using the same, and a touch device.
  • touch technology has been widely used in electronic devices such as mobile phones and tablet computers.
  • Touch technology provides an efficient and convenient way of human-computer interaction.
  • the basic principle is to capture the touch and motion information of a touch object (such as a human finger or a stylus), and convert the acquired touch and motion information into The electrical signal is judged and identified to realize the control function.
  • At least one embodiment of the present invention provides a thin film transistor including: an active layer; a source and a drain spaced apart from each other and both connected to the active layer; a first insulating layer, which is A source layer is stacked; and a piezoelectric layer spaced apart from the source and drain and spaced apart from the active layer by the first insulating layer.
  • the thin film transistor further includes a gate electrode and a second insulating layer, the second insulating layer spacing the gate from the active layer, and in a direction perpendicular to the active layer
  • the second insulating layer and the first insulating layer are respectively disposed on opposite sides of the active layer.
  • the first insulating layer is disposed between the layer in which the source and drain are located and the piezoelectric layer.
  • the size of the piezoelectric layer is greater than or equal to the distance between the source and the drain in a direction from the source to the drain.
  • the piezoelectric layer is configured as a gate of the thin film transistor.
  • the thin film transistor further includes a carrier substrate carrying the active layer, the source, the drain, the first insulating layer and the piezoelectric layer, the piezoelectric layer being disposed away from the active layer Carry one side of the substrate.
  • the piezoelectric layer is located on a side of the layer where the source and the drain are located away from the active layer.
  • the material of the piezoelectric layer comprises a flexible piezoelectric material.
  • the material of the piezoelectric layer includes a polymer piezoelectric material.
  • At least one embodiment of the present invention provides a method of detecting a pressure of a thin film transistor according to any of the above, the method comprising: detecting a current value between a source and a drain of the thin film transistor; The current value determines whether the piezoelectric layer of the thin film transistor is applied with pressure or the magnitude of the applied pressure of the piezoelectric layer.
  • At least one embodiment of the present invention also provides a touch device including a plurality of thin film transistors described above, the piezoelectric layers of the plurality of thin film transistors being spaced apart from each other.
  • the touch device further includes: a plurality of first signal lines respectively connected to sources of the plurality of thin film transistors; and a plurality of second signal lines respectively associated with the plurality of thin film transistors a drain connection, the second signal line intersecting an extending direction of the first signal line.
  • the thin film transistor further includes a second insulating layer and a gate, the gate being spaced apart from the active layer by the second insulating layer.
  • the touch device further includes: a plurality of first signal lines respectively connected to sources of the plurality of thin film transistors; and a plurality of second signal lines respectively connected to drains of the plurality of thin film transistors; And a plurality of third signal lines respectively connected to the gates of the plurality of thin film transistors, the extending direction of the third signal lines intersecting the extending direction of the first signal line or the second signal line.
  • FIG. 1 is a cross-sectional view of a thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is an equivalent circuit diagram of a thin film transistor according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of an I DS detection circuit according to an embodiment of the present invention.
  • FIG. 4a is a schematic top view of a touch device according to an embodiment of the present invention.
  • FIG. 4b is a top view of the touch device according to an embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of a touch device according to an embodiment of the invention.
  • At least one embodiment of the present invention provides a thin film transistor 100 including: an active layer 40; a source 51 and a drain 52 spaced apart from each other and both connected to the active layer 40; An insulating layer 60, which is disposed in layer with the active layer 40; and a piezoelectric layer 70 spaced apart from the source 51 and the drain 52 (eg, spaced apart from the source 51 and the drain 52 by the first insulating layer 60) A portion located between the source 51 and the drain 52 in a direction parallel to the active layer 40 and spaced apart from the active layer 40 by the first insulating layer 60.
  • the source 51 and the drain 52 may be disposed above or below the active layer 40; for example, the piezoelectric layer 70 may be disposed above or below the active layer 40.
  • a piezoelectric sensing device is used, and a piezoelectric layer 70 is disposed in the thin film transistor 100.
  • the piezoelectric layer 70 can serve as a gate of the thin film transistor 100, and a pressure is applied to the piezoelectric layer 70.
  • positive and negative charges ie, gate voltages
  • the amount of generated charges is proportional to the applied pressure, so that the source 51 and the drain of the thin film transistor 100 are The current between 52 changes. According to the electricity between the source 51 and the drain 52
  • the flow can be subjected to pressure detection to determine whether the piezoelectric layer 70 is pressurized or to determine the magnitude of the applied pressure.
  • the thin film transistor 100 provided by at least one embodiment of the present invention further includes a second insulating layer 30 and a gate electrode 20 spaced apart from the active layer 40 by the second insulating layer 30 and perpendicular to the active layer
  • the second insulating layer 30 and the first insulating layer 60 are disposed on opposite sides of the active layer 40, respectively. That is, in a direction perpendicular to the active layer 40, the piezoelectric layer 70 and the gate electrode 20 are respectively disposed on both sides of the active layer 40.
  • the thin film transistor 100 is a double gate thin film transistor having piezoelectric characteristics.
  • the first insulating layer 60 is disposed between the layer where the source 51 and the drain 52 are located and the piezoelectric layer 70.
  • the size d1 of the piezoelectric layer 70 is greater than or equal to the distance d2 between the source 51 and the drain 52, which facilitates the piezoelectric layer 70 to cover the active layer 40.
  • the entire channel region is such that the source 51 and the drain 52 are turned on to generate a channel current when the piezoelectric layer 70 is applied with pressure.
  • At least one embodiment of the present invention provides a thin film transistor 100 further including a carrier substrate 10 carrying an active layer 40 , a source 51 , a drain 52 , a first insulating layer 60 , and a piezoelectric layer 70 .
  • the piezoelectric layer 70 is disposed on a side of the active layer 40 away from the carrier substrate 10. Since the piezoelectric layer 70 is disposed on the upper side of the active layer 40, when the thin film transistor 100 is touched by the user, the piezoelectric layer 70 is closer to the user's finger, and thus the piezoelectric layer 70 is easily pressed, thereby contributing to the pressure increase. Detection performance.
  • the piezoelectric layer 70 is located on the side of the layer where the source 51 and the drain 52 are located away from the active layer 40.
  • the piezoelectric layer 70 is disposed on the upper side of the active layer 40, by placing the piezoelectric layer 70 on the upper side of the layer where the source 51 and the drain 52 are located, it is further advantageous to apply pressure to the piezoelectric layer 70. Thereby further improving the pressure detection performance.
  • the material of the piezoelectric layer 70 includes a flexible piezoelectric material. Since the flexible material has the advantages of being soft and not brittle, the embodiment of the present invention is particularly suitable for touch detection of a flexible display screen by using a flexible piezoelectric material.
  • the material of the piezoelectric layer 70 includes a piezoelectric polymer material such as polyvinylidene fluoride (PVDF) or the like.
  • PVDF is a soft piezoelectric material that is not easily broken, waterproof, and frequency It should have a wide advantage and the like, and the material can be formed by a common thin film transistor process, for example, in forming the gate electrode 20 of the thin film transistor, the second insulating layer 30, the active layer 40, the source 51, the drain 52, and the After an insulating layer 60, the thin film transistor 100 shown in FIG. 1 can be obtained by forming a PVDF film layer on the first insulating layer 60.
  • the material of the active layer 40 may be a semiconductor material such as amorphous silicon, polysilicon or metal oxide semiconductor; the source 51, the drain 52 and the gate 20 may be made of aluminum, aluminum-bismuth alloy or copper.
  • a metal material such as titanium, molybdenum or molybdenum-niobium alloy is used; the first insulating layer 60 and the second insulating layer 30 may be an organic insulating layer, an inorganic insulating layer or a laminate of the two.
  • Materials for the various components of the embodiments of the invention include, but are not limited to, the materials listed.
  • At least one embodiment of the present invention also provides a method of detecting pressure using the thin film transistor 100 provided by any of the above embodiments, the method comprising: detecting a source 51 and a drain 52 of the thin film transistor 100 as shown in FIG. The current value between; and the magnitude of the pressure applied to the piezoelectric layer 70 of the thin film transistor 100 or the piezoelectric layer 70 is applied based on the current value.
  • the first insulating layer 60 is disposed between the layer where the source 51 and the drain 52 are located and the piezoelectric layer 70, and the piezoelectric layer 70 and the gate are
  • an equivalent circuit diagram of the thin film transistor 100 can be as shown in FIG. 2, and the thin film transistor 100 is equivalent to a double gate thin film transistor including a second gate. a source, a drain, a first gate, and a capacitor connected to the first gate, the source and the drain; the piezoelectric layer 70 shown in FIG.
  • the layer 60 and the piezoelectric layer 70 are equivalent to the first gate and the capacitor as a whole, and the gate 20, the source 51 and the drain 52 shown in FIG. 1 respectively correspond to the second gate, the source and the gate in FIG. Drain.
  • the current value (ie, channel current) I DS between the source and the drain is affected by the first gate (ie, the piezoelectric layer 70) and the second gate (ie, the gate). 20)
  • ⁇ FE is the carrier mobility of the active layer
  • C i is the parasitic capacitance of the second insulating layer
  • W and L are the width and length of the thin film transistor, respectively
  • V GS is the second gate and source.
  • the voltage between the poles, V T is the threshold voltage of the thin film transistor.
  • V T0 is a threshold voltage formed by the second gate, which is determined by the design parameters and process recipe of the second gate (ie, gate 20 in FIG. 1);
  • V PG is the first gate (ie, the piezoelectric layer 70 in FIG. 1) forms a threshold voltage, and V PG is related to the applied pressure of the piezoelectric layer, namely:
  • C top is the parasitic capacitance of the first insulating layer
  • d 33 is the piezoelectric coefficient of the piezoelectric layer and is determined by the piezoelectric layer material itself
  • F is the pressure to which the piezoelectric layer is applied.
  • the piezoelectric layer 70 is maintained when the thin film transistor is under the same V GS voltage and the voltage difference (V DS ) between the source and the drain remains unchanged.
  • the applied voltage is different, and the current I DS between the source and the drain is also different (it is known from the above formula that the current I DS decreases as the pressure F increases). Therefore, by detecting the size of I DS , it is possible to determine whether the piezoelectric layer is applied with pressure or the magnitude of the applied pressure.
  • FIG. 3 is a schematic diagram of an I DS detection circuit according to an embodiment of the present invention.
  • the source is applied with a voltage V DD and the drain is connected to a resistor R.
  • the voltage V d I DS *R
  • V d is amplified by an operational amplifier to obtain V out , and then V out is input to the processor for calculation. It can be established by calculating the relationship between the pressure F V out applied to the piezoelectric layer, thereby determining the magnitude of force F.
  • the at least one embodiment of the present invention further provides a touch device, as shown in FIG. 4a and FIG. 4b, the touch device includes the thin film transistor 100 provided by any one of the above embodiments, and the plurality of thin film transistors 100
  • the piezoelectric layers 70 are spaced apart from one another.
  • the thin film transistor 100 included in the touch device can form a thin film transistor array, and in the case of a touch, the position of the touched thin film transistor and the touch pressure can be determined according to the current between the source and the drain of each thin film transistor 100.
  • the size of the touched film transistor can be obtained according to the position of the touched thin film transistor.
  • the touch device of the embodiment of the invention can be configured as follows.
  • the touch device provided by at least one embodiment of the present invention further includes a plurality of first signal lines 81 and a plurality of second signal lines 82; the first signal lines 81 and the plurality of thin film transistors respectively
  • the source 51 of 100 is connected (as shown in FIG. 4a, the source 51 of each thin film transistor 100 is connected to a first signal line 81); the second signal line 82 is respectively connected to the drain 52 of the plurality of thin film transistors 100 (eg, As shown in FIG. 4a, the drain 52 of each thin film transistor 100 is connected to a second signal line 82), and the second signal line 82 intersects the extending direction of the first signal line 81.
  • a source voltage may be applied one by one to the first signal line 81 as shown in FIG. 4a for column-by-column scanning, and when the first signal line 81 of the j-th column is scanned, the first signal is detected.
  • Method 2 As shown in FIG. 4b, in the case where the thin film transistor 100 includes the second insulating layer 30 as shown in FIG. 1 and the gate electrode 20 spaced apart from the active layer 40 by the second insulating layer 30, the present invention
  • the touch device provided by at least one embodiment further includes: a plurality of first signal lines 81 respectively connected to the source 51 of the plurality of thin film transistors 100; and a plurality of second signal lines 82 respectively connected to the plurality of thin film transistors 100
  • the drain 52 is connected; and a plurality of third signal lines 83 are respectively connected to the gates 20 of the plurality of thin film transistors 100 (as shown in FIG. 4b, the gate 20 of each thin film transistor 100 is connected to a third signal line).
  • the extending direction of the third signal line 83 intersects with the extending direction of the first signal line 81 or the second signal line 82.
  • the first signal line 81 is parallel to the extending direction of the second signal line 82.
  • the third signal line 83 may be progressively scanned to determine the ordinate of the touch position according to the third signal line 83, and determine the abscissa of the touch position according to the second signal line 82 to obtain Touch the coordinates of the location.
  • the embodiments of the present invention can be applied to an On cell touch display device.
  • the touch device provided by at least one embodiment of the present invention further includes an array substrate 300 carrying a plurality of pixels 320 and an opposite substrate 200 disposed opposite the array substrate (eg, the opposite substrate)
  • the substrate 200 may be a carrier substrate 10 as shown in FIG. 1 .
  • the plurality of thin film transistors 100 as described above may be disposed on a side of the opposite substrate 200 away from the array substrate 300 . In this way, when the user touches the touch device, the piezoelectric layer of the thin film transistor 100 is closer to the user's finger, which is advantageous for improving the touch positioning effect.
  • the touch device provided by the embodiment of the present invention can also be applied to other modes of the touch display device, as long as the piezoelectric device can be realized.
  • the piezoelectric effect of the layer and the touch positioning can be realized according to the position of the thin film transistor.
  • the touch device provided by the embodiment of the present invention may be a liquid crystal touch display panel, an electronic paper, an OLED (Organic Light Emitting Diode) touch display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigation device. Any product or part that has display and touch functions.
  • OLED Organic Light Emitting Diode
  • the thin film transistor and the method for detecting the pressure thereof and the embodiment of the touch device can be referred to each other. Further, the features of the embodiments and the embodiments of the present invention may be combined with each other without conflict.

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Abstract

一种薄膜晶体管和利用其检测压力的方法、以及触控装置。薄膜晶体管（100）包括：有源层(40)；源极(51)和漏极(52)，其彼此间隔开并且都与所述有源层(40)连接；第一绝缘层(60)，其与所述有源层(40)层叠设置；以及压电层(70)，其与所述源极(51)和所述漏极(52)间隔开并且通过所述第一绝缘层(60)与所述有源层(40)间隔开。

Description

薄膜晶体管和利用其检测压力的方法、以及触控装置 技术领域
本发明的实施例涉及一种薄膜晶体管和利用其检测压力的方法、以及触控装置。
背景技术
目前，触控技术已广泛应用在手机、平板电脑等电子设备中。触控技术提供了一种高效、便利的人机交互方式，其基本原理是以捕捉触摸物(例如人体手指或触控笔)的触摸、动作信息为出发点，将获取的触摸及动作信息转化为电信号并加以判断识别，以实现控制功能。
发明内容
本发明的至少一个实施例提供一种薄膜晶体管，其包括：有源层；源极和漏极，其彼此间隔开并且都与所述有源层连接；第一绝缘层，其与所述有源层层叠设置；以及压电层，其与所述源极和漏极间隔开并且通过所述第一绝缘层与所述有源层间隔开。
例如，所述的薄膜晶体管还包括栅极和第二绝缘层，所述第二绝缘层将所述栅极与所述有源层间隔开，并且在垂直于所述有源层的方向上，所述第二绝缘层和所述第一绝缘层分别设置于所述有源层的相对的两侧。
例如，在垂直于所述有源层的方向上，所述第一绝缘层设置于所述源极和漏极所在层与所述压电层之间。
例如，在从所述源极到所述漏极的方向上，所述压电层的尺寸大于或等于所述源极和所述漏极之间的距离。
例如，在所述压电层被施加压力的情况下，所述压电层被配置为所述薄膜晶体管的栅极。
例如，所述的薄膜晶体管还包括承载所述有源层、源极、漏极、第一绝缘层和压电层的承载基板，所述压电层设置于所述有源层的远离所述承载基板的一侧。
例如，所述压电层位于所述源极和所述漏极所在层的远离所述有源层的一侧。
例如，所述压电层的材料包括柔性压电材料。
例如，所述压电层的材料包括高分子压电材料。
本发明的至少一个实施例还提供一种以上任一项所述的薄膜晶体管检测压力的方法，该方法包括：检测所述薄膜晶体管的源极和漏极之间的电流值；以及根据所述电流值判断所述薄膜晶体管的压电层是否被施加压力或者所述压电层被施加的压力的大小。
本发明的至少一个实施例还提供一种触控装置，其包括多个以上所述的薄膜晶体管，所述多个薄膜晶体管的压电层彼此间隔开。
例如，所述的触控装置还包括：多条第一信号线，其分别与所述多个薄膜晶体管的源极连接；以及多条第二信号线，其分别与所述多个薄膜晶体管的漏极连接，所述第二信号线与所述第一信号线的延伸方向相交。
例如，所述薄膜晶体管还包括第二绝缘层以及栅极，所述栅极通过所述第二绝缘层与所述有源层间隔开。所述触控装置还包括：多条第一信号线，其分别与所述多个薄膜晶体管的源极连接；多条第二信号线，其分别与所述多个薄膜晶体管的漏极连接；以及多条第三信号线，其分别与所述多个薄膜晶体管的栅极连接，所述第三信号线的延伸方向与所述第一信号线或所述第二信号线的延伸方向相交。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明实施例提供的薄膜晶体管的剖视示意图；
图2为本发明实施例提供的薄膜晶体管的等效电路图；
图3为本发明实施例提供的一种IDS检测电路的示意图；
图4a为本发明实施例提供的触控装置的俯视示意图一；
图4b为本发明实施例提供的触控装置的俯视示意图二；
图5为本发明实施例提供的触控装置的剖视示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面结合附图，对本发明实施例提供的薄膜晶体管和利用该薄膜晶体管检测压力的方法以及触控装置进行详细说明。
如图1所示，本发明的至少一个实施例提供一种薄膜晶体管100，其包括：有源层40；源极51和漏极52，其彼此间隔开并且都与有源层40连接；第一绝缘层60，其与有源层40层叠设置；以及压电层70，其与源极51和漏极52间隔开(例如通过第一绝缘层60与源极51和漏极52间隔开)、包括在平行于有源层40的方向上位于源极51和漏极52之间的部分并且通过第一绝缘层60与有源层40间隔开。
例如，源极51和漏极52可以设置于有源层40的上方或者下方；例如，压电层70也可以设置于有源层40的上方或者下方。
本发明实施例采用压电式感应检测手段，在薄膜晶体管100中设置有压电层70，该压电层70可以作为该薄膜晶体管100的栅极，在该压电层70被施加压力的情况下，由于压电效应，该压电层70的两侧产生正、负电荷(即产生栅极电压)，产生的电荷量与施加的压力成正比，使得薄膜晶体管100的源极51和漏极52之间的电流发生变化。根据源极51和漏极52之间的电 流可以进行压力检测，以判断压电层70是否被施加压力或者判断被施加的压力的大小。
例如，本发明的至少一个实施例提供的薄膜晶体管100还包括第二绝缘层30以及栅极20，栅极20通过第二绝缘层30与有源层40间隔开，并且在垂直于有源层40的方向上(即在图1中的垂直方向上)，第二绝缘层30和第一绝缘层60分别设置于有源层40的相对的两侧。也就是说，在垂直于有源层40的方向上，压电层70与栅极20分别设置于有源层40的两侧。在这种情况下，该薄膜晶体管100为具有压电特性的双栅极薄膜晶体管。
例如，在垂直于有源层40的方向上，第一绝缘层60设置于源极51和漏极52所在层与压电层70之间。
例如，在从源极51到漏极52的方向上，压电层70的尺寸d1大于或等于源极51和漏极52之间的距离d2，这样有利于压电层70覆盖有源层40的整个沟道区域，从而在压电层70被施加压力的情况下使源极51和漏极52之间导通以产生沟道电流。
例如，继续参见图1，本发明的至少一个实施例提供的薄膜晶体管100还包括承载有源层40、源极51、漏极52、第一绝缘层60和压电层70的承载基板10，压电层70设置于有源层40的远离承载基板10的一侧。由于压电层70设置于有源层40的上侧，在薄膜晶体管100被用户触摸时，压电层70距离用户的手指较近，因而压电层70容易被施加压力，从而有利于提高压力检测性能。
例如，在压电层70设置于有源层40的远离承载基板10的一侧的情况下，压电层70位于源极51和漏极52所在层的远离有源层40的一侧。在压电层70设置于有源层40的上侧的基础上，通过将压电层70设置于源极51以及漏极52所在层的上侧，进一步有利于压电层70被施加压力，从而进一步提高压力检测性能。
例如，压电层70的材料包括柔性压电材料。由于柔性材料具有柔软、不易碎的优点，通过采用柔性压电材料，使得本发明实施例尤其适用于柔性显示屏的触摸检测。
例如，压电层70的材料包括高分子压电材料，例如聚偏二氟乙烯(PVDF)或类似材料。PVDF是一种柔软的压电材料，具有不易破碎、防水、频率响 应较宽等优点，并且该材料可通过常用的薄膜晶体管制程制作形成，例如，在形成薄膜晶体管的栅极20、第二绝缘层30、有源层40、源极51、漏极52以及第一绝缘层60之后，通过在第一绝缘层60上形成PVDF膜层即可得到如图1所示的薄膜晶体管100。
例如，本发明实施例中，有源层40的材料可以为非晶硅、多晶硅或金属氧化物半导体等半导体材料；源极51、漏极52和栅极20可以采用铝、铝钕合金、铜、钛、钼、钼铌合金等金属材料制作；第一绝缘层60和第二绝缘层30可以为有机绝缘层、无机绝缘层或者二者的叠层。本发明实施例中各部件的材料包括但不限于所列举的材料。
本发明的至少一个实施例还提供一种利用以上任一项实施例提供的薄膜晶体管100检测压力的方法，该方法包括：检测如图1所示的薄膜晶体管100的源极51和漏极52之间的电流值；以及根据该电流值判断薄膜晶体管100的压电层70是否被施加压力或者压电层70被施加的压力的大小。
下面结合图2和图3对利用本发明实施例提供的薄膜晶体管实现压力检测的原理进行说明。
对于本发明任一实施例提供的薄膜晶体管100，如图1所示，在第一绝缘层60设置于源极51和漏极52所在层与压电层70之间并且压电层70与栅极20分别设置于有源层40的两侧的情况下，薄膜晶体管100的等效电路图可以如图2所示，该薄膜晶体管100等效为一个双栅极薄膜晶体管，其包括第二栅极、源极、漏极、第一栅极和电容，该电容与第一栅极、源极和漏极连接；图1所示的压电层70等效为该第一栅极，第一绝缘层60和压电层70整体上等效为该第一栅极和电容，图1所示的栅极20、源极51和漏极52分别对应图2中的第二栅极、源极和漏极。
根据图2所示的等效电路图可知，源极、漏极之间的电流值(即沟道电流)IDS受第一栅极(即压电层70)和第二栅极(即栅极20)的共同影响，并且可以得出：
Figure PCTCN2017082326-appb-000001
在以上公式中，μFE是有源层的载流子迁移率，Ci是第二绝缘层的寄生电容，W、L分别是薄膜晶体管的宽和长，VGS是第二栅极和源极间的电压， VT是薄膜晶体管的阈值电压。
由于该薄膜晶体管是一个双栅极薄膜晶体管，因此阈值电压VT由第二栅极和第一栅极这两部分形成的阈值电压组成，即VT＝VT0+VPG。在该公式中，VT0是第二栅极形成的阈值电压，该阈值电压由第二栅极(即图1中的栅极20)的设计参数和工艺制程决定；VPG是第一栅极(即图1中的压电层70)形成的阈值电压，VPG和压电层被施加的压力有关，即：
Figure PCTCN2017082326-appb-000002
在以上公式中，Ctop是第一绝缘层的寄生电容，d33是压电层的压电系数并且由压电层材料本身决定，F是压电层被施加的压力。
从以上关于IDS和VPG的公式可以看出，当薄膜晶体管在同样的VGS电压作用下并且源极和漏极之间的电压差(VDS)也保持不变时，压电层70被施加的压力不同，则源极和漏极之间的电流IDS也不同(根据以上公式可知，电流IDS随着压力F的增大而减小)。因此，通过检测IDS的大小，即可确定压电层是否被施加压力或者被施加的压力的大小。
例如，根据薄膜晶体管的源、漏极之间的电流值IDS确定压电层是否被施加压力或者被施加的压力的大小，可以通过将IDS转化为电压进行检测的方式实现。图3为本发明实施例提供的一种IDS检测电路的示意图。如图3所示，源极被施加电压VDD，漏极连接电阻R，在压力F的作用下，沟道电流IDS从漏极流出后流入电阻R，电压Vd＝IDS*R，Vd经过运算放大器放大后得到Vout，之后Vout被输入处理器进行计算。通过计算可建立Vout与压电层被施加的压力F之间的关系，从而确定出压力F的大小。
本发明的至少一个实施例还提供一种触控装置，如图4a和图4b所示，该触控装置包括多个以上任一实施例提供的薄膜晶体管100，并且该多个薄膜晶体管100的压电层70彼此间隔开。该触控装置包括的薄膜晶体管100可以形成薄膜晶体管阵列，在发生触摸的情况下，根据各薄膜晶体管100输出的源、漏极之间的电流可判断出被触摸的薄膜晶体管的位置以及触摸压力的大小，根据该被触摸的薄膜晶体管的位置可以得到触摸位置。
例如，为了判断出被触摸的薄膜晶体管的位置以实现触摸定位，根据本 发明实施例的触控装置可以如下设置。
方式一：如图4a所示，本发明的至少一个实施例提供的触控装置还包括多条第一信号线81和多条第二信号线82；第一信号线81分别与多个薄膜晶体管100的源极51连接(如图4a所示，每个薄膜晶体管100的源极51连接一条第一信号线81)；第二信号线82分别与多个薄膜晶体管100的漏极52连接(如图4a所示，每个薄膜晶体管100的漏极52连接一条第二信号线82)，第二信号线82与第一信号线81的延伸方向相交。在触摸检测过程中，例如，可以对如图4a所示的第一信号线81逐个施加源极电压以进行逐列扫描，当扫描到第j列第一信号线81时，检测该第一信号线81连接的多个薄膜晶体管100对应的第二信号线82的输出信号；若检测出该第一信号线81连接的第i行薄膜晶体管被触摸，则可确定出触摸位置的坐标为(i，j)。
方式二：如图4b所示，在薄膜晶体管100包括如图1所示的第二绝缘层30以及通过第二绝缘层30与有源层40间隔开的栅极20的情况下，本发明的至少一个实施例提供的触控装置还包括：多条第一信号线81，其分别与多个薄膜晶体管100的源极51连接；多条第二信号线82，其分别与多个薄膜晶体管100的漏极52连接；以及多条第三信号线83，其分别与多个薄膜晶体管100的栅极20连接(如图4b所示，每个薄膜晶体管100的栅极20连接一条第三信号线83)，第三信号线83的延伸方向与第一信号线81或第二信号线82的延伸方向相交。例如，如图4b所示，第一信号线81与第二信号线82的延伸方向平行。在触摸检测过程中，例如，可以对第三信号线83进行逐行扫描，从而根据第三信号线83确定触摸位置的纵坐标，并根据第二信号线82确定触摸位置的横坐标，以得到触摸位置的坐标。
例如，本发明实施例可以应用于覆盖表面式(On cell)触控显示装置中。例如，如图5所示，本发明的至少一个实施例提供的触控装置还包括承载有多个像素320的阵列基板300以及与该阵列基板相对设置的对置基板200(例如，该对置基板200可以为如图1所示的承载基板10)，该触控装置包括的如上所述的多个薄膜晶体管100可以设置于对置基板200的远离阵列基板300的一侧。这样，在用户触摸该触控装置时，薄膜晶体管100的压电层距离用户的手指较近，有利于提高触摸定位效果。当然，本发明实施例提供的触控装置也可以应用于其他模式的触控显示装置中，只要能够实现利用压电 层的压电效应并根据薄膜晶体管的位置实现触摸定位即可。
例如，本发明实施例提供的触控装置可以为液晶触控显示面板、电子纸、OLED(有机发光二极管)触控显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示和触控功能的产品或部件。
上述薄膜晶体管和利用其检测压力的方法、以及触控装置的实施例可以互相参照。此外，在不冲突的情况下，本发明的实施例及实施例中的特征可以相互组合。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2016年8月26日递交的第201610742811.8号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (13)

  1. 一种薄膜晶体管，包括：
    有源层；
    源极和漏极，所述源极和漏极彼此间隔并且都与所述有源层连接；
    第一绝缘层，其与所述有源层层叠设置；以及
    压电层，其与所述源极和所述漏极间隔开并且通过所述第一绝缘层与所述有源层间隔开。
  2. 根据权利要求1所述的薄膜晶体管，还包括栅极和第二绝缘层，其中，所述第二绝缘层将所述栅极与所述有源层间隔开，并且在垂直于所述有源层的方向上，所述第二绝缘层和所述第一绝缘层分别设置于所述有源层的相对的两侧。
  3. 根据权利要求1所述的薄膜晶体管，其中，在垂直于所述有源层的方向上，所述第一绝缘层设置于所述源极和漏极所在层与所述压电层之间。
  4. 根据权利要求1所述的薄膜晶体管，其中，在从所述源极到所述漏极的方向上，所述压电层的尺寸大于或等于所述源极和所述漏极之间的距离。
  5. 根据权利要求1至4中任一项所述的薄膜晶体管，其中，在所述压电层被施加压力的情况下，所述压电层被配置为所述薄膜晶体管的栅极。
  6. 根据权利要求1至4中任一项所述的薄膜晶体管，还包括承载所述有源层、源极、漏极、第一绝缘层和压电层的承载基板，其中，所述压电层设置于所述有源层的远离所述承载基板的一侧。
  7. 根据权利要求6所述的薄膜晶体管，其中，所述压电层位于所述源极和所述漏极所在层的远离所述有源层的一侧。
  8. 根据权利要求1至4中任一项所述的薄膜晶体管，其中，所述压电层的材料包括柔性压电材料。
  9. 根据权利要求1至4中任一项所述的薄膜晶体管，其中，所述压电层的材料包括高分子压电材料。
  10. 一种利用权利要求1至9中任一项所述的薄膜晶体管检测压力的方法，包括：
    检测所述薄膜晶体管的源极和漏极之间的电流值；以及
    根据所述电流值判断所述薄膜晶体管的压电层是否被施加压力或者所述压电层被施加的压力的大小。
  11. 一种触控装置，包括多个根据权利要求1至9中任一项所述的薄膜晶体管，其中，所述多个薄膜晶体管的压电层彼此间隔开。
  12. 根据权利要求11所述的触控装置，还包括：
    多条第一信号线，其分别与所述多个薄膜晶体管的源极连接；以及
    多条第二信号线，其分别与所述多个薄膜晶体管的漏极连接，其中，所述第二信号线与所述第一信号线的延伸方向相交。
  13. 根据权利要求11所述的触控装置，其中，
    所述薄膜晶体管还包括第二绝缘层以及栅极，所述栅极通过所述第二绝缘层与所述有源层间隔开；
    所述触控装置还包括：
    多条第一信号线，其分别与所述多个薄膜晶体管的源极连接；
    多条第二信号线，其分别与所述多个薄膜晶体管的漏极连接；以及
    多条第三信号线，其分别与所述多个薄膜晶体管的栅极连接，其中，所述第三信号线的延伸方向与所述第一信号线或所述第二信号线的延伸方向相交。
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