WO2018212119A1 - 積層型電子部品および積層型電子部品の製造方法 - Google Patents
積層型電子部品および積層型電子部品の製造方法 Download PDFInfo
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- WO2018212119A1 WO2018212119A1 PCT/JP2018/018466 JP2018018466W WO2018212119A1 WO 2018212119 A1 WO2018212119 A1 WO 2018212119A1 JP 2018018466 W JP2018018466 W JP 2018018466W WO 2018212119 A1 WO2018212119 A1 WO 2018212119A1
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- electronic component
- laminate
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- recess
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- 238000004519 manufacturing process Methods 0.000 title claims description 36
- 238000000034 method Methods 0.000 title description 11
- 239000000919 ceramic Substances 0.000 claims abstract description 69
- 230000015572 biosynthetic process Effects 0.000 claims description 30
- 239000003990 capacitor Substances 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 20
- 238000010304 firing Methods 0.000 claims description 13
- 238000010030 laminating Methods 0.000 claims description 7
- 238000003825 pressing Methods 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 5
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 230000002950 deficient Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 75
- 230000004907 flux Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- ORQBXQOJMQIAOY-UHFFFAOYSA-N nobelium Chemical compound [No] ORQBXQOJMQIAOY-UHFFFAOYSA-N 0.000 description 4
- 239000000843 powder Substances 0.000 description 4
- 239000002002 slurry Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 239000011230 binding agent Substances 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 230000005764 inhibitory process Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004014 plasticizer Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
- H01G4/302—Stacked capacitors obtained by injection of metal in cavities formed in a ceramic body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/40—Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F17/0013—Printed inductances with stacked layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
- H01F27/36—Electric or magnetic shields or screens
- H01F27/363—Electric or magnetic shields or screens made of electrically conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
- H01G2/24—Distinguishing marks, e.g. colour coding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
- H01G4/12—Ceramic dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/0115—Frequency selective two-port networks comprising only inductors and capacitors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/17—Structural details of sub-circuits of frequency selective networks
- H03H7/1741—Comprising typical LC combinations, irrespective of presence and location of additional resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F2017/008—Electric or magnetic shielding of printed inductances
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
- H03H2001/0021—Constructional details
- H03H2001/0085—Multilayer, e.g. LTCC, HTCC, green sheets
Definitions
- the present invention relates to a multilayer electronic component including a laminate in which a plurality of ceramic layers are laminated.
- the present invention also relates to a method for manufacturing a multilayer electronic component suitable for manufacturing the multilayer electronic component of the present invention.
- the IC element is prevented from malfunctioning due to noise entering from the outside, and the IC element does not emit noise to the outside.
- a shield layer was formed on the surface.
- Patent Document 1 Japanese Patent No. 57792257 discloses an electronic component module (semiconductor device) in which a shield layer is formed on the outer surface.
- FIG. 10 shows an electronic component module (semiconductor device) 1000 disclosed in Patent Document 1.
- the electronic component module 1000 includes a wiring board 101.
- a plurality of IC elements (semiconductor chips) 102 are mounted on the upper main surface of the wiring board 101.
- the wiring board 101 and the IC element 102 are wire-bonded by a wire (signal line wire) 103. Further, the IC elements 102 are wire-bonded by wires 103.
- the mold resin 104 is formed on the upper main surface of the wiring substrate 101 so as to cover the IC element 102.
- Shield layer 105 is formed on the outer surface of mold resin 104.
- the shield layer 105 is provided so that the IC element 102 does not malfunction due to noise entering from the outside, and the IC element 102 does not emit noise to the outside.
- a recess (marking) 106 is formed on the top surface of the mold resin 104.
- the concave portion 106 is stamped by laser light irradiation, and displays product information such as a product number, a manufacturing date, and a manufacturing factory.
- the shadow of the concave portion 106 is visually read from above the shield layer 105 to recognize information such as a product number, a manufacturing date, and a manufacturing factory.
- a directional mark is formed on the top surface of the multilayer body so that the multilayer electronic component is mounted in the correct direction. It was. In some cases, a product number, a manufacturing date, a manufacturing factory, or the like is displayed on the top surface of the laminate in addition to or instead of the direction mark.
- the electrode formed immediately below the concave part is partially extruded. As a result of plastic deformation, the electrode may be disconnected or a crack may occur in the electrode.
- heat is applied to the electrode formed immediately below the recess and the electrode is disconnected. Or cracks may occur in the electrode.
- the present invention has been made to solve the above-described problems, and as a means for the multilayer electronic component of the present invention, a plurality of ceramic layers are laminated, and a bottom surface, a top surface, a bottom surface and a top surface are provided.
- a laminate having a plurality of side surfaces that connect each other, at least one recess representing at least one of a mark, a letter, and a number formed on the top surface of the laminate, and an electrode formed between the layers of the laminate And a shield layer formed on at least a part of the top surface including at least a part of the inner bottom surface and the inner wall surface of the recess and at least a part of the side surface of the laminate,
- An electrode non-formation region in which no electrode is formed is provided immediately below the inner bottom surface of the recess, and the thickness of the electrode non-formation region is set to be larger than the depth of the recess starting from the inner bottom surface of the recess.
- the multilayer electronic component according to the present invention includes an electrode non-formation portion having a thickness larger than the depth of the recess inside the laminate, thereby preventing the electrode from being broken or cracked. . Further, stray capacitance is prevented from being generated between the shield layer formed on the inner bottom surface of the recess formed on the top surface of the multilayer body and the electrode formed inside the multilayer body. Furthermore, the shield layer formed on the inner bottom surface of the recess formed on the top surface of the multilayer body suppresses the inhibition of magnetic flux formation of the inductor formed by the inductor electrode formed inside the multilayer body. .
- the thickness of the electrode non-formation region is preferably twice or more the depth of the recess starting from the inner bottom surface of the recess. In this case, the electrode is not disconnected or cracked almost certainly. Further, it is possible to more effectively suppress the generation of stray capacitance between the shield layer formed on the inner bottom surface of the recess formed on the top surface of the multilayer body and the electrode formed inside the multilayer body. be able to. Furthermore, it is more effective that the shield layer formed on the inner bottom surface of the concave portion formed on the top surface of the multilayer body inhibits the magnetic flux formation of the inductor constituted by the inductor electrode formed inside the multilayer body. Can be suppressed.
- no electrode is formed immediately below the inner bottom surface of the concave portion of the laminate. In this case, it is possible to more effectively suppress the influence of the formation of the concave portion on the top surface of the laminate and the formation of the shield layer on the inner bottom surface thereof immediately below the inner bottom surface of the concave portion.
- the size of the electrode non-formation region in the planar direction is extended by 1.5 times or more in the vertical direction and 1.5 times or more in the horizontal direction with the recess as the center. In this case, the influence by having formed the recessed part in the top
- the types of electrodes are, for example, inductor electrodes, capacitor electrodes, wiring electrodes, ground electrodes, and the like.
- At least one capacitor is formed by the capacitor electrode and at least one inductor is formed by the inductor electrode, and the LC filter circuit is formed by the capacitor and the inductor.
- the method for manufacturing a multilayer electronic component according to the present invention includes a step of preparing a plurality of ceramic green sheets, and at least one main surface of the plurality of ceramic green sheets, A step of applying a paste to form a first paste pattern, a step of laminating a plurality of ceramic green sheets in a predetermined order to produce an aggregated substrate-like unfired laminate, and an aggregated substrate-like unfired Applying a paste that disappears upon firing to the top surface of the laminate to form a second paste pattern having a certain thickness and representing at least one of a mark, a letter, and a number; and a second paste pattern Are pressed into the top surface of the aggregated substrate-like unfired laminate to flatten the top surface of the aggregated substrate-like unfired laminate, and the aggregated substrate-like unfired laminate is singulated.
- the paste which disappears by baking is applied to the top surface of the unfired laminated body in the form of a collective substrate to form a second paste pattern having a certain thickness and representing at least one of marks, letters and numbers.
- the paste that disappears by firing is applied to the upper main surface of the plurality of ceramic green sheets that are stacked on the uppermost layer, and represents at least one of marks, letters, and numbers. You may make it form the 2nd paste pattern provided with fixed thickness.
- the concave portion on the top surface of the laminate may be formed by irradiation with laser light without using a paste that disappears by firing.
- the concave portion of the top surface of the laminate may be formed by pressing the convex portion formed on the inner top surface of the mold into the top surface of the unfired laminate without using paste that disappears by firing. good.
- the multilayer electronic component manufactured by the method for manufacturing a multilayer electronic component according to the present invention is provided with an electrode non-formation region in which no electrode is formed immediately below the inner bottom surface of the concave portion of the laminate. It is preferable that the thickness of the is larger than the depth of the recess starting from the inner bottom surface of the recess. In this case, it is possible to avoid disconnection or cracks in the electrode.
- the multilayer electronic component of the present invention suppresses intrusion of noise from the outside and emission of noise to the outside, and displays highly visible marks, characters, numbers, and the like on the top surface, and further defective products Is suppressed.
- the multilayer electronic component of the present invention can be easily manufactured.
- FIG. 1 is a perspective view showing a multilayer electronic component 100 according to a first embodiment. Moreover, it is also a perspective view which shows the multilayer electronic component 300 concerning 3rd Embodiment. 1 is a cross-sectional view showing a multilayer electronic component 100. FIG. Further, it is a cross-sectional view showing the multilayer electronic component 300.
- FIGS. 3A and 3B are cross-sectional views illustrating steps performed in an example of a method for manufacturing the multilayer electronic component 100.
- 4 (C) to 4 (E) are continuations of FIG. 3 (B), and are cross-sectional views illustrating steps performed in an example of a method for manufacturing the multilayer electronic component 100.
- FIG. 5 (F) to 5 (H) are continuations of FIG.
- FIG. 4 (E) are cross-sectional views illustrating steps performed in an example of a method for manufacturing the multilayer electronic component 100.
- 6 (I) to 6 (K) are continuations of FIG. 5 (H), and are cross-sectional views illustrating steps performed in an example of a method for manufacturing the multilayer electronic component 100.
- FIG. 1 is a perspective view of the multilayer electronic component 100.
- FIG. 2 is a cross-sectional view of the multilayer electronic component 100, and shows the portion of the dashed line XX in FIG.
- the multilayer electronic component 100 is, for example, a multilayer LC filter in which capacitors and inductors are formed and a predetermined LC filter circuit is configured.
- the type of the multilayer electronic component 100 is arbitrary and is not limited to the multilayer LC filter.
- the multilayer electronic component 100 includes a multilayer body 1 in which ceramic layers 1a to 1h are laminated.
- the laminate 1 includes a bottom surface B, a top surface U, and four side surfaces S that connect the bottom surface B and the top surface U.
- the thicknesses of the ceramic layer 1a and the ceramic layer 1h, which are protective layers, are each 20 ⁇ m.
- the thicknesses of the ceramic layers 1b to 1g laminated between the ceramic layer 1a and the ceramic layer 1h were each 10 ⁇ m.
- the thickness and number of layers of the ceramic layer are arbitrary and can be selected as necessary.
- via electrodes 2 for connecting the upper and lower main surfaces are formed as necessary.
- a ground electrode 3, an inductor electrode 4, a capacitor electrode 5, and a wiring electrode 6 are formed between the ceramic layers 1a to 1h as necessary.
- a plurality of inductor electrodes 4 are spirally connected by via conductors (not shown) to form an inductor L.
- a capacitor C is formed by a pair of capacitor electrodes 5 and 5 formed to face each other.
- the inductor L and the capacitor C are connected by the via electrode 2 and the wiring electrode 6, and a predetermined LC filter circuit is configured inside the multilayer body 1.
- a plurality of external electrodes 7 are formed on the bottom surface B of the laminate 1.
- a plating layer 7a is formed on the surface of the external electrode 7 as necessary.
- Each of the external electrodes 7 is connected to a predetermined part of the LC filter circuit.
- a cylindrical recess 8 is formed on the top surface U of the laminate 1.
- the recess 8 is a directional mark.
- the depth of the recess 8 is 20 ⁇ m.
- the depth of the recess 8 is arbitrary and can be selected from about 5 ⁇ m to 50 ⁇ m.
- the recess 8 is not limited to a mark such as a directional mark, and may be a letter or a number, for example, a product number, a manufacturing date, a manufacturing factory, or the like.
- the recess 8 is formed by pressing the paste that disappears by firing into the top surface of the unfired stacked body.
- the ceramic layers 1e, 1f, 1g, and 1h are respectively plastically deformed toward the bottom surface B side by being pressed by the recess 8 immediately below the inner bottom surface of the recess 8.
- the shield layer 9 is formed on the top surface U including the inner bottom surface and the inner wall surface of the recess 8 and the four side surfaces S of the laminate 1.
- the shield layer 9 is provided so that noise does not enter from the outside and does not emit noise to the outside.
- An electrode non-formation region NE in which electrodes such as the ground electrode 3, the inductor electrode 4, the capacitor electrode 5, and the wiring electrode 6 are not formed is provided immediately below the inner bottom surface of the recess 8 in the laminate 1.
- the thickness of the electrode non-forming region NE is set to 20 ⁇ m starting from the inner bottom surface of the recess 8. That is, the thickness of the electrode non-forming region NE was set to 20 ⁇ m, which is the same as the depth of the recess 8.
- the electrode non-forming region NE having the same thickness as the depth of the concave portion 8 is formed immediately below the inner bottom surface of the concave portion 8.
- the capacitor electrode 5 and the wiring electrode 6 are not broken or cracked.
- the electrode non-formation region NE is provided by expanding the size in the planar direction by about 1.5 in the vertical direction and about 1.5 times in the horizontal direction with the recess 8 as the center. In this case, it is because it can suppress more effectively that disconnection and a crack generate
- the multilayer electronic component 100 of the first embodiment having the above structure has the following advantages.
- the shield layer 9 is formed on the outer surface of the multilayer body 1, intrusion of noise from the outside and emission of noise to the outside are suppressed.
- the multilayer electronic component 100 is provided with the concave portion 8 on the top surface U of the multilayer body 1 and displays information using marks, letters, numbers, etc., it is clearly shaded even from above the shield layer 9. Appears and information can be recognized with high visibility.
- the electrode non-forming region NE having a thickness of 20 ⁇ m, which is the same as the depth of the concave portion 8, is provided immediately below the inner bottom surface of the concave portion 8 of the multilayer body 1. No disconnection or cracking occurs in the electrodes such as the electrode 4, the capacitor electrode 5, and the wiring electrode 6. More specifically, as described above, the formation of the concave portion 8 causes the ceramic layers 1e, 1f, 1g, and 1h to be plastically deformed toward the bottom surface B side immediately below the inner bottom surface of the concave portion 8, respectively. . However, the ceramic layer 1d is not plastically deformed because the distance from the inner bottom surface of the recess 8 is increased by providing the electrode non-forming region NE. As a result, the capacitor electrode 5 formed between the ceramic layer 1d and the ceramic layer 1e is not plastically deformed, and no disconnection or crack is generated.
- the multilayer electronic component 100 is provided with the electrode non-forming region NE having a thickness of 20 ⁇ m, which is the same as the depth of the concave portion 8, immediately below the inner bottom surface of the concave portion 8 of the multilayer body 1, the inner bottom surface of the concave portion 8 is provided.
- the generation of stray capacitance is suppressed between the shield layer 9 formed on the first electrode and the electrodes such as the ground electrode 3, the inductor electrode 4, the capacitor electrode 5, and the wiring electrode 6.
- the shield layer 9 formed on the inner bottom surface of the recess 8 is also inhibited from inhibiting the magnetic flux formation of the inductor L formed by the inductor electrode 4. That is, in a multilayer electronic component, when a recess is formed on the top surface of the laminate and a shield layer is formed on the outer surface of the laminate, it is formed on the inner bottom surface of the recess formed on the top surface of the laminate.
- the shield layer obstructs the magnetic flux of the inductor formed by the inductor electrode formed inside the multilayer body, which is required when the Q value of the inductor is lowered or the inductance value of the inductor is lowered. The electrical characteristics may not be obtained.
- the multilayer electronic component 100 is provided with the electrode non-forming region NE having a thickness of 20 ⁇ m, which is the same as the depth of the concave portion 8, immediately below the inner bottom surface of the concave portion 8 of the multilayer body 1, the inner bottom surface of the concave portion 8 is provided. It is suppressed that the shield layer 9 formed in (1) inhibits the magnetic flux formation of the inductor L constituted by the inductor electrode 4.
- the multilayer electronic component 100 can be manufactured, for example, by the method shown in FIGS. 3 (A) to 6 (K).
- a ceramic slurry is prepared. Specifically, a ceramic slurry is prepared by mixing ceramic powder, a binder, and a plasticizer in predetermined amounts.
- a ceramic slurry is applied on a carrier film to produce a ceramic green sheet.
- a lip coater, a doctor blade, or the like can be used for applying the slurry.
- the ceramic green sheet is a mother ceramic green sheet 11a in which a large number of ceramic green sheets are arranged in a matrix in order to manufacture a large number of laminated electronic components 100 in a batch.
- ⁇ 11h are prepared.
- through holes 22 for forming the via electrodes 2 are formed in the ceramic green sheets 11a to 11h as necessary.
- the hole diameter of the through hole 22 is arbitrary, but is set to 20 ⁇ m to 200 ⁇ m, for example.
- a mechanical punch, irradiation with CO 2 laser light, irradiation with UV laser light, or the like can be used.
- a conductive paste is prepared. Specifically, a conductive paste is prepared by mixing conductive powder, a binder, and a plasticizer in predetermined amounts. You may add the base material (ceramic powder) for shrinkage
- base material ceramic powder
- the conductive paste 12 is filled into the through holes 22 of the ceramic green sheets 11a to 11h, and the main surfaces of the ceramic green sheets 11a to 11h are made conductive as necessary.
- a pattern 15, a conductive paste pattern 16 for forming the wiring electrode 6, and a conductive paste pattern 17 for forming the external electrode 7 are formed.
- a paste pattern 18 that disappears by firing is formed on the top surface of the ceramic green sheet 11h to form the recesses 8.
- the material of the paste pattern 18 is arbitrary as long as it is a material that disappears by firing, but for example, resin or carbon can be used.
- the paste pattern 18 can be formed by, for example, ink jet application or transfer.
- the thickness of the paste pattern 18 is slightly larger than the depth of the recess 8.
- the paste pattern 18 is not formed on the top surface (upper main surface) of the ceramic green sheet 11h, but before the ceramic green sheets 11a to 11h are laminated.
- the paste pattern 18 may be formed on the upper main surface of the ceramic green sheet 11h.
- the ceramic green sheets 11a to 11h are sandwiched between the lower mold 51 and the upper mold 52, and are integrated by applying pressure from above and below while being heated. A green unfired laminate 11 is produced. At this time, since the inner top surface of the upper mold 52 is flat, the paste pattern 18 is pushed into the top surface of the unfired laminate 11 having the aggregate substrate shape.
- each unfired laminated body 1 ' is formed by laminating ceramic green sheets 1a' to 1h '.
- the unfired laminate 1 ' is fired with a predetermined profile.
- the unfired laminated body 1 ′ on which the ceramic green sheets 1 a ′ to 1 h ′ are laminated is fired to become the laminated body 1 on which the ceramic layers 1 a to 1 h are laminated.
- the conductive paste 12 filled in the through hole 22 is baked to become the via electrode 2.
- the conductive paste pattern 13 is baked to become the ground electrode 3.
- the conductive paste pattern 14 is fired to become the inductor electrode 4.
- the conductive paste pattern 15 is baked to become the capacitor electrode 5.
- the conductive paste pattern 16 is baked to become the wiring electrode 6.
- the conductive paste pattern 17 is baked to become the external electrode 7.
- the paste pattern 18 that has been pushed into the top surface of the unfired laminate 1 ′ is baked and disappears, and a recess 8 is formed on the top surface of the laminate 1.
- a batch furnace, a belt furnace, etc. can be used for baking of the unbaking laminated body 1 '.
- a Cu paste is used as the conductive paste, it is fired in a reducing atmosphere.
- a plating layer 7 a is formed on the surface of the external electrode 7.
- the material and the number of layers of the plating layer 7a are arbitrary.
- the first layer can be a Ni plating layer and the second layer can be a Sn plating layer by electrolytic plating.
- an Au plating layer may be formed by electroless plating.
- the laminate 1 is fixed to a fixing jig 53 having adhesiveness on the upper main surface.
- a shield layer 9 is formed on the outer surface of the laminate 1 by sputtering. If necessary, plasma cleaning is performed on the outer surface of the laminate 1 before sputtering.
- the shield layer 9 is also formed on the inner bottom surface and inner wall surface of the recess 8.
- the shield layer 9 is formed in three layers in the order of an adhesion layer, a conductive layer, and a protective layer.
- the adhesive layer may be omitted.
- SUS, Ti, Cr, Ni, or the like can be used as the material for the adhesion layer and the protective layer.
- Cu, Ag, Al, or the like can be used as the material of the conductive layer.
- the sputtering equipment for example, an in-line type, a batch type, a single wafer type, or the like can be used.
- the shield layer 9 is formed by sputtering, but the shield layer 9 may be formed by spin coating.
- a resin paste containing conductive powder is attached to the outer surface of the laminate 1 by spin coating.
- you may plasma-clean the outer surface of the laminated body 1 before spin coating.
- the multilayer electronic component 100 according to the first embodiment is completed.
- FIG. 7 shows a multilayer electronic component 200 according to the second embodiment. However, FIG. 7 is a cross-sectional view of the multilayer electronic component 200.
- the manufacturing method of the multilayer electronic component 200 is partially changed from the manufacturing method of the multilayer electronic component 100 according to the first embodiment described above. Specifically, in the first embodiment, the paste pattern 18 is pushed into the top surface of the aggregated substrate-like unfired laminate 11, and the paste pattern 18 disappears during firing to form the recesses 8. In 2nd Embodiment, the recessed part 8 was formed by irradiating a laser beam to the top
- the ceramic layers 1e, 1f, 1g, and 1h are not plastically deformed immediately below the inner bottom surface of the recess 8.
- the electrode non-formation region NE having the same size as the depth of the recess 8 (20 ⁇ m) is provided immediately below the inner bottom surface of the recess 8; No disconnection or cracking occurs in the electrode (capacitor electrode 5 or the like) formed immediately below the inner bottom surface. Moreover, generation
- a multilayer electronic component 300 according to the third embodiment was produced. Since the multilayer electronic component 300 has the same structure as the multilayer electronic component 100 according to the first embodiment shown in FIGS. 1 and 2, the multilayer electronic component 300 will be described with reference to FIGS. 1 and 2.
- the manufacturing method of the multilayer electronic component 300 is also partially changed from the manufacturing method of the multilayer electronic component 100 according to the first embodiment described above. Specifically, in the first embodiment, the paste pattern 18 is pushed into the top surface of the aggregated substrate-like unfired laminate 11, and the paste pattern 18 disappears during firing to form the recesses 8. In 3rd Embodiment, the recessed part 8 was formed by pushing the convex part formed in the inner bottom face of an upper metal mold
- the multilayer electronic component 300 also has breaks or cracks in the electrodes (ground electrode 3, inductor electrode 4, capacitor electrode 5, wiring electrode 6, etc.) formed inside the multilayer body 1. Does not occur. Moreover, the generation of stray capacitance is suppressed, and the inhibition of the magnetic flux formation of the inductor is suppressed.
- FIG. 8 shows a multilayer electronic component 400 according to the fourth embodiment. However, FIG. 8 is a cross-sectional view of the multilayer electronic component 400.
- the multilayer electronic component 400 is a part of the structure of the multilayer electronic component 100 according to the first embodiment. Specifically, in the multilayer electronic component 100, the electrode non-formation region NE having the same thickness (20 ⁇ m) as the depth of the concave portion 8 is provided immediately below the inner bottom surface of the concave portion 8. In 400, an electrode non-forming region NE having a thickness (40 ⁇ m) twice as large as the depth of the recess 8 is provided immediately below the inner bottom surface of the recess 8. Accordingly, the content and arrangement of the LC filter circuit formed in the laminated body 1 were changed.
- the multilayer electronic component 400 is less likely to cause disconnection or cracks in the electrodes (such as the wiring electrode 6) immediately below the inner bottom surface of the recess 8. Further, the stray capacitance between the shield layer 9 formed on the inner bottom surface of the recess 8 and the electrode formed inside the stacked body is more effectively suppressed. Further, it is more effectively suppressed that the shield layer 9 formed on the inner bottom surface of the recess 8 inhibits the magnetic flux formation of the inductor L formed by the inductor electrode 4.
- FIG. 9 shows a multilayer electronic component 500 according to the fifth embodiment. However, FIG. 9 is a cross-sectional view of the multilayer electronic component 500.
- the multilayer electronic component 500 is a further modification of the multilayer electronic component 400 according to the fourth embodiment. Specifically, in the multilayer electronic component 500, no electrode is formed immediately below the inner bottom surface of the recess 8, and the region from the inner bottom surface of the recess 8 to the bottom surface B of the multilayer body 1 is defined as an electrode non-forming region NE. . Accordingly, the content and arrangement of the LC filter circuit formed in the laminated body 1 were changed.
- the electrode 8 is disconnected or cracked due to the formation of the recess 8 immediately below the recess 8 and the formation of the shield layer 9 on the inner bottom surface of the recess 8. Effects such as the generation of stray capacitance between them are further effectively suppressed.
- the multilayer electronic components 100, 200, 300, 400, 500 according to the first to fifth embodiments have been described above.
- the present invention is not limited to the contents described above, and various modifications can be made in accordance with the spirit of the invention.
- the multilayer electronic component 100, 200, 300, 400, 500 is a multilayer LC filter in which an LC filter circuit is configured inside the multilayer body 1, but the type of the multilayer electronic component is arbitrary. It is not limited to a stacked LC filter.
- the concave portion 8 is a mark (directional mark).
- the concave portion 8 is not limited to the mark, and may be a product number, a manufacture, etc. It may be a date indicating the date of manufacture and the manufacturing factory.
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Abstract
Description
図1、図2に、第1実施形態にかかる積層型電子部品100を示す。ただし、図1は、積層型電子部品100の斜視図である。図2は、積層型電子部品100の断面図であり、図1の一点鎖線X-X部分を示している。
図7に、第2実施形態にかかる積層型電子部品200を示す。ただし、図7は、積層型電子部品200の断面図である。
第3実施形態にかかる積層型電子部品300を作製した。積層型電子部品300は、図1、図2に示した第1実施形態にかかる積層型電子部品100と同じ構造からなるので、図1、図2を援用して説明する。
図8に、第4実施形態にかかる積層型電子部品400を示す。ただし、図8は、積層型電子部品400の断面図である。
図9に、第5実施形態にかかる積層型電子部品500を示す。ただし、図9は、積層型電子部品500の断面図である。
1a~1h・・・セラミック層
2・・・ビア電極
3・・・グランド電極
4・・・インダクタ電極
5・・・キャパシタ電極
6・・・配線電極
7・・・外部電極
8・・・凹部
9・・・シールド層
NE・・・電極非形成領域
11・・・集合基板状の未焼成積層体
11a~11h・・・マザーのセラミックグリーンシート
1’・・・未焼成積層体
1’a~1’h・・・セラミックグリーンシート
12・・・導電性ペースト
13~17・・・導電性のペーストパターン(第1のペーストパターン)
18・・・焼成により消失するペーストパターン(第2のペーストパターン)
22・・・貫通孔
51・・・下金型
52・・・上金型
53・・・固定用治具
100、200、300、400、500・・・積層型電子部品(積層型LCフィルタ)
Claims (11)
- 複数のセラミック層が積層され、底面と、天面と、前記底面と前記天面とを繋ぐ複数の側面とを備えた積層体と、
前記積層体の前記天面に形成された、マーク、文字、数字の少なくとも1種を表した少なくとも1つの凹部と、
前記積層体の層間に形成された電極と、を備えた積層型電子部品であって、
さらに、前記積層体の、前記凹部の内底面および内壁面の少なくとも一部を含む前記天面の少なくとも一部と、前記側面の少なくとも一部とに形成されたシールド層を備え、
前記積層体における、前記凹部の前記内底面の直下に、前記電極が形成されない電極非形成領域が設けられ、
前記電極非形成領域の厚みが、前記凹部の前記内底面を起点にして、前記凹部の深さ以上の大きさである、積層型電子部品。 - 前記電極非形成領域の厚みが、前記凹部の前記内底面を起点にして、前記凹部の深さの2倍以上の大きさである、請求項1に記載された積層型電子部品。
- 前記積層体の、前記凹部の前記内底面の直下に、前記電極が全く形成されていない、請求項1または2に記載された積層型電子部品。
- 前記電極非形成領域の平面方向の大きさが、前記凹部を中心にして、縦方向に1.5倍以上、横方向に1.5倍以上、それぞれ拡張された、請求項1ないし3のいずれか1項に記載された積層型電子部品。
- 前記電極が、インダクタ電極、キャパシタ電極、配線電極、グランド電極の少なくとも1種である、請求項1ないし4のいずれか1項に記載された積層型電子部品。
- 前記キャパシタ電極によって少なくとも1つのキャパシタが構成され、前記インダクタ電極によって少なくとも1つのインダクタが構成され、
前記キャパシタと前記インダクタとによって、LCフィルタ回路が構成された、請求項5に記載された積層型電子部品。 - 複数のセラミックグリーンシートを用意する工程と、
複数の前記セラミックグリーンシートのうち、少なくともひとつの一方の主面、または両方の主面に、導電性ペーストを塗布して、第1のペーストパターンを形成する工程と、
複数の前記セラミックグリーンシートを所定の順番に積層し、集合基板状の未焼成積層体を作製する工程と、
集合基板状の前記未焼成積層体の天面に、焼成により消失するペーストを塗布し、マーク、文字、数字の少なくとも1種を表す、一定の厚みを備えた第2のペーストパターンを形成する工程と、
前記第2のペーストパターンを、集合基板状の前記未焼成積層体の天面に押込み、集合基板状の前記未焼成積層体の前記天面を平坦にする工程と、
集合基板状の前記未焼成積層体を、個片化された前記未焼成積層体にカットする工程と、
個片化された前記未焼成積層体を、所定のプロファイルで焼成し、同時に前記第2のペーストパターンを消失させ、複数のセラミック層が積層され、底面と、天面と、前記底面と前記天面とを繋ぐ複数の側面とを備え、天面に少なくとも1つの凹部が形成された積層体を作製する工程と、
前記積層体の、前記凹部の内底面および内壁面の少なくとも一部を含む前記天面の少なくとも一部と、前記側面の少なくとも一部とに、シールド層を形成する工程と、を備えた、積層型電子部品の製造方法。 - 複数のセラミックグリーンシートを用意する工程と、
複数の前記セラミックグリーンシートのうち、少なくともひとつの一方の主面、または両方の主面に、導電性ペーストを塗布して、第1のペーストパターンを形成する工程と、
複数の前記セラミックグリーンシートのうちの、最上層に積層されるものの上側の主面に、焼成により消失するペーストを塗布し、マーク、文字、数字の少なくとも1種を表す、一定の厚みを備えた第2のペーストパターンを形成する工程と、
複数の前記セラミックグリーンシートを所定の順番に積層し、集合基板状の未焼成積層体を作製する工程と、
前記第2のペーストパターンを、集合基板状の前記未焼成積層体の天面に押込み、集合基板状の前記未焼成積層体の前記天面を平坦にする工程と、
集合基板状の前記未焼成積層体を、個片化された前記未焼成積層体にカットする工程と、
個片化された前記未焼成積層体を、所定のプロファイルで焼成し、同時に前記第2のペーストパターンを消失させ、複数のセラミック層が積層され、底面と、天面と、前記底面と前記天面とを繋ぐ複数の側面とを備え、天面に少なくとも1つの凹部が形成された積層体を作製する工程と、
前記積層体の、前記凹部の内底面および内壁面の少なくとも一部を含む前記天面の少なくとも一部と、前記側面の少なくとも一部とに、シールド層を形成する工程と、を備えた、積層型電子部品の製造方法。 - 複数のセラミックグリーンシートを用意する工程と、
複数の前記セラミックグリーンシートのうち、少なくともひとつの一方の主面、または両方の主面に、導電性ペーストを塗布して、ペーストパターンを形成する工程と、
複数の前記セラミックグリーンシートを所定の順番に積層し、集合基板状の未焼成積層体を作製する工程と、
集合基板状の前記未焼成積層体の天面に、レーザー光を照射して、マーク、文字、数字の少なくとも1種を表す、少なくとも1つの凹部を形成する工程と、
集合基板状の前記未焼成積層体を、個片化された前記未焼成積層体にカットする工程と、
個片化された前記未焼成積層体を、所定のプロファイルで焼成し、複数のセラミック層が積層され、底面と、天面と、前記底面と前記天面とを繋ぐ複数の側面とを備え、天面に少なくとも1つの凹部が形成された積層体を作製する工程と、
前記積層体の、前記凹部の内底面および内壁面の少なくとも一部を含む前記天面の少なくとも一部と、前記側面の少なくとも一部とに、シールド層を形成する工程と、を備えた、積層型電子部品の製造方法。 - 複数のセラミックグリーンシートを用意する工程と、
複数の前記セラミックグリーンシートのうち、少なくともひとつの一方の主面、または両方の主面に、導電性ペーストを塗布して、ペーストパターンを形成する工程と、
複数の前記セラミックグリーンシートを所定の順番に積層し、集合基板状の未焼成積層体を作製する工程と、
集合基板状の前記未焼成積層体の天面に、金型の内天面に形成された凸部を押込み、マーク、文字、数字の少なくとも1種を表す、少なくとも1つの凹部を形成する工程と、
集合基板状の前記未焼成積層体を、個片化された前記未焼成積層体にカットする工程と、
個片化された前記未焼成積層体を、所定のプロファイルで焼成し、複数のセラミック層が積層され、底面と、天面と、前記底面と前記天面とを繋ぐ複数の側面とを備え、天面に少なくとも1つの凹部が形成された積層体を作製する工程と、
前記積層体の、前記凹部の内底面および内壁面の少なくとも一部を含む前記天面の少なくとも一部と、前記側面の少なくとも一部とに、シールド層を形成する工程と、を備えた、積層型電子部品の製造方法。 - 作製された前記積層体の、前記凹部の前記内底面の直下に、電極が形成されない電極非形成領域が設けられ、
前記電極非形成領域の厚みが、前記凹部の前記内底面を起点にして、前記凹部の深さ以上の大きさである、請求項7ないし10のいずれか1項に記載された積層型電子部品の製造方法。
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JP6863458B2 (ja) | 2021-04-21 |
CN110574131B (zh) | 2022-05-17 |
US20200082990A1 (en) | 2020-03-12 |
JPWO2018212119A1 (ja) | 2020-03-12 |
CN110574131A (zh) | 2019-12-13 |
KR20190100393A (ko) | 2019-08-28 |
US11152157B2 (en) | 2021-10-19 |
KR102267242B1 (ko) | 2021-06-21 |
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