WO2018188285A1 - 移位寄存器单元、栅极驱动电路及其驱动方法 - Google Patents

移位寄存器单元、栅极驱动电路及其驱动方法 Download PDF

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Publication number
WO2018188285A1
WO2018188285A1 PCT/CN2017/104812 CN2017104812W WO2018188285A1 WO 2018188285 A1 WO2018188285 A1 WO 2018188285A1 CN 2017104812 W CN2017104812 W CN 2017104812W WO 2018188285 A1 WO2018188285 A1 WO 2018188285A1
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Prior art keywords
pull
signal
clock signal
terminal
control
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PCT/CN2017/104812
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English (en)
French (fr)
Inventor
赵剑
王慧
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/766,659 priority Critical patent/US10872578B2/en
Publication of WO2018188285A1 publication Critical patent/WO2018188285A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/30—Image reproducers
    • H04N13/356—Image reproducers having separate monoscopic and stereoscopic modes
    • H04N13/359—Switching between monoscopic and stereoscopic modes

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a gate driving circuit including a multi-stage shift register unit, and a driving method thereof.
  • the gate line voltage for driving the pixels on the display panel is generated by the gate driving circuit.
  • the gate line voltage is output through the gate driving circuit, and each pixel is scanned line by line.
  • the gate driving circuit can be integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate line.
  • GOA Gate driver On Array
  • the GOA unit is used to directly form the GOA unit on the liquid crystal panel, which simplifies the process, reduces the cost, and easily realizes a narrow bezel.
  • a GOA composed of a multi-stage shift register unit can be used to provide a switching signal for each row of gate lines of the pixel array, thereby controlling the plurality of rows of gate lines to be sequentially turned on, and inputting display data from the data lines to pixels of corresponding rows in the pixel array.
  • the signal is formed to form a gray voltage required for each gray scale of the displayed image, thereby displaying each frame of the image.
  • 3D (Three-Dimensional) display is increasingly favored by consumers in the market.
  • 3D shutter display technology has higher resolution, lower cost and better stereo effect.
  • Other advantages are widely recognized in the market.
  • the 3D shutter display technology also has certain disadvantages. For example, due to the influence of the response time of the liquid crystal, crosstalk occurs (the previous frame remains to the next frame, resulting in ghosting).
  • a black insertion technique is generally used between the left and right eye signals to reduce the crosstalk phenomenon. Since the 3D shutter type display technology alternately receives signals from left and right eyes, the frame rate required for display is high, and generally requires 120 Hz. With black insertion technology, the frame rate needs to be doubled or higher.
  • the use of high frequency driving has a great influence on the charging saturation of the liquid crystal panel, and requires great changes to the gate integrated circuit, increasing design difficulty and system complexity.
  • the present disclosure proposes a shift register unit, a gate drive circuit including a multi-stage shift register unit, and a driving method thereof.
  • a shift register unit comprising: an input sub-circuit between a connection signal input terminal and a pull-up node, configured to pull up a node input signal; and an output sub-circuit connected to The pull node and the signal output end are configured to output a pulse signal to the signal output end under the control of the pull-up node; the reset sub-circuit is connected between the reset end, the pull-up node and the signal output end, and is configured to Under the control of the reset terminal, resetting the pull-up node and the signal output terminal; and the clock signal selection sub-circuit, the input end of which is connected to the first clock signal end and the second clock signal end, and the first output end is connected to the output sub-circuit And configured to select whether to provide the first clock signal or the second clock signal to the output sub-circuit according to the levels of the first control terminal and the second control terminal.
  • a gate driving circuit including N stages of shift register units as described above, wherein the kth stage shift register unit is configured to scan a corresponding gate line,
  • the signal output terminal is connected to the signal input terminal of the k+1th stage shift register unit via a first switching transistor corresponding to the kth stage, and is also connected to the k+2th stage via a second switching transistor corresponding to the kth stage a signal input terminal of the shift register unit, wherein k ⁇ 3;
  • the kth stage shift register unit signal input terminal is connected to the signal output end of the k-1th stage shift register unit via a third switching transistor corresponding to the kth stage And is also connected to the output of the k-2th stage shift register unit via a fourth switching transistor corresponding to the kth stage.
  • a method for applying the above-described gate driving circuit comprising: inputting a second level to a first switching control line and a second switching control line in a 2D display mode Inputting a first level, thereby turning on a first switching transistor disposed between adjacent two stages of GOA units and turning off a second switching transistor disposed between two stages of GOA units at an intermediate interval level;
  • the control line and the third control line input the second level, and input the first level to the second control line and the fourth control line, so that the clock signals of the selected output of the adjacent two-stage GOA units are respectively the first clock a signal and a second clock signal; inputting a frame revelation signal to a signal input end of the first stage dummy shift register unit, and inputting the first clock signal and the second clock signal to the first clock of the first stage dummy shift register unit
  • the signal end and the second clock signal end enable the scan shift registers of each stage to sequentially sequentially output drive signals to the connected gate lines.
  • the method further includes: inputting a first level to the first switch control line and a second level to the second switch control line in the 3D display mode, thereby being disposed in the adjacent two-stage GOA unit
  • the first switching transistor is turned off, and the second switching transistor disposed between the two stages of the GOA unit at the intermediate interval level is turned on;
  • the second level is input to the first control line and the fourth control line, and
  • the second control line and the third control line are input to the first level;
  • the frame revelation signal is input to the first level and the second level a signal input end of the dummy shift register unit, respectively inputting the first clock signal and the second clock signal to the first clock signal end and the second clock signal end of the first stage dummy shift register unit, so that each adjacent two
  • the timing of the signals received by the signal input terminals of the stage shift register unit is the same, and the timing of the output signals is the same.
  • the first level is a low level and the second level is a high level.
  • switching transistors are provided between the shift register units of the stages, and the respective switching transistors are controlled by the respective control lines so that in 2D In the display mode and in the 3D display mode, the connection mode of each shift register unit is changed, thereby realizing that the display panel can be freely switched in two different display modes of 2D and 3D, and the double gate line can be realized in the 3D display.
  • the simultaneous scanning reduces the scanning frequency, reduces the influence of the high-frequency scanning signal on the charging of the display panel, and does not require additional design, thereby effectively reducing the product cost.
  • FIG. 1 illustrates a block diagram of a shift register unit in accordance with an embodiment of the present disclosure
  • FIG. 2 illustrates a specific circuit structure of a shift register unit in accordance with an embodiment of the present disclosure
  • FIG. 3 illustrates a signal timing that can be used with the shift register unit shown in FIG. 2, in accordance with an embodiment of the present disclosure
  • FIG. 4 illustrates a schematic structure of a gate driving circuit including a multi-stage shift register unit, according to an embodiment of the present disclosure
  • FIG. 5 illustrates signal timings employed when the 2D display driving is performed by the gate driving circuit illustrated in FIG. 4 according to an embodiment of the present disclosure
  • FIG. 6 illustrates signal timings employed when the 3D display driving is performed by the gate driving circuit illustrated in FIG. 4 according to an embodiment of the present disclosure
  • FIG. 7 illustrates a schematic flow of a method applied to the gate driving circuit illustrated in FIG. 4 according to an embodiment of the present disclosure
  • FIG. 8 illustrates a schematic flow of another method applied to the gate driving circuit illustrated in FIG. 4 according to an embodiment of the present disclosure.
  • FIG. 1 illustrates a block diagram of a shift register unit in accordance with an embodiment of the present disclosure.
  • the shift register unit includes: an input sub-circuit 101, between the connection signal input terminal INPUT and the pull-up node PU, configured to pull up the node input signal; and the output sub-circuit 102 connected to the pull-up node Between the PU and the signal output terminal OUTPUT, configured to output a pulse signal to the signal output terminal OUTPUT under the control of the pull-up node PU; the reset sub-circuit 103 is connected to the reset terminal RESET, the pull-up node PU, and the signal output terminal OUTPUT Between, is configured to reset the pull-up node PU and the signal output terminal OUTPUT under the control of the reset terminal RESET; and the clock signal selection sub-circuit 104 whose input terminal is connected to the first clock signal terminal CLK1 and the second clock The signal terminal CLK2, the first output terminal is connected to the output sub-circuit 102,
  • the shift register unit according to the present disclosure further includes a pull-down node control sub-circuit 105 connected to the second output of the pull-up node PU and the clock signal selection sub-circuit 104, configured The level of the pull-down node is controlled to select the level of the first clock signal or the second clock signal provided by the sub-circuit 104 and the pull-up node PU according to the clock signal.
  • a pull-down node control sub-circuit 105 connected to the second output of the pull-up node PU and the clock signal selection sub-circuit 104, configured The level of the pull-down node is controlled to select the level of the first clock signal or the second clock signal provided by the sub-circuit 104 and the pull-up node PU according to the clock signal.
  • the shift register unit according to the present disclosure further includes a pull-down sub-circuit 106 connected to the pull-down node, the pull-up node, and the signal output, configured to be based on the level of the pull-down node The pull-up node and the signal output are pulled down.
  • a pull-down sub-circuit 106 connected to the pull-down node, the pull-up node, and the signal output, configured to be based on the level of the pull-down node The pull-up node and the signal output are pulled down.
  • the shift register unit according to the present disclosure further includes an auxiliary control sub-circuit 107 connected to the pull-up node PU, the signal output terminal, and the second output terminal of the clock signal selection sub-circuit 104. And configured to select a clock signal provided by the sub-circuit according to the clock signal to assist in controlling the levels of the pull-up node and the signal output.
  • an auxiliary control sub-circuit 107 connected to the pull-up node PU, the signal output terminal, and the second output terminal of the clock signal selection sub-circuit 104. And configured to select a clock signal provided by the sub-circuit according to the clock signal to assist in controlling the levels of the pull-up node and the signal output.
  • the clock signal supplied to the output sub-circuit can be selected by the clock signal selection sub-circuit, thereby outputting the corresponding pulse signal at the signal output end.
  • the clock signal can be selected by the clock signal
  • the circuit selects a clock signal provided to the pull-down node control sub-circuit and the auxiliary control sub-circuit to control the levels of the pull-down node, the pull-up node, and the signal output.
  • FIG. 2 illustrates a specific circuit structure of a shift register unit according to an embodiment of the present disclosure.
  • the input sub-circuit includes an input transistor M1 having a control electrode and a first electrode connected to the signal input terminal, and a second electrode connected to the pull-up node.
  • the output sub-circuit includes: an output transistor M3 whose control electrode is connected to the pull-up node, the first pole is connected to the first output terminal CLKOUT1 of the clock signal selection sub-circuit, and the second pole is connected to The signal output terminal OUTPUT; and the capacitor C1 have a first end connected to the pull-up node PU and a second end connected to the signal output terminal OUTPUT.
  • the reset sub-circuit includes: a first reset transistor M2 having a control electrode connected to the reset terminal RESET, a first pole connected to the pull-up node PU, and a second pole connected to the first power supply terminal VSS And a second reset transistor M4 whose control terminal is connected to the reset terminal RESET, the first electrode is connected to the signal output terminal OUTPUT, and the second electrode is connected to the first power supply terminal VSS.
  • the clock signal selection sub-circuit includes: a first selection transistor T1 having a control electrode connected to the first control terminal CLR1, a first electrode connected to the first clock signal terminal CLK1, and a second pole connection a first output terminal CLKOUT1 to the clock signal selection sub-circuit; a second selection transistor T2 whose control electrode is connected to the second control terminal CLR2, the first electrode is connected to the second clock signal terminal CLK2, and the second electrode is connected to the first selection The second pole of transistor T1.
  • the clock signal selection sub-circuit further includes: a third selection transistor T3 having a control electrode connected to the first control terminal CLR1, a first electrode connected to the second clock signal terminal CLK2, and a second pole Connected to the second output terminal CLKOUT2 of the clock signal selection sub-circuit 104; the fourth selection transistor T4, whose control electrode is connected to the second control terminal CLR2, the first electrode is connected to the first clock signal terminal CLK1, and the second electrode is connected to the second terminal Three selects the second pole of transistor T3.
  • a third selection transistor T3 having a control electrode connected to the first control terminal CLR1, a first electrode connected to the second clock signal terminal CLK2, and a second pole Connected to the second output terminal CLKOUT2 of the clock signal selection sub-circuit 104
  • the fourth selection transistor T4 whose control electrode is connected to the second control terminal CLR2, the first electrode is connected to the first clock signal terminal CLK1, and the second electrode is connected to the second terminal Three selects the second pole of transistor T3.
  • the pull-down node control sub-circuit includes: a first pull-down control transistor M9 whose control pole and the first pole are connected to the second output terminal CLKOUT2 of the clock signal selection sub-circuit, and the second pole is connected To the pull-down control node PD_CN; the second pull-down control transistor M5, whose control electrode is connected to the pull-down control node PD_CN, the first pole is connected to the first pole of the first pull-down control transistor M9, and the second pole is connected to the pull-down node PD; a three pull-down control transistor M8 having a control electrode connected to the pull-up node PU, a first pole connected to the pull-down control node PD_CN, a second pole connected to the first power supply terminal VSS, and a fourth pull-down control transistor M6 having a control terminal connected thereto
  • the pull-up node PU has a first pole connected to the pull-down node PD and a second pole connected to the first power supply
  • the pull-down sub-circuit includes: a first pull-down transistor M10 having a control electrode connected to the pull-down node PD, a first pole connected to the pull-up node PU, and a second pole connected to the first power terminal VSS; and a second pull-down transistor M11 whose control electrode is connected to the pull-down node PD, the first pole is connected to the signal output terminal OUTPUT, and the second pole is connected to the first power supply terminal VSS.
  • the auxiliary control sub-circuit 107 includes: a first auxiliary control transistor M13 whose control electrode is connected to the second output terminal CLKOUT2 of the clock signal selection sub-circuit, and the first electrode is connected to the signal input terminal INPUT a second pole connected to the pull-up node PU; and a second auxiliary control transistor M12 whose control electrode is connected to the second output terminal CLKOUT2 of the clock signal selection sub-circuit, the first pole is connected to the signal output terminal OUTPUT, and the second pole is connected Go to the first power terminal VSS.
  • each of the above transistors may adopt a TFT transistor, wherein a gate of the transistor is a gate, a first pole is a drain, and a second pole is a source.
  • a gate of the transistor is a gate
  • a first pole is a drain
  • a second pole is a source.
  • the source and drain of the transistor used herein are symmetrical, the source and the drain are interchangeable.
  • one of the poles may be referred to as a source and the other pole may be referred to as a drain. If the source is selected as the signal input, the drain acts as the signal output and vice versa.
  • the first power supply terminal is shown as being connected to the low level VSS.
  • the first power supply terminal can be connected to different low levels, such as low levels VSS and VGL having different voltage values.
  • a low level connected to a transistor for pulling down the output of the shift register unit can be connected to a low level VGL
  • a low level to a pull-up node for a pull-down shift register unit can be connected to a low level VSS.
  • the level of VGL is lower than the level of VSS.
  • the gate-source potential of the output transistor of the shift register unit can be reversed when both the pull-up node and the output terminal are pulled low, and the output can be guaranteed even when the output transistor uses a depletion transistor.
  • the transistor is completely turned off.
  • the operation of the shift register unit shown in Fig. 2 will be briefly explained below with reference to the signal timing illustrated in Fig. 3.
  • the first control terminal CLR1 is at a high level
  • the second control terminal CLR2 is at a low level as an example to describe a, b, c, d, and e of the shift register unit in the timing chart shown in FIG. Five phases of operation.
  • the first control terminal CLR1 is at a high level
  • the second control terminal CLR2 is at a low level
  • the first selection transistor T1 and the third selection transistor T3 in the clock signal selection sub-circuit are turned on
  • the second selection transistor T2 and the fourth Select transistor T4 is turned off to provide a first clock signal CLKA to the first output of the clock signal selection sub-circuit and a second clock signal CLKB to the second output of the clock signal selection sub-circuit.
  • the periods of the first clock signal CLKA and the second clock signal CLKB are equal, the duty ratio is 50%, and the phases are 180 degrees out of phase.
  • the input signal of the signal input terminal INPUT is at a high level
  • the first clock signal CLKA is at a low level
  • the second clock signal CLKB is at a high level
  • the transistor M1 is turned on, so that a high level
  • the input signal charges the pull-up node PU; since the second clock signal CLKB is at a high level, the transistor M13 is turned on to accelerate the charging process of the pull-up node PU; thereby, the pull-up node PU is charged to the first high level
  • the output transistor M3 is turned on, and outputs a low-level clock signal CLKA to the signal output terminal; the transistor M9 is turned on to charge the pull-down control node PD_CN, however, since the pull-up node PU is at the first high level, the transistors M6 and M8 are turned on;
  • the size ratio of the transistors M8 and M9 can be configured such that when both M9 and M8 are turned on, the level of the pull-down control
  • Transistor M5 remains off; since transistor M6 is turned on, the level of pull-down node PD is pulled low, so that transistors M10 and M11 are in an off state at this stage; since CLKB is high, transistor M12 is on, It can be ensured that the output of the shift register unit is pulled low to VSS;
  • the first clock signal CLKA is at a high level
  • the second clock signal CLKB is at a low level
  • the signal input to the signal input terminal INPUT is at a low level
  • the transistors M1, M13, M9, M5, and M12 are off.
  • the output transistor M3 remains on, and the high-level clock signal CLKA is output as a pulse signal; due to the bootstrap effect of the storage capacitor C1, the level of the pull-up node PU further rises to reach the second high level, The conduction of the output transistor M3 is more sufficient; since the level of the pull-up node PU is raised relative to the level of the stage a, the conduction of the transistors M8 and M6 is more sufficient, and the pull-down control node PD_CN and the pull-down node PD are further pulled down, respectively. Since the pull-down node PD is at a low level, the transistors M10 and M11 remain in an off state, thereby not affecting the output pulse signal of the shift register unit;
  • the first clock signal CLKA is at a low level
  • the second clock signal CLKB is at a high level
  • the signal input terminal INPUT continues to be connected to a low level
  • the reset terminal RESET is connected to a high level
  • the transistors M2 and M4 are turned on, and the output terminals of the pull-up node PU and the shift register unit are respectively pulled down to the low level VSS; while the transistor M1 is turned off, the transistor M13 is turned on, and the low level is connected.
  • the level is such that the transistor M3 is turned off; since the second clock signal CLKB is at a high level, the transistor M12 is turned on, pulling the output terminal of the shift register unit to the low level VSS; the transistor M9 is turned on, and the pull-down control node PD_CN is charged.
  • the transistor M5 is turned on, thereby charging the pull-down node PD; since the pull-up node PU is at a low level, the transistors M6 and M8 are turned off; the pull-down node PD is charged to a high level, and the transistors M10 and M11 are turned on, respectively Pulling the output of the node PU and the shift register unit to a low level VSS;
  • the first clock signal CLKA is at a high level
  • the second clock signal CLKB is at a low level
  • the signal input terminal INPUT continues to be connected to a low level
  • the reset terminal is connected to a low level
  • the transistors M1, M13 , M2, M4, M9 and M12 are turned off
  • the pull-up node PU is kept low
  • the transistors M6 and M8 continue to be turned off
  • the discharge path of the pull-down control node PD_CN is turned off, pull-down control
  • the node PD_CN maintains the previous high level, so that the transistor M5 remains on, and since the second clock signal CLKB is at a low level, the pull-down node PD is discharged.
  • the first clock signal CLK is at a low level
  • the second clock signal CLKB is at a high level
  • the input terminal INPUT continues to be connected to a low level
  • the reset terminal is connected to a low level
  • the transistors M1, M2 M4 is turned off
  • transistor M13 is turned on, and the low level is connected to the pull-up node PU, and the pull-up node PU is discharged to ensure that the transistor M3 is turned off
  • CLKB is at a high level
  • the transistor M12 is turned on, and the output of the shift register unit is turned off.
  • transistor M9 is turned on, charging the pull-down control node PD_CN, making transistor M5 more fully enabled, and charging the pull-down node PD, causing the pull-down node PD to become High level; due to the pull-up node PU being discharged, transistors M6 and M8 remain off; the high level of the pull-down node PD causes transistors M10 and M11 to be turned on, respectively pulling down the output of the pull-up node PU and the shift register unit To low VSS, the noise formed at the pull-up node and the output is eliminated.
  • the shift register unit repeats the operations of stages d and e until the next valid input signal arrives.
  • a gate driving circuit including a plurality of stages of the above-described shift register unit (GOA unit) is proposed.
  • Fig. 4 shows a schematic structure of the gate driving circuit.
  • the gate driving circuit includes a plurality of GOA units, wherein a plurality of GOA units are divided into There are roughly four kinds, that is, the first level Dummy GOA 1, the second level Dummy GOA 2, the odd level scan GOA 2N+1 (N ⁇ 0, N is an integer), and the even level scan GOA 2N+ 2 (N ⁇ 0, N is an integer).
  • the internal structure of each GOA unit is as shown in FIG. 2, and specifically includes sixteen TFTs and one capacitor.
  • the Dummy GOA 1 and the Dummy GOA 2 are mainly responsible for signal activation, and function as a signal for the opening of the subsequent GOA unit, and are not responsible for providing control of the gate line scanning of the active area of the display panel.
  • the signal input terminal INPUT of the Dummy GOA 1 is connected to the STV signal, and the signal output terminal of the Dummy GOA 1 is connected to the signal input terminal of the Dummy GOA 2 via the first switching transistor SW1 corresponding to the Dummy GOA 1, and via The second switching transistor SW2 corresponding to the Dummy GOA 1 is connected to the signal input terminal of the first-stage scan GOA 1; the reset terminal of the Dummy GOA 1 is connected to the signal output of the Dummy GOA 2 via the third switching transistor SW3 corresponding to the Dummy GOA 1 And connected to the signal output end of the first-stage scan GOA 1 via the fourth switch transistor SW4 corresponding to the Dummy GOA 1; the first control terminal of the Dummy GOA 1 is connected to the first control line CTR1, and the second control terminal is connected To the second control line CTR2, the control electrode of the first switching transistor SW1 is connected to the first switching control line SCL1, the control electrode of the second switching transistor SW2 is connected to the second switching control line SCL2, and
  • the signal input terminal INPUT of the Dummy GOA 2 is connected to the STV signal via the fifth switching transistor SW5 corresponding to the Dummy GOA 2, and the signal output terminal of the Dummy GOA 2 is connected to the first level scanning via the sixth switching transistor SW6 corresponding to the Dummy GOA 2 a signal input terminal of the GOA 1, and connected to a signal input terminal of the second-stage scan GOA 2 via a seventh switching transistor SW7 corresponding to the Dummy GOA 2; a reset terminal of the Dummy GOA 2 is directly connected to the signal of the first-stage scan GOA 1
  • the output terminal; the first control terminal of the Dummy GOA 2 is connected to the third control line CTR3, the second control terminal thereof is connected to the fourth control line CTR4, and the control electrode of the fifth switching transistor SW5 is connected to the second switch control line SCL2,
  • the control electrode of the six-switch transistor SW6 is connected to the first switch control line SCL1, the control electrode of the seventh switch transistor SW7 is connected to the second switch control line SCL2,
  • the signal output terminal is connected to the corresponding gate line GL1 in addition to the reset terminals of Dummy GOA 1 and Dummy GOA 2, and is used as a gate line.
  • GL1 provides a scan signal to drive a corresponding pixel sub-circuit on the display panel;
  • the signal output of the first-stage scan GOA 1 is also connected to the second-level scan via an eighth switch transistor SW8 corresponding to the first-stage scan GOA 1 a signal input terminal of the GOA 2, and connected to a signal input terminal of the third-stage scan GOA 3 via a ninth switching transistor SW9 corresponding to the first-stage scan GOA 1; a reset stage of the first-stage scan GOA 1 via the first stage
  • the tenth switching transistor SW10 corresponding to the scan GOA 1 is connected to the signal output terminal of the second-stage scan GOA 2, and is connected to the signal of the third-stage scan GOA 3 via the eleventh switching transistor SW11 corresponding to the first-stage scan GOA 1
  • the signal output terminal is connected to the corresponding gate line GL2 in addition to the reset terminal of the first-stage scan GOA 1, for the gate line GL2.
  • the signal output end of the second-stage scan GOA 2 is also connected to the third-level scan via the twelfth switch transistor SW12 corresponding to the second-stage scan GOA 2 a signal input terminal of the GOA 3, and connected to the signal input terminal of the fourth-stage scan GOA 4 via a thirteenth switching transistor SW13 corresponding to the second-stage scan GOA 2;
  • the reset terminal of the second-stage scan GOA 2 is directly connected to the
  • the third stage scans the signal output end of the GOA 3;
  • the first control end of the second stage scan GOA 2 is connected to the first control line CTR1, the second control end thereof is connected to the second control line CTR2, and the control of the twelfth switching transistor SW12
  • the input signal of the Dummy GOA 1 sub-circuit has only one source from the frame start signal STV; the source of the reset signal has two sources, and the output of the successive two-stage GOA, that is, the Dummy GOA 2 sub-circuit and The output of the first scan GOA1 sub-circuit; the input signal of the Dummy GOA 2 sub-circuit has two sources, the STV signal and the previous stage GOA unit (ie Dummy) The output of the GOA 1 sub-circuit), and the reset signal of the Dummy GOA 2 sub-circuit has only one source, that is, the output from the previous stage GOA unit, that is, the output of the first scan GOA 1 sub-circuit.
  • the input signal of the scanning GOA unit for example, the first scan GOA1 and the second scan GOA2 sub-circuit shown in FIG. 4, there are two sources of input signals from the output of the previous two consecutive stages of GOA units; for example, the first The input signal of the scan GOA1 sub-circuit is derived from the outputs of the Dummy GOA 1 sub-circuit and the Dummy GOA 2 sub-circuit, and the input signal of the second scan GOA2 sub-circuit is derived from the output of the Dummy GOA 2 sub-circuit and the first scan GOA 1 sub-circuit.
  • the reset signal of the scanning GOA unit for example, there are two sources of the reset signal of the first scan GOA1 shown in FIG. 4, that is, the output of the subsequent two-stage GOA unit, that is, the outputs of GOA2 and GOA3;
  • the source of the reset signal of the second scan GOA2 has one, that is, the output of the successive first-order GOA unit, that is, the output of GOA3.
  • the source of the input and reset signals of the subsequent GOA units is deduced by analogy.
  • the source of the input signal is the output of the previous two consecutive stages of GOA units, ie the outputs of the GOA K-1 sub-circuit and the GOAK-2 sub-circuit
  • the source of the reset signal is the output of the subsequent two consecutive stages of GOA units, namely the outputs of GOA K+1 and GOAK+2.
  • the source of the input signal is the output of the previous two consecutive GOA units, ie the outputs of GOA K-1 and GOA K-2
  • the source of the reset signal is The output of successive successive levels of GOA units, ie the output of the GOA K+1 sub-circuit.
  • the clock signals connected to the first clock signal terminal and the second clock signal terminal of the clock signal selection sub-circuit in the odd-numbered and even-numbered GOAs are alternately switched with each other, for example, an odd-numbered stage.
  • the first clock signal end of the clock signal selection sub-circuit in the GOA receives the first clock signal CLKA
  • the second clock signal end receives the second clock signal CLKB
  • the first clock signal end of the even-numbered stage GOA receives the second clock signal CLKB
  • the second clock signal terminal receives the first clock signal CLKA.
  • different display modes of the display panels 2D and 3D can be freely switched by setting corresponding control lines in the GOA area and using a certain number of TFT switches.
  • the double gate line is simultaneously turned on in the 3D display, which can reduce the influence of high frequency on the charging of the display panel. No additional design is required to effectively reduce costs.
  • Dummy GOA1, scanning GOA unit that is, GOA2, GOA3, GOA6, GOA7, GOA10, GOA11, ... Clock signal selection in GOA 4N+2, GOA 4N+3 (N ⁇ 0, N is an integer)
  • the first control end of the path is connected to the first control line CTR1, the second control end is connected to the second control line CTR2;
  • Dummy GOA2, scanning GOA unit ie, GOA1, GOA4, GOA5, GOA8, GOA9, GOA12...
  • the first control terminal of ... GOA 4N+1, GOA 4N+4 (N ⁇ 0, N is an integer) is connected to the third control line CTR3, and the second control terminal thereof is connected to the fourth control line CTR4.
  • the gate driving circuit provided by the present disclosure includes N stages of shift register units as shown in FIG. 2, wherein the kth stage shift register unit is configured to scan corresponding gate lines, and the signal output ends thereof a first switching transistor corresponding to the kth stage is connected to a signal input terminal of the k+1th stage shift register unit, and is also connected to the k+2th stage shift register unit via a second switching transistor corresponding to the kth stage Signal input terminal, where k ⁇ 3, N and k are integers; the kth stage shift register unit signal input terminal is connected to the signal of the k-1th stage shift register unit via a third switching transistor corresponding to the kth stage The output terminal is also connected to the output of the k-2th stage shift register unit via a fourth switching transistor corresponding to the kth stage.
  • the first stage and the second stage shift register unit are configured as a dummy shift register unit; wherein the signal output end of the first stage shift register unit is connected to the first stage The corresponding first switching transistor is connected to the signal input end of the second stage shift register unit, and the signal input end of the first stage shift register unit receives the frame start signal STV; the signal input end of the second stage shift register unit The frame start signal STV is also received via the second switching transistor corresponding to the second stage.
  • the reset end of the 2j-1th stage shift register unit is connected to the signal output of the 2jth stage shift register unit via the fifth switching transistor corresponding to the 2j-1th stage. And connected to the signal output end of the 2j+1th stage shift register unit via a sixth switching transistor corresponding to the 2j-1th stage; the reset end of the 2jth stage shift register unit is connected to the 2j+1 The signal output of the stage shift register unit, where 1 ⁇ j ⁇ (N-1) /2, j is an integer.
  • the odd-numbered GOA units and the even-numbered GOA units in the gate driving circuit of the embodiment of the present disclosure The control principle is slightly different.
  • the operation principle when the gate driving circuit according to the embodiment of the present disclosure performs 2D display driving will be first described below in conjunction with the signal timing shown in FIG. 5.
  • the first switch control line SCL1 provides a high level
  • the second switch control line SCL2 provides a low level
  • the first control line CTR1 and the third control line CTR3 provides a high level
  • the second control line CTR2 and the fourth control line CTR4 provide Low level.
  • the switching transistor disposed between the adjacent two-stage GOA units Since the control electrode of the switching transistor disposed between the adjacent two-stage GOA units is connected to the first switching control line SCL1, the switching transistor disposed between the adjacent two-stage GOA units is turned on, thereby bringing the adjacent two-stage GOA The signal path of the unit is turned on; specifically, the output signal of the Dummy GOA1 can be supplied to the signal input terminal of the Dummy GOA 2 via the turned-on switching transistor SW1, and the output signal of the Dummy GOA 2 can be supplied to the Dummy via the turned-on switching transistor SW3.
  • the reset terminal of GOA 1 similarly, the output signal of Dummy GOA2 can be supplied to the signal input terminal of the first-stage scan GOA1 via the turned-on switching transistor SW6, and the output signal of the first-stage scan GOA 1 can be directly supplied to Dummy GOA 2
  • the reset signal of the first stage scan GOA1 can also be supplied to the signal input terminal of the second stage scan GOA 2 via the turned-on switching transistor SW8, and the output signal of the second stage scan GOA 2 can be turned on via the open switch transistor SW10 is supplied to the reset terminal of the first-stage scan GOA 1; in addition, due to the arrangement between the two-stage GOA units at the intermediate interval level
  • the control electrode of the switching transistor is connected to the second switch control line SCL2, thereby cutting off the signal path of the two-stage GOA unit of the intermediate interval level; specifically, since the switching transistor SW2 is turned off, the signal output end of the Dummy GOA1 is The signal path between the signal inputs of the primary scan GOA1 is cut off; since the switching transistor SW
  • the switching transistor SW5 since the second switch control line SCL2 is supplied with a low level, the switching transistor SW5 whose control electrode is connected to the second switch control line SCL2 is turned off, that is, the signal path between the signal input terminal of the Dummy GOA2 and the STV signal is cut off. .
  • each level of the GOA unit when the STV signal is input, the scanning GOA units of each level are triggered by the output signal of the GOA unit of the previous stage to drive the corresponding gate lines, and the GOA of each level The output signal of the unit is provided as a reset signal to the upper level GOA unit.
  • the working principle of each level of the GOA unit can be referred to the working principle of the shift register unit described above in connection with FIG. 2 and FIG. 3, and details are not described herein again.
  • the clock signal selection sub-circuit selection portion thereof A clock signal CLKA is output at its first output and a second clock signal CLKB is selected for output at its second output.
  • the first control terminal of the clock signal selection sub-circuit in the Dummy GOA 2 is connected to the third control line CTR3
  • the second control terminal thereof is connected to the fourth control line CTR4, wherein the clock signal selection sub-circuit selects the second The clock signal CLKB is output at its first output and the first clock signal CLKA is selected for output at its second output.
  • the first control terminal of the clock signal selection sub-circuit in the first scan GOA 1 is connected to the third control line CTR3
  • the second control terminal thereof is connected to the fourth control line CTR4, wherein the clock signal selection sub-circuit selection
  • the first clock signal CLKA is output at its first output
  • the second clock signal CLKB is selected for output at its second output.
  • the clock signal selection sub-circuit selects the second clock signal CLKB at Its first output is output and the first clock signal CLKA is selected for output at its second output.
  • stages scan the clock signal of the GOA to select the clock signal selected by the sub-circuit, and so on. For details, refer to the timing of the output signals of the GOA units of each stage as schematically shown in FIG.
  • the double gate line needs to be turned on at the same time.
  • the operation principle when the gate driving circuit performs 3D display driving according to an embodiment of the present disclosure will be described below in conjunction with the signal timing schematically shown in FIG. 6.
  • the first switch control line SCL1 provides a low level
  • the second switch control line SCL2 provides a high level
  • the first control line CTR1 and the fourth control line CTR4 provides a high level
  • the second control line CTR2 and the third control line CTR3 provide a low level.
  • the switching transistor disposed between the adjacent two-stage GOA units Since the gate electrode of the switching transistor disposed between the adjacent two-stage GOA units is connected to the first switch control line SCL1, the switching transistor disposed between the adjacent two-stage GOA units is turned off, thereby adjacent two The GOA unit is cut off via the signal path of the switching transistor; specifically, the signal path between the signal output of Dummy GOA1 and the signal input of Dummy GOA2 is cut off, and the signal output of Dummy GOA 2 is reset with Dummy GOA 1
  • the signal path between the ends is cut off; similarly, the signal output of Dummy GOA2 and the first stage scan GOA 1
  • the signal path between the signal inputs is cut off, and the output signal of the first stage scan GOA 1 can be directly supplied to the reset terminal of the Dummy GOA 2; the first stage scans the signal output of the GOA1 and the second stage scans the GOA 2
  • the signal path between the signal inputs is cut off, and the signal path between the signal output of the second stage scan GOA
  • the gate electrode of the switching transistor disposed between the two-stage GOA cells at the intermediate interval level is connected to the second switch control line SCL2, it is turned on, thereby guiding the signal path of the two-stage GOA unit of the intermediate interval one.
  • the switching transistor SW2 since the switching transistor SW2 is turned on, the signal path between the signal output terminal of the Dummy GOA1 and the signal input terminal of the first-stage scan GOA1 is turned on; since the switching transistor SW4 is turned on, the reset terminal of the Dummy GOA1 The signal path between the signal output of the first stage scan GOA1 is turned on; similarly, since the switch transistor SW7 is turned on, the signal path between the signal output of the Dummy GOA2 and the signal input of the second stage scan GOA2 Being turned on; since the switching transistor SW9 is turned on, the signal path between the signal output end of the first stage scan GOA1 and the signal input end of the third stage scan GOA3 is turned on; since the switching transistor SW11 is turned on, the first stage scan The signal path between the reset end
  • the switching transistor SW5 since the second switch control line SCL2 is supplied with a high level, the switching transistor SW5 whose gate is connected to the second switch control line SCL2 is turned on, that is, the signal path between the signal input terminal of the Dummy GOA2 and the STV signal is turned on. .
  • the input signal terminal and the reset signal terminal of the Dummy GOA1 and the Dummy GOA2 are connected in parallel with each other, and the signals output by the Dummy GOA1 and the Dummy GOA2 serve as input signals of the first-stage scanning GOA1 and the second-stage scanning GOA2, respectively.
  • the reset ends of the first-stage scan GOA1 and the second-stage scan GOA2 are both connected to the signal output end of the third-stage scan GOA3, and the signals output by the first-stage scan GOA1 and the second-stage scan GOA2 are driven in addition to the corresponding gate lines.
  • the input signals of the third-level scan GOA3 and the second-level scan GOA4 are respectively used; the subsequent signal connection relationship of the scanned GOA is similar.
  • the working principle of the GOA unit of each level can be referred to the working principle of the shift register unit described above in connection with FIG. 2 and FIG. 3, and details are not described herein again.
  • the input signals of the Dummy GOA1 and the Dummy GOA2 both receive the STV signal as a trigger signal, and the reset terminals thereof receive the scan from the first stage.
  • the output signal of GOA 1 is used as a reset signal. Therefore, as shown in FIG. 6, the signal timings of the outputs of Dummy GOA1 and Dummy GOA2 are the same; as described above, since the first polar scan GOA1 and the second scan GOA2 respectively receive the output signals from Dummy GOA1 and Dummy GOA2 as trigger signals, And the reset end thereof receives the output signal from the third-stage scan GOA 3 as a reset signal. Therefore, as shown in FIG.
  • the signal timings output by the first-stage scan GOA1 and the second-stage scan GOA2 are the same; that is, the first The gate line corresponding to the first-level scan GOA1 and the gate line corresponding to the second-stage scan GOA2 are simultaneously turned on; similarly, the signal timings outputted by the third-stage scan GOA3 and the fourth-stage scan GOA4 are the same, and their respective gate lines are simultaneously turned on; The timing of other scan GOAs is deduced so that double gate lines are simultaneously turned on.
  • the first control line CTR1 and the fourth control line CTR4 provide a high level
  • the second control line CTR2 and the third control line CTR3 provide a low level
  • the sub-circuit is selected due to the clock signal in the Dummy GOA 1.
  • a control terminal is connected to the first control line CTR1
  • a second control terminal is connected to the second control line CTR2. Therefore, the clock signal selection sub-circuit therein selects the first clock signal CLKA to be output at the first output end thereof, and selects the The second clock signal CLKB is output at its second output.
  • the first control terminal of the clock signal selection sub-circuit in the Dummy GOA 2 is connected to the third control line CTR3
  • the second control terminal thereof is connected to the fourth control line CTR4, wherein the clock signal selection sub-circuit selects the first The clock signal CLKA is output at its first output and the second clock signal CLKB is selected for output at its second output.
  • the first control terminal of the clock signal selection sub-circuit in the first scan GOA 1 is connected to the third control line CTR3
  • the second control terminal thereof is connected to the fourth control line CTR4, wherein the clock signal selection sub-circuit selection
  • the second clock signal CLKB is output at its first output and the first clock signal CLKA is selected for output at its second output.
  • the clock signal selection sub-circuit selects the second clock signal CLKB at Its first output is output and the first clock signal CLKA is selected for output at its second output.
  • the clock signals of the other stages scan the GOA select the clock signal selected by the sub-circuit and so on. Can See the timing of the output signals of the GOA units of each stage as schematically illustrated in FIG.
  • successive two-stage scanning GOA units for example, GOA1&GOA2, GOA3&GOA4, GOA5&GOA6...GOA 2N+1&GOA 2N+2 inputs
  • the timings of the signal, the clock signal, and the reset signal are identical, so that the same signal is output to the corresponding two gate lines, and the dual gates are simultaneously turned on.
  • 6 is a schematic diagram showing the timing diagram of the entire display panel, so that the normal 3D display of the display panel is completed with the frame rate reduced, wherein the working principle of each level of the GOA unit can be referred to the above description with reference to FIG. 2 and FIG. The working principle of the shift register unit will not be described in detail.
  • a method for controlling the gate driving circuit illustrated in FIG. 4 is also provided.
  • the method mainly includes: inputting a second level to the first switch control line and a first level to the second switch control line in the 2D display mode, thereby being disposed at two adjacent levels of GOA a first switching transistor between the cells is turned on and turns off a second switching transistor disposed between two stages of GOA cells at an intermediate interval level; a second level is input to the first control line and the third control line, and The second control line and the fourth control line are input to the first level, so that the clock signals selected and outputted in the adjacent two-stage GOA units are respectively the first clock signal and the second clock signal; and the frame revelation signal is input to the first level a signal input end of the dummy shift register unit, respectively inputting the first clock signal and the second clock signal to the first clock signal end and the second clock signal end of the first stage dummy shift register unit, so that scanning shifts of each level
  • the register sequentially outputs
  • the method further includes: inputting a first level to the first switch control line and a second level to the second switch control line in the 3D display mode, thereby being disposed in the phase
  • the first switching transistor between the adjacent two-stage GOA units is turned off, and the second switching transistor disposed between the two-stage GOA units of the intermediate interval one is turned on;
  • the second control line is input to the first control line and the fourth control line Level, and inputting a first level to the second control line and the third control line, so that the clock signal of each adjacent two-stage GOA unit selection output is the same, which is one of the first clock signal and the second clock signal
  • the other two adjacent GOA units select the output clock signal as the other of the first clock signal and the second clock signal; input the frame revelation signal into the first stage and the second stage dummy shift register a signal input end of the unit, respectively inputting the first clock signal and the second clock signal to the first clock signal end and the second clock signal end of the first stage dummy shift register unit, so that each adjacent
  • the gate driving circuit includes switching transistors provided between the stages of shift register units, and controls respective switching transistors with respective control lines so that in the 2D display mode and in the 3D display mode
  • the connection mode of the shift register unit of the lower stage is changed, thereby realizing that the display panel can be freely switched in two different display modes of 2D and 3D, and simultaneous scanning of the double gate line can be realized in the 3D display, and the scanning frequency is reduced.
  • the effect of the high-frequency scanning signal on the charging of the display panel is reduced, and no additional design is required, which effectively reduces the product cost.

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Abstract

一种移位寄存器单元及其驱动方法、栅极驱动电路，以及阵列基板，其中移位寄存器单元包括：输入子电路(101)，连接在信号输入端(INPUT)和上拉节点(PU)之间，被配置为向上拉节点(PU)输入信号；输出子电路(102)，连接在上拉节点(PU)和信号输出端(OUTPUT)之间，被配置为在上拉节点(PU)的控制下，向信号输出端(OUTPUT)输出脉冲信号；复位子电路(103)，连接在复位端(RESET)、上拉节点(PU)和信号输出端(OUTPUT)之间，被配置为在复位端(RESET)的控制下，对上拉节点(PU)和信号输出端(OUTPUT)进行复位；以及时钟信号选择子电路(104)，其输入端连接到第一时钟信号端(CLK1)和第二时钟信号端(CLK2)，第一输出端连接到输出子电路(102)，被配置为根据第一控制端(CLR1)和第二控制端(CLR2)的电平来选择向输出子电路(102)提供第一时钟信号还是第二时钟信号。由此，实现了显示面板在2D和3D两种不同的显示模式下自由切换，并且能够在3D显示中实现对双栅线的同时扫描。

Description

移位寄存器单元、栅极驱动电路及其驱动方法 技术领域
本公开涉及显示技术领域，具体涉及一种移位寄存器单元、包括多级移位寄存器单元的栅极驱动电路及其驱动方法。
背景技术
在包括像素阵列的液晶显示面板的显示过程中，利用栅极驱动电路产生驱动显示面板上的像素的栅线电压。通过栅极驱动电路输出栅线电压，逐行扫描各像素。近几年随着非晶硅薄膜工艺的不断提高，可以将栅极驱动电路集成在薄膜晶体管阵列基板上构成GOA(Gate driver On Array)而对栅线进行驱动。采用GOA驱动，将GOA单元直接制成在液晶面板上，可以简化工艺，降低了成本，而且容易实现窄边框。
通常，可以采用由多级移位寄存器单元构成的GOA为像素阵列的各行栅线提供开关信号，从而控制多行栅线依序打开，并由数据线向像素阵列中对应行的像素输入显示数据信号，以形成显示图像的各灰阶所需要的灰度电压，进而显示每一帧图像。
目前，3D(Three-Dimensional)显示越来越得到市场上消费者的青睐,作为一种主流的3D显示技术，3D快门式显示技术由于具有画面分辨率较高、成本较低、立体效果较好等优势得到市场的广泛认可。然而3D快门式显示技术同样存在一定不足，如受到液晶响应时间的影响，出现串扰现象(上一帧画面残留到下一帧，导致重影)。为了解决串扰问题，一般在左右眼信号之间采用插黑技术来降低串扰现象。由于3D快门式显示技术是左右眼交替接收信号，所以对显示的帧频要求较高，一般要求120Hz。采用插黑技术之后，帧频需要提升一倍或更高。然而，采用高频率驱动对于液晶面板的充电饱和度有很大的影响，并且需要对栅极集成电路做出很大改动，增加设计难度和系统复杂度。
发明内容
为此，本公开提出了一种移位寄存器单元、包括多级移位寄存器单元的栅极驱动电路及其驱动方法。
根据本公开的一方面，提供了一种移位寄存器单元，其包括：输入子电路，连接信号输入端和上拉节点之间，被配置为向上拉节点输入信号；输出子电路，连接在上拉节点和信号输出端之间，被配置为在上拉节点的控制下，向信号输出端输出脉冲信号；复位子电路，连接在复位端、上拉节点和信号输出端之间，被配置为在复位端的控制下，对上拉节点和信号输出端进行复位；以及时钟信号选择子电路，其输入端连接到第一时钟信号端和第二时钟信号端，第一输出端连接到输出子电路，被配置为根据第一控制端和第二控制端的电平来选择向输出子电路提供第一时钟信号还是第二时钟信号。
根据本公开的另一方面，还提供了一种栅极驱动电路，其包括N级如上所述的移位寄存器单元，其中，第k级移位寄存器单元被配置为扫描对应的栅线，其信号输出端经由与第k级对应的第一开关晶体管连接到第k+1级移位寄存器单元的信号输入端，并且还经由与第k级对应的第二开关晶体管连接到第k+2级移位寄存器单元的信号输入端,其中k≥3；第k级移位寄存器单元信号输入端经由与第k级对应的第三开关晶体管连接到第k-1级移位寄存器单元的信号输出端，并且还经由与第k级对应的第四开关晶体管连接到第k-2级移位寄存器单元的输出端。
根据本公开的又一方面，还提供了一种应用于上述栅极驱动电路的方法，其包括：在2D显示模式下，向第一开关控制线输入第二电平而向第二开关控制线输入第一电平、从而将布置在相邻两级GOA单元之间的第一开关晶体管开启并且将布置在中间间隔一级的两级GOA单元之间的第二开关晶体管关断；向第一控制线和第三控制线输入第二电平，而向第二控制线和第四控制线输入第一电平，从而使得相邻的两级GOA单元中选择输出的时钟信号分别为第一时钟信号和第二时钟信号；将帧启示信号输入第一级哑移位寄存器单元的信号输入端，将第一时钟信号和第二时钟信号分别输入到第一级哑移位寄存器单元的第一时钟信号端和第二时钟信号端，使得各级扫描移位寄存器向所连接的栅线依次顺序输出驱动信号。
可选地，上述方法还包括：在3D显示模式下，向第一开关控制线输入第一电平而向第二开关控制线输入第二电平，从而将布置在相邻两级GOA单元之间的第一开关晶体管关断，而将布置在中间间隔一级的两级GOA单元之间的第二开关晶体管开启；向第一控制线和第四控制线输入第二电平，而向第二控制线和第三控制线输入第一电平；将帧启示信号输入第一级和第二级 哑移位寄存器单元的信号输入端，将第一时钟信号和第二时钟信号分别输入到第一级哑移位寄存器单元的第一时钟信号端和第二时钟信号端，使得每相邻的两级移位寄存器单元的信号输入端接收的信号的时序相同，并且输出的信号的时序相同。可选地，其中第一电平为低电平，第二电平为高电平。
在根据本公开提出的移位寄存器单元、栅极驱动电路及其驱动方法中，在各级移位寄存器单元之间设置有开关晶体管，并且利用相应的控制线来控制各个开关晶体管，使得在2D显示模式下和在3D显示模式下各级移位寄存器单元的连接方式发生改变，从而实现显示面板在2D和3D两种不同的显示模式下自由切换，并且能够在3D显示中实现对双栅线的同时扫描，降低了扫描频率，减小了高频扫描信号对于显示面板充电的影响，并且不需额外设计，有效降低了产品成本。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1图示了根据本公开实施例的一种移位寄存器单元的框图；
图2图示了根据本公开实施例的一种移位寄存器单元的具体电路结构；
图3图示了根据本公开实施例的一种可用于图2所示的移位寄存器单元的信号时序；
图4图示了根据本公开实施例的一种包括多级移位寄存器单元的栅极驱动电路的示意性结构；
图5图示了根据本公开实施例的在图4所示的栅极驱动电路进行2D显示驱动时采用的信号时序；
图6图示了根据本公开实施例的在图4所示的栅极驱动电路进行3D显示驱动时采用的信号时序；
图7图示了根据本公开实施例的一种应用于图4所示的栅极驱动电路的方法的示意性流程；以及
图8图示了根据本公开实施例的另一种应用于图4所示的栅极驱动电路的方法的示意性流程。
具体实施方式
下面将结合附图对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，也属于本公开保护的范围。
图1图示了根据本公开实施例的一种移位寄存器单元的框图。如图1所示，该移位寄存器单元包括：输入子电路101，连接信号输入端INPUT和上拉节点PU之间，被配置为向上拉节点输入信号；输出子电路102，连接在上拉节点PU和信号输出端OUTPUT之间，被配置为在上拉节点PU的控制下，向信号输出端OUTPUT输出脉冲信号；复位子电路103，连接在复位端RESET、上拉节点PU和信号输出端OUTPUT之间，被配置为在复位端RESET的控制下，对上拉节点PU和信号输出端OUTPUT进行复位；以及时钟信号选择子电路104，其输入端连接到第一时钟信号端CLK1和第二时钟信号端CLK2，第一输出端连接到输出子电路102，被配置为根据第一控制端和第二控制端的电平来选择向输出子电路102提供第一时钟信号还是第二时钟信号。
可选地，根据本公开的移位寄存器单元，如图1所示，还包括下拉节点控制子电路105，其连接到上拉节点PU和时钟信号选择子电路104的第二输出端，被配置为根据时钟信号选择子电路104提供的第一时钟信号或第二时钟信号以及上拉节点PU的电平，控制下拉节点的电平。
可选地，根据本公开的移位寄存器单元，如图1所示，还包括下拉子电路106，其连接到下拉节点、上拉节点和信号输出端，被配置为根据下拉节点的电平对上拉节点和信号输出端进行下拉。
可选地，根据本公开的移位寄存器单元，如图1所示，还包括辅助控制子电路107，其连接到上拉节点PU、信号输出端和时钟信号选择子电路104的第二输出端，被配置为根据时钟信号选择子电路提供的时钟信号，辅助控制上拉节点和信号输出端的电平。
根据本公开实施例的移位寄存器单元，可以通过时钟信号选择子电路来选择向输出子电路提供的时钟信号，从而在信号输出端输出相应的脉冲信号。
此外，根据本公开实施例的移位寄存器单元，可以通过时钟信号选择子 电路来选择向下拉节点控制子电路和辅助控制子电路提供的时钟信号，以便对下拉节点、上拉节点以及信号输出端的电平进行控制。
图2图示了根据本公开实施例的一种移位寄存器单元的具体电路结构。如图2所示，可选地，输入子电路包括：输入晶体管M1，其控制极和第一极连接到信号输入端，第二极连接到上拉节点。
可选地，如图2所示，输出子电路包括：输出晶体管M3，其控制极连接到上拉节点，第一极连接到时钟信号选择子电路的第一输出端CLKOUT1，第二极连接到信号输出端OUTPUT；以及电容C1，其第一端连接到上拉节点PU，第二端连接到信号输出端OUTPUT。
可选地，如图2所示，复位子电路包括：第一复位晶体管M2，其控制极连接到复位端RESET，第一极连接到上拉节点PU，第二极连接到第一电源端VSS；以及第二复位晶体管M4，其控制极连接到复位端RESET，第一极连接到信号输出端OUTPUT，第二极连接到第一电源端VSS。
可选地，如图2所示，时钟信号选择子电路包括：第一选择晶体管T1，其控制极连接到第一控制端CLR1，第一极连接到第一时钟信号端CLK1，第二极连接到时钟信号选择子电路的第一输出端CLKOUT1；第二选择晶体管T2，其控制极连接到第二控制端CLR2，第一极连接到第二时钟信号端CLK2，第二极连接到第一选择晶体管T1的第二极。
可选地，如图2所示，时钟信号选择子电路还包括：第三选择晶体管T3，其控制极连接到第一控制端CLR1，第一极连接到第二时钟信号端CLK2，第二极连接到时钟信号选择子电路104的第二输出端CLKOUT2；第四选择晶体管T4，其控制极连接到第二控制端CLR2，第一极连接到第一时钟信号端CLK1，第二极连接到第三选择晶体管T3的第二极。
可选地，如图2所示，下拉节点控制子电路包括：第一下拉控制晶体管M9，其控制极和第一极连接到时钟信号选择子电路的第二输出端CLKOUT2，第二极连接到下拉控制节点PD_CN；第二下拉控制晶体管M5，其控制极连接到下拉控制节点PD_CN，第一极连接到第一下拉控制晶体管M9的第一极，第二极连接到下拉节点PD；第三下拉控制晶体管M8，其控制极连接到上拉节点PU，第一极连接到下拉控制节点PD_CN，第二极连接到第一电源端VSS；以及第四下拉控制晶体管M6，其控制极连接到上拉节点PU，第一极连接到下拉节点PD，第二极连接到第一电源端VSS。
可选地，如图2所示，下拉子电路包括：第一下拉晶体管M10，其控制极连接到下拉节点PD，第一极连接到上拉节点PU，第二极连接到第一电源端VSS；以及第二下拉晶体管M11，其控制极连接到下拉节点PD，第一极连接到信号输出端OUTPUT，第二极连接到第一电源端VSS。
可选地，如图2所示，辅助控制子电路107包括：第一辅助控制晶体管M13，其控制极连接到时钟信号选择子电路的第二输出端CLKOUT2，第一极连接到信号输入端INPUT，第二极连接到上拉节点PU；以及第二辅助控制晶体管M12，其控制极连接到时钟信号选择子电路的第二输出端CLKOUT2，第一极连接到信号输出端OUTPUT，第二极连接到第一电源端VSS。
可选地，在上述移位寄存器单元中，上述的各个晶体管可以采用TFT晶体管，其中晶体管的控制极是栅极，第一极是漏极，第二极是源极。此外，应理解，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，为区分晶体管除栅极之外的两极，其中的一极可以被称为源极，另一极可以被称为漏极。若选取源极作为信号输入端、则漏极作为信号输出端，反之亦然。
另外，在图2中，以所有的TFT采用N型TFT为例进行了说明。然而，应理解，其中的一部分或者全部TFT可以采用P型TFT，只要相应地调整其栅极的控制电平以及向其提供的电源电压即可，这样的实施方式也在本公开的保护范围之内。
此外，在图2中，第一电源端被示为接入低电平VSS。然而，为实现本公开的原理，第一电源端可以接入到不同的低电平，例如具有不同电压值的低电平VSS和VGL。例如，与用于下拉移位寄存器单元输出端的晶体管连接的低电平可以接入低电平VGL，而与用于下拉移位寄存器单元的上拉节点的低电平可以接入低电平VSS，其中VGL的电平低于VSS的电平。通过这种方式，可以在上拉节点和输出端均被下拉到低电平时，将移位寄存器单元的输出晶体管的栅源电势反偏，即便输出晶体管采用耗尽型晶体管时，也能保证输出晶体管的完全关断。
下面参照图3图示的信号时序来简要说明图2所示的移位寄存器单元的工作原理。其中，以第一控制端CLR1为高电平，第二控制端CLR2为低电平为例，来描述移位寄存器单元在图3所示的时序图中的a、b、c、d和e五个阶段的操作。
由于第一控制端CLR1为高电平，第二控制端CLR2为低电平，时钟信号选择子电路中的第一选择晶体管T1和第三选择晶体管T3开启，而第二选择晶体管T2和第四选择晶体管T4关闭，从而向时钟信号选择子电路的第一输出端提供第一时钟信号CLKA，而向时钟信号选择子电路的第二输出端提供第二时钟信号CLKB。第一时钟信号CLKA和第二时钟信号CLKB的周期相等、占空比均为50％，并且相位相差180度。
在第一阶段a中，信号输入端INPUT接入的输入信号为高电平，第一时钟信号CLKA为低电平，第二时钟信号CLKB为高电平；晶体管M1开启，使得高电平的输入信号对上拉节点PU进行充电；由于第二时钟信号CLKB为高电平，晶体管M13开启，加速上拉节点PU的充电过程；由此，上拉节点PU被充电到第一高电平，输出晶体管M3开启，向信号输出端输出低电平的时钟信号CLKA；晶体管M9开启，对下拉控制节点PD_CN充电，然而，由于上拉节点PU处于第一高电平，晶体管M6和M8开启；在晶体管的设计上，可以将晶体管M8与M9的尺寸比配置为在M9和M8均开启时，下拉控制节点PD_CN的电平被下拉到低电平，在这种情况下，PD_CN为低电平，晶体管M5保持关断；由于晶体管M6开启，下拉节点PD的电平被下拉到低电平，从而晶体管M10和M11在此阶段处于关断状态；由于CLKB为高电平，晶体管M12开启，可以确保将移位寄存器单元的输出端拉低到低电平VSS；
在第二阶段b中，第一时钟信号CLKA为高电平，第二时钟信号CLKB为低电平，信号输入端INPUT输入的信号为低电平；晶体管M1、M13、M9、M5和M12关断；输出晶体管M3保持开启，将高电平的时钟信号CLKA输出，作为脉冲信号；由于存储电容C1的自举效应，上拉节点PU的电平进一步升高，达到第二高电平，使得输出晶体管M3的导通更充分；由于上拉节点PU的电平相对于阶段a的电平被提升，晶体管M8和M6的导通更充分，分别将下拉控制节点PD_CN和下拉节点PD进一步拉低；由于下拉节点PD为低电平，晶体管M10和M11保持关断状态，从而不会影响移位寄存器单元输出脉冲信号；
在第三阶段c中，第一时钟信号CLKA为低电平，第二时钟信号CLKB为高电平，信号输入端INPUT继续接入低电平，复位端RESET接入高电平；由于复位端接入高电平，晶体管M2和M4开启，分别将上拉节点PU和移位寄存器单元的输出端下拉到低电平VSS；而晶体管M1关断，晶体管M13开启，将低电平接入上拉节点PU，对上拉节点PU进行放电；上拉节点PU被放电到低 电平，使得晶体管M3关断；由于第二时钟信号CLKB为高电平，晶体管M12开启，将移位寄存器单元的输出端拉低到低电平VSS；晶体管M9开启，对下拉控制节点PD_CN充电，进而使得晶体管M5开启，从而对下拉节点PD充电；由于上拉节点PU处于低电平，晶体管M6和M8关断；下拉节点PD被充电到高电平，晶体管M10和M11开启，分别将上拉节点PU和移位寄存器单元的输出端下拉到低电平VSS；
在第四阶段d中，第一时钟信号CLKA为高电平，第二时钟信号CLKB为低电平，信号输入端INPUT继续接入低电平，复位端接入低电平；晶体管M1、M13、M2、M4、M9和M12关断；由于上拉节点PU保持低电平，晶体管M6和M8继续关断；由于晶体管M8和M9均关断，下拉控制节点PD_CN的放电路径被关闭，下拉控制节点PD_CN保持之前的高电平，从而使得晶体管M5保持开启，由于第二时钟信号CLKB为低电平，因此，下拉节点PD被放电。
在第五阶段e中，第一时钟信号CLK为低电平，第二时钟信号CLKB为高电平，输入端INPUT继续接入低电平，复位端接入低电平；晶体管M1、M2、M4关断；晶体管M13开启，将低电平接入上拉节点PU，对上拉节点PU进行放电，确保关断晶体管M3；CLKB为高电平，晶体管M12开启，将移位寄存器单元的输出端拉低到低电平VSS，消除移位寄存器单元的输出端的噪声；晶体管M9开启，对下拉控制节点PD_CN充电，使得晶体管M5的开启更充分，并且对下拉节点PD充电，使得下拉节点PD变成高电平；由于上拉节点PU被放电，晶体管M6和M8保持关断；下拉节点PD的高电平使得晶体管M10和M11开启，分别将上拉节点PU和移位寄存器单元的输出端下拉到低电平VSS，消除了在上拉节点和输出端处形成的噪声。
之后，移位寄存器单元重复阶段d和e的操作，直至下一个有效输入信号到来。
尽管以上是以第一控制端CLR1为高电平，第二控制端CLR2为低电平为例对图2所示的移位寄存器单元的工作原理进行了说明，然而，基于上面的原理，当第一控制端CLR1为低电平，而第二控制端CLR2为高电平的情形是类似的，具体细节不在此赘述。
根据本公开的一实施例，提出了一种包括多级上述的移位寄存器单元(GOA单元)的栅极驱动电路。图4示出了该栅极驱动电路的示意性的结构。如图4所示，该栅极驱动电路包括多个GOA单元，其中，多个GOA单元分 为大致4种，即，第一级哑(Dummy)GOA 1、第二级哑(Dummy)GOA 2、奇数级扫描GOA 2N+1(N≥0，N为整数)，偶数级扫描GOA 2N+2(N≥0，N为整数)。其中，每个GOA单元的内部结构如图2所示，具体包括十六个TFT和一个电容。
具体地，Dummy GOA 1和Dummy GOA 2主要负责信号启动，为后续GOA单元的开启起到信号开启的作用，不负责对显示面板有效区域(Active Area)的栅线扫描提供控制。
如图4所示，Dummy GOA 1的信号输入端INPUT接入STV信号，Dummy GOA 1的信号输出端经由与Dummy GOA 1对应的第一开关晶体管SW1连接到Dummy GOA 2的信号输入端，并且经由与Dummy GOA 1对应的第二开关晶体管SW2连接到第一级扫描GOA 1的信号输入端；Dummy GOA 1的复位端经由与Dummy GOA 1对应的第三开关晶体管SW3连接到Dummy GOA 2的信号输出端，并且经由与Dummy GOA 1对应的第四开关晶体管SW4连接到第一级扫描GOA 1的信号输出端；Dummy GOA 1的第一控制端连接到第一控制线CTR1，其第二控制端连接到第二控制线CTR2,第一开关晶体管SW1的控制极连接到第一开关控制线SCL1、第二开关晶体管SW2的控制极连接到第二开关控制线SCL2，第三开关晶体管SW3的控制极连接到第一开关控制线SCL1，第四开关晶体管SW4的控制极连接到第二开关控制线SCL2，第一时钟信号端接收第一时钟信号CLKA，第二时钟信号端接收第二时钟信号CLKB。
Dummy GOA 2的信号输入端INPUT经由与Dummy GOA 2对应的第五开关晶体管SW5接入STV信号，Dummy GOA 2的信号输出端经由与Dummy GOA 2对应的第六开关晶体管SW6连接到第一级扫描GOA 1的信号输入端，并且经由与Dummy GOA 2对应的第七开关晶体管SW7连接到第二级扫描GOA 2的信号输入端；Dummy GOA 2的复位端直接连接到第一级扫描GOA 1的信号输出端；Dummy GOA 2的第一控制端连接到第三控制线CTR3，其第二控制端连接到第四控制线CTR4,第五开关晶体管SW5的控制极连接到第二开关控制线SCL2、第六开关晶体管SW6的控制极连接到第一开关控制线SCL1，第七开关晶体管SW7的控制极连接到第二开关控制线SCL2，第一时钟信号端接收第二时钟信号CLKB，第二时钟信号端接收第一时钟信号CLKA。
如图4所示，对于第一级扫描GOA 1而言，其信号输出端除了与Dummy GOA 1和Dummy GOA 2的复位端连接之外，还连接到对应的栅线GL1，用于为栅线GL1提供扫描信号，从而驱动显示面板上相应的像素子电路；此外，第一级扫描GOA 1的信号输出端还经由与第一级扫描GOA 1对应的第八开关晶体管SW8连接到第二级扫描GOA 2的信号输入端，并且经由与第一级扫描GOA 1对应的第九开关晶体管SW9连接到第三级扫描GOA 3的信号输入端；第一级扫描GOA 1的复位端经由与第一级扫描GOA 1对应的第十开关晶体管SW10连接到第二级扫描GOA 2的信号输出端，并且经由与第一级扫描GOA 1对应的第十一开关晶体管SW11连接到第三级扫描GOA 3的信号输出端；第一级扫描GOA 1的第一控制端连接到第三控制线CTR3，其第二控制端连接到第四控制线CTR4,第八开关晶体管SW8的控制极连接到第一开关控制线SCL1、第九开关晶体管SW9的控制极连接到第二开关控制线SCL2，第十开关晶体管SW10的控制极连接到第一开关控制线SCL1，第十一开关晶体管SW11的控制极连接到第二开关控制线SCL2，第一时钟信号端接收第一时钟信号CLKA，第二时钟信号端接收第二时钟信号CLKB。
如图4所示，对于第二级扫描GOA 2而言，其信号输出端除了与第一级扫描GOA 1的复位端连接之外，还连接到对应的栅线GL2，用于为栅线GL2提供扫描信号，从而驱动显示面板上相应的像素子电路；此外，第二级扫描GOA 2的信号输出端还经由与第二级扫描GOA 2对应的第十二开关晶体管SW12连接到第三级扫描GOA 3的信号输入端，并且经由与第二级扫描GOA 2对应的第十三开关晶体管SW13连接到第四级扫描GOA 4的信号输入端；第二级扫描GOA 2的复位端直接连接到第三级扫描GOA 3的信号输出端；第二级扫描GOA 2的第一控制端连接到第一控制线CTR1，其第二控制端连接到第二控制线CTR2,第十二开关晶体管SW12的控制极连接到第一开关控制线SCL1、第十三开关晶体管SW13的控制极连接到第二开关控制线SCL2，第一时钟信号端接收第二时钟信号CLKB，第二时钟信号端接收第一时钟信号CLKA。
由此可见，Dummy GOA 1子电路的输入信号的来源只有一个，来自帧起始信号STV；复位信号的来源有两个，来自之后的连续两级GOA的输出，即，Dummy GOA 2子电路和第一扫描GOA1子电路的输出；Dummy GOA 2子电路的输入信号的来源有两个，STV信号和前一级GOA单元(即Dummy  GOA 1子电路)的输出，而Dummy GOA 2子电路的复位信号的来源只有一个，即来自前一级GOA单元的输出，即第一扫描GOA 1子电路的输出。
对于扫描GOA单元的输入信号，例如，图4所示的第一扫描GOA1和第二扫描GOA2子电路，输入信号的来源有两个，来自之前的连续两级GOA单元的输出；例如，第一扫描GOA1子电路的输入信号来自于Dummy GOA 1子电路和Dummy GOA 2子电路的输出，第二扫描GOA2子电路的输入信号来自于Dummy GOA 2子电路和第一扫描GOA 1子电路的输出。
对于扫描GOA单元的复位信号，例如，图4所示的第一扫描GOA1的复位信号的来源有两个，即，之后的连续两级GOA单元的输出，也就是GOA2和GOA3的输出；而第二扫描GOA2的复位信号的来源有一个，即，之后的连续一级GOA单元的输出，也就是GOA3的输出。
之后的各级GOA单元的输入信号和复位信号的来源以此类推。例如，针对GOA K子电路(K≥3，K为奇数)，其输入信号的来源是之前的连续两级GOA单元的输出，即GOA K-1子电路和GOAK-2子电路的输出，其复位信号的来源是之后的连续两级GOA单元的输出，即是GOA K+1和GOAK+2的输出。针对GOA K’(K’≥4，K为偶数)，其输入信号的来源是之前的连续两级GOA单元的输出，即GOA K-1和GOA K-2的输出，其复位信号的来源是之后的连续一级GOA单元的输出，即，GOA K+1子电路的输出。另外，需要注意，如上所述，奇数级和偶数级GOA中的时钟信号选择子电路的第一时钟信号端和第二时钟信号端所接入的时钟信号是彼此交替切换的，例如，奇数级GOA中的时钟信号选择子电路的第一时钟信号端接收第一时钟信号CLKA，第二时钟信号端接收第二时钟信号CLKB，而偶数级GOA的第一时钟信号端接收第二时钟信号CLKB，第二时钟信号端接收第一时钟信号CLKA。
根据本公开的上述实施例，通过在GOA区域设置相应的控制线并且利用一定数量TFT开关，可以实现显示面板2D和3D不同显示模式自由切换。同时在3D显示中实现双栅线同时打开，可以降低高频对于显示面板充电的影响。不需额外设计，有效降低成本。
为此，在根据本公开的上述实施例的栅极驱动电路中，如图4所示，Dummy GOA1、扫描GOA单元，即，GOA2、GOA3、GOA6、GOA7、GOA10、GOA11......GOA 4N+2、GOA 4N+3(N≥0，N为整数)中的时钟信号选择子电 路的第一控制端连接到第一控制线CTR1，其第二控制端连接到第二控制线CTR2；Dummy GOA2、扫描GOA单元，即，GOA1、GOA4、GOA5、GOA8、GOA9、GOA12......GOA 4N+1、GOA 4N+4(N≥0，N为整数)的第一控制端连接到第三控制线CTR3，其第二控制端连接到第四控制线CTR4。
根据以上实施例，本公开提供的栅极驱动电路包括N级如图2所示的移位寄存器单元，其中，第k级移位寄存器单元被配置为扫描对应的栅线，其信号输出端经由与第k级对应的第一开关晶体管连接到第k+1级移位寄存器单元的信号输入端，并且还经由与第k级对应的第二开关晶体管连接到第k+2级移位寄存器单元的信号输入端,其中k≥3，N和k为整数；第k级移位寄存器单元信号输入端经由与第k级对应的第三开关晶体管连接到第k-1级移位寄存器单元的信号输出端，并且还经由与第k级对应的第四开关晶体管连接到第k-2级移位寄存器单元的输出端。
可选地，在上述栅极驱动电路中，第一级和第二级移位寄存器单元被配置为哑移位寄存器单元；其中，第1级移位寄存器单元的信号输出端经由与第1级对应的第一开关晶体管连接到第2级移位寄存器单元的信号输入端，并且第1级移位寄存器单元的信号输入端接收帧起始信号STV；第2级移位寄存器单元的信号输入端还经由与第2级对应的第二开关晶体管接收帧起始信号STV。
可选地，在上述栅极驱动电路中，第2j-1级移位寄存器单元的复位端经由与该第2j-1级对应的第五开关晶体管连接到第2j级移位寄存器单元的信号输出端，并且还经由与该第2j-1级对应的第六开关晶体管连接到第2j+1级移位寄存器单元的信号输出端；第2j级移位寄存器单元的复位端连接到第2j+1级移位寄存器单元的信号输出端，其中1≤j≤(N-1)/2，j为整数。
为了实现显示面板在2D-3D之间不同显示模式的转换，同时保证在3D显示过程中双栅线同时开启，本公开实施例的栅极驱动电路中的奇数级GOA单元与偶数级GOA单元的控制原理略有差异，以下将结合图5所示的信号时序来首先说明根据本公开实施例的栅极驱动电路进行2D显示驱动时的工作原理。
当显示面板在2D模式下进行2D显示时，如图5所示，第一开关控制线SCL1提供高电平，第二开关控制线SCL2提供低电平，第一控制线CTR1和第三控制线CTR3提供高电平，而第二控制线CTR2和第四控制线CTR4提 供低电平。
由于布置在相邻两级GOA单元之间的开关晶体管的控制极与第一开关控制线SCL1连接，因此，布置在相邻两级GOA单元之间的开关晶体管开启，从而将相邻两级GOA单元的信号路径导通；具体而言，Dummy GOA1的输出信号可以经由开启的开关晶体管SW1提供给Dummy GOA 2的信号输入端，而Dummy GOA 2的输出信号可以经由开启的开关晶体管SW3提供给Dummy GOA 1的复位端；类似地，Dummy GOA2的输出信号可以经由开启的开关晶体管SW6提供给第一级扫描GOA1的信号输入端，而第一级扫描GOA 1的输出信号可以直接提供给Dummy GOA 2的复位端；而第一级扫描GOA1的输出信号还可以经由开启的开关晶体管SW8提供给第二级扫描GOA 2的信号输入端，而第二级扫描GOA 2的输出信号可以经由开启的开关晶体管SW10提供给第一级扫描GOA 1的复位端；此外，由于布置在中间间隔一级的两级GOA单元之间的开关晶体管的控制极与第二开关控制线SCL2连接，从而将中间间隔一级的两级GOA单元的信号路径切断；具体而言，由于开关晶体管SW2被关断，Dummy GOA1的信号输出端与第一级扫描GOA1的信号输入端之间的信号路径被切断；由于开关晶体管SW4被关断，Dummy GOA1的复位端与第一级扫描GOA1的信号输出端之间的信号路径被切断；类似地，由于开关晶体管SW7被关断，Dummy GOA2的信号输出端与第二级扫描GOA2的信号输入端之间的信号路径被切断；由于开关晶体管SW9被关断，第一级扫描GOA1的信号输出端与第三级扫描GOA3的信号输入端之间的信号路径被切断；由于开关晶体管SW11被关断，第一级扫描GOA1的复位端与第三级扫描GOA3的信号输出端之间的信号路径被切断；其余各级扫描GOA单元的信号连接关系以此类推。
此外，由于第二开关控制线SCL2提供低电平，控制极连接到第二开关控制线SCL2的开关晶体管SW5被关断，也就是Dummy GOA2的信号输入端与STV信号之间的信号路径被切断。
由此可见，在2D显示模式下，例如在正向扫描方式下，当输入STV信号时，各级扫描GOA单元由上一级GOA单元的输出信号触发而驱动相应的栅线，并且各级GOA单元的输出信号作为复位信号而提供给上一级GOA单元，其中各级GOA单元的工作原理可以参见以上结合图2和图3所描述的移位寄存器单元的工作原理，具体细节不再赘述。
此外，由于Dummy GOA 1中的时钟信号选择子电路的第一控制端连接到第一控制线CTR1，其第二控制端连接到第二控制线CTR2，因此，其中的时钟信号选择子电路选择第一时钟信号CLKA在其第一输出端输出，并且选择第二时钟信号CLKB在其第二输出端输出。
类似地，由于Dummy GOA 2中的时钟信号选择子电路的第一控制端连接到第三控制线CTR3，其第二控制端连接到第四控制线CTR4，其中的时钟信号选择子电路选择第二时钟信号CLKB在其第一输出端输出，并且选择第一时钟信号CLKA在其第二输出端输出。
类似地，由于第一扫描GOA 1中的时钟信号选择子电路的第一控制端连接到第三控制线CTR3，其第二控制端连接到第四控制线CTR4，其中的时钟信号选择子电路选择第一时钟信号CLKA在其第一输出端输出，并且选择第二时钟信号CLKB在其第二输出端输出。
类似地，由于第二级扫描GOA 2的第一控制端连接到第一控制线CTR1，其第二控制端连接到第二控制线CTR2，其中的时钟信号选择子电路选择第二时钟信号CLKB在其第一输出端输出，并且选择第一时钟信号CLKA在其第二输出端输出。
其它各级扫描GOA的时钟信号选择子电路选择的时钟信号以此类推，具体可以参见如图5示意性示出的各级GOA单元的输出信号的时序。
当显示面板的显示模式切换到3D时，需要双栅线同时开启。以下将结合图6示意性示出的信号时序来说明根据本公开实施例的栅极驱动电路进行3D显示驱动时的工作原理。
当显示面板切换到3D模式进行3D显示时，如图6所示，第一开关控制线SCL1提供低电平，第二开关控制线SCL2提供高电平，第一控制线CTR1和第四控制线CTR4提供高电平，而第二控制线CTR2和第三控制线CTR3提供低电平。
由于布置在相邻两级GOA单元之间的开关晶体管的控制极与第一开关控制线SCL1连接，因此，布置在相邻两级GOA单元之间的开关晶体管被关断，从而将相邻两级GOA单元经由开关晶体管的信号路径切断；具体而言，Dummy GOA1的信号输出端与Dummy GOA2的信号输入端之间的信号路径被切断，而Dummy GOA 2的信号输出端与Dummy GOA 1的复位端之间的信号路径被切断；类似地，Dummy GOA2的信号输出端与第一级扫描GOA 1 的信号输入端之间的信号路径被切断，而第一级扫描GOA 1的输出信号可以直接提供给Dummy GOA 2的复位端；第一级扫描GOA1的信号输出端与第二级扫描GOA 2的信号输入端之间的信号路径被切断，而第二级扫描GOA 2的信号输出端与第一级扫描GOA 1的复位端之间的信号路径被切断。
此外，由于布置在中间间隔一级的两级GOA单元之间的开关晶体管的控制极与第二开关控制线SCL2连接，因此被开启，从而将中间间隔一级的两级GOA单元的信号路径导通；具体而言，由于开关晶体管SW2被开启，Dummy GOA1的信号输出端与第一级扫描GOA1的信号输入端之间的信号路径被导通；由于开关晶体管SW4被开启，Dummy GOA1的复位端与第一级扫描GOA1的信号输出端之间的信号路径被导通；类似地，由于开关晶体管SW7被开启，Dummy GOA2的信号输出端与第二级扫描GOA2的信号输入端之间的信号路径被导通；由于开关晶体管SW9被开启，第一级扫描GOA1的信号输出端与第三级扫描GOA3的信号输入端之间的信号路径被导通；由于开关晶体管SW11被开启，第一级扫描GOA1的复位端与第三级扫描GOA3的信号输出端之间的信号路径被导通；其余各级扫描GOA单元的信号连接关系以此类推。
此外，由于第二开关控制线SCL2提供高电平，控制极连接到第二开关控制线SCL2的开关晶体管SW5被开启，也就是Dummy GOA2的信号输入端与STV信号之间的信号路径被导通。
由此可见，在3D显示模式下，Dummy GOA1和Dummy GOA2的输入信号端和复位信号端彼此并联，Dummy GOA1和Dummy GOA2输出的信号分别作为第一级扫描GOA1和第二级扫描GOA2的输入信号；第一级扫描GOA1和第二级扫描GOA2的复位端均与第三级扫描GOA3的信号输出端连接，而第一级扫描GOA1和第二级扫描GOA2输出的信号除了驱动相应的栅线之外，还分别作为第三级扫描GOA3和第二级扫描GOA4的输入信号；之后的扫描GOA的信号连接关系以此类推。其中各级GOA单元的工作原理可以参见以上结合图2和图3所描述的移位寄存器单元的工作原理，具体细节不再赘述。
因此，在3D显示模式下，例如在正向扫描方式下，当输入STV信号时，Dummy GOA1和Dummy GOA2的输入信号端均接收STV信号作为触发信号，并且其复位端均接收来自第一级扫描GOA 1的输出信号作为复位信号， 因此如图6所示，Dummy GOA1和Dummy GOA2输出的信号时序相同；如上所述，由于第一极扫描GOA1和第二级扫描GOA2分别接收来自于Dummy GOA1和Dummy GOA2的输出信号作为触发信号，并且其复位端均接收来自第三级扫描GOA 3的输出信号作为复位信号，因此，如图6所示，第一级扫描GOA1和第二级扫描GOA2输出的信号时序相同；也就是说，第一级扫描GOA1对应的栅线和第二级扫描GOA2对应的栅线同时开启；类似地，第三级扫描GOA3和第四级扫描GOA4输出的信号时序相同，其各自对应的栅线同时开启；其它扫描GOA的时序以此类推，从而实现了双栅线同时开启。
如上所述，第一控制线CTR1和第四控制线CTR4提供高电平，而第二控制线CTR2和第三控制线CTR3提供低电平，由于Dummy GOA 1中的时钟信号选择子电路的第一控制端连接到第一控制线CTR1，其第二控制端连接到第二控制线CTR2，因此，其中的时钟信号选择子电路选择第一时钟信号CLKA在其第一输出端输出，并且选择第二时钟信号CLKB在其第二输出端输出。
类似地，由于Dummy GOA 2中的时钟信号选择子电路的第一控制端连接到第三控制线CTR3，其第二控制端连接到第四控制线CTR4，其中的时钟信号选择子电路选择第一时钟信号CLKA在其第一输出端输出，并且选择第二时钟信号CLKB在其第二输出端输出。
由此可见，Dummy GOA 1和Dummy GOA 2的时钟信号的时序是相同的。
类似地，由于第一扫描GOA 1中的时钟信号选择子电路的第一控制端连接到第三控制线CTR3，其第二控制端连接到第四控制线CTR4，其中的时钟信号选择子电路选择第二时钟信号CLKB在其第一输出端输出，并且选择第一时钟信号CLKA在其第二输出端输出。
类似地，由于第二级扫描GOA 2的第一控制端连接到第一控制线CTR1，其第二控制端连接到第二控制线CTR2，其中的时钟信号选择子电路选择第二时钟信号CLKB在其第一输出端输出，并且选择第一时钟信号CLKA在其第二输出端输出。
由此可见，第一级扫描GOA 1和第二级扫描GOA 2的时钟信号的时序也是相同的。
其它各级扫描GOA的时钟信号选择子电路选择的时钟信号以此类推。可 以参见如图6示意性示出的各级GOA单元的输出信号的时序。
由此可见，在3D显示模式下，例如在正向扫描方式下，当输入STV信号时，连续的两级扫描GOA单元，例如，GOA1&GOA2、GOA3&GOA4、GOA5&GOA6……GOA 2N+1&GOA 2N+2的输入信号、时钟信号以及复位信号的时序完全相同，从而向对应的两条栅线输出相同的信号，实现了双栅极同时打开。图6示意性地示出整个显示面板的时序图，使得在降低帧频的情况下，完成显示面板正常的3D显示，其中各级GOA单元的工作原理可以参见以上结合图2和图3所描述的移位寄存器单元的工作原理，具体细节不再赘述。
根据本公开的又一方面，还提供了一种用于对图4所示的栅极驱动电路进行控制的方法。如图7图示，该方法主要包括：在2D显示模式下，向第一开关控制线输入第二电平而向第二开关控制线输入第一电平、从而将布置在相邻两级GOA单元之间的第一开关晶体管开启并且将布置在中间间隔一级的两级GOA单元之间的第二开关晶体管关断；向第一控制线和第三控制线输入第二电平，而向第二控制线和第四控制线输入第一电平，从而使得相邻的两级GOA单元中选择输出的时钟信号分别为第一时钟信号和第二时钟信号；将帧启示信号输入第一级哑移位寄存器单元的信号输入端，将第一时钟信号和第二时钟信号分别输入到第一级哑移位寄存器单元的第一时钟信号端和第二时钟信号端，使得各级扫描移位寄存器向所连接的栅线依次顺序输出驱动信号，其中，第m级移位寄存器，在其信号输入端接收来自于第(m-1)级移位寄存器输出的信号，在其信号输出端向第(m+1)级移位寄存器输出触发信号，并且在其复位端接收来自于第(m+1)输出的信号作为复位信号。可选地，其中第一电平为低电平，第二电平为高电平。
可选地，如图8所示，上述方法还包括：在3D显示模式下，向第一开关控制线输入第一电平而向第二开关控制线输入第二电平，从而将布置在相邻两级GOA单元之间的第一开关晶体管关断，而将布置在中间间隔一级的两级GOA单元之间的第二开关晶体管开启；向第一控制线和第四控制线输入第二电平，而向第二控制线和第三控制线输入第一电平，从而使得每相邻的两级GOA单元选择输出的时钟信号相同，为第一时钟信号和第二时钟信号中的一个，而与之相邻的另两级GOA单元选择输出的时钟信号为第一时钟信号和第二时钟信号中的另一个；将帧启示信号输入第一级和第二级哑移位寄存器 单元的信号输入端，将第一时钟信号和第二时钟信号分别输入到第一级哑移位寄存器单元的第一时钟信号端和第二时钟信号端，使得每相邻的两级移位寄存器单元的信号输入端接收的信号的时序相同，并且输出的信号的时序相同。可选地，其中第一电平为低电平，第二电平为高电平。
根据本公开的上述实施例的栅极驱动电路包括在各级移位寄存器单元之间设置的开关晶体管，并且利用相应的控制线来控制各个开关晶体管，使得在2D显示模式下和在3D显示模式下各级移位寄存器单元的连接方式发生改变，从而实现显示面板在2D和3D两种不同的显示模式下自由切换，并且能够在3D显示中实现对双栅线的同时扫描，降低了扫描频率，减小了高频扫描信号对于显示面板充电的影响，并且不需额外设计，有效降低了产品成本。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开实施例公开的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应该以权利要求的保护范围为准。
本申请要求于2017年4月12日递交的中国专利申请第201710237626.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种移位寄存器单元，包括：
    输入子电路(101)，连接信号输入端和上拉节点之间，被配置为向上拉节点输入信号；
    输出子电路(102)，连接在上拉节点和信号输出端之间，被配置为在上拉节点的控制下，向信号输出端输出脉冲信号；
    复位子电路(103)，连接在复位端、上拉节点和信号输出端之间，被配置为在复位端的控制下，对上拉节点和信号输出端进行复位；以及
    时钟信号选择子电路(104)，其输入端连接到第一时钟信号端和第二时钟信号端，控制端连接到第一控制端和第二控制端，第一输出端连接到输出子电路，被配置为根据第一控制端和第二控制端的电平来选择向输出子电路提供第一时钟信号还是第二时钟信号。
  2. 根据权利要求1所述的移位寄存器单元，还包括：下拉节点控制子电路(105)，其连接到上拉节点(PU)和时钟信号选择子电路(104)的第二输出端，被配置为根据时钟信号选择子电路提供的第一时钟信号或第二时钟信号以及上拉节点的电平，控制下拉节点的电平。
  3. 根据权利要求1或2所述的移位寄存器单元，还包括：下拉子电路(106)，连接到下拉节点、上拉节点和信号输出端，被配置为根据下拉节点的电平对上拉节点和信号输出端进行下拉。
  4. 根据权利要求1-3任一项所述的移位寄存器单元，还包括：辅助控制子电路(107)，连接到上拉节点(PU)、信号输出端和时钟信号选择子电路(104)的第二输出端，被配置为根据时钟信号选择子电路提供的时钟信号，辅助控制上拉节点和信号输出端的电平。
  5. 根据权利要求1-4任一项所述的移位寄存器单元，其中，
    输入子电路包括：输入晶体管(M1)，其控制极和第一极连接到信号输入端，第二极连接到上拉节点；
    输出子电路包括：输出晶体管(M3)，其控制极连接到上拉节点，第一极连接到时钟信号选择子电路的第一输出端，第二极连接到信号输出端；以及电容(C1)，其第一端连接到上拉节点，第二端连接到信号输出端；以及
    复位子电路(103)包括：第一复位晶体管(M2)，其控制极连接到复位端，第一极连接到上拉节点，第二极连接到第一电源端；以及第二复位晶体管(M4)，其控制极连接到复位端，第一极连接到信号输出端，第二极连接到第一电源端。
  6. 根据权利要求1-5任一项所述的移位寄存器单元，其中，
    时钟信号选择子电路(104)包括：第一选择晶体管(T1)，其控制极连接到第一控制端，第一极连接到第一时钟信号端，第二极连接到时钟信号选择子电路的第一输出端；第二选择晶体管(T2)，其控制极连接到第二控制端，第一极连接到第二时钟信号端，第二极连接到时钟信号选择子电路的第一输出端。
  7. 根据权利要求6所述的移位寄存器单元，其中，
    时钟信号选择子电路(104)还包括：第三选择晶体管(T3)，其控制极连接到第一控制端，第一极连接到第二时钟信号端，第二极连接到时钟信号选择子电路的第二输出端；第四选择晶体管(T4)，其控制极连接到第二控制端，第一极连接到第一时钟信号端，第二极连接到第三选择晶体管的第二极。
  8. 根据权利要求2所述的移位寄存器单元，其中，
    其中，下拉节点控制子电路(105)包括：第一下拉控制晶体管(M9)，其控制极和第一极连接到时钟信号选择子电路的第二输出端，第二极连接到下拉控制节点(PD_CN)；第二下拉控制晶体管(M5)，其控制极连接到下拉控制节点(PD_CN)，第一极连接到第一下拉控制晶体管(M9)的第一极，第二极连接到下拉节点；第三下拉控制晶体管(M8)，其控制极连接到上拉节点，第一极连接到下拉控制节点，第二极连接到第一电源端；以及第四下拉控制晶体管(M6)，其控制极连接到上拉节点，第一极连接到下拉节点，第二极连接到第一电源端。
  9. 根据权利要求3所述的移位寄存器单元，其中，
    下拉子电路(106)包括：第一下拉晶体管(M10)，其控制极连接到下拉节点，第一极连接到上拉节点，第二极连接到第一电源端；以及第二下拉晶体管(M11)，其控制极连接到下拉节点，第一极连接到信号输出端，第二极连接到第一电源端。
  10. 根据权利要求4所述的移位寄存器单元，其中，
    辅助控制子电路(107)包括：
    第一辅助控制晶体管(M13)，其控制极连接到时钟信号选择子电路的第二输出端，第一极连接到信号输入端，第二极连接到上拉节点；以及
    第二辅助控制晶体管(M12)，其控制极连接到时钟信号选择子电路的第二输出端，第一极连接到信号输出端，第二极连接到第一电源端。
  11. 一种栅极驱动电路，包括N级如权利要求1-10任一项所述的移位寄存器单元，其中，第k级移位寄存器单元被配置为扫描对应的栅线，其信号输出端经由与第k级对应的第一开关晶体管连接到第k+1级移位寄存器单元的信号输入端，并且还经由与第k级对应的第二开关晶体管连接到第k+2级移位寄存器单元的信号输入端,其中k≥3，N和k为整数；
    其信号输入端经由与第k级对应的第三开关晶体管连接到第k-1级移位寄存器单元的信号输出端，并且还经由与第k级对应的第四开关晶体管连接到第k-2级移位寄存器单元的输出端。
  12. 根据权利要求11所述的栅极驱动电路，其中，第一级和第二级移位寄存器单元被配置为哑移位寄存器单元；
    其中，第1级移位寄存器单元的信号输出端经由与第1级对应的第一开关晶体管连接到第2级移位寄存器单元的信号输入端，并且第1级移位寄存器单元的信号输入端接收帧起始信号STV；
    第2级移位寄存器单元的信号输入端还经由与第2级对应的第二开关晶体管接收帧起始信号STV。
  13. 根据权利要求11或12所述的栅极驱动电路，其中，
    第2j-1级移位寄存器单元的复位端经由与该第2j-1级对应的第五开关晶体管连接到第2j级移位寄存器单元的信号输出端，并且还经由与该第2j-1级对应的第六开关晶体管连接到第2j+1级移位寄存器单元的信号输出端；
    第2j级移位寄存器单元的复位端连接到第2j+1级移位寄存器单元的信号输出端，其中1≤j≤(N-1)/2，j为整数。
  14. 一种应用于权利要求11-13任一项所述的栅极驱动电路的驱动方法，包括：
    在2D显示模式下，向第一开关控制线输入第二电平而向第二开关控制线输入第一电平、从而将布置在相邻两级GOA单元之间的第一开关晶体管开启并且将布置在中间间隔一级的两级GOA单元之间的第二开关晶体管关断；
    向第一控制线和第三控制线输入第二电平，而向第二控制线和第四控制 线输入第一电平，从而使得相邻的两级GOA单元中选择输出的时钟信号分别为第一时钟信号和第二时钟信号；
    将帧启示信号输入第一级哑移位寄存器单元的信号输入端，将第一时钟信号和第二时钟信号分别输入到第一级哑移位寄存器单元的第一时钟信号端和第二时钟信号端，使得各级扫描移位寄存器单元向所连接的栅线依次顺序输出驱动信号。
  15. 根据权利要求14所述的驱动方法，还包括：
    在3D显示模式下，向第一开关控制线输入第一电平而向第二开关控制线输入第二电平，从而将布置在相邻两级GOA单元之间的第一开关晶体管关断，而将布置在中间间隔一级的两级GOA单元之间的第二开关晶体管开启；
    向第一控制线和第四控制线输入第二电平，而向第二控制线和第三控制线输入第一电平，从而使得每相邻的两级GOA单元选择输出的时钟信号相同，为第一时钟信号和第二时钟信号中的一个，而与之相邻的另两级GOA单元选择输出的时钟信号为第一时钟信号和第二时钟信号中的另一个；
    将帧启示信号输入第一级和第二级哑移位寄存器单元的信号输入端，将第一时钟信号和第二时钟信号分别输入到第一级哑移位寄存器单元的第一时钟信号端和第二时钟信号端，使得每相邻的两级移位寄存器单元的信号输入端接收的信号的时序相同，并且输出的信号的时序相同。
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