WO2018188272A1 - 显示装置及其goa电路 - Google Patents

显示装置及其goa电路 Download PDF

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Publication number
WO2018188272A1
WO2018188272A1 PCT/CN2017/102353 CN2017102353W WO2018188272A1 WO 2018188272 A1 WO2018188272 A1 WO 2018188272A1 CN 2017102353 W CN2017102353 W CN 2017102353W WO 2018188272 A1 WO2018188272 A1 WO 2018188272A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
layer
goa circuit
input
Prior art date
Application number
PCT/CN2017/102353
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English (en)
French (fr)
Inventor
石龙强
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US15/739,746 priority Critical patent/US10410564B2/en
Priority to JP2019554874A priority patent/JP6811340B2/ja
Priority to EP17905554.6A priority patent/EP3611764A4/en
Priority to KR1020197033297A priority patent/KR102257166B1/ko
Publication of WO2018188272A1 publication Critical patent/WO2018188272A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display device and a GOA thereof (Gate Driver on Array, array substrate row drive) circuit.
  • GOA Gate Driver on Array, array substrate row drive
  • GOA circuits usually use a thin film transistor with a top gate structure (Top gate IGZO).
  • TFT top gate structure
  • the source of the thin film transistor of the top gate structure and the gate, the drain, and the gate have no overlapping portions, and thus the parasitic capacitance of the thin film transistor is small.
  • the semiconductor layer of the thin film transistor Since the semiconductor layer of the thin film transistor has no light blocking by the gate, the semiconductor layer is greatly affected by the illumination, which in turn causes electrical failure of the semiconductor layer.
  • the technical problem to be solved by the present invention is to provide a display device and a GOA circuit thereof, which can avoid electrical failure of the semiconductor layer and avoid coupling effects of the metal light shielding layer.
  • a technical solution adopted by the present invention is to provide a GOA circuit including a plurality of thin film transistors disposed on a substrate, the thin film transistor including at least a metal light shielding layer and a semiconductor sequentially disposed on the substrate
  • the metal light shielding layer of the plurality of thin film transistors is input with a ground signal, and the metal light shielding layers of the plurality of thin film transistors are connected together;
  • the semiconductor layer is an IGZO layer, and the thin film transistor further comprises:
  • An insulating layer disposed on the substrate, the metal light shielding layer, and the IGZO layer;
  • a gate layer disposed on the insulating layer
  • An interlayer dielectric layer disposed on the gate layer and the insulating layer;
  • the source layer and the drain layer are disposed on the interlayer dielectric layer;
  • the interlayer dielectric layer and the insulating layer are provided with a first via hole and a second via hole, the source layer is connected to the IGZO layer through the first via hole, and the drain layer is connected to the IGZO layer through the second via hole.
  • a GOA circuit including a plurality of thin film transistors disposed on a substrate, the thin film transistors including at least a substrate disposed in sequence And a metal light shielding layer and a semiconductor layer, wherein the metal light shielding layers of the plurality of thin film transistors respectively input a ground signal.
  • a display device including a GOA circuit for generating a driving signal, the GOA circuit including a plurality of thin film transistors, the thin film transistor being disposed on a substrate
  • the thin film transistor includes at least a metal light shielding layer and a semiconductor layer which are sequentially disposed on the substrate, and the metal light shielding layers of the plurality of thin film transistors respectively input a ground signal.
  • the thin film transistor of the present invention comprises a metal light shielding layer and a semiconductor layer which are sequentially disposed on the substrate, and the metal light shielding layer is used for blocking the semiconductor layer, thereby avoiding the semiconductor layer electricity.
  • the metal light shielding layers of the plurality of thin film transistors are all input to the ground signal, which can avoid the coupling effect of the metal light shielding layer and ensure the normal output signal of the GOA circuit.
  • FIG. 1 is a circuit diagram of a GOA circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural view of the thin film transistor of FIG. 1;
  • FIG. 3 is a schematic waveform diagram of a scan signal in the prior art
  • FIG. 4 is a waveform diagram of a scan signal of the normal output in FIG. 1;
  • FIG. 5 is a schematic structural view of a display device according to an embodiment of the present invention.
  • FIG. 1 is a schematic circuit diagram of a GOA circuit according to an embodiment of the present invention
  • FIG. 2 is a schematic structural view of the thin film transistor of FIG.
  • the GOA circuit 10 of the present embodiment includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, and a sixth thin film transistor T6.
  • a seventh thin film transistor T7 an eighth thin film transistor T8, a ninth thin film transistor T9, a tenth thin film transistor T10, an eleventh thin film transistor T11, a twelfth thin film transistor T12, a thirteenth thin film transistor T13, and a fourteenth thin film transistor T14, the fifteenth thin film transistor T15, and the capacitor C.
  • the first end of the first thin film transistor T1 is input with the first control signal DCH
  • the second end of the first thin film transistor T1 is input with the second control signal ST(n-1)
  • the third end of the first thin film transistor T1 is respectively The first and second ends of the second thin film transistor T2, the second end of the third thin film transistor T3, the second end of the fourth thin film transistor T4, and one end of the capacitor C are connected.
  • the third end of the second thin film transistor T2 is connected to the first end of the fifth thin film transistor T5; the first end of the third thin film transistor T3 and the first end of the fourth thin film transistor T4 are input with the first clock signal CK(n),
  • the third terminal of the third thin film transistor T3 is connected to the GOA circuit of the next stage, and outputs the third control signal ST(n+1) to the GOA circuit of the next stage.
  • the third end of the fourth thin film transistor T4 outputs the scan signal G(n); the second end of the fifth thin film transistor T5 inputs the second clock signal XCK(n), and the third end of the fifth thin film transistor T5 is connected to the capacitor C.
  • the first end and the second end of the sixth thin film transistor T6 are input with a first control signal DCH, and the third end of the sixth thin film transistor T6 is connected to the first end of the seventh thin film transistor T7, the second end of the eighth thin film transistor T8, and a second end of the tenth thin film transistor T10; a second end of the seventh thin film transistor T7 and a second end of the ninth thin film transistor T9 are connected to the second end of the third thin film transistor T3, and the third end of the seventh thin film transistor T7 is input The first reference voltage V1.
  • the first end of the eighth thin film transistor T8, the first end of the tenth thin film transistor T10 and the first end of the twelfth thin film transistor T12 are connected to the first end of the sixth thin film transistor T6, and the third end of the eighth thin film transistor T8
  • the terminal is connected to the first end of the ninth thin film transistor T9, the second end of the thirteenth thin film transistor T13, the second end of the fourteenth thin film transistor T14, and the second end of the fifteenth thin film transistor T15;
  • the third end of the T9 is connected to the third end of the tenth thin film transistor T10 and the first end of the eleventh thin film transistor T11;
  • the second end of the eleventh thin film transistor T11 is connected to the second end of the twelfth thin film transistor T12 and
  • the second end of the third thin film transistor T3, the third end of the eleventh thin film transistor T11 and the third end of the fourteenth thin film transistor T14 are input with the second reference voltage V2.
  • the third end of the twelfth thin film transistor T12 is connected to the third end of the thirteenth thin film transistor T13 and the first end of the fourteenth thin film transistor T14; the first end of the thirteenth thin film transistor T13 is connected to the first thin film transistor T1
  • the third end of the fifteenth thin film transistor T15 is connected to the third end of the fifth thin film transistor T5, and the third end of the fifteenth thin film transistor T15 is input with the first reference voltage V1.
  • the ninth thin film transistor T9, the tenth thin film transistor T10, the eleventh thin film transistor T11, the twelfth thin film transistor T12, the thirteenth thin film transistor T13, the fourteenth thin film transistor T14, and the fifteenth thin film transistor T15 are all P type
  • the thin film transistor has a first terminal as a source, a second terminal as a gate, and a third terminal as a drain.
  • the GOA circuit 10 includes a plurality of thin film transistors disposed on a substrate.
  • the thin film transistor includes at least a metal light shielding layer and a semiconductor layer sequentially disposed on the substrate, and the metal light shielding layers of the plurality of thin film transistors are input with a ground signal Ground.
  • the GOA circuit 10 of the present embodiment includes 15 thin film transistors, and the structures of the 15 thin film transistors are the same. As shown in FIG. 2, each of the thin film transistors includes:
  • a metal light shielding layer 22 disposed on the substrate 21;
  • IGZO indium gallium zinc Oxide, indium gallium zinc oxide
  • the insulating layer 24 is disposed on the substrate 21, the metal light shielding layer 22, and the IGZO layer 23;
  • ILD interlayer dielectric layer
  • the source layer 27 and the drain layer 28 are disposed on the interlayer dielectric layer 26;
  • the interlayer dielectric layer 26 and the insulating layer 24 are provided with a first via hole 261 and a second via hole 262.
  • the source layer 27 is connected to the IGZO layer 23 through the first via hole 261, and the drain layer 28 passes through the second via hole 262. Connected to the IGZO layer 23.
  • the metal light shielding layer 22 is disposed on the light incident surface of the IGZO layer 23, and thus the metal light shielding layer 22 is used to block the IGZO layer 23 to prevent the IGZO layer 23 from causing electrical failure due to illumination effects.
  • the metal light shielding layer and the gate layer, the metal light shielding layer and the source layer, and the metal light shielding layer and the drain layer can each form a coupling capacitance, so the waveform of the output scan signal of the prior art GOA circuit is coupled.
  • the effect of the effect causes the waveform of the scan signal to be distorted, as shown in Figure 3.
  • the metal light shielding layers of the plurality of thin film transistors of the present embodiment are all input with the ground signal Ground, that is, the metal light shielding layers 22 of the 15 thin film transistors are all input with the ground signal Ground, and the metal light shielding layer 22 cannot store the electric charge. Therefore, the metal light shielding layer 22 and the gate layer 25, the metal light shielding layer 22 and the source layer 27, and the metal light shielding layer 22 and the drain layer 28 cannot form a coupling capacitance, thereby ensuring that the GOA circuit 10 normally outputs the scanning signal G(n).
  • the waveform of the scanning signal G(n) is as shown in FIG.
  • the metal light shielding layers of the plurality of thin film transistors are connected together, that is, the metal light shielding layers 22 of the 15 thin film transistors are connected together, and grounded, and then input to the ground signal Ground, as shown in FIG.
  • Metal shading of the ninth thin film transistor T9, the tenth thin film transistor T10, the eleventh thin film transistor T11, the twelfth thin film transistor T12, the thirteenth thin film transistor T13, the fourteenth thin film transistor T14, and the fifteenth thin film transistor T15 Layer 22 is both grounded.
  • the thin film transistor of the present embodiment is provided with a metal light shielding layer 22 on the substrate for blocking the IGZO layer 23 of the thin film transistor, thereby preventing electrical failure of the IGZO layer 23; the metal light shielding layer 22 of the plurality of thin film transistors
  • the ground signal is input, and the coupling effect of the metal light shielding layer and the gate layer, the drain layer or the source layer can be avoided, and the GOA circuit 10 can normally output a signal.
  • the present invention also provides a display device 50 including a display area 51 for generating a drive signal and a GOA circuit 52 for driving display of the display area 51, wherein the GOA circuit 52 is the above embodiment
  • the described GOA circuit 10 will not be described here.
  • the thin film transistor of the present invention is provided with a metal light shielding layer on the substrate for blocking the semiconductor layer of the thin film transistor, thereby avoiding electrical failure of the semiconductor layer; the metal light shielding layers of the plurality of thin film transistors are input to the ground.
  • the signal can avoid the coupling effect of the metal light shielding layer and ensure the normal output signal of the GOA circuit.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Shift Register Type Memory (AREA)

Abstract

提供一种显示装置及其阵列基板行驱动（GOA）电路。该GOA电路包括多个薄膜晶体管，所述薄膜晶体管设置在基板（21）上，所述薄膜晶体管至少包括依次设置在所述基板（21）上的金属遮光层（22）和半导体层（23），所述多个薄膜晶体管的金属遮光层（23）均输入地信号。该显示装置及其GOA电路能够避免金属遮光层产生耦合效应，保证GOA电路正常输出信号。

Description

显示装置及其GOA电路
【技术领域】
本发明涉及显示技术领域，特别是涉及一种显示装置及其GOA（Gate Driver on Array，阵列基板行驱动）电路。
【背景技术】
目前，GOA电路通常采用顶栅结构的薄膜晶体管（Top gate IGZO TFT），其中顶栅结构的薄膜晶体管的源极和栅极、漏极和栅极均没有重叠部分，因此薄膜晶体管的寄生电容很小。
由于薄膜晶体管的半导体层没有栅极的挡光，因此半导体层受到光照的影响非常严重，进而导致半导体层电性失效。
【发明内容】
本发明主要解决的技术问题是提供一种显示装置及其GOA电路，能够避免半导体层电性失效，并且避免金属遮光层产生耦合效应。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种GOA电路，其包括多个薄膜晶体管，薄膜晶体管设置在基板上，薄膜晶体管至少包括依次设置在基板上的金属遮光层和半导体层，多个薄膜晶体管的金属遮光层均输入地信号，多个薄膜晶体管的金属遮光层连接在一起；半导体层为IGZO层，薄膜晶体管进一步包括：
绝缘层，设置在基板、金属遮光层以及IGZO层上；
栅极层，设置在绝缘层上；
层间介质层，设置在栅极层和绝缘层上；
源极层和漏极层设置在层间介质层上；
在层间介质层和绝缘层设置有第一通孔和第二通孔，源极层通过第一通孔与IGZO层连接，漏极层通过第二通孔与IGZO层连接。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种GOA电路，其包括多个薄膜晶体管，所述薄膜晶体管设置在基板上，所述薄膜晶体管至少包括依次设置在所述基板上的金属遮光层和半导体层，所述多个薄膜晶体管的金属遮光层均输入地信号。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种显示装置，其包括用于产生驱动信号的GOA电路，所述GOA电路包括多个薄膜晶体管，所述薄膜晶体管设置在基板上，所述薄膜晶体管至少包括依次设置在所述基板上的金属遮光层和半导体层，所述多个薄膜晶体管的金属遮光层均输入地信号。
本发明的有益效果是：区别于现有技术的情况，本发明的薄膜晶体管包括依次设置在基板上的金属遮光层和半导体层，金属遮光层用于为半导体层挡光，进而避免半导体层电性失效；多个薄膜晶体管的金属遮光层均输入地信号，能够避免金属遮光层产生耦合效应，保证GOA电路正常输出信号。
【附图说明】
图1是本发明一实施例的GOA电路的电路示意图；
图2是图1中薄膜晶体管的结构示意图；
图3是现有技术中扫描信号的波形示意图；
图4是图1中正常输出的扫描信号的波形示意图；
图5是本发明一实施例的显示装置的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1-2所示，图1是本发明一实施例的GOA电路的电路示意图；图2是图1中薄膜晶体管的结构示意图。如图1所示，本实施例的GOA电路10包括第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12、第十三薄膜晶体管T13、第十四薄膜晶体管T14、第十五薄膜晶体管T15以及电容C。
其中，第一薄膜晶体管T1的第一端输入第一控制信号DCH，第一薄膜晶体管T1的第二端输入第二控制信号ST（n-1），第一薄膜晶体管T1的第三端分别与第二薄膜晶体管T2的第一端和第二端、第三薄膜晶体管T3的第二端、第四薄膜晶体管T4的第二端以及电容C的一端连接。第二薄膜晶体管T2的第三端与第五薄膜晶体管T5的第一端连接；第三薄膜晶体管T3的第一端和第四薄膜晶体管T4的第一端输入第一时钟信号CK（n），第三薄膜晶体管T3的第三端连接下一级的GOA电路，以向下一级的GOA电路输出第三控制信号ST（n+1）。
第四薄膜晶体管T4的第三端输出扫描信号G（n）；第五薄膜晶体管T5的第二端输入第二时钟信号XCK（n），第五薄膜晶体管T5的第三端连接电容C的另一端和第四薄膜晶体管T4的第三端。
第六薄膜晶体管T6的第一端和第二端输入第一控制信号DCH，第六薄膜晶体管T6的第三端连接第七薄膜晶体管T7的第一端、第八薄膜晶体管T8的第二端和第十薄膜晶体管T10的第二端；第七薄膜晶体管T7的第二端和第九薄膜晶体管T9的第二端连接第三薄膜晶体管T3的第二端，第七薄膜晶体管T7的第三端输入第一参考电压V1。
第八薄膜晶体管T8的第一端、第十薄膜晶体管T10的第一端和第十二薄膜晶体管T12的第一端与第六薄膜晶体管T6的第一端连接，第八薄膜晶体管T8的第三端与第九薄膜晶体管T9的第一端、第十三薄膜晶体管T13的第二端、第十四薄膜晶体管T14的第二端以及第十五薄膜晶体管T15的第二端连接；第九薄膜晶体管T9的第三端与第十薄膜晶体管T10的第三端和第十一薄膜晶体管T11的第一端连接；第十一薄膜晶体管T11的第二端连接第十二薄膜晶体管T12的第二端和第三薄膜晶体管T3的第二端，第十一薄膜晶体管T11的第三端和第十四薄膜晶体管T14的第三端输入第二参考电压V2。
第十二薄膜晶体管T12的第三端与第十三薄膜晶体管T13的第三端和第十四薄膜晶体管T14的第一端连接；第十三薄膜晶体管T13的第一端连接第一薄膜晶体管T1的第三端；第十五薄膜晶体管T15的第一端连接第五薄膜晶体管T5的第三端，第十五薄膜晶体管T15的第三端输入第一参考电压V1。
其中，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12、第十三薄膜晶体管T13、第十四薄膜晶体管T14以及第十五薄膜晶体管T15均为P型薄膜晶体管，第一端为源极，第二端为栅极，第三端为漏极。在其他实施例中，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12、第十三薄膜晶体管T13、第十四薄膜晶体管T14以及第十五薄膜晶体管T15均为N型薄膜晶体管，在此不再赘述。
其中，GOA电路10包括多个薄膜晶体管，薄膜晶体管设置在基板上，薄膜晶体管至少包括依次设置在基板上的金属遮光层和半导体层，多个薄膜晶体管的金属遮光层均输入地信号Ground。
本实施例GOA电路10包括15个薄膜晶体管，15个薄膜晶体管的结构相同，如图2所示，每个薄膜晶体管均包括：
设置在基板21上的金属遮光层22；
IGZO（indium gallium zinc oxide，铟镓锌氧化物）层23，即半导体层，设置在金属遮光层22上；
绝缘层24，设置在基板21、金属遮光层22以及IGZO层23上；
栅极层25，设置在绝缘层24上；
层间介质层（ILD）26，设置在栅极层25和绝缘层24上；
源极层27和漏极层28设置在层间介质层26上；
在层间介质层26和绝缘层24设置有第一通孔261和第二通孔262，源极层27通过第一通孔261与IGZO层23连接，漏极层28通过第二通孔262与IGZO层23连接。
其中，金属遮光层22设置在IGZO层23的入光面，因此金属遮光层22用于为IGZO层23挡光，以避免IGZO层23在光照影响导致电性失效。
在现有技术中，金属遮光层和栅极层、金属遮光层和源极层以及金属遮光层和漏极层均可形成耦合电容，因此现有技术的GOA电路输出扫描信号的波形会受到耦合效应的影响，导致扫描信号的波形变形，如图3所示。
相对于现有技术的GOA电路，本实施例的多个薄膜晶体管的金属遮光层均输入地信号Ground，即15个薄膜晶体管的金属遮光层22均输入地信号Ground，金属遮光层22不能存储电荷，因此金属遮光层22和栅极层25、金属遮光层22和源极层27以及金属遮光层22和漏极层28均不能形成耦合电容，进而保证GOA电路10正常输出扫描信号G（n），扫描信号G（n）的波形图如图4所示。
本实施例多个薄膜晶体管的金属遮光层连接在一起，即15个薄膜晶体管的金属遮光层22连接在一起，并且接地，进而输入地信号Ground，如图1所示。具体地，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12、第十三薄膜晶体管T13、第十四薄膜晶体管T14以及第十五薄膜晶体管T15的金属遮光层22均接地。
因此，本实施例的薄膜晶体管在基板上的设置有金属遮光层22，用于为薄膜晶体管的IGZO层23挡光，进而避免IGZO层23的电性失效；多个薄膜晶体管的金属遮光层22均输入地信号，能够避免金属遮光层和栅极层、漏极层或者源极层产生耦合效应，保证GOA电路10正常输出信号。
本发明还提供一种显示装置，该显示装置50包括显示区域51和GOA电路52，GOA电路52用于产生驱动信号，驱动信号用于驱动显示区域51显示，其中GOA电路52为上述实施例所描述的GOA电路10，在此不再赘述。
综上所述，本发明的薄膜晶体管在基板上的设置有金属遮光层，用于为薄膜晶体管的半导体层挡光，进而避免半导体层电性失效；多个薄膜晶体管的金属遮光层均输入地信号，能够避免金属遮光层产生耦合效应，保证GOA电路正常输出信号。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种GOA电路，其中，所述GOA电路包括多个薄膜晶体管，所述薄膜晶体管设置在基板上，所述薄膜晶体管至少包括依次设置在所述基板上的金属遮光层和半导体层，所述多个薄膜晶体管的金属遮光层均输入地信号，所述多个薄膜晶体管的金属遮光层连接在一起；
    所述半导体层为IGZO层，所述薄膜晶体管进一步包括：
    绝缘层，设置在所述基板、所述金属遮光层以及所述IGZO层上；
    栅极层，设置在所述绝缘层上；
    层间介质层，设置在所述栅极层和所述绝缘层上；
    源极层和漏极层设置在所述层间介质层上；
    在所述层间介质层和所述绝缘层设置有第一通孔和第二通孔，所述源极层通过所述第一通孔与所述IGZO层连接，所述漏极层通过所述第二通孔与所述IGZO层连接。
  2. 根据权利要求1所述的GOA电路，其中，所述GOA电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、第十三薄膜晶体管、第十四薄膜晶体管、第十五薄膜晶体管以及电容；
    所述第一薄膜晶体管的第一端输入第一控制信号，所述第一薄膜晶体管的第二端输入第二控制信号，所述第一薄膜晶体管的第三端分别与所述第二薄膜晶体管的第一端和第二端、所述第三薄膜晶体管的第二端、所述第四薄膜晶体管的第二端以及所述电容的一端连接；
    所述第二薄膜晶体管的第三端与所述第五薄膜晶体管的第一端连接；
    所述第三薄膜晶体管的第一端和所述第四薄膜晶体管的第一端输入第一时钟信号，所述第三薄膜晶体管的第三端连接下一级的GOA电路；
    所述第四薄膜晶体管的第三端输出扫描信号；
    所述第五薄膜晶体管的第二端输入第二时钟信号，所述第五薄膜晶体管的第三端连接所述电容的另一端和所述第四薄膜晶体管的第三端；
    所述第六薄膜晶体管的第一端和第二端输入所述第一控制信号，所述第六薄膜晶体管的第三端连接所述第七薄膜晶体管的第一端、所述第八薄膜晶体管的第二端和所述第十薄膜晶体管的第二端；
    所述第七薄膜晶体管的第二端和所述第九薄膜晶体管的第二端连接所述第三薄膜晶体管的第二端，所述第七薄膜晶体管的第三端输入第一参考电压；
    所述第八薄膜晶体管的第一端、所述第十薄膜晶体管的第一端和所述第十二薄膜晶体管的第一端与所述第六薄膜晶体管的第一端连接，所述第八薄膜晶体管的第三端与所述第九薄膜晶体管的第一端、所述第十三薄膜晶体管的第二端、所述第十四薄膜晶体管的第二端以及所述第十五薄膜晶体管的第二端连接；
    所述第九薄膜晶体管的第三端与所述第十薄膜晶体管的第三端和所述第十一薄膜晶体管的第一端连接；
    所述第十一薄膜晶体管的第二端连接所述第十二薄膜晶体管的第二端和所述第三薄膜晶体管的第二端，所述第十一薄膜晶体管的第三端和所述第十四薄膜晶体管的第三端输入第二参考电压；
    所述第十二薄膜晶体管的第三端与所述第十三薄膜晶体管的第三端和所述第十四薄膜晶体管的第一端连接；
    所述第十三薄膜晶体管的第一端连接所述第一薄膜晶体管的第三端；
    所述第十五薄膜晶体管的第一端连接所述第五薄膜晶体管的第三端，所述第十五薄膜晶体管的第三端输入所述第一参考电压。
  3. 根据权利要求2所述的GOA电路，其中，所述第一至第十五薄膜晶体管的金属遮光层均接地。
  4. 根据权利要求2所述的GOA电路，其中，所述第一至第十五薄膜晶体管均为P型薄膜晶体管，所述第一端为源极，所述第二端为栅极，所述第三端为漏极。
  5. 根据权利要求2所述的GOA电路，其中，所述第一至第十五薄膜晶体管均为N型薄膜晶体管。
  6. 一种GOA电路，其中，所述GOA电路包括多个薄膜晶体管，所述薄膜晶体管设置在基板上，所述薄膜晶体管至少包括依次设置在所述基板上的金属遮光层和半导体层，所述多个薄膜晶体管的金属遮光层均输入地信号。
  7. 根据权利要求6所述的GOA电路，其中，所述多个薄膜晶体管的金属遮光层连接在一起。
  8. 根据权利要求6所述的GOA电路，其中，所述半导体层为IGZO层，所述薄膜晶体管进一步包括：
    绝缘层，设置在所述基板、所述金属遮光层以及所述IGZO层上；
    栅极层，设置在所述绝缘层上；
    层间介质层，设置在所述栅极层和所述绝缘层上；
    源极层和漏极层设置在所述层间介质层上；
    在所述层间介质层和所述绝缘层设置有第一通孔和第二通孔，所述源极层通过所述第一通孔与所述IGZO层连接，所述漏极层通过所述第二通孔与所述IGZO层连接。
  9. 根据权利要求8所述的GOA电路，其中，所述GOA电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、第十三薄膜晶体管、第十四薄膜晶体管、第十五薄膜晶体管以及电容；
    所述第一薄膜晶体管的第一端输入第一控制信号，所述第一薄膜晶体管的第二端输入第二控制信号，所述第一薄膜晶体管的第三端分别与所述第二薄膜晶体管的第一端和第二端、所述第三薄膜晶体管的第二端、所述第四薄膜晶体管的第二端以及所述电容的一端连接；
    所述第二薄膜晶体管的第三端与所述第五薄膜晶体管的第一端连接；
    所述第三薄膜晶体管的第一端和所述第四薄膜晶体管的第一端输入第一时钟信号，所述第三薄膜晶体管的第三端连接下一级的GOA电路；
    所述第四薄膜晶体管的第三端输出扫描信号；
    所述第五薄膜晶体管的第二端输入第二时钟信号，所述第五薄膜晶体管的第三端连接所述电容的另一端和所述第四薄膜晶体管的第三端；
    所述第六薄膜晶体管的第一端和第二端输入所述第一控制信号，所述第六薄膜晶体管的第三端连接所述第七薄膜晶体管的第一端、所述第八薄膜晶体管的第二端和所述第十薄膜晶体管的第二端；
    所述第七薄膜晶体管的第二端和所述第九薄膜晶体管的第二端连接所述第三薄膜晶体管的第二端，所述第七薄膜晶体管的第三端输入第一参考电压；
    所述第八薄膜晶体管的第一端、所述第十薄膜晶体管的第一端和所述第十二薄膜晶体管的第一端与所述第六薄膜晶体管的第一端连接，所述第八薄膜晶体管的第三端与所述第九薄膜晶体管的第一端、所述第十三薄膜晶体管的第二端、所述第十四薄膜晶体管的第二端以及所述第十五薄膜晶体管的第二端连接；
    所述第九薄膜晶体管的第三端与所述第十薄膜晶体管的第三端和所述第十一薄膜晶体管的第一端连接；
    所述第十一薄膜晶体管的第二端连接所述第十二薄膜晶体管的第二端和所述第三薄膜晶体管的第二端，所述第十一薄膜晶体管的第三端和所述第十四薄膜晶体管的第三端输入第二参考电压；
    所述第十二薄膜晶体管的第三端与所述第十三薄膜晶体管的第三端和所述第十四薄膜晶体管的第一端连接；
    所述第十三薄膜晶体管的第一端连接所述第一薄膜晶体管的第三端；
    所述第十五薄膜晶体管的第一端连接所述第五薄膜晶体管的第三端，所述第十五薄膜晶体管的第三端输入所述第一参考电压。
  10. 根据权利要求9所述的GOA电路，其中，所述第一至第十五薄膜晶体管的金属遮光层均接地。
  11. 根据权利要求9所述的GOA电路，其中，所述第一至第十五薄膜晶体管均为P型薄膜晶体管，所述第一端为源极，所述第二端为栅极，所述第三端为漏极。
  12. 根据权利要求9所述的GOA电路，其中，所述第一至第十五薄膜晶体管均为N型薄膜晶体管。
  13. 一种显示装置，其中，所述显示装置包括用于产生驱动信号的GOA电路，所述GOA电路包括多个薄膜晶体管，所述薄膜晶体管设置在基板上，所述薄膜晶体管至少包括依次设置在所述基板上的金属遮光层和半导体层，所述多个薄膜晶体管的金属遮光层均输入地信号。
  14. 根据权利要求13所述的显示装置，其中，所述多个薄膜晶体管的金属遮光层连接在一起。
  15. 根据权利要求13所述的显示装置，其中，所述半导体层为IGZO层，所述薄膜晶体管进一步包括：
    绝缘层，设置在所述基板、所述金属遮光层以及所述IGZO层上；
    栅极层，设置在所述绝缘层上；
    层间介质层，设置在所述栅极层和所述绝缘层上；
    源极层和漏极层设置在所述层间介质层上；
    在所述层间介质层和所述绝缘层设置有第一通孔和第二通孔，所述源极层通过所述第一通孔与所述IGZO层连接，所述漏极层通过所述第二通孔与所述IGZO层连接。
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