CN107134460B - 显示装置及其goa电路 - Google Patents

显示装置及其goa电路 Download PDF

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CN107134460B
CN107134460B CN201710233389.8A CN201710233389A CN107134460B CN 107134460 B CN107134460 B CN 107134460B CN 201710233389 A CN201710233389 A CN 201710233389A CN 107134460 B CN107134460 B CN 107134460B
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film transistor
tft
thin film
layer
connects
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CN107134460A (zh
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石龙强
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to KR1020197033297A priority patent/KR102257166B1/ko
Priority to PCT/CN2017/102353 priority patent/WO2018188272A1/zh
Priority to US15/739,746 priority patent/US10410564B2/en
Priority to EP17905554.6A priority patent/EP3611764A4/en
Priority to JP2019554874A priority patent/JP6811340B2/ja
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
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    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • G09G2310/0264—Details of driving circuits
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    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract

本发明公开了一种显示装置及其GOA电路。该GOA电路包括多个薄膜晶体管，所述薄膜晶体管设置在基板上，所述薄膜晶体管至少包括依次设置在所述基板上的金属遮光层和半导体层，所述多个薄膜晶体管的金属遮光层均输入地信号。本发明能够避免金属遮光层产生耦合效应，保证GOA电路正常输出信号。

Description

显示装置及其GOA电路
技术领域
本发明涉及显示技术领域，特别是涉及一种显示装置及其GOA(Gate Driver onArray，阵列基板行驱动)电路。
背景技术
目前，GOA电路通常采用顶栅结构的薄膜晶体管(Top gate IGZO TFT)，其中顶栅结构的薄膜晶体管的源极和栅极、漏极和栅极均没有重叠部分，因此薄膜晶体管的寄生电容很小。
由于薄膜晶体管的半导体层没有栅极的挡光，因此半导体层受到光照的影响非常严重，进而导致半导体层电性失效。
发明内容
本发明主要解决的技术问题是提供一种显示装置及其GOA电路，能够避免半导体层电性失效，并且避免金属遮光层产生耦合效应。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种GOA电路，其包括多个薄膜晶体管，所述薄膜晶体管设置在基板上，所述薄膜晶体管至少包括依次设置在所述基板上的金属遮光层和半导体层，所述多个薄膜晶体管的金属遮光层均输入地信号。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种显示装置，其包括用于产生驱动信号的GOA电路，所述GOA电路包括多个薄膜晶体管，所述薄膜晶体管设置在基板上，所述薄膜晶体管至少包括依次设置在所述基板上的金属遮光层和半导体层，所述多个薄膜晶体管的金属遮光层均输入地信号。
本发明的有益效果是：区别于现有技术的情况，本发明的薄膜晶体管包括依次设置在基板上的金属遮光层和半导体层，金属遮光层用于为半导体层挡光，进而避免半导体层电性失效；多个薄膜晶体管的金属遮光层均输入地信号，能够避免金属遮光层产生耦合效应，保证GOA电路正常输出信号。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要采用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明一实施例的GOA电路的电路示意图；
图2是图1中薄膜晶体管的结构示意图；
图3是现有技术中扫描信号的波形示意图；
图4是图1中正常输出的扫描信号的波形示意图；
图5是本发明一实施例的显示装置的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1-2所示，图1是本发明一实施例的GOA电路的电路示意图；图2是图1中薄膜晶体管的结构示意图。如图1所示，本实施例的GOA电路10包括第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12、第十三薄膜晶体管T13、第十四薄膜晶体管T14、第十五薄膜晶体管T15以及电容C。
其中，第一薄膜晶体管T1的第一端输入第一控制信号DCH，第一薄膜晶体管T1的第二端输入第二控制信号ST(n-1)，第一薄膜晶体管T1的第三端分别与第二薄膜晶体管T2的第一端和第二端、第三薄膜晶体管T3的第二端、第四薄膜晶体管T4的第二端以及电容C的一端连接。第二薄膜晶体管T2的第三端与第五薄膜晶体管T5的第一端连接；第三薄膜晶体管T3的第一端和第四薄膜晶体管T4的第一端输入第一时钟信号CK(n)，第三薄膜晶体管T3的第三端连接下一级的GOA电路，以向下一级的GOA电路输出第三控制信号ST(n+1)。
第四薄膜晶体管T4的第三端输出扫描信号G(n)；第五薄膜晶体管T5的第二端输入第二时钟信号XCK(n)，第五薄膜晶体管T5的第三端连接电容C的另一端和第四薄膜晶体管T4的第三端。
第六薄膜晶体管T6的第一端和第二端输入第一控制信号DCH，第六薄膜晶体管T6的第三端连接第七薄膜晶体管T7的第一端、第八薄膜晶体管T8的第二端和第十薄膜晶体管T10的第二端；第七薄膜晶体管T7的第二端和第九薄膜晶体管T9的第二端连接第三薄膜晶体管T3的第二端，第七薄膜晶体管T7的第三端输入第一参考电压V1。
第八薄膜晶体管T8的第一端、第十薄膜晶体管T10的第一端和第十二薄膜晶体管T12的第一端与第六薄膜晶体管T6的第一端连接，第八薄膜晶体管T8的第三端与第九薄膜晶体管T9的第一端、第十三薄膜晶体管T13的第二端、第十四薄膜晶体管T14的第二端以及第十五薄膜晶体管T15的第二端连接；第九薄膜晶体管T9的第三端与第十薄膜晶体管T10的第三端和第十一薄膜晶体管T11的第一端连接；第十一薄膜晶体管T11的第二端连接第十二薄膜晶体管T12的第二端和第三薄膜晶体管T3的第二端，第十一薄膜晶体管T11的第三端和第十四薄膜晶体管T14的第三端输入第二参考电压V2。
第十二薄膜晶体管T12的第三端与第十三薄膜晶体管T13的第三端和第十四薄膜晶体管T14的第一端连接；第十三薄膜晶体管T13的第一端连接第一薄膜晶体管T1的第三端；第十五薄膜晶体管T15的第一端连接第五薄膜晶体管T5的第三端，第十五薄膜晶体管T15的第三端输入第一参考电压V1。
其中，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12、第十三薄膜晶体管T13、第十四薄膜晶体管T14以及第十五薄膜晶体管T15均为P型薄膜晶体管，第一端为源极，第二端为栅极，第三端为漏极。在其他实施例中，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12、第十三薄膜晶体管T13、第十四薄膜晶体管T14以及第十五薄膜晶体管T15均为N型薄膜晶体管，在此不再赘述。
其中，GOA电路10包括多个薄膜晶体管，薄膜晶体管设置在基板上，薄膜晶体管至少包括依次设置在基板上的金属遮光层和半导体层，多个薄膜晶体管的金属遮光层均输入地信号Ground。
本实施例GOA电路10包括15个薄膜晶体管，15个薄膜晶体管的结构相同，如图2所示，每个薄膜晶体管均包括：
设置在基板21上的金属遮光层22；
IGZO(indium gallium zinc oxide，铟镓锌氧化物)层23，即半导体层，设置在金属遮光层22上；
绝缘层24，设置在基板21、金属遮光层22以及IGZO层23上；
栅极层25，设置在绝缘层24上；
层间介质层(ILD)26，设置在栅极层25和绝缘层24上；
源极层27和漏极层28设置在层间介质层26上；
在层间介质层26和绝缘层24设置有第一通孔261和第二通孔262，源极层27通过第一通孔261与IGZO层23连接，漏极层28通过第二通孔262与IGZO层23连接。
其中，金属遮光层22设置在IGZO层23的入光面，因此金属遮光层22用于为IGZO层23挡光，以避免IGZO层23在光照影响导致电性失效。
在现有技术中，金属遮光层和栅极层、金属遮光层和源极层以及金属遮光层和漏极层均可形成耦合电容，因此现有技术的GOA电路输出扫描信号的波形会受到耦合效应的影响，导致扫描信号的波形变形，如图3所示。
相对于现有技术的GOA电路，本实施例的多个薄膜晶体管的金属遮光层均输入地信号Ground，即15个薄膜晶体管的金属遮光层22均输入地信号Ground，金属遮光层22不能存储电荷，因此金属遮光层22和栅极层25、金属遮光层22和源极层27以及金属遮光层22和漏极层28均不能形成耦合电容，进而保证GOA电路10正常输出扫描信号G(n)，扫描信号G(n)的波形图如图4所示。
本实施例多个薄膜晶体管的金属遮光层连接在一起，即15个薄膜晶体管的金属遮光层22连接在一起，并且接地，进而输入地信号Ground，如图1所示。具体地，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11、第十二薄膜晶体管T12、第十三薄膜晶体管T13、第十四薄膜晶体管T14以及第十五薄膜晶体管T15的金属遮光层22均接地。
因此，本实施例的薄膜晶体管在基板上的设置有金属遮光层22，用于为薄膜晶体管的IGZO层23挡光，进而避免IGZO层23的电性失效；多个薄膜晶体管的金属遮光层22均输入地信号，能够避免金属遮光层和栅极层、漏极层或者源极层产生耦合效应，保证GOA电路10正常输出信号。
本发明还提供一种显示装置，该显示装置50包括显示区域51和GOA电路52，GOA电路52用于产生驱动信号，驱动信号用于驱动显示区域51显示，其中GOA电路52为上述实施例所描述的GOA电路10，在此不再赘述。
综上所述，本发明的薄膜晶体管在基板上的设置有金属遮光层，用于为薄膜晶体管的半导体层挡光，进而避免半导体层电性失效；多个薄膜晶体管的金属遮光层均输入地信号，能够避免金属遮光层产生耦合效应，保证GOA电路正常输出信号。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (8)

1.一种GOA电路，其特征在于，所述GOA电路包括多个薄膜晶体管，所述薄膜晶体管设置在基板上，所述薄膜晶体管至少包括依次设置在所述基板上的金属遮光层和半导体层，多个所述薄膜晶体管的金属遮光层均输入地信号；
所述半导体层为IGZO层，所述薄膜晶体管进一步包括：
绝缘层，设置在所述基板、所述金属遮光层以及所述IGZO层上；
栅极层，设置在所述绝缘层上；
层间介质层，设置在所述栅极层和所述绝缘层上；
源极层和漏极层设置在所述层间介质层上；
在所述层间介质层和所述绝缘层设置有第一通孔和第二通孔，所述源极层通过所述第一通孔与所述IGZO层连接，所述漏极层通过所述第二通孔与所述IGZO层连接；
所述GOA电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、第十三薄膜晶体管、第十四薄膜晶体管、第十五薄膜晶体管以及电容；
所述第一薄膜晶体管的第一端输入第一控制信号，所述第一薄膜晶体管的第二端输入第二控制信号，所述第一薄膜晶体管的第三端分别与所述第二薄膜晶体管的第一端和第二端、所述第三薄膜晶体管的第二端、所述第四薄膜晶体管的第二端以及所述电容的一端连接；
所述第二薄膜晶体管的第三端与所述第五薄膜晶体管的第一端连接；
所述第三薄膜晶体管的第一端和所述第四薄膜晶体管的第一端输入第一时钟信号，所述第三薄膜晶体管的第三端连接下一级的GOA电路；
所述第四薄膜晶体管的第三端输出扫描信号；
所述第五薄膜晶体管的第二端输入第二时钟信号，所述第五薄膜晶体管的第三端连接所述电容的另一端和所述第四薄膜晶体管的第三端；
所述第六薄膜晶体管的第一端和第二端输入所述第一控制信号，所述第六薄膜晶体管的第三端连接所述第七薄膜晶体管的第一端、所述第八薄膜晶体管的第二端和所述第十薄膜晶体管的第二端；
所述第七薄膜晶体管的第二端和所述第九薄膜晶体管的第二端连接所述第三薄膜晶体管的第二端，所述第七薄膜晶体管的第三端输入第一参考电压；
所述第八薄膜晶体管的第一端、所述第十薄膜晶体管的第一端和所述第十二薄膜晶体管的第一端与所述第六薄膜晶体管的第一端连接，所述第八薄膜晶体管的第三端与所述第九薄膜晶体管的第一端、所述第十三薄膜晶体管的第二端、所述第十四薄膜晶体管的第二端以及所述第十五薄膜晶体管的第二端连接；
所述第九薄膜晶体管的第三端与所述第十薄膜晶体管的第三端和所述第十一薄膜晶体管的第一端连接；
所述第十一薄膜晶体管的第二端连接所述第十二薄膜晶体管的第二端和所述第三薄膜晶体管的第二端，所述第十一薄膜晶体管的第三端和所述第十四薄膜晶体管的第三端输入第二参考电压；
所述第十二薄膜晶体管的第三端与所述第十三薄膜晶体管的第三端和所述第十四薄膜晶体管的第一端连接；
所述第十三薄膜晶体管的第一端连接所述第一薄膜晶体管的第三端；
所述第十五薄膜晶体管的第一端连接所述第五薄膜晶体管的第三端，所述第十五薄膜晶体管的第三端输入所述第一参考电压。
2.根据权利要求1所述的GOA电路，其特征在于，多个所述薄膜晶体管的金属遮光层连接在一起。
3.根据权利要求1所述的GOA电路，其特征在于，所述第一至第十五薄膜晶体管的金属遮光层均接地。
4.根据权利要求1所述的GOA电路，其特征在于，所述第一至第十五薄膜晶体管均为P型薄膜晶体管，所述第一端为源极，所述第二端为栅极，所述第三端为漏极。
5.根据权利要求1所述的GOA电路，其特征在于，所述第一至第十五薄膜晶体管均为N型薄膜晶体管。
6.一种显示装置，其特征在于，所述显示装置包括用于产生驱动信号的GOA电路，所述GOA电路包括多个薄膜晶体管，所述薄膜晶体管设置在基板上，所述薄膜晶体管至少包括依次设置在所述基板上的金属遮光层和半导体层，多个所述薄膜晶体管的金属遮光层均输入地信号；
所述GOA电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管、第十二薄膜晶体管、第十三薄膜晶体管、第十四薄膜晶体管、第十五薄膜晶体管以及电容；
所述第一薄膜晶体管的第一端输入第一控制信号，所述第一薄膜晶体管的第二端输入第二控制信号，所述第一薄膜晶体管的第三端分别与所述第二薄膜晶体管的第一端和第二端、所述第三薄膜晶体管的第二端、所述第四薄膜晶体管的第二端以及所述电容的一端连接；
所述第二薄膜晶体管的第三端与所述第五薄膜晶体管的第一端连接；
所述第三薄膜晶体管的第一端和所述第四薄膜晶体管的第一端输入第一时钟信号，所述第三薄膜晶体管的第三端连接下一级的GOA电路；
所述第四薄膜晶体管的第三端输出扫描信号；
所述第五薄膜晶体管的第二端输入第二时钟信号，所述第五薄膜晶体管的第三端连接所述电容的另一端和所述第四薄膜晶体管的第三端；
所述第六薄膜晶体管的第一端和第二端输入所述第一控制信号，所述第六薄膜晶体管的第三端连接所述第七薄膜晶体管的第一端、所述第八薄膜晶体管的第二端和所述第十薄膜晶体管的第二端；
所述第七薄膜晶体管的第二端和所述第九薄膜晶体管的第二端连接所述第三薄膜晶体管的第二端，所述第七薄膜晶体管的第三端输入第一参考电压；
所述第八薄膜晶体管的第一端、所述第十薄膜晶体管的第一端和所述第十二薄膜晶体管的第一端与所述第六薄膜晶体管的第一端连接，所述第八薄膜晶体管的第三端与所述第九薄膜晶体管的第一端、所述第十三薄膜晶体管的第二端、所述第十四薄膜晶体管的第二端以及所述第十五薄膜晶体管的第二端连接；
所述第九薄膜晶体管的第三端与所述第十薄膜晶体管的第三端和所述第十一薄膜晶体管的第一端连接；
所述第十一薄膜晶体管的第二端连接所述第十二薄膜晶体管的第二端和所述第三薄膜晶体管的第二端，所述第十一薄膜晶体管的第三端和所述第十四薄膜晶体管的第三端输入第二参考电压；
所述第十二薄膜晶体管的第三端与所述第十三薄膜晶体管的第三端和所述第十四薄膜晶体管的第一端连接；
所述第十三薄膜晶体管的第一端连接所述第一薄膜晶体管的第三端；
所述第十五薄膜晶体管的第一端连接所述第五薄膜晶体管的第三端，所述第十五薄膜晶体管的第三端输入所述第一参考电压。
7.根据权利要求6所述的显示装置，其特征在于，多个所述薄膜晶体管的金属遮光层连接在一起。
8.根据权利要求6所述的显示装置，其特征在于，所述半导体层为IGZO层，所述薄膜晶体管进一步包括：
绝缘层，设置在所述基板、所述金属遮光层以及所述IGZO层上；
栅极层，设置在所述绝缘层上；
层间介质层，设置在所述栅极层和所述绝缘层上；
源极层和漏极层设置在所述层间介质层上；
在所述层间介质层和所述绝缘层设置有第一通孔和第二通孔，所述源极层通过所述第一通孔与所述IGZO层连接，所述漏极层通过所述第二通孔与所述IGZO层连接。
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