WO2018157523A1 - 高击穿电压的氮化镓高电子迁移率晶体管及其形成方法 - Google Patents

高击穿电压的氮化镓高电子迁移率晶体管及其形成方法 Download PDF

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WO2018157523A1
WO2018157523A1 PCT/CN2017/090232 CN2017090232W WO2018157523A1 WO 2018157523 A1 WO2018157523 A1 WO 2018157523A1 CN 2017090232 W CN2017090232 W CN 2017090232W WO 2018157523 A1 WO2018157523 A1 WO 2018157523A1
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layer
gallium nitride
sub
barrier layer
aluminum
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PCT/CN2017/090232
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English (en)
French (fr)
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李晨
闫发旺
张峰
赵倍吉
刘春雪
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上海新傲科技股份有限公司
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Priority to JP2019546957A priority Critical patent/JP6882503B2/ja
Priority to EP17898726.9A priority patent/EP3591708A4/en
Publication of WO2018157523A1 publication Critical patent/WO2018157523A1/zh
Priority to US16/559,284 priority patent/US11158702B2/en

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Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a gallium nitride high electron mobility transistor with high breakdown voltage and a method of forming the same.
  • Gallium nitride has received great attention because it meets the high-performance requirements of modern electronic technology for high temperature, high frequency, high voltage, high power and radiation resistance.
  • GaN-based high electron mobility transistor HEMT is a hot-spot technology that is currently developing vigorously in the world, and is also the core technology of key power electronics technology urgently needed in China's energy development.
  • the theoretical breakdown voltage of the GaN-based HEMT itself is very high, the current high-voltage capability of the GaN-based HEMT as a power switching device is far less than the theoretically calculated breakdown voltage value, which greatly limits its application in the field of high voltage and high power.
  • the main reason for the low breakdown voltage of GaN-based HEMT is the gate electric field concentration effect and the leakage of the buffer layer, especially the gate electric field concentration effect: after the device withstands the high voltage between the source and the drain in the off state, An end of the gate close to the drain generates an electric field peak to make the electric field distribution uneven, resulting in early breakdown of the device.
  • the method of field plate structure can increase the breakdown voltage to a certain extent, but due to lattice mismatch and thermal stress mismatch between metal and gallium nitride, defects and interface charge traps are additionally introduced, resulting in degradation of device quality and affecting device. Reliable and stable.
  • the technical problem to be solved by the present invention is to provide a gallium nitride high electron mobility transistor having a high breakdown voltage and a method of forming the same to increase the breakdown voltage of the high electron mobility transistor.
  • the present invention provides a gallium nitride high electron mobility transistor having a high breakdown voltage, comprising: a substrate; a gallium nitride channel layer on the substrate; and the gallium nitride a first barrier layer on the channel layer; a gate, a source and a drain on the first barrier layer, the source and the drain are respectively located on both sides of the gate; Surface of the first barrier layer between the gate and the drain a second barrier layer, the second barrier layer sidewall is connected to the gate side sidewall for generating two-dimensional hole gas.
  • the second barrier layer includes: a first sub-layer on a surface of the first barrier layer, a second sub-layer on a surface of the first sub-layer, and a surface on the second sub-layer
  • the third sub-layer, the first sub-layer and the second sub-layer constitute a heterojunction, and the third sub-layer is P-type doped.
  • the substrate and the gallium nitride channel layer further have a nucleation layer and a buffer layer on the surface of the nucleation layer.
  • an intervening layer is further disposed between the gallium nitride channel layer and the first barrier layer.
  • the material of the first sub-layer is aluminum nitride, gallium nitride or aluminum gallium nitride; the material of the second sub-layer is gallium nitride, aluminum nitride or aluminum gallium nitride;
  • the material of the third sub-layer is P-type gallium nitride, P-type aluminum nitride or P-type aluminum gallium nitride; the material of the nucleation layer is gallium nitride, aluminum nitride or aluminum gallium nitride; the buffer The material of the layer is gallium nitride; the material of the intercalation layer is aluminum nitride; the material of the first barrier layer is aluminum gallium nitride or aluminum indium nitride.
  • the present invention also provides a method for forming a high electron mobility transistor, comprising: providing a substrate; sequentially forming a gallium nitride channel layer on the substrate, and a first potential on the gallium nitride channel layer a second barrier layer is formed on the surface of the first barrier layer, the second barrier layer is used to generate a two-dimensional hole gas; and the second barrier layer is etched to expose the first barrier layer a portion of the surface of the barrier layer; a source, a drain, and a gate are respectively formed on the surface of the first barrier layer, the gate is located between the source and the second barrier layer, and the gate is The side sidewalls are connected to the sidewalls of the second barrier layer.
  • the second barrier layer includes a first sub-layer on a surface of the first barrier layer, a second sub-layer on a surface of the first sub-layer, and a surface on the surface of the second sub-layer
  • the third sub-layer, the first sub-layer and the second sub-layer constitute a heterojunction, and the third sub-layer is P-type doped.
  • the second barrier layer is etched by a reactive ion etching process or an inductively coupled plasma etching process.
  • the method further includes: forming a nucleation layer between the substrate and the gallium nitride channel layer and a buffer layer on a surface of the nucleation layer; and the first potential in the gallium nitride channel layer An intervening layer is formed between the barrier layers.
  • the material of the first sub-layer is aluminum nitride, gallium nitride or aluminum gallium nitride; the second sub- The material of the layer is gallium nitride, aluminum nitride or aluminum gallium nitride; the material of the third sub-layer is P-type gallium nitride, P-type aluminum nitride or P-type aluminum gallium nitride; the nucleation layer
  • the material of the buffer is gallium nitride, aluminum nitride or aluminum gallium nitride; the material of the buffer layer is gallium nitride; the material of the interposer layer is aluminum nitride; the material of the first barrier layer is nitrided Aluminum gallium or aluminum nitride indium.
  • the high electron mobility transistor of the present invention has a second barrier layer between the gate and the drain, the second barrier layer capable of generating two-dimensional hole gas to deplete the gate and drain drift region channels
  • the two-dimensional electron gas smoothes the channel electric field distribution, thereby increasing the breakdown voltage of the high electron mobility transistor.
  • FIG. 1 is a schematic flow chart of a method for forming a high breakdown voltage gallium nitride high electron mobility transistor according to an embodiment of the present invention
  • FIG. 2 to FIG. 6 are schematic cross-sectional views showing a process of forming a high breakdown voltage gallium nitride high electron mobility transistor according to an embodiment of the present invention.
  • FIG. 1 is a schematic flow chart of a method for forming a gallium nitride high electron mobility crystal having a high breakdown voltage according to an embodiment of the present invention.
  • the method for forming a gallium nitride high electron mobility crystal having a high breakdown voltage includes: step S101: providing a substrate; step S102: sequentially forming a gallium nitride channel layer on the substrate, located in the nitrogen a first barrier layer on the gallium channel layer; step S103: forming a second barrier layer on the surface of the first barrier layer, the second barrier layer for generating two-dimensional hole gas; step S104 Etching the second barrier layer to expose a portion of the surface of the first barrier layer; Step S105: forming a source, a drain, and a gate on the surface of the first barrier layer, respectively The pole is located between the source and the second barrier layer, and the gate side sidewall is connected to the second barrier layer sidewall.
  • FIG. 2 to FIG. 6 are cross-sectional structural diagrams showing a process of forming a high electron mobility crystal according to an embodiment of the present invention.
  • a substrate 200 is provided.
  • the material of the substrate 200 may be sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, nitride Aluminum or gallium nitride.
  • a channel layer 303 and a first barrier layer 305 on the channel layer 303 are sequentially formed on the substrate 200.
  • the channel layer 303 as a two-dimensional electron gas transmission channel, requires a higher crystal quality to reduce the background concentration in the channel, thereby reducing scattering and increasing the mobility of the two-dimensional electron gas.
  • An undoped group III metal nitride may be employed as the material of the channel layer 303, such as an undoped GaN layer.
  • the first barrier layer 305 and the channel layer 303 form a heterojunction, and the band discontinuity on the interface of the heterojunction and piezoelectric polarization and spontaneous polarization can generate a high concentration of two-dimensional Electronic gas.
  • the material of the first barrier layer 305 includes aluminum gallium nitride or aluminum aluminum nitride, and may be a single layer or a multilayer structure.
  • the method further includes forming a nucleation layer 301 and a buffer layer 302 on the surface of the nucleation layer 301 between the substrate 200 and the channel layer 303.
  • the main function of the nucleation layer 301 is to provide an effective nucleation center for the growth of the subsequent epitaxial layer, and at the same time, release the mismatch stress between the nucleation layer and the substrate through the formation of a large number of dislocations and defects, which can be significantly improved.
  • the material of the nucleation layer 301 includes GaN, AlN or AlGaN.
  • the buffer layer 302 has a higher resistivity to prevent electrons in the channel layer 303 from leaking to the buffer layer 302.
  • the buffer layer 302 is generally required to have a resistivity of 10 6 ⁇ cm or more.
  • the material of the buffer layer 302 may be gallium nitride, a deep level defect is generated in the buffer layer by ion implantation to form a high resistance, or a P-type impurity doping is introduced to compensate for a high resistance by mutually compensating with the N-type background concentration. .
  • the buffer layer 302 of high resistance can also be obtained in other ways.
  • the method further includes forming an interposer layer 304 between the channel layer 303 and the first barrier layer 305.
  • the insertion layer 304 is used to improve the crystal quality of the first barrier layer 305, and the material of the insertion layer 304 may be aluminum nitride.
  • the nucleation layer 301, the buffer layer 302, the channel layer 303, the interposer layer 304, and the first barrier layer 305 may be formed by an atomic layer deposition process, a metal organic chemical vapor deposition process, a molecular beam epitaxy process, or a hydride vapor phase epitaxy process. A deposition process is formed.
  • only a part of the structure in the nucleation layer 301, the buffer layer 302, or the insertion layer 304 may be formed.
  • a second barrier layer 400 is formed on the surface of the first barrier layer 305, and the second barrier layer 400 is used to generate two-dimensional hole gas.
  • the material of the second barrier layer 400 includes a Group III metal nitride for generating a two-dimensional hole gas, such as a P-type doped Group III metal nitride or a heterojunction capable of generating a two-dimensional hole gas.
  • a Group III metal nitride for generating a two-dimensional hole gas such as a P-type doped Group III metal nitride or a heterojunction capable of generating a two-dimensional hole gas.
  • the second barrier layer 400 includes a first sub-layer 401 on a surface of the first barrier layer 305, a second sub-layer 402 on a surface of the first sub-layer 401, and A third sub-layer 403 located on a surface of the second sub-layer 402, the first sub-layer 401 and the second sub-layer 402 constitute a heterojunction, and the third sub-layer 403 is P-type doped.
  • the material of the first sub-layer 401 is aluminum nitride, gallium nitride or aluminum gallium nitride; the material of the second sub-layer 402 is gallium nitride and aluminum nitride. Or aluminum gallium nitride; the material of the third sub-layer 403 is P-type gallium nitride, P-type aluminum nitride or P-type aluminum gallium nitride.
  • the first sub-layer 401 and the second sub-layer 402 form a heterojunction, by adjusting the ratio of the aluminum element and/or the gallium element in the first sub-layer 401 and the second sub-layer 402, so that the first Two-dimensional hole gas is generated at the interface of the sub-layer 401 and the second sub-layer 402.
  • the thickness of the first sub-layer 401 may be 1 nm to 100 nm; the thickness of the second sub-layer 402 may be 1 nm to 100 nm; and the thickness of the third sub-layer 403 may be 1 nm to 100 nm.
  • the second barrier layer 400 may be selected to form the second barrier layer 400 of a single layer or a multilayer structure such that the second barrier layer 400 is polarized at the spontaneous polarization or the external electrode.
  • Two-dimensional hole gas can be produced under the conditions.
  • the second barrier layer 400 may also be formed by a deposition process such as an atomic layer deposition process, a metal organic chemical vapor deposition process, a molecular beam epitaxy process, or a hydride vapor phase epitaxy process.
  • a deposition process such as an atomic layer deposition process, a metal organic chemical vapor deposition process, a molecular beam epitaxy process, or a hydride vapor phase epitaxy process.
  • the second barrier layer 400 is etched to expose a portion of the surface of the first barrier layer 305.
  • the second barrier layer 400 is patterned and etched to retain a portion of the second barrier layer 400a over the channel region between the gate and the drain of the HEMT to be formed.
  • the second barrier layer 400a includes: a first sub-layer 401a on a surface of the first barrier layer 305, a second sub-layer 402a on a surface of the first sub-layer 401a, and The third sub-layer 403a of the surface of the second sub-layer 402a.
  • the second barrier layer 400 may be etched using a dry etching process. Further, in order to avoid causing large damage to the second barrier layer 400, affecting the interface quality of the second barrier layer 400 and the subsequently formed gate, a low damage dry etching process may be used.
  • the second barrier layer 400 is etched.
  • the ion etching process of etching the reactive ion etching process or an inductively coupled second barrier layer 400 may be employed, the etching gas includes Cl 2 and BCl 3.
  • a source 601 , a drain 602 and a gate 603 are respectively formed on the surface of the first barrier layer 305 , and the gate 603 is located between the source 601 and the second barrier layer 600 .
  • the side wall of the gate 603 is connected to the sidewall of the second barrier layer 400.
  • the method of forming the source 601, the drain 602, and the gate 603 includes: forming a metal layer covering the first barrier layer 305 and the second barrier layer 400a, such as Ti, Al, Cu, Au, or Ag, etc. Graphically etching the metal layer to form a source 601, a drain 602, and a gate 603 on a surface of the first barrier layer 305, and the gate 603 is located at the source 601 Between the second barrier layer 400a and the second barrier layer 400a, the sidewall of the gate 603 is connected to the sidewall of the second barrier layer 400a to polarize the second barrier layer 400a by the gate 603. Produce two-dimensional hole gas.
  • the second barrier layer 400a increases the breakdown voltage of the high electron mobility transistor by a two-dimensional air hole generated by polarization.
  • the second barrier layer 400a is ionized by the impurity of the P-type doped third sub-layer 403a and the second sub-layer 402a and the first sub-layer 401a are interfacially polarized.
  • the hole gas is exhausted to deplete the two-dimensional electron gas in the channel of the gate and drain drift regions, smoothing the channel electric field distribution, thereby increasing the breakdown voltage of the high electron mobility transistor.
  • an 8-inch silicon having a crystal orientation of ⁇ 111> is used as a substrate, and then an aluminum nitride nucleation layer and a gallium nitride buffer are sequentially epitaxially grown by metal organic chemical vapor deposition (MOCVD).
  • MOCVD metal organic chemical vapor deposition
  • the MOCVD system is the German Aixtron planetary reaction chamber G5+, which can hold five 8-inch silicon substrates.
  • TMAl trimethylaluminum
  • TMGa trimethylgallium
  • Ammonia gas is supplied to Group V raw materials at a flow rate of 5 slm to 50 slm.
  • Hydrogen and nitrogen are carrier gases, and the flow rate is from 10 slm to 80 slm.
  • the thickness of the first sub-layer of aluminum nitride is 20 nm
  • the thickness of the second sub-layer of gallium nitride is 50 nm
  • the thickness of the third sub-layer of p-type gallium nitride is 100 nm.
  • the first sub-layer of aluminum nitride, the second sub-layer of gallium nitride, and the third sub-layer of P-type gallium nitride are etched by inductively coupled plasma (ICP), but the portion between the gate and the drain is retained. region.
  • the etching gas used in the ICP process is boron trichloride (BCl 3 ) and Cl 2 , the flow rate of BCl 3 is 100 sccm, the flow rate of Cl 2 is 5 sccm, and the etching power is 50 W.
  • a source, a gate, and a drain are separately fabricated, wherein a composite layer of a Ti layer and an Al layer is deposited by an electron beam as an electrode metal, wherein the Ti layer has a thickness of 20 nm, the Al layer has a thickness of 200 nm, and is annealed under nitrogen.
  • the temperature is 850 ° C and the time is 30 s.
  • a high electron mobility transistor having a high breakdown voltage.
  • the high electron mobility transistor includes: a substrate 200; a channel layer 303 on the substrate 200; a first barrier layer 305 on the channel layer 303; a gate 603, a source 601 and a drain 602 on the first barrier layer 305.
  • the source 601 and the drain 602 are respectively located at two sides of the gate 603; and the gate 603 and the drain 602 are located at the gate 603 and the drain 602.
  • a second barrier layer 400a is formed on the surface of the first barrier layer 305.
  • the sidewall of the second barrier layer 400a is connected to the sidewall of the gate 603 for generating two-dimensional hole gas.
  • the material of the substrate 200 may be sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride or gallium nitride.
  • the channel layer 303 as a two-dimensional electron gas transmission channel, requires a higher crystal quality to reduce the background concentration in the channel, thereby reducing scattering and increasing the mobility of the two-dimensional electron gas.
  • An undoped group III metal nitride may be employed as the material of the channel layer 303, such as an undoped GaN layer.
  • the material of the first barrier layer 305 includes aluminum gallium nitride or aluminum aluminum nitride, and may be a single layer or a multilayer structure.
  • the first barrier layer 305 forms a heterojunction with the channel layer 303 to generate two-dimensional electricity. Childhood.
  • a nucleation layer 301 between the substrate 200 and the channel layer 303 and a buffer layer 302 on the surface of the nucleation layer 301 are further included.
  • the nucleation layer 301 can significantly improve the quality of the group III metal nitride layer epitaxially grown on the nucleation layer 301.
  • the material of the nucleation layer 301 includes GaN, AlN or AlGaN.
  • the buffer layer 302 has a higher resistivity, and the material of the buffer layer 302 may be gallium nitride.
  • an interposer layer 304 is disposed between the channel layer 303 and the first barrier layer 305, and the interposer layer 304 is used to improve the crystal quality of the first barrier layer 305.
  • the material of the insertion layer 304 may be aluminum nitride.
  • the high electron mobility transistor may have only a partial structure in the nucleation layer 301, the buffer layer 302, and the insertion layer 304.
  • the material of the second barrier layer 400a includes a Group III metal nitride for generating a two-dimensional hole gas, such as a P-type doped Group III metal nitride or a heterojunction capable of generating a two-dimensional hole gas.
  • the second barrier layer 400a includes: a first sub-layer 401a on a surface of the first barrier layer 305, a second sub-layer 402a on a surface of the first sub-layer 401a, and A third sub-layer 403a located on a surface of the second sub-layer 402a, the first sub-layer 401a and the second sub-layer 402a constitute a heterojunction, and the third sub-layer 403a is P-type doped.
  • the material of the first sub-layer 401a is aluminum nitride, gallium nitride or aluminum gallium nitride; the material of the second sub-layer 402a is gallium nitride or aluminum nitride. Or aluminum gallium nitride; the material of the third sub-layer 403a is P-type gallium nitride, P-type aluminum nitride or P-type aluminum gallium nitride.
  • the first sub-layer 401a and the second sub-layer 402a form a heterojunction, by adjusting the ratio of the aluminum element and/or the gallium element in the first sub-layer 401a and the second sub-layer 402a, so that the first Two-dimensional hole gas is generated at the interface between the sub-layer 401a and the second sub-layer 402a.
  • the thickness of the first sub-layer 401a may be 1 nm to 100 nm; the thickness of the second sub-layer 402a may be 1 nm to 100 nm; and the thickness of the third sub-layer 403a may be 1 nm to 100 nm.
  • the second barrier layer 400a may also be other suitable materials having a single layer or a multilayer structure such that the second barrier layer 400a is in spontaneous polarization or an external electrode. Two-dimensional hole gas can be generated under polarized conditions.
  • the source 601, the drain 602, and the gate 603 are all metal, such as Ti, Al, Cu, Au, or Ag, and the gate 603 is located between the source 601 and the second barrier layer 600.
  • the side wall of the gate 603 is connected to the sidewall of the second barrier layer 400 to generate a two-dimensional hole gas by polarizing the second barrier layer 400a with the gate 603.
  • the second barrier layer 400a is capable of generating a two-dimensional air pocket to increase a breakdown voltage of the high electron mobility transistor.
  • the second barrier layer 400a is ionized by the impurity of the P-type doped third sub-layer 403a and the second sub-layer 402a and the first sub-layer 401a are interfacially polarized.
  • the hole gas is exhausted to deplete the two-dimensional electron gas in the channel of the gate and drain drift regions, smoothing the channel electric field distribution, thereby increasing the breakdown voltage of the high electron mobility transistor.

Abstract

一种具有高击穿电压的氮化镓高电子迁移率晶体管及其形成方法，该高电子迁移率晶体管包括：衬底（200）；位于衬底上的氮化镓沟道层（303）；位于氮化镓沟道层上的第一势垒层（305）；位于第一势垒层上的栅极（603）、源极（601）和漏极（602），源极和漏极分别位于栅极的两侧；位于栅极与漏极之间的第一势垒层表面的第二势垒层（400a），第二势垒层侧壁与栅极一侧侧壁连接，用于产生二维空穴气。该高电子迁移率晶体管具有更高的击穿电压。

Description

高击穿电压的氮化镓高电子迁移率晶体管及其形成方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种高击穿电压的氮化镓高电子迁移率晶体管及其形成方法。
背景技术
由于能满足现代电子科技对高温、高频、高压、高功率以及抗辐射等高性能的要求，氮化镓(GaN)获得了人们极大的关注。GaN基高电子迁移率晶体管(HEMT)作为功率器件应用，是目前国际上大力发展的前沿热点技术，也是我国能源发展中迫切需要的关键电力电子技术的核心技术。
虽然GaN基HEMT本身理论击穿电压值很高，但是当前作为功率开关器件的GaN基HEMT耐高压能力远不及理论计算的击穿电压值，这极大地限制了其在高压大功率领域的应用。研究表明，GaN基HEMT击穿电压低的主要原因在于栅极电场集中效应和缓冲层的漏电，尤其是栅极电场集中效应：在截止状态下当器件承受源极-漏极间高电压后，栅极靠近漏极的一端会产生电场峰值使电场分布不均匀，从而造成器件的提前击穿。
目前，人们多利用在源区、栅区或漏区制作各种金属层场板结构来平滑表面电场分布来提高击穿电压。场板结构的方法在一定程度能提高击穿电压，但由于金属和氮化镓间的晶格失配和热应力失配，会额外引入缺陷和界面电荷陷阱，导致器件质量下降，影响器件的可靠稳定性。
因此，寻找提高GaN基HEMT功率器件的击穿电压的具体解决方案，充分发挥GaN基电子功率器件高压、大功率特点的技术具有深远意义。
发明内容
本发明所要解决的技术问题是，提供一种高击穿电压的氮化镓高电子迁移率晶体管及其形成方法，以提高所述高电子迁移率晶体管的击穿电压。
为了解决上述问题，本发明提供了一种高击穿电压的氮化镓高电子迁移率晶体管，包括：衬底；位于所述衬底上的氮化镓沟道层；位于所述氮化镓沟道层上的第一势垒层；位于所述第一势垒层上的栅极、源极和漏极，所述源极和漏极分别位于所述栅极的两侧；位于所述栅极与漏极之间的第一势垒层表面的 第二势垒层，所述第二势垒层侧壁与所述栅极一侧侧壁连接，用于产生二维空穴气。
可选的，所述第二势垒层包括：位于所述第一势垒层表面的第一子层、位于所述第一子层表面的第二子层和位于所述第二子层表面的第三子层，所述第一子层和第二子层构成异质结，所述第三子层为P型掺杂。
可选的，所述衬底与氮化镓沟道层之间还具有成核层和位于所述成核层表面的缓冲层。
可选的，所述氮化镓沟道层与第一势垒层之间还具有插入层。
可选的，所述第一子层的材料为氮化铝、氮化镓或氮化铝镓；所述第二子层的材料为氮化镓、氮化铝或氮化铝镓；所述第三子层的材料为P型氮化镓、P型氮化铝或P型氮化铝镓；所述成核层的材料为氮化镓、氮化铝或氮化镓铝；所述缓冲层的材料为氮化镓；所述插入层的材料为氮化铝；所述第一势垒层的材料为氮化铝镓或氮化铝铟。
本发明还提供一种高电子迁移率晶体管的形成方法，包括：提供衬底；在所述衬底上依次形成氮化镓沟道层、位于所述氮化镓沟道层上的第一势垒层；在所述第一势垒层表面形成第二势垒层，所述第二势垒层用于产生二维空穴气；对所述第二势垒层进行刻蚀，暴露出第一势垒层的部分表面；在所述第一势垒层表面分别形成源极、漏极和栅极，所述栅极位于源极和第二势垒层之间，且所述栅极一侧侧壁与所述第二势垒层侧壁连接。
可选的，所述第二势垒层包括位于所述第一势垒层表面的第一子层、位于所述第一子层表面的第二子层和位于所述第二子层表面的第三子层，所述第一子层和第二子层构成异质结，所述第三子层为P型掺杂。
可选的，采用反应离子刻蚀工艺或感应耦合等离子刻蚀工艺刻蚀所述第二势垒层。
可选的，还包括：在所述衬底与氮化镓沟道层之间形成成核层和位于所述成核层表面的缓冲层；在所述氮化镓沟道层与第一势垒层之间形成插入层。
可选的，所述第一子层的材料为氮化铝、氮化镓或氮化铝镓；所述第二子 层的材料为氮化镓、氮化铝或氮化铝镓；所述第三子层的材料为P型氮化镓、P型氮化铝或P型氮化铝镓；所述成核层的材料为氮化镓、氮化铝或氮化镓铝；所述缓冲层的材料为氮化镓；所述插入层的材料为氮化铝；所述第一势垒层的材料为氮化铝镓或氮化铝铟。
本发明的高电子迁移率晶体管在栅极与漏极之间具有第二势垒层，所述第二势垒层能够产生二维空穴气，来耗尽栅极和漏极漂移区沟道内的二维电子气，平滑沟道电场分布，从而提高所述高电子迁移率晶体管的击穿电压。
附图说明
图1为本发明一具体实施方式的高击穿电压的氮化镓高电子迁移率晶体管的形成方法的流程示意图；
图2至图6为本发明一具体实施方式的高击穿电压的氮化镓高电子迁移率晶体管的形成过程的剖面结构示意图。
具体实施方式
下面结合附图对本发明提供的具有高击穿电压的氮化镓高电子迁移率晶体管及其形成方法的具体实施方式做详细说明。
请参考图1，为本发明一具体实施方式的具有高击穿电压的氮化镓高电子迁移率晶体的形成方法的流程示意图。
所述具有高击穿电压的氮化镓高电子迁移率晶体的形成方法包括：步骤S101：提供衬底；步骤S102：在所述衬底上依次形成氮化镓沟道层、位于所述氮化镓沟道层上的第一势垒层；步骤S103：在所述第一势垒层表面形成第二势垒层，所述第二势垒层用于产生二维空穴气；步骤S104：对所述第二势垒层进行刻蚀，暴露出第一势垒层的部分表面；步骤S105：在所述第一势垒层表面分别形成源极、漏极和栅极，所述栅极位于源极和第二势垒层之间，且所述栅极一侧侧壁与所述第二势垒层侧壁连接。
请参考图2至图6，为本发明一具体实施方式的高电子迁移率晶体的形成过程的剖面结构示意图。
请参考图2，提供衬底200。
所述衬底200的材料可以是蓝宝石、碳化硅、硅、氧化锌、铝酸锂、氮化 铝或氮化镓等。
请参考图3，在所述衬底200上依次形成沟道层303、位于所述沟道层303上的第一势垒层305。
所述沟道层303作为二维电子气的传输通道，需要有较高的晶体质量，以降低所述沟道内的背景浓度，从而减少散射和提高二维电子气的迁移率。可以采用非掺杂的III族金属氮化物作为所述沟道层303的材料，例如非掺杂的GaN层。
所述第一势垒层305与所述沟道层303形成异质结，所述异质结界面上的能带带阶不连续及压电极化和自发极化可产生高浓度的二维电子气。所述第一势垒层305的材料包括氮化铝镓或氮化铝铟，可以是单层也可以是多层结构。
在本发明的具体实施方式中，还包括：在所述衬底200与沟道层303之间形成成核层301和位于所述成核层301表面的缓冲层302。
所述成核层301的主要作用是为后续外延层的生长提供有效的成核中心，同时通过大量位错和缺陷的形成，释放成核层和衬底之间的失配应力，可显著提高在所述成核层301上外延生长的III族金属氮化物层的质量。所述成核层301的材料包括GaN、AlN或AlGaN。
所述缓冲层302具有较高的电阻率，以阻止沟道层303内的电子向缓冲层302泄漏。通常要求所述缓冲层302的电阻率在106Ω·cm以上。所述缓冲层302的材料可以为氮化镓，通过离子注入在所述缓冲层中产生深能级缺陷来形成高阻，或者引入P型杂质掺杂通过与N型背景浓度互相补偿得到高阻。在本发明的其他具体方式中，也可以采用其他方式获得高阻的缓冲层302。
在本发明的具体实施方式中，还包括：在所述沟道层303与第一势垒层305之间形成插入层304。所述插入层304用于提高所述第一势垒层305晶体质量，所述插入层304的材料可以为氮化铝。
上述成核层301、缓冲层302、沟道层303、插入层304和第一势垒层305可以采用原子层沉积工艺、金属有机物化学气相沉积工艺、分子束外延工艺或氢化物气相外延工艺等沉积工艺形成。
在本发明的其他具体实施方式中，也可以仅形成所述成核层301、缓冲层302、或插入层304中的部分结构。
请参考图4，在所述第一势垒层305表面形成第二势垒层400，所述第二势垒层400用于产生二维空穴气。
所述第二势垒层400的材料包括III族金属氮化物，用于产生二维空穴气，例如P型掺杂的III族金属氮化物或者能够产生二维空穴气的异质结。
本发明的具体实施方式中，所述第二势垒层400包括位于所述第一势垒层305表面的第一子层401、位于所述第一子层401表面的第二子层402和位于所述第二子层402表面的第三子层403，所述第一子层401和第二子层402构成异质结，所述第三子层403为P型掺杂。
在本发明的一个具体实施方式中，所述第一子层401的材料为氮化铝、氮化镓或氮化铝镓；所述第二子层402的材料为氮化镓、氮化铝或氮化铝镓；所述第三子层403的材料为P型氮化镓、P型氮化铝或P型氮化铝镓。所述第一子层401和第二子层402形成异质结，通过调整所述第一子层401和第二子层402内的铝元素和/或镓元素比例，使得在所述第一子层401和第二子层402界面上产生二维空穴气。
所述第一子层401的厚度可以为1nm～100nm；所述第二子层402的厚度可以为1nm～100nm；所述第三子层403的厚度可以为1nm～100nm。
在本发明的其他具体实施方式中，可以选择其他合适的材料形成单层或多层结构的第二势垒层400，使得所述第二势垒层400在自发极化或外电极极化的条件下能够产生二维空穴气。
所述第二势垒层400也可以采用原子层沉积工艺、金属有机物化学气相沉积工艺、分子束外延工艺或氢化物气相外延工艺等沉积工艺形成。
请参考图5，对所述第二势垒层400进行刻蚀，暴露出第一势垒层305的部分表面。
对所述第二势垒层400进行图形化刻蚀，保留待形成的HEMT的栅极和漏极之间的沟道区域上方的部分第二势垒层400a。在本发明的一个具体实施方 式中，所述第二势垒层400a包括：位于所述第一势垒层305表面的第一子层401a、位于所述第一子层401a表面的第二子层402a和位于所述第二子层402a表面的第三子层403a。
可以采用干法刻蚀工艺对所述第二势垒层400进行刻蚀。进一步，为了避免对所述第二势垒层400造成较大损伤，影响所述第二势垒层400与后续形成的栅极的界面质量，可以采用低损伤的干法刻蚀工艺对所述第二势垒层400进行刻蚀。在本发明的具体实施方式中，可以采用反应离子刻蚀工艺或感应耦合等离子刻蚀工艺刻蚀所述第二势垒层400，刻蚀气体包括Cl2和BCl3。
请参考图6，在所述第一势垒层305表面分别形成源极601、漏极602和栅极603，所述栅极603位于源极601和第二势垒层600之间，且所述栅极603一侧侧壁与所述第二势垒层400侧壁连接。
形成所述源极601、漏极602和栅极603的方法包括：形成覆盖所述第一势垒层305和第二势垒层400a的金属层，例如Ti、Al、Cu、Au或Ag等；对所述金属层进行图形化刻蚀，形成位于所述第一势垒层305表面的源极601、漏极602和栅极603，并且，使得所述栅极603位于所述源极601与第二势垒层400a之间，且所述栅极603的侧壁与所述第二势垒层400a的侧壁连接，以通过对栅极603对第二势垒层400a进行极化，产生二维空穴气。
所述第二势垒层400a通过极化产生的二维空气穴，提高所述高电子迁移率晶体管的击穿电压。在本发明的具体实施方式中，所述第二势垒层400a利用P型掺杂的第三子层403a的杂质电离以及第二子层402a和第一子层401a界面极化电荷产生的二维空穴气，来耗尽栅极和漏极漂移区沟道内的二维电子气，平滑沟道电场分布，从而提高所述高电子迁移率晶体管的击穿电压。
在本发明的一个实施例中，采用8英寸的晶向为<111>的硅作为衬底，然后，利用金属有机物化学气相沉积(MOCVD)依次外延生长氮化铝成核层、氮化镓缓冲层、氮化镓沟道层、氮化铝插入层、氮化铝镓势垒层、氮化铝第一子层、氮化镓第二子层和P型氮化镓第三子层。MOCVD系统为德国爱思强(Aixtron)行星式反应腔G5+，其可以放置5个8英寸硅衬底。生长温度为 1100～1150℃，三甲基铝(TMAl)其流量为50μmol/min～180μmol/min；三甲基镓(TMGa)，流量为80μmol/min～220μmol/min。氨气为V族原材料供应，流量为5slm～50slm。氢气和氮气为载气，流量为10slm～80slm。氮化铝第一子层的厚度是20nm，氮化镓第二子层的厚度是50nm，p型氮化镓第三子层的厚度是100nm。
然后，利用感应耦合等离子(ICP)来刻蚀所述氮化铝第一子层、氮化镓第二子层和P型氮化镓第三子层，但保留栅极和漏极间的部分区域。所述ICP工艺采用的刻蚀气体为三氯化硼(BCl3)和Cl2，BCl3流量为100sccm，Cl2流量为5sccm，刻蚀功率为50W。之后，分别制作源极、栅极和漏极，其中，利用电子束沉积Ti层和Al层的复合层作为电极金属，其中Ti层厚度为20nm，Al层厚度为200nm，并在氮气下退火处理，温度为850℃，时间30s。
本发明的具体实施方式，还提供一种采用具有高击穿电压的高电子迁移率晶体管。
请参考图6，所述高电子迁移率晶体管包括：衬底200；位于所述衬底200上的沟道层303；位于所述沟道层303上的第一势垒层305；位于所述第一势垒层305上的栅极603、源极601和漏极602，所述源极601和漏极602分别位于所述栅极603的两侧；位于所述栅极603与漏极602之间的第一势垒层305表面的第二势垒层400a，所述第二势垒层400a侧壁与所述栅极603一侧侧壁连接，用于产生二维空穴气。
所述衬底200的材料可以是蓝宝石、碳化硅、硅、氧化锌、铝酸锂、氮化铝或氮化镓等。
所述沟道层303作为二维电子气的传输通道，需要有较高的晶体质量，以降低所述沟道内的背景浓度，从而减少散射和提高二维电子气的迁移率。可以采用非掺杂的III族金属氮化物作为所述沟道层303的材料，例如非掺杂的GaN层。
所述第一势垒层305的材料包括氮化铝镓或氮化铝铟，可以是单层也可以是多层结构。所述第一势垒层305与所述沟道层303形成异质结，产生二维电 子气。
在本发明的一个具体实施方式中，还包括位于所述衬底200与沟道层303之间的成核层301和位于所述成核层301表面的缓冲层302。所述成核层301可显著提高在所述成核层301上外延生长的III族金属氮化物层的质量。所述成核层301的材料包括GaN、AlN或AlGaN。所述缓冲层302具有较高的电阻率，所述缓冲层302的材料可以为氮化镓。
在本发明的一个具体实施方式中，还包括位于沟道层303和第一势垒层305之间的插入层304，所述插入层304用于提高所述第一势垒层305晶体质量，所述插入层304的材料可以为氮化铝。
在本发明的其他具体实施方式，所述高电子迁移率晶体管也可以仅具备上述成核层301、缓冲层302和插入层304中的部分结构。
所述第二势垒层400a的材料包括III族金属氮化物，用于产生二维空穴气，例如P型掺杂的III族金属氮化物或者能够产生二维空穴气的异质结。在该具体实施方式中，所述第二势垒层400a包括：位于所述第一势垒层305表面的第一子层401a、位于所述第一子层401a表面的第二子层402a和位于所述第二子层402a表面的第三子层403a，所述第一子层401a和第二子层402a构成异质结，所述第三子层403a为P型掺杂。在本发明的一个具体实施方式中，所述第一子层401a的材料为氮化铝、氮化镓或氮化铝镓；所述第二子层402a的材料为氮化镓、氮化铝或氮化铝镓；所述第三子层403a的材料为P型氮化镓、P型氮化铝或P型氮化铝镓。所述第一子层401a和第二子层402a形成异质结，通过调整所述第一子层401a和第二子层402a内的铝元素和/或镓元素比例，使得在所述第一子层401a和第二子层402a界面上产生二维空穴气。
所述第一子层401a的厚度可以为1nm～100nm；所述第二子层402a的厚度可以为1nm～100nm；所述第三子层403a的厚度可以为1nm～100nm。在本发明的其他具体实施方式中，所述第二势垒层400a也可以是其他合适的材料，具有单层或多层结构，使得所述第二势垒层400a在自发极化或外电极极化的条件下能够产生二维空穴气。
所述源极601、漏极602和栅极603均为金属，例如Ti、Al、Cu、Au或Ag等，所述栅极603位于源极601和第二势垒层600之间，且所述栅极603一侧侧壁与所述第二势垒层400侧壁连接，以通过对栅极603对第二势垒层400a进行极化，产生二维空穴气。
所述第二势垒层400a能够产生二维空气穴，提高所述高电子迁移率晶体管的击穿电压。在本发明的具体实施方式中，所述第二势垒层400a利用P型掺杂的第三子层403a的杂质电离以及第二子层402a和第一子层401a界面极化电荷产生的二维空穴气，来耗尽栅极和漏极漂移区沟道内的二维电子气，平滑沟道电场分布，从而提高所述高电子迁移率晶体管的击穿电压。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种高击穿电压的氮化镓高电子迁移率晶体管，其特征在于，包括：
    衬底；
    位于所述衬底上的氮化镓沟道层；
    位于所述氮化镓沟道层上的第一势垒层；
    位于所述第一势垒层上的栅极、源极和漏极，所述源极和漏极分别位于所述栅极的两侧；
    位于所述栅极与漏极之间的第一势垒层表面的第二势垒层，所述第二势垒层侧壁与所述栅极一侧侧壁连接，用于产生二维空穴气。
  2. 根据权利要求1所述的氮化镓高电子迁移率晶体管，其特征在于，所述第二势垒层包括：位于所述第一势垒层表面的第一子层、位于所述第一子层表面的第二子层和位于所述第二子层表面的第三子层，所述第一子层和第二子层构成异质结，所述第三子层为P型掺杂。
  3. 根据权利要求2所述的氮化镓高电子迁移率晶体管，其特征在于，所述衬底与氮化镓沟道层之间还具有成核层和位于所述成核层表面的缓冲层。
  4. 根据权利要求3所述的氮化镓高电子迁移率晶体管，其特征在于，所述氮化镓沟道层与第一势垒层之间还具有插入层。
  5. 根据权利要求4所述的氮化镓高电子迁移率晶体管，其特征在于，所述第一子层的材料为氮化铝、氮化镓或氮化铝镓；所述第二子层的材料为氮化镓、氮化铝或氮化铝镓；所述第三子层的材料为P型氮化镓、P型氮化铝或P型氮化铝镓；所述成核层的材料为氮化镓、氮化铝或氮化镓铝；所述缓冲层的材料为氮化镓；所述插入层的材料为氮化铝；所述第一势垒层的材料为氮化铝镓或氮化铝铟。
  6. 一种高击穿电压的氮化镓高电子迁移率晶体管的形成方法，其特征在于，
    包括：
    提供衬底；
    在所述衬底上依次形成氮化镓沟道层、位于所述氮化镓沟道层上的第一势垒层；
    在所述第一势垒层表面形成第二势垒层，所述第二势垒层用于产生二维空穴气；
    对所述第二势垒层进行刻蚀，暴露出第一势垒层的部分表面；
    在所述第一势垒层表面分别形成源极、漏极和栅极，所述栅极位于源极和第二势垒层之间，且所述栅极一侧侧壁与所述第二势垒层侧壁连接。
  7. 根据权利要求6所述的氮化镓高电子迁移率晶体管的形成方法，其特征在于，所述第二势垒层包括位于所述第一势垒层表面的第一子层、位于所述第一子层表面的第二子层和位于所述第二子层表面的第三子层，所述第一子层和第二子层构成异质结，所述第三子层为P型掺杂。
  8. 根据权利要求7所述的氮化镓高电子迁移率晶体管的形成方法，其特征在于，采用反应离子刻蚀工艺或感应耦合等离子刻蚀工艺刻蚀所述第二势垒层。
  9. 根据权利要求8所述的氮化镓高电子迁移率晶体管的形成方法，其特征在于，还包括：在所述衬底与氮化镓沟道层之间形成成核层和位于所述成核层表面的缓冲层；在所述氮化镓沟道层与第一势垒层之间形成插入层。
  10. 根据权利要求9所述的氮化镓高电子迁移率晶体管的形成方法，其特征在于，所述第一子层的材料为氮化铝、氮化镓或氮化铝镓；所述第二子层的材料为氮化镓、氮化铝或氮化铝镓；所述第三子层的材料为P型氮化镓、P型氮化铝或P型氮化铝镓；所述成核层的材料为氮化镓、氮化铝或氮化镓铝；所述缓冲层的材料为氮化镓；所述插入层的材料为氮化铝；所述第一势垒层的材料为氮化铝镓或氮化铝铟。
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