WO2018138764A1 - Transistor - Google Patents

Transistor Download PDF

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Publication number
WO2018138764A1
WO2018138764A1 PCT/JP2017/002280 JP2017002280W WO2018138764A1 WO 2018138764 A1 WO2018138764 A1 WO 2018138764A1 JP 2017002280 W JP2017002280 W JP 2017002280W WO 2018138764 A1 WO2018138764 A1 WO 2018138764A1
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WO
WIPO (PCT)
Prior art keywords
gate
dielectric substrate
bus bar
drain
transistor
Prior art date
Application number
PCT/JP2017/002280
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English (en)
Japanese (ja)
Inventor
純 神岡
山中　宏治
政毅 半谷
Original Assignee
三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2017/002280 priority Critical patent/WO2018138764A1/fr
Priority to JP2017533986A priority patent/JP6246432B1/ja
Publication of WO2018138764A1 publication Critical patent/WO2018138764A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate

Definitions

  • the present invention relates to a transistor, and more particularly to a high-frequency transistor.
  • a transistor is used to amplify a high-frequency signal in a wireless communication device or a radar device.
  • a source-grounded field effect transistor Field Effect Transistor, FET
  • Patent Document 1 discloses an FET in which a substantially comb-shaped gate electrode and a substantially comb-shaped drain electrode are arranged so as to mesh with each other, a so-called “multi-finger type” FET.
  • a gate electrode in a multi-finger type FET (hereinafter referred to as “multi-finger FET”) has at least one gate bus bar and a plurality of gate fingers provided substantially perpendicular to the gate bus bar. Yes. Further, the drain electrode in the multi-finger FET has one or more drain bus bars and a plurality of drain fingers provided substantially perpendicular to the drain bus bars.
  • the gate electrode and the drain electrode are provided on the front surface portion of the dielectric substrate, and a metal layer is provided on the back surface portion of the dielectric substrate. This metal layer is electrically grounded.
  • a microstrip line is constituted by the gate bus bar, and a microstrip line is constituted by the drain bus bar.
  • a high-frequency signal propagates through these microstrip lines, an electromagnetic field is generated in the dielectric substrate, so that a dielectric loss corresponding to the dielectric loss tangent occurs. Due to this dielectric loss, there is a problem that the gain, output power and efficiency of the transistor are lowered.
  • the present invention has been made to solve the above-described problems, and an object thereof is to provide a transistor having high gain, high output power, and high efficiency.
  • the transistor of the present invention includes a metal layer provided on the back surface of the dielectric substrate, and a plurality of gate fingers provided on the front surface of the dielectric substrate and electrically connected to each other by the gate bus bar. And a source electrode electrically connected to the metal layer by a via penetrating the dielectric substrate, and a part of the gate bus bar is an air bridge It is constituted by wiring, and a part of the source electrode is arranged between the air bridge wiring and the dielectric substrate.
  • the transistor of the present invention includes a metal layer provided on the back surface of the dielectric substrate and a plurality of drain fingers provided on the front surface of the dielectric substrate and electrically connected to each other by the drain bus bar and the drain bus bar. And a source electrode electrically connected to the metal layer by a via penetrating the dielectric substrate, and a part of the drain bus bar is an air bridge It is constituted by wiring, and a part of the source electrode is arranged between the air bridge wiring and the dielectric substrate.
  • FIG. 1A is a plan view showing a gate electrode according to Embodiment 1 of the present invention.
  • FIG. 1B is a plan view showing the drain electrode according to Embodiment 1 of the present invention.
  • 2A is a cross-sectional view taken along line A-A ′ shown in FIG. 1A.
  • 2B is a cross-sectional view taken along line B-B ′ shown in FIG. 1B.
  • It is a top view which shows the source electrode which concerns on Embodiment 1 of this invention.
  • FIG. 5A is a cross-sectional view taken along line A-A ′ shown in FIG. FIG.
  • FIG. 5B is a cross-sectional view taken along line B-B ′ shown in FIG.
  • FIG. 5C is a cross-sectional view taken along line C-C ′ shown in FIG. It is a top view which shows the principal part of the transistor used as the comparison object with the transistor which concerns on Embodiment 1 of this invention.
  • FIG. 7A is a cross-sectional view taken along line C-C ′ shown in FIG.
  • FIG. 7B is a cross-sectional view taken along line C-C ′ shown in FIG.
  • FIG. 8A is a plan view showing a gate electrode according to Embodiment 2 of the present invention.
  • FIG. 8B is a plan view showing the drain electrode according to Embodiment 2 of the present invention.
  • FIG. 9A is a cross-sectional view taken along line A-A ′ shown in FIG. 8A.
  • FIG. 9B is a cross-sectional view taken along line B-B ′ shown in FIG. 8B. It is a top view which shows the source electrode which concerns on Embodiment 2 of this invention. It is a top view which shows the principal part of the transistor which concerns on Embodiment 2 of this invention.
  • 12A is a cross-sectional view taken along line A-A ′ shown in FIG. 12B is a cross-sectional view taken along line B-B ′ shown in FIG. 12C is a cross-sectional view taken along line C-C ′ shown in FIG.
  • FIG. 13A is a plan view showing a gate electrode according to Embodiment 3 of the present invention.
  • FIG. 13B is a plan view showing the drain electrode according to Embodiment 3 of the present invention.
  • 14A is a cross-sectional view taken along line A-A ′ shown in FIG. 13A.
  • 14B is a cross-sectional view taken along line B-B ′ shown in FIG. 13B.
  • It is a top view which shows the source electrode which concerns on Embodiment 3 of this invention.
  • FIG. 17A is a cross-sectional view along the line A-A ′ shown in FIG. 16.
  • FIG. 17B is a cross-sectional view along the line B-B ′ shown in FIG. 16.
  • FIG. 17C is a cross-sectional view taken along line C-C ′ shown in FIG.
  • FIG. 18A is a plan view showing a gate electrode according to Embodiment 4 of the present invention.
  • FIG. 18B is a plan view showing the drain electrode according to Embodiment 4 of the present invention.
  • FIG. 19A is a cross-sectional view taken along line A-A ′ shown in FIG. 18A.
  • FIG. 19B is a cross-sectional view taken along line B-B ′ shown in FIG. 18B. It is a top view which shows the source electrode which concerns on Embodiment 4 of this invention.
  • 22A is a cross-sectional view taken along line A-A ′ shown in FIG. 22B is a cross-sectional view taken along line B-B ′ shown in FIG. 22C is a cross-sectional view taken along line C-C ′ shown in FIG.
  • FIG. 1A is a plan view showing a gate electrode according to Embodiment 1 of the present invention.
  • FIG. 1B is a plan view showing the drain electrode according to Embodiment 1 of the present invention.
  • 2A is a cross-sectional view taken along line AA ′ shown in FIG. 1A.
  • 2B is a cross-sectional view taken along line BB ′ shown in FIG. 1B.
  • FIG. 3 is a plan view showing the source electrode according to Embodiment 1 of the present invention.
  • FIG. 4 is a plan view showing the main part of the transistor according to Embodiment 1 of the present invention.
  • FIG. 5A is a cross-sectional view taken along line AA ′ shown in FIG.
  • FIG. 5B is a cross-sectional view taken along the line BB ′ shown in FIG.
  • FIG. 5C is a cross-sectional view taken along the line CC ′ shown in FIG.
  • the transistor 100 of Embodiment 1 will be described.
  • 1 is a dielectric substrate.
  • An electrically grounded metal layer 2 is provided on the back surface of the dielectric substrate 1.
  • a gate electrode 3, a drain electrode 4, and a source electrode 5 are provided on the surface portion of the dielectric substrate 1.
  • the gate electrode 3 has one gate bus bar 31 and ten gate fingers 32 1 to 32 10 provided substantially perpendicular to the gate bus bar 31. Thereby, the outer shape of the gate electrode 3 is substantially comb-shaped.
  • the gate fingers 32 1 to 32 10 are electrically connected to each other by a gate bus bar 31.
  • Each of the gate fingers 32 1 to 32 10 is electrically connected to the gate terminal 6 via the gate bus bar 31.
  • the drain electrode 4 has one drain bus bar 41 and five drain fingers 42 1 to 42 5 provided substantially perpendicular to the drain bus bar 41. Thereby, the external shape of the drain electrode 4 is substantially comb-shaped. Drain finger 42 1-42 5 are electrically connected to each other by the drain bus bar 41. Further, each of the drain finger 42 1-42 5 are drain terminals 7 electrically connected via a drain bus bar 41.
  • the gate electrode 3 and the drain electrode 4 are arranged to face each other so that the gate fingers 32 1 to 32 10 and the drain fingers 42 1 to 42 5 are engaged with each other. More specifically, the drain finger 42 1 is disposed between the gate fingers 32 1, 32 2 adjacent to each other, the drain finger 42 2 is disposed between the gate fingers 32 3, 32 4 adjacent to each other, gate adjacent to each other a drain finger 42 3 disposed fingers 32 5, 32 between 6, the drain finger 42 4 is disposed between the gate fingers 32 7, 32 8 which are adjacent to each other, the drain finger between the gate fingers 32 9, 32 10 that are adjacent to each other 42 5 is arranged. That is, the transistor 100 is a multi-finger type.
  • a part of gate bus-bar 31 is comprised by the air bridge wiring. More specifically, the gate finger 32 and the gate fingers 32 1, 32 parts 33 1 connecting between 2 and portion 33 2 for connecting the gate fingers 32 2, 32 3 which are adjacent to each other, adjacent to each other adjacent to each other 3, and 32 4 sites 33 3 which connects a portion 33 4 for connecting the gate fingers 32 4, 32 5 which are adjacent to each other, the portion 33 5 for connecting the gate fingers 32 6, 32 7 adjacent to each other , A portion 33 6 connecting the gate fingers 32 7 and 32 8 adjacent to each other, a portion 33 7 connecting the gate fingers 32 8 and 32 9 adjacent to each other, and between the gate fingers 32 9 and 32 10 adjacent to each other each of the sites 33 8 for connecting is formed by an air-bridge wiring.
  • gate air bridge the portion 33 1-33 8 constituted by an air bridge line of the gate bus bar 31 may be referred to as "gate air bridge".
  • the remaining part of the gate bus bar 31 constitutes a microstrip line.
  • drain bus bar 41 a part of the drain bus bar 41 is constituted by an air bridge wiring.
  • Drain finger 42 More specifically, a portion 43 1 that connects between the drain finger 42 1, 42 2 adjacent to each other, the portion 43 2 which connects between the drain finger 42 2, 42 3 adjacent to each other, adjacent to each other 3, and 42 4 sites 43 3 which connects the, each of the drain finger 42 4, 42 5 parts 43 4 for connecting the adjacent is constituted by an air-bridge interconnection with each other.
  • drain air bridge the portions 43 1 to 43 4 constituted by the air bridge wiring in the drain bus bar 41 may be referred to as “drain air bridge”.
  • the remaining part of the drain bus bar 41 constitutes a microstrip line.
  • the source electrode 5 is composed of a pair of electrodes 5a and 5b.
  • One electrode 5 a is electrically connected to the metal layer 2 by a via 11 a penetrating the dielectric substrate 1.
  • the other electrode 5 b is electrically connected to the metal layer 2 by a via 11 b that penetrates the dielectric substrate 1.
  • the vias 11a and 11b are arranged in the half portion on the gate terminal 6 side of the dielectric substrate 1. That is, the source electrode 5 is electrically grounded, and the transistor 100 is a grounded source type.
  • the source electrode 5 has portions 51 1 to 51 6 arranged in parallel to the gate fingers 32 1 to 32 10 and the drain fingers 42 1 to 42 5 . More specifically, the source electrode 5 is disposed between a portion 51 1 disposed outside the gate finger 32 1 provided at one end of the gate bus bar 31 and the gate fingers 32 2 and 32 3 adjacent to each other. a portion 51 2 which is, the gate finger 32 4, 32 5 parts 51 3 disposed between the mutually adjacent gate fingers 32 6, 32 7 sites 51 4 disposed between the adjacent, adjacent the gate fingers 32 8, 32 parts 51 5 disposed between 9 and a portion 51 6 arranged outside the gate fingers 32 10 provided on the other end of the gate bus bar 31.
  • the dielectric substrate 1, the metal layer 2, the gate electrode 3, the drain electrode 4, the source electrode 5, the gate terminal 6 and the drain terminal 7 constitute the main part of the transistor 100.
  • a high frequency signal is input to the gate terminal 6.
  • the input high frequency signal is distributed to each of the gate fingers 32 1 to 32 10 via the gate bus bar 31.
  • amplified radio frequency signal is output.
  • These high frequency signals are combined by the drain bus bar 41 and output to the drain terminal 7.
  • FIG. 6 is a plan view showing a main part of a transistor 100 ′ to be compared with the transistor 100 according to the first embodiment.
  • FIG. 7A is a cross-sectional view taken along line C-C ′ shown in FIG. 6, that is, a cross-sectional view of the transistor 100 ′.
  • FIG. 7B is a cross-sectional view taken along the line C-C ′ shown in FIG. 4, that is, a cross-sectional view of the transistor 100.
  • an electrically grounded metal layer 2 ′ is provided on the back surface of the dielectric substrate 1 ′, and the gate electrode 3 ′ and the surface of the dielectric substrate 1 ′ are provided.
  • a drain electrode 4 ' is provided. 6 and 7A, the source electrode is not shown.
  • the gate electrode 3 ' is one gate bus bar 31' has a gate finger 32 first ten and ' ⁇ 32 10' and each of the gate fingers 32 1 'to 32 10' through the gate bus bar 31 ' Are electrically connected to the gate terminal 6 '.
  • a drain electrode 4 ' is one of the drain bus bar 41' has a five drain finger 42 1 'to 42 5' and each of the drain finger 42 1 ' ⁇ 42 5' is via the drain bus bar 41 ' Are electrically connected to the drain terminal 7 '.
  • the gate bus bar 31 'does not have an air bridge wiring, and substantially the entire gate bus bar 31' constitutes a microstrip line.
  • the drain bus bar 41 ′ does not have an air bridge wiring, and substantially the entire drain bus bar 41 ′ constitutes a microstrip line.
  • the high frequency signal is transmitted in the micro trip mode.
  • An electromagnetic field corresponding to the high-frequency signal is generated between the gate bus bar 31 'and the metal layer 2'.
  • Six arrows A1 'shown in FIG. 7A indicate electric lines of force corresponding to the power of the high-frequency signal propagating through the gate bus bar 31'.
  • the electric force lines A1 ' start at the gate bus bar 31', and the electric lines A1 'end at the electrically grounded metal layer 2'. That is, the electric lines of force A1 'pass through the dielectric substrate 1'. Since the dielectric substrate 1 'has a finite conductance and a finite dielectric loss tangent, a dielectric loss corresponding to the dielectric loss tangent occurs. This dielectric loss reduces the gain, output power and efficiency of transistor 100 '.
  • a part of the gate bus bar 31 is configured by an air bridge wiring, and a part of the source electrode 5 is interposed between the air bridge wiring and the dielectric substrate 1.
  • the six arrows A1 shown in FIG. 7B indicate electric lines of force corresponding to the power of the high-frequency signal propagating through the gate air bridge.
  • the beginning of the electric power line A1 denotes a gate bus bar 31 (region 33 2)
  • the end of the electric line of force A1 is the source electrode 5 which is electrically grounded (sites 52 2). That is, the electric lines of force A1 do not pass through the dielectric substrate 1 but pass through the air. Thereby, it is possible to prevent the dielectric loss due to the dielectric loss tangent of the dielectric substrate 1 from occurring.
  • the high frequency signal is transmitted in the micro trip mode in the drain bus bar 41 ′ of the transistor 100 ′.
  • An electromagnetic field corresponding to the high-frequency signal is generated between the drain bus bar 41 'and the metal layer 2'.
  • Six arrows A2 'shown in FIG. 7A indicate electric lines of force corresponding to the power of the high-frequency signal propagating through the drain bus bar 41'.
  • the electric force line A2 ' starts at the drain bus bar 41'
  • a part of the drain bus bar 41 is configured by an air bridge wiring, and a part of the source electrode 5 is interposed between the air bridge wiring and the dielectric substrate 1.
  • the six arrows A2 shown in FIG. 7B indicate electric lines of force corresponding to the power of the high-frequency signal propagating through the drain air bridge.
  • the starting end of the electric force line A2 is the drain bus bar 41 (part 43 1 )
  • the end of the electric line of force A2 is the electrically grounded source electrode 5 (part 53 1 ). That is, the electric lines of force A2 do not pass through the dielectric substrate 1 but pass through the air. Thereby, it is possible to prevent the dielectric loss due to the dielectric loss tangent of the dielectric substrate 1 from occurring.
  • the drain bus bar 41 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire drain bus bar 41. That is, the drain bus bar 41 may have the same shape as the drain bus bar 41 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5 may have a shape obtained by removing the portions 53 1 to 53 4 shown in FIG.
  • the number of gate bus bars 31 may be one or more, and is not limited to one.
  • the number of gate fingers 32 1 to 32 10 may be plural, and is not limited to ten.
  • the number of drain bus bars 41 may be one or more, and is not limited to one.
  • the number of drain fingers 42 1 to 42 5 may be a plurality, and is not limited to five.
  • the transistor 100 of the first embodiment is provided on the metal layer 2 provided on the back surface portion of the dielectric substrate 1 and on the front surface portion of the dielectric substrate 1, and includes the gate bus bar 31 and the gate bus bar 31.
  • the gate electrode 3 having a plurality of gate fingers 32 1 to 32 10 that are electrically connected to each other by the above, and vias 11 a and 11 b that are provided on the surface portion of the dielectric substrate 1 and penetrate the dielectric substrate 1.
  • the transistor 100 of the first embodiment is provided on the metal layer 2 provided on the back surface of the dielectric substrate 1 and on the front surface of the dielectric substrate 1, and is electrically connected to each other by the drain bus bar 41 and the drain bus bar 41.
  • the drain electrode 4 having a plurality of connected drain fingers 42 1 to 42 5 and a metal layer formed by vias 11 a and 11 b penetrating the dielectric substrate 1 are provided on the surface of the dielectric substrate 1. 2 and a source electrode 5 electrically connected to each other, and a part of the drain bus bar 41 (parts 43 1 to 43 4 ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric substrate 1 are connected to each other. part of the source electrode 5 (sites 53 1-53 4) is disposed between.
  • FIG. FIG. 8A is a plan view showing a gate electrode according to Embodiment 2 of the present invention.
  • FIG. 8B is a plan view showing the drain electrode according to Embodiment 2 of the present invention.
  • FIG. 9A is a cross-sectional view taken along line AA ′ shown in FIG. 8A.
  • FIG. 9B is a cross-sectional view taken along line BB ′ shown in FIG. 8B.
  • FIG. 10 is a plan view showing a source electrode according to Embodiment 2 of the present invention.
  • FIG. 11 is a plan view showing a main part of a transistor according to Embodiment 2 of the present invention.
  • 12A is a cross-sectional view taken along line AA ′ shown in FIG. 12B is a cross-sectional view taken along the line BB ′ shown in FIG. 12C is a cross-sectional view taken along the line CC ′ shown in FIG.
  • the transistor 100 of the second embodiment will be described with reference to FIGS. Components similar to those of the transistor 100 of Embodiment 1 shown in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof is omitted.
  • a part of the gate bus bar 31 is configured by air bridge wiring. More specifically, the gate finger 32 and the gate fingers 32 2, 32 3 parts 33 2 connected between a site 33 4 for connecting the gate fingers 32 4, 32 5 which are adjacent to each other, adjacent to each other adjacent to each other 6, and 32 7 sites 33 5 connecting between each of the gate fingers 32 8, 32 9 parts 33 7 connecting between adjacent is constituted by an air-bridge interconnection with each other.
  • the remaining part of the gate bus bar 31 constitutes a microstrip line.
  • the source electrode 5 is composed of six substantially rectangular electrodes 5c to 5h.
  • the electrodes 5c to 5h are electrically connected to the metal layer 2 through vias 11c to 11h penetrating the dielectric substrate 1, respectively.
  • the source electrode 5 has portions 51 1 to 51 6 arranged in parallel to the gate fingers 32 1 to 32 10 and the drain fingers 42 1 to 42 5 . These sites 51 1-51 6 are provided one on electrodes 5c ⁇ 5h.
  • the via 11c ⁇ 11h are respectively arranged in the center of these sites 51 1-51 6.
  • the four vias 11d to 11g among the six vias 11c to 11h are arranged between the adjacent gate fingers of the gate fingers 32 2 to 32 10 , and the drain fingers 42 1 to 42 are provided. 5 between the adjacent drain fingers.
  • the via 11d is disposed between the gate fingers 32 2, 32 3 which are adjacent to each other, via 11e is disposed between the gate fingers 32 4, 32 5 which are adjacent to each other, the gate fingers via 11f adjacent to each other 32 6, 32 are disposed between 7, vias 11g is disposed between the gate fingers 32 8, 32 9 adjacent to each other.
  • the via 11d is disposed between the drain fingers 42 1 and 42 2 adjacent to each other, the via 11e is disposed between the drain fingers 42 2 and 42 3 adjacent to each other, and the via 11f is disposed adjacent to the drain fingers 42 3 and 42. 4 , the via 11 g is disposed between the drain fingers 42 4 and 4 5 adjacent to each other.
  • the source electrode 5 is disposed between each gate air bridge and the dielectric substrate 1, that is, between each of the portions 33 2 , 33 4 , 33 5 , and 33 7 of the gate bus bar 31 and the dielectric substrate 1.
  • the region 52 2 , 52 4 , 52 5 , 52 7 is formed.
  • These portions 52 2 , 52 4 , 52 5 , and 52 7 are connected to the four electrodes 5d to 5g excluding the electrodes 5c and 5h arranged at both ends of the six electrodes 5c to 5h arranged in parallel to each other. One by one.
  • Each of these portions 53 1 to 53 4 is provided on each of the four electrodes 5d to 5g excluding the electrodes 5c and 5h arranged at both ends of the six electrodes 5c to 5h arranged in parallel to each other. Yes.
  • the dielectric substrate 1, the metal layer 2, the gate electrode 3, the drain electrode 4, the source electrode 5, the gate terminal 6 and the drain terminal 7 constitute the main part of the transistor 100.
  • the operation of the transistor 100 according to the second embodiment is the same as that described in the first embodiment, description thereof is omitted.
  • the effect of the transistor 100 according to the second embodiment is the same as that described with reference to FIGS. 6 and 7 in the first embodiment, and thus illustration and description thereof are omitted.
  • the gate bus bar 31 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire gate bus bar 31. That is, the gate bus bar 31 may have the same shape as the gate bus bar 31 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5, part 52 2, 52 4 shown in FIG. 10, 52 5, 52 7 may be then formed by the shape removed.
  • the drain bus bar 41 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire drain bus bar 41. That is, the drain bus bar 41 may have the same shape as the drain bus bar 41 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5 may have a shape formed by removing the portions 53 1 to 53 4 shown in FIG.
  • the number of electrodes 5c to 5h constituting the source electrode 5 may be a number corresponding to the number of gate fingers 32 1 to 32 10 and the number of drain fingers 42 1 to 42 5 , and is limited to six. It is not a thing.
  • the transistor 100 according to the second embodiment is provided on the metal layer 2 provided on the back surface portion of the dielectric substrate 1 and on the front surface portion of the dielectric substrate 1, and includes the gate bus bar 31 and the gate bus bar 31.
  • the gate electrode 3 having a plurality of gate fingers 32 1 to 32 10 that are electrically connected to each other by the above, and vias 11c to 11h that are provided on the surface portion of the dielectric substrate 1 and penetrate the dielectric substrate 1
  • a part of the gate bus bar 31 are configured by air bridge wiring, and the source electrode 5 is electrically connected to the metal layer 2 by the air bridge wiring.
  • Part of the source electrode 5 (parts 52 2 , 52 4 , 52 5 , 52 7 ) is disposed between the bridge wiring and the dielectric substrate 1. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the gate air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.
  • the vias 11d to 11g are arranged between the gate fingers adjacent to each other. Accordingly, since the area of the source electrode 5 can be reduced, the transistor 100 can be reduced in size.
  • the transistor 100 of the second embodiment is provided on the metal layer 2 provided on the back surface of the dielectric substrate 1 and on the front surface of the dielectric substrate 1, and is electrically connected to each other by the drain bus bar 41 and the drain bus bar 41.
  • the drain electrode 4 having a plurality of connected drain fingers 42 1 to 42 5 and a metal layer formed on the surface of the dielectric substrate 1 and vias 11c to 11h penetrating the dielectric substrate 1 2 and a source electrode 5 electrically connected to each other, and a part of the drain bus bar 41 (parts 43 1 to 43 4 ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric substrate 1 are connected to each other.
  • a part of the source electrode 5 (parts 53 1 to 53 4 ) is disposed between them.
  • the vias 11d to 11g are arranged between the drain fingers adjacent to each other. Accordingly, since the area of the source electrode 5 can be reduced, the transistor 100 can be reduced in size.
  • FIG. 13A is a plan view showing a gate electrode according to Embodiment 3 of the present invention.
  • FIG. 13B is a plan view showing the drain electrode according to Embodiment 3 of the present invention.
  • 14A is a cross-sectional view taken along line AA ′ shown in FIG. 13A.
  • 14B is a cross-sectional view taken along line BB ′ shown in FIG. 13B.
  • FIG. 15 is a plan view showing a source electrode according to Embodiment 3 of the present invention.
  • FIG. 16 is a plan view showing a main part of a transistor according to Embodiment 3 of the present invention.
  • 17A is a cross-sectional view taken along line AA ′ shown in FIG.
  • FIG. 17B is a cross-sectional view taken along the line BB ′ shown in FIG.
  • FIG. 17C is a cross-sectional view taken along the line CC ′ shown in FIG.
  • the transistor 100 of the third embodiment will be described with reference to FIGS. Components similar to those of the transistor 100 of Embodiment 1 shown in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof is omitted.
  • a part of the gate bus bar 31 is configured by air bridge wiring. More specifically, the gate finger 32 and the gate fingers 32 2, 32 3 parts 33 2 connected between a site 33 4 for connecting the gate fingers 32 4, 32 5 which are adjacent to each other, adjacent to each other adjacent to each other 6, and 32 7 sites 33 5 connecting between each of the gate fingers 32 8, 32 9 parts 33 7 connecting between adjacent is constituted by an air-bridge interconnection with each other.
  • the remaining part of the gate bus bar 31 constitutes a microstrip line.
  • the source electrode 5 is composed of a pair of electrodes 5i and 5j.
  • One electrode 5 i is electrically connected to the metal layer 2 through a via 11 i penetrating the dielectric substrate 1.
  • the other electrode 5j is electrically connected to the metal layer 2 by a via 11j penetrating the dielectric substrate 1.
  • the vias 11 i and 11 j are arranged in the half part of the dielectric substrate 1 on the drain terminal 7 side.
  • the source electrode 5 has portions 51 1 to 51 6 arranged in parallel to the gate fingers 32 1 to 32 10 and the drain fingers 42 1 to 42 5 .
  • the source electrode 5 is disposed between each gate air bridge and the dielectric substrate 1, that is, between each of the portions 33 2 , 33 4 , 33 5 , and 33 7 of the gate bus bar 31 and the dielectric substrate 1.
  • the region 52 2 , 52 4 , 52 5 , 52 7 is formed.
  • the dielectric substrate 1, the metal layer 2, the gate electrode 3, the drain electrode 4, the source electrode 5, the gate terminal 6 and the drain terminal 7 constitute the main part of the transistor 100.
  • the operation of the transistor 100 according to Embodiment 3 is the same as that described in Embodiment 1, description thereof is omitted.
  • the effect of the transistor 100 according to the third embodiment is the same as that described with reference to FIGS. 6 and 7 in the first embodiment, and thus illustration and description thereof are omitted.
  • the gate bus bar 31 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire gate bus bar 31. That is, the gate bus bar 31 may have the same shape as the gate bus bar 31 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5, part 52 2, 52 4 shown in FIG. 15, 52 5, 52 7 may be then formed by the shape removed.
  • the transistor 100 of the third embodiment is provided on the metal layer 2 provided on the back surface portion of the dielectric substrate 1 and on the front surface portion of the dielectric substrate 1, and includes the gate bus bar 31 and the gate bus bar 31.
  • the gate electrode 3 having a plurality of gate fingers 32 1 to 32 10 that are electrically connected to each other by the above, and vias 11 i and 11 j that are provided on the surface portion of the dielectric substrate 1 and penetrate the dielectric substrate 1.
  • a part of the gate bus bar 31 (parts 33 2 , 33 4 , 33 5 , 33 7 ) are configured by air bridge wiring, and the source electrode 5 is electrically connected to the metal layer 2 by the air bridge wiring.
  • Part of the source electrode 5 (parts 52 2 , 52 4 , 52 5 , 52 7 ) is disposed between the bridge wiring and the dielectric substrate 1. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the gate air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.
  • the transistor 100 of the third embodiment is provided on the metal layer 2 provided on the back surface of the dielectric substrate 1 and on the front surface of the dielectric substrate 1, and is electrically connected to each other by the drain bus bar 41 and the drain bus bar 41.
  • the drain electrode 4 having a plurality of connected drain fingers 42 1 to 42 5 and a metal layer by vias 11 i and 11 j that are provided on the surface of the dielectric substrate 1 and penetrate the dielectric substrate 1. 2 and a source electrode 5 electrically connected to each other, and a part of the drain bus bar 41 (parts 43 1 to 43 4 ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric substrate 1 are connected to each other.
  • a part of the source electrode 5 (parts 53 1 to 53 4 ) is disposed between them.
  • FIG. 18A is a plan view showing a gate electrode according to Embodiment 4 of the present invention.
  • FIG. 18B is a plan view showing the drain electrode according to Embodiment 4 of the present invention.
  • FIG. 19A is a cross-sectional view along the line AA ′ shown in FIG. 18A.
  • FIG. 19B is a cross-sectional view taken along line BB ′ shown in FIG. 18B.
  • FIG. 20 is a plan view showing a source electrode according to Embodiment 4 of the present invention.
  • FIG. 21 is a plan view showing a main part of a transistor according to Embodiment 4 of the present invention.
  • 22A is a cross-sectional view taken along line AA ′ shown in FIG. 22B is a cross-sectional view taken along the line BB ′ shown in FIG. 22C is a cross-sectional view taken along the line CC ′ shown in FIG.
  • the transistor 100 of the fourth embodiment will be described with reference to FIGS. Components similar to those of the transistor 100 of Embodiment 1 shown in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof is omitted.
  • the source electrode 5 is composed of a pair of electrodes 5k and 5l.
  • One electrode 5k is electrically connected to the metal layer 2 by vias 11k and 12k penetrating the dielectric substrate 1.
  • the other electrode 5 l is electrically connected to the metal layer 2 by vias 11 l and 12 l penetrating the dielectric substrate 1.
  • the vias 11k and 11l are arranged in a half portion on the gate terminal 6 side of the dielectric substrate 1.
  • the vias 12k and 12l are arranged in a half part on the dielectric substrate 1 on the drain terminal 7 side.
  • the dielectric substrate 1, the metal layer 2, the gate electrode 3, the drain electrode 4, the source electrode 5, the gate terminal 6 and the drain terminal 7 constitute the main part of the transistor 100.
  • the operation of the transistor 100 according to the fourth embodiment is the same as that described in the first embodiment, description thereof is omitted. Further, the effect of the transistor 100 according to the fourth embodiment is the same as that described with reference to FIGS. 6 and 7 in the first embodiment, and thus illustration and description thereof are omitted.
  • the gate bus bar 31 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire gate bus bar 31. That is, the gate bus bar 31 may have the same shape as the gate bus bar 31 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5 may have a shape formed by removing the portions 52 1 to 52 8 shown in FIG.
  • the drain bus bar 41 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire drain bus bar 41. That is, the drain bus bar 41 may have the same shape as the drain bus bar 41 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5 may have a shape formed by removing the portions 53 1 to 53 4 shown in FIG.
  • the transistor 100 according to the fourth embodiment is provided on the metal layer 2 provided on the back surface portion of the dielectric substrate 1 and on the front surface portion of the dielectric substrate 1, and includes the gate bus bar 31 and the gate bus bar 31.
  • the gate electrode 3 having a plurality of gate fingers 32 1 to 32 10 that are electrically connected to each other by the above and vias 11k, 11l that are provided on the surface portion of the dielectric substrate 1 and penetrate the dielectric substrate 1.
  • part of the gate bus bar 31 (region 33 1-33 8) is constituted by an air bridge wiring, the air bridge wiring And part of the source electrode 5 (parts 52 1 to 52 8 ) are disposed between the dielectric substrate 1 and the dielectric substrate 1.
  • the transistor 100 according to the fourth embodiment is provided on the metal layer 2 provided on the back surface of the dielectric substrate 1 and on the front surface of the dielectric substrate 1, and is electrically connected to each other by the drain bus bar 41 and the drain bus bar 41.
  • a source electrode 5 electrically connected to the metal layer 2 and a part of the drain bus bar 41 (parts 43 1 to 43 4 ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric A part of the source electrode 5 (parts 53 1 to 53 4 ) is disposed between the substrate 1 and the substrate 1.
  • the transistor of the present invention can be used, for example, for amplifying a high frequency signal in a radio communication device or a radar device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un transistor (100) comprenant : une couche métallique (2) disposée sur une partie de surface arrière d'un substrat diélectrique (1); une électrode de grille (3) disposée sur une partie de surface du substrat diélectrique (1), et ayant une barre omnibus de grille (31) et une pluralité de doigts de grille (321-3210) connectés électriquement l'un à l'autre par la barre omnibus de grille (31); et une électrode de source (5) qui est disposée sur la partie de surface du substrat diélectrique (1) et connectée électriquement à la couche métallique (2) par des trous d'interconnexion (11a, 11b) qui passent à travers le substrat diélectrique (1), une partie de la barre omnibus de grille (31) étant configurée à partir d'un fil de pont aérien, et une partie de l'électrode de source (5) étant disposée entre ledit fil de pont aérien et le substrat diélectrique (1).
PCT/JP2017/002280 2017-01-24 2017-01-24 Transistor WO2018138764A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200062938A (ko) * 2018-11-27 2020-06-04 삼성전기주식회사 스택된 전계효과트랜지스터(fet)를 갖는 반도체 디바이스

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0750422A (ja) * 1993-08-05 1995-02-21 Nec Corp 半導体装置
JPH098064A (ja) * 1995-06-20 1997-01-10 Siemens Ag 半導体デバイス
JP2007081124A (ja) * 2005-09-14 2007-03-29 Toshiba Corp 半導体装置
JP2013183061A (ja) * 2012-03-02 2013-09-12 Toshiba Corp 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0750422A (ja) * 1993-08-05 1995-02-21 Nec Corp 半導体装置
JPH098064A (ja) * 1995-06-20 1997-01-10 Siemens Ag 半導体デバイス
JP2007081124A (ja) * 2005-09-14 2007-03-29 Toshiba Corp 半導体装置
JP2013183061A (ja) * 2012-03-02 2013-09-12 Toshiba Corp 半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200062938A (ko) * 2018-11-27 2020-06-04 삼성전기주식회사 스택된 전계효과트랜지스터(fet)를 갖는 반도체 디바이스
KR102149388B1 (ko) 2018-11-27 2020-08-28 삼성전기주식회사 스택된 전계효과트랜지스터(fet)를 갖는 반도체 디바이스

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