JPWO2018138764A1 - トランジスタ - Google Patents
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- JPWO2018138764A1 JPWO2018138764A1 JP2017533986A JP2017533986A JPWO2018138764A1 JP WO2018138764 A1 JPWO2018138764 A1 JP WO2018138764A1 JP 2017533986 A JP2017533986 A JP 2017533986A JP 2017533986 A JP2017533986 A JP 2017533986A JP WO2018138764 A1 JPWO2018138764 A1 JP WO2018138764A1
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- 239000000758 substrate Substances 0.000 claims abstract description 139
- 239000002184 metal Substances 0.000 claims abstract description 56
- 230000000149 penetrating effect Effects 0.000 claims abstract description 17
- 230000000694 effects Effects 0.000 description 4
- 230000001902 propagating effect Effects 0.000 description 4
- 230000005672 electromagnetic field Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
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- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
図1Aは、本発明の実施の形態1に係るゲート電極を示す平面図である。図1Bは、本発明の実施の形態1に係るドレイン電極を示す平面図である。図2Aは、図1Aに示すA−A’線に沿う断面図である。図2Bは、図1Bに示すB−B’線に沿う断面図である。図3は、本発明の実施の形態1に係るソース電極を示す平面図である。図4は、本発明の実施の形態1に係るトランジスタの要部を示す平面図である。図5Aは、図4に示すA−A’線に沿う断面図である。図5Bは、図4に示すB−B’線に沿う断面図である。図5Cは、図4に示すC−C’線に沿う断面図である。図1〜図5を参照して、実施の形態1のトランジスタ100について説明する。
図8Aは、本発明の実施の形態2に係るゲート電極を示す平面図である。図8Bは、本発明の実施の形態2に係るドレイン電極を示す平面図である。図9Aは、図8Aに示すA−A’線に沿う断面図である。図9Bは、図8Bに示すB−B’線に沿う断面図である。図10は、本発明の実施の形態2に係るソース電極を示す平面図である。図11は、本発明の実施の形態2に係るトランジスタの要部を示す平面図である。図12Aは、図11に示すA−A’線に沿う断面図である。図12Bは、図11に示すB−B’線に沿う断面図である。図12Cは、図11に示すC−C’線に沿う断面図である。
図13Aは、本発明の実施の形態3に係るゲート電極を示す平面図である。図13Bは、本発明の実施の形態3に係るドレイン電極を示す平面図である。図14Aは、図13Aに示すA−A’線に沿う断面図である。図14Bは、図13Bに示すB−B’線に沿う断面図である。図15は、本発明の実施の形態3に係るソース電極を示す平面図である。図16は、本発明の実施の形態3に係るトランジスタの要部を示す平面図である。図17Aは、図16に示すA−A’線に沿う断面図である。図17Bは、図16に示すB−B’線に沿う断面図である。図17Cは、図16に示すC−C’線に沿う断面図である。
図18Aは、本発明の実施の形態4に係るゲート電極を示す平面図である。図18Bは、本発明の実施の形態4に係るドレイン電極を示す平面図である。図19Aは、図18Aに示すA−A’線に沿う断面図である。図19Bは、図18Bに示すB−B’線に沿う断面図である。図20は、本発明の実施の形態4に係るソース電極を示す平面図である。図21は、本発明の実施の形態4に係るトランジスタの要部を示す平面図である。図22Aは、図21に示すA−A’線に沿う断面図である。図22Bは、図21に示すB−B’線に沿う断面図である。図22Cは、図21に示すC−C’線に沿う断面図である。
Claims (8)
- 誘電体基板の裏面部に設けられた金属層と、
前記誘電体基板の表面部に設けられており、ゲートバスバーと前記ゲートバスバーにより互いに電気的に接続された複数本のゲートフィンガーとを有するゲート電極と、
前記誘電体基板の表面部に設けられており、前記誘電体基板を貫通したビアにより前記金属層と電気的に接続されたソース電極と、を備え、
前記ゲートバスバーの一部がエアブリッジ配線により構成されており、当該エアブリッジ配線と前記誘電体基板との間に前記ソース電極の一部が配置されている
ことを特徴とするトランジスタ。 - 前記金属層は電気的に接地されていることを特徴とする請求項1記載のトランジスタ。
- 前記ビアは互いに隣接する前記ゲートフィンガー間に配置されていることを特徴とする請求項1記載のトランジスタ。
- 前記誘電体基板の表面部に設けられており、ドレインバスバーと前記ドレインバスバーにより互いに電気的に接続された複数本のドレインフィンガーとを有するドレイン電極を備え、
前記ドレインバスバーの一部がエアブリッジ配線により構成されており、当該エアブリッジ配線と前記誘電体基板との間に前記ソース電極の一部が配置されている
ことを特徴とする請求項1記載のトランジスタ。 - 誘電体基板の裏面部に設けられた金属層と、
前記誘電体基板の表面部に設けられており、ドレインバスバーと前記ドレインバスバーにより互いに電気的に接続された複数本のドレインフィンガーとを有するドレイン電極と、
前記誘電体基板の表面部に設けられており、前記誘電体基板を貫通したビアにより前記金属層と電気的に接続されたソース電極と、を備え、
前記ドレインバスバーの一部がエアブリッジ配線により構成されており、当該エアブリッジ配線と前記誘電体基板との間に前記ソース電極の一部が配置されている
ことを特徴とするトランジスタ。 - 前記金属層は電気的に接地されていることを特徴とする請求項5記載のトランジスタ。
- 前記ビアは互いに隣接する前記ドレインフィンガー間に配置されていることを特徴とする請求項5記載のトランジスタ。
- 前記誘電体基板の表面部に設けられており、ゲートバスバーと前記ゲートバスバーにより互いに電気的に接続された複数本のゲートフィンガーとを有するゲート電極を備え、
前記ゲートバスバーの一部がエアブリッジ配線により構成されており、当該エアブリッジ配線と前記誘電体基板との間に前記ソース電極の一部が配置されている
ことを特徴とする請求項5記載のトランジスタ。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2017/002280 WO2018138764A1 (ja) | 2017-01-24 | 2017-01-24 | トランジスタ |
Publications (2)
Publication Number | Publication Date |
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JP6246432B1 JP6246432B1 (ja) | 2017-12-13 |
JPWO2018138764A1 true JPWO2018138764A1 (ja) | 2019-02-07 |
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JP2017533986A Active JP6246432B1 (ja) | 2017-01-24 | 2017-01-24 | トランジスタ |
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JP (1) | JP6246432B1 (ja) |
WO (1) | WO2018138764A1 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102149388B1 (ko) * | 2018-11-27 | 2020-08-28 | 삼성전기주식회사 | 스택된 전계효과트랜지스터(fet)를 갖는 반도체 디바이스 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2580966B2 (ja) * | 1993-08-05 | 1997-02-12 | 日本電気株式会社 | 半導体装置 |
DE19522364C1 (de) * | 1995-06-20 | 1996-07-04 | Siemens Ag | Halbleiter-Bauelement |
JP2007081124A (ja) * | 2005-09-14 | 2007-03-29 | Toshiba Corp | 半導体装置 |
JP2013183061A (ja) * | 2012-03-02 | 2013-09-12 | Toshiba Corp | 半導体装置 |
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2017
- 2017-01-24 JP JP2017533986A patent/JP6246432B1/ja active Active
- 2017-01-24 WO PCT/JP2017/002280 patent/WO2018138764A1/ja active Application Filing
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