WO2018138764A1 - Transistor - Google Patents

Transistor Download PDF

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Publication number
WO2018138764A1
WO2018138764A1 PCT/JP2017/002280 JP2017002280W WO2018138764A1 WO 2018138764 A1 WO2018138764 A1 WO 2018138764A1 JP 2017002280 W JP2017002280 W JP 2017002280W WO 2018138764 A1 WO2018138764 A1 WO 2018138764A1
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WO
WIPO (PCT)
Prior art keywords
gate
dielectric substrate
bus bar
drain
transistor
Prior art date
Application number
PCT/JP2017/002280
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French (fr)
Japanese (ja)
Inventor
純 神岡
山中 宏治
政毅 半谷
Original Assignee
三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2017533986A priority Critical patent/JP6246432B1/en
Priority to PCT/JP2017/002280 priority patent/WO2018138764A1/en
Publication of WO2018138764A1 publication Critical patent/WO2018138764A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41758Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate

Definitions

  • the present invention relates to a transistor, and more particularly to a high-frequency transistor.
  • a transistor is used to amplify a high-frequency signal in a wireless communication device or a radar device.
  • a source-grounded field effect transistor Field Effect Transistor, FET
  • Patent Document 1 discloses an FET in which a substantially comb-shaped gate electrode and a substantially comb-shaped drain electrode are arranged so as to mesh with each other, a so-called “multi-finger type” FET.
  • a gate electrode in a multi-finger type FET (hereinafter referred to as “multi-finger FET”) has at least one gate bus bar and a plurality of gate fingers provided substantially perpendicular to the gate bus bar. Yes. Further, the drain electrode in the multi-finger FET has one or more drain bus bars and a plurality of drain fingers provided substantially perpendicular to the drain bus bars.
  • the gate electrode and the drain electrode are provided on the front surface portion of the dielectric substrate, and a metal layer is provided on the back surface portion of the dielectric substrate. This metal layer is electrically grounded.
  • a microstrip line is constituted by the gate bus bar, and a microstrip line is constituted by the drain bus bar.
  • a high-frequency signal propagates through these microstrip lines, an electromagnetic field is generated in the dielectric substrate, so that a dielectric loss corresponding to the dielectric loss tangent occurs. Due to this dielectric loss, there is a problem that the gain, output power and efficiency of the transistor are lowered.
  • the present invention has been made to solve the above-described problems, and an object thereof is to provide a transistor having high gain, high output power, and high efficiency.
  • the transistor of the present invention includes a metal layer provided on the back surface of the dielectric substrate, and a plurality of gate fingers provided on the front surface of the dielectric substrate and electrically connected to each other by the gate bus bar. And a source electrode electrically connected to the metal layer by a via penetrating the dielectric substrate, and a part of the gate bus bar is an air bridge It is constituted by wiring, and a part of the source electrode is arranged between the air bridge wiring and the dielectric substrate.
  • the transistor of the present invention includes a metal layer provided on the back surface of the dielectric substrate and a plurality of drain fingers provided on the front surface of the dielectric substrate and electrically connected to each other by the drain bus bar and the drain bus bar. And a source electrode electrically connected to the metal layer by a via penetrating the dielectric substrate, and a part of the drain bus bar is an air bridge It is constituted by wiring, and a part of the source electrode is arranged between the air bridge wiring and the dielectric substrate.
  • FIG. 1A is a plan view showing a gate electrode according to Embodiment 1 of the present invention.
  • FIG. 1B is a plan view showing the drain electrode according to Embodiment 1 of the present invention.
  • 2A is a cross-sectional view taken along line A-A ′ shown in FIG. 1A.
  • 2B is a cross-sectional view taken along line B-B ′ shown in FIG. 1B.
  • It is a top view which shows the source electrode which concerns on Embodiment 1 of this invention.
  • FIG. 5A is a cross-sectional view taken along line A-A ′ shown in FIG. FIG.
  • FIG. 5B is a cross-sectional view taken along line B-B ′ shown in FIG.
  • FIG. 5C is a cross-sectional view taken along line C-C ′ shown in FIG. It is a top view which shows the principal part of the transistor used as the comparison object with the transistor which concerns on Embodiment 1 of this invention.
  • FIG. 7A is a cross-sectional view taken along line C-C ′ shown in FIG.
  • FIG. 7B is a cross-sectional view taken along line C-C ′ shown in FIG.
  • FIG. 8A is a plan view showing a gate electrode according to Embodiment 2 of the present invention.
  • FIG. 8B is a plan view showing the drain electrode according to Embodiment 2 of the present invention.
  • FIG. 9A is a cross-sectional view taken along line A-A ′ shown in FIG. 8A.
  • FIG. 9B is a cross-sectional view taken along line B-B ′ shown in FIG. 8B. It is a top view which shows the source electrode which concerns on Embodiment 2 of this invention. It is a top view which shows the principal part of the transistor which concerns on Embodiment 2 of this invention.
  • 12A is a cross-sectional view taken along line A-A ′ shown in FIG. 12B is a cross-sectional view taken along line B-B ′ shown in FIG. 12C is a cross-sectional view taken along line C-C ′ shown in FIG.
  • FIG. 13A is a plan view showing a gate electrode according to Embodiment 3 of the present invention.
  • FIG. 13B is a plan view showing the drain electrode according to Embodiment 3 of the present invention.
  • 14A is a cross-sectional view taken along line A-A ′ shown in FIG. 13A.
  • 14B is a cross-sectional view taken along line B-B ′ shown in FIG. 13B.
  • It is a top view which shows the source electrode which concerns on Embodiment 3 of this invention.
  • FIG. 17A is a cross-sectional view along the line A-A ′ shown in FIG. 16.
  • FIG. 17B is a cross-sectional view along the line B-B ′ shown in FIG. 16.
  • FIG. 17C is a cross-sectional view taken along line C-C ′ shown in FIG.
  • FIG. 18A is a plan view showing a gate electrode according to Embodiment 4 of the present invention.
  • FIG. 18B is a plan view showing the drain electrode according to Embodiment 4 of the present invention.
  • FIG. 19A is a cross-sectional view taken along line A-A ′ shown in FIG. 18A.
  • FIG. 19B is a cross-sectional view taken along line B-B ′ shown in FIG. 18B. It is a top view which shows the source electrode which concerns on Embodiment 4 of this invention.
  • 22A is a cross-sectional view taken along line A-A ′ shown in FIG. 22B is a cross-sectional view taken along line B-B ′ shown in FIG. 22C is a cross-sectional view taken along line C-C ′ shown in FIG.
  • FIG. 1A is a plan view showing a gate electrode according to Embodiment 1 of the present invention.
  • FIG. 1B is a plan view showing the drain electrode according to Embodiment 1 of the present invention.
  • 2A is a cross-sectional view taken along line AA ′ shown in FIG. 1A.
  • 2B is a cross-sectional view taken along line BB ′ shown in FIG. 1B.
  • FIG. 3 is a plan view showing the source electrode according to Embodiment 1 of the present invention.
  • FIG. 4 is a plan view showing the main part of the transistor according to Embodiment 1 of the present invention.
  • FIG. 5A is a cross-sectional view taken along line AA ′ shown in FIG.
  • FIG. 5B is a cross-sectional view taken along the line BB ′ shown in FIG.
  • FIG. 5C is a cross-sectional view taken along the line CC ′ shown in FIG.
  • the transistor 100 of Embodiment 1 will be described.
  • 1 is a dielectric substrate.
  • An electrically grounded metal layer 2 is provided on the back surface of the dielectric substrate 1.
  • a gate electrode 3, a drain electrode 4, and a source electrode 5 are provided on the surface portion of the dielectric substrate 1.
  • the gate electrode 3 has one gate bus bar 31 and ten gate fingers 32 1 to 32 10 provided substantially perpendicular to the gate bus bar 31. Thereby, the outer shape of the gate electrode 3 is substantially comb-shaped.
  • the gate fingers 32 1 to 32 10 are electrically connected to each other by a gate bus bar 31.
  • Each of the gate fingers 32 1 to 32 10 is electrically connected to the gate terminal 6 via the gate bus bar 31.
  • the drain electrode 4 has one drain bus bar 41 and five drain fingers 42 1 to 42 5 provided substantially perpendicular to the drain bus bar 41. Thereby, the external shape of the drain electrode 4 is substantially comb-shaped. Drain finger 42 1-42 5 are electrically connected to each other by the drain bus bar 41. Further, each of the drain finger 42 1-42 5 are drain terminals 7 electrically connected via a drain bus bar 41.
  • the gate electrode 3 and the drain electrode 4 are arranged to face each other so that the gate fingers 32 1 to 32 10 and the drain fingers 42 1 to 42 5 are engaged with each other. More specifically, the drain finger 42 1 is disposed between the gate fingers 32 1, 32 2 adjacent to each other, the drain finger 42 2 is disposed between the gate fingers 32 3, 32 4 adjacent to each other, gate adjacent to each other a drain finger 42 3 disposed fingers 32 5, 32 between 6, the drain finger 42 4 is disposed between the gate fingers 32 7, 32 8 which are adjacent to each other, the drain finger between the gate fingers 32 9, 32 10 that are adjacent to each other 42 5 is arranged. That is, the transistor 100 is a multi-finger type.
  • a part of gate bus-bar 31 is comprised by the air bridge wiring. More specifically, the gate finger 32 and the gate fingers 32 1, 32 parts 33 1 connecting between 2 and portion 33 2 for connecting the gate fingers 32 2, 32 3 which are adjacent to each other, adjacent to each other adjacent to each other 3, and 32 4 sites 33 3 which connects a portion 33 4 for connecting the gate fingers 32 4, 32 5 which are adjacent to each other, the portion 33 5 for connecting the gate fingers 32 6, 32 7 adjacent to each other , A portion 33 6 connecting the gate fingers 32 7 and 32 8 adjacent to each other, a portion 33 7 connecting the gate fingers 32 8 and 32 9 adjacent to each other, and between the gate fingers 32 9 and 32 10 adjacent to each other each of the sites 33 8 for connecting is formed by an air-bridge wiring.
  • gate air bridge the portion 33 1-33 8 constituted by an air bridge line of the gate bus bar 31 may be referred to as "gate air bridge".
  • the remaining part of the gate bus bar 31 constitutes a microstrip line.
  • drain bus bar 41 a part of the drain bus bar 41 is constituted by an air bridge wiring.
  • Drain finger 42 More specifically, a portion 43 1 that connects between the drain finger 42 1, 42 2 adjacent to each other, the portion 43 2 which connects between the drain finger 42 2, 42 3 adjacent to each other, adjacent to each other 3, and 42 4 sites 43 3 which connects the, each of the drain finger 42 4, 42 5 parts 43 4 for connecting the adjacent is constituted by an air-bridge interconnection with each other.
  • drain air bridge the portions 43 1 to 43 4 constituted by the air bridge wiring in the drain bus bar 41 may be referred to as “drain air bridge”.
  • the remaining part of the drain bus bar 41 constitutes a microstrip line.
  • the source electrode 5 is composed of a pair of electrodes 5a and 5b.
  • One electrode 5 a is electrically connected to the metal layer 2 by a via 11 a penetrating the dielectric substrate 1.
  • the other electrode 5 b is electrically connected to the metal layer 2 by a via 11 b that penetrates the dielectric substrate 1.
  • the vias 11a and 11b are arranged in the half portion on the gate terminal 6 side of the dielectric substrate 1. That is, the source electrode 5 is electrically grounded, and the transistor 100 is a grounded source type.
  • the source electrode 5 has portions 51 1 to 51 6 arranged in parallel to the gate fingers 32 1 to 32 10 and the drain fingers 42 1 to 42 5 . More specifically, the source electrode 5 is disposed between a portion 51 1 disposed outside the gate finger 32 1 provided at one end of the gate bus bar 31 and the gate fingers 32 2 and 32 3 adjacent to each other. a portion 51 2 which is, the gate finger 32 4, 32 5 parts 51 3 disposed between the mutually adjacent gate fingers 32 6, 32 7 sites 51 4 disposed between the adjacent, adjacent the gate fingers 32 8, 32 parts 51 5 disposed between 9 and a portion 51 6 arranged outside the gate fingers 32 10 provided on the other end of the gate bus bar 31.
  • the dielectric substrate 1, the metal layer 2, the gate electrode 3, the drain electrode 4, the source electrode 5, the gate terminal 6 and the drain terminal 7 constitute the main part of the transistor 100.
  • a high frequency signal is input to the gate terminal 6.
  • the input high frequency signal is distributed to each of the gate fingers 32 1 to 32 10 via the gate bus bar 31.
  • amplified radio frequency signal is output.
  • These high frequency signals are combined by the drain bus bar 41 and output to the drain terminal 7.
  • FIG. 6 is a plan view showing a main part of a transistor 100 ′ to be compared with the transistor 100 according to the first embodiment.
  • FIG. 7A is a cross-sectional view taken along line C-C ′ shown in FIG. 6, that is, a cross-sectional view of the transistor 100 ′.
  • FIG. 7B is a cross-sectional view taken along the line C-C ′ shown in FIG. 4, that is, a cross-sectional view of the transistor 100.
  • an electrically grounded metal layer 2 ′ is provided on the back surface of the dielectric substrate 1 ′, and the gate electrode 3 ′ and the surface of the dielectric substrate 1 ′ are provided.
  • a drain electrode 4 ' is provided. 6 and 7A, the source electrode is not shown.
  • the gate electrode 3 ' is one gate bus bar 31' has a gate finger 32 first ten and ' ⁇ 32 10' and each of the gate fingers 32 1 'to 32 10' through the gate bus bar 31 ' Are electrically connected to the gate terminal 6 '.
  • a drain electrode 4 ' is one of the drain bus bar 41' has a five drain finger 42 1 'to 42 5' and each of the drain finger 42 1 ' ⁇ 42 5' is via the drain bus bar 41 ' Are electrically connected to the drain terminal 7 '.
  • the gate bus bar 31 'does not have an air bridge wiring, and substantially the entire gate bus bar 31' constitutes a microstrip line.
  • the drain bus bar 41 ′ does not have an air bridge wiring, and substantially the entire drain bus bar 41 ′ constitutes a microstrip line.
  • the high frequency signal is transmitted in the micro trip mode.
  • An electromagnetic field corresponding to the high-frequency signal is generated between the gate bus bar 31 'and the metal layer 2'.
  • Six arrows A1 'shown in FIG. 7A indicate electric lines of force corresponding to the power of the high-frequency signal propagating through the gate bus bar 31'.
  • the electric force lines A1 ' start at the gate bus bar 31', and the electric lines A1 'end at the electrically grounded metal layer 2'. That is, the electric lines of force A1 'pass through the dielectric substrate 1'. Since the dielectric substrate 1 'has a finite conductance and a finite dielectric loss tangent, a dielectric loss corresponding to the dielectric loss tangent occurs. This dielectric loss reduces the gain, output power and efficiency of transistor 100 '.
  • a part of the gate bus bar 31 is configured by an air bridge wiring, and a part of the source electrode 5 is interposed between the air bridge wiring and the dielectric substrate 1.
  • the six arrows A1 shown in FIG. 7B indicate electric lines of force corresponding to the power of the high-frequency signal propagating through the gate air bridge.
  • the beginning of the electric power line A1 denotes a gate bus bar 31 (region 33 2)
  • the end of the electric line of force A1 is the source electrode 5 which is electrically grounded (sites 52 2). That is, the electric lines of force A1 do not pass through the dielectric substrate 1 but pass through the air. Thereby, it is possible to prevent the dielectric loss due to the dielectric loss tangent of the dielectric substrate 1 from occurring.
  • the high frequency signal is transmitted in the micro trip mode in the drain bus bar 41 ′ of the transistor 100 ′.
  • An electromagnetic field corresponding to the high-frequency signal is generated between the drain bus bar 41 'and the metal layer 2'.
  • Six arrows A2 'shown in FIG. 7A indicate electric lines of force corresponding to the power of the high-frequency signal propagating through the drain bus bar 41'.
  • the electric force line A2 ' starts at the drain bus bar 41'
  • a part of the drain bus bar 41 is configured by an air bridge wiring, and a part of the source electrode 5 is interposed between the air bridge wiring and the dielectric substrate 1.
  • the six arrows A2 shown in FIG. 7B indicate electric lines of force corresponding to the power of the high-frequency signal propagating through the drain air bridge.
  • the starting end of the electric force line A2 is the drain bus bar 41 (part 43 1 )
  • the end of the electric line of force A2 is the electrically grounded source electrode 5 (part 53 1 ). That is, the electric lines of force A2 do not pass through the dielectric substrate 1 but pass through the air. Thereby, it is possible to prevent the dielectric loss due to the dielectric loss tangent of the dielectric substrate 1 from occurring.
  • the drain bus bar 41 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire drain bus bar 41. That is, the drain bus bar 41 may have the same shape as the drain bus bar 41 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5 may have a shape obtained by removing the portions 53 1 to 53 4 shown in FIG.
  • the number of gate bus bars 31 may be one or more, and is not limited to one.
  • the number of gate fingers 32 1 to 32 10 may be plural, and is not limited to ten.
  • the number of drain bus bars 41 may be one or more, and is not limited to one.
  • the number of drain fingers 42 1 to 42 5 may be a plurality, and is not limited to five.
  • the transistor 100 of the first embodiment is provided on the metal layer 2 provided on the back surface portion of the dielectric substrate 1 and on the front surface portion of the dielectric substrate 1, and includes the gate bus bar 31 and the gate bus bar 31.
  • the gate electrode 3 having a plurality of gate fingers 32 1 to 32 10 that are electrically connected to each other by the above, and vias 11 a and 11 b that are provided on the surface portion of the dielectric substrate 1 and penetrate the dielectric substrate 1.
  • the transistor 100 of the first embodiment is provided on the metal layer 2 provided on the back surface of the dielectric substrate 1 and on the front surface of the dielectric substrate 1, and is electrically connected to each other by the drain bus bar 41 and the drain bus bar 41.
  • the drain electrode 4 having a plurality of connected drain fingers 42 1 to 42 5 and a metal layer formed by vias 11 a and 11 b penetrating the dielectric substrate 1 are provided on the surface of the dielectric substrate 1. 2 and a source electrode 5 electrically connected to each other, and a part of the drain bus bar 41 (parts 43 1 to 43 4 ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric substrate 1 are connected to each other. part of the source electrode 5 (sites 53 1-53 4) is disposed between.
  • FIG. FIG. 8A is a plan view showing a gate electrode according to Embodiment 2 of the present invention.
  • FIG. 8B is a plan view showing the drain electrode according to Embodiment 2 of the present invention.
  • FIG. 9A is a cross-sectional view taken along line AA ′ shown in FIG. 8A.
  • FIG. 9B is a cross-sectional view taken along line BB ′ shown in FIG. 8B.
  • FIG. 10 is a plan view showing a source electrode according to Embodiment 2 of the present invention.
  • FIG. 11 is a plan view showing a main part of a transistor according to Embodiment 2 of the present invention.
  • 12A is a cross-sectional view taken along line AA ′ shown in FIG. 12B is a cross-sectional view taken along the line BB ′ shown in FIG. 12C is a cross-sectional view taken along the line CC ′ shown in FIG.
  • the transistor 100 of the second embodiment will be described with reference to FIGS. Components similar to those of the transistor 100 of Embodiment 1 shown in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof is omitted.
  • a part of the gate bus bar 31 is configured by air bridge wiring. More specifically, the gate finger 32 and the gate fingers 32 2, 32 3 parts 33 2 connected between a site 33 4 for connecting the gate fingers 32 4, 32 5 which are adjacent to each other, adjacent to each other adjacent to each other 6, and 32 7 sites 33 5 connecting between each of the gate fingers 32 8, 32 9 parts 33 7 connecting between adjacent is constituted by an air-bridge interconnection with each other.
  • the remaining part of the gate bus bar 31 constitutes a microstrip line.
  • the source electrode 5 is composed of six substantially rectangular electrodes 5c to 5h.
  • the electrodes 5c to 5h are electrically connected to the metal layer 2 through vias 11c to 11h penetrating the dielectric substrate 1, respectively.
  • the source electrode 5 has portions 51 1 to 51 6 arranged in parallel to the gate fingers 32 1 to 32 10 and the drain fingers 42 1 to 42 5 . These sites 51 1-51 6 are provided one on electrodes 5c ⁇ 5h.
  • the via 11c ⁇ 11h are respectively arranged in the center of these sites 51 1-51 6.
  • the four vias 11d to 11g among the six vias 11c to 11h are arranged between the adjacent gate fingers of the gate fingers 32 2 to 32 10 , and the drain fingers 42 1 to 42 are provided. 5 between the adjacent drain fingers.
  • the via 11d is disposed between the gate fingers 32 2, 32 3 which are adjacent to each other, via 11e is disposed between the gate fingers 32 4, 32 5 which are adjacent to each other, the gate fingers via 11f adjacent to each other 32 6, 32 are disposed between 7, vias 11g is disposed between the gate fingers 32 8, 32 9 adjacent to each other.
  • the via 11d is disposed between the drain fingers 42 1 and 42 2 adjacent to each other, the via 11e is disposed between the drain fingers 42 2 and 42 3 adjacent to each other, and the via 11f is disposed adjacent to the drain fingers 42 3 and 42. 4 , the via 11 g is disposed between the drain fingers 42 4 and 4 5 adjacent to each other.
  • the source electrode 5 is disposed between each gate air bridge and the dielectric substrate 1, that is, between each of the portions 33 2 , 33 4 , 33 5 , and 33 7 of the gate bus bar 31 and the dielectric substrate 1.
  • the region 52 2 , 52 4 , 52 5 , 52 7 is formed.
  • These portions 52 2 , 52 4 , 52 5 , and 52 7 are connected to the four electrodes 5d to 5g excluding the electrodes 5c and 5h arranged at both ends of the six electrodes 5c to 5h arranged in parallel to each other. One by one.
  • Each of these portions 53 1 to 53 4 is provided on each of the four electrodes 5d to 5g excluding the electrodes 5c and 5h arranged at both ends of the six electrodes 5c to 5h arranged in parallel to each other. Yes.
  • the dielectric substrate 1, the metal layer 2, the gate electrode 3, the drain electrode 4, the source electrode 5, the gate terminal 6 and the drain terminal 7 constitute the main part of the transistor 100.
  • the operation of the transistor 100 according to the second embodiment is the same as that described in the first embodiment, description thereof is omitted.
  • the effect of the transistor 100 according to the second embodiment is the same as that described with reference to FIGS. 6 and 7 in the first embodiment, and thus illustration and description thereof are omitted.
  • the gate bus bar 31 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire gate bus bar 31. That is, the gate bus bar 31 may have the same shape as the gate bus bar 31 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5, part 52 2, 52 4 shown in FIG. 10, 52 5, 52 7 may be then formed by the shape removed.
  • the drain bus bar 41 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire drain bus bar 41. That is, the drain bus bar 41 may have the same shape as the drain bus bar 41 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5 may have a shape formed by removing the portions 53 1 to 53 4 shown in FIG.
  • the number of electrodes 5c to 5h constituting the source electrode 5 may be a number corresponding to the number of gate fingers 32 1 to 32 10 and the number of drain fingers 42 1 to 42 5 , and is limited to six. It is not a thing.
  • the transistor 100 according to the second embodiment is provided on the metal layer 2 provided on the back surface portion of the dielectric substrate 1 and on the front surface portion of the dielectric substrate 1, and includes the gate bus bar 31 and the gate bus bar 31.
  • the gate electrode 3 having a plurality of gate fingers 32 1 to 32 10 that are electrically connected to each other by the above, and vias 11c to 11h that are provided on the surface portion of the dielectric substrate 1 and penetrate the dielectric substrate 1
  • a part of the gate bus bar 31 are configured by air bridge wiring, and the source electrode 5 is electrically connected to the metal layer 2 by the air bridge wiring.
  • Part of the source electrode 5 (parts 52 2 , 52 4 , 52 5 , 52 7 ) is disposed between the bridge wiring and the dielectric substrate 1. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the gate air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.
  • the vias 11d to 11g are arranged between the gate fingers adjacent to each other. Accordingly, since the area of the source electrode 5 can be reduced, the transistor 100 can be reduced in size.
  • the transistor 100 of the second embodiment is provided on the metal layer 2 provided on the back surface of the dielectric substrate 1 and on the front surface of the dielectric substrate 1, and is electrically connected to each other by the drain bus bar 41 and the drain bus bar 41.
  • the drain electrode 4 having a plurality of connected drain fingers 42 1 to 42 5 and a metal layer formed on the surface of the dielectric substrate 1 and vias 11c to 11h penetrating the dielectric substrate 1 2 and a source electrode 5 electrically connected to each other, and a part of the drain bus bar 41 (parts 43 1 to 43 4 ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric substrate 1 are connected to each other.
  • a part of the source electrode 5 (parts 53 1 to 53 4 ) is disposed between them.
  • the vias 11d to 11g are arranged between the drain fingers adjacent to each other. Accordingly, since the area of the source electrode 5 can be reduced, the transistor 100 can be reduced in size.
  • FIG. 13A is a plan view showing a gate electrode according to Embodiment 3 of the present invention.
  • FIG. 13B is a plan view showing the drain electrode according to Embodiment 3 of the present invention.
  • 14A is a cross-sectional view taken along line AA ′ shown in FIG. 13A.
  • 14B is a cross-sectional view taken along line BB ′ shown in FIG. 13B.
  • FIG. 15 is a plan view showing a source electrode according to Embodiment 3 of the present invention.
  • FIG. 16 is a plan view showing a main part of a transistor according to Embodiment 3 of the present invention.
  • 17A is a cross-sectional view taken along line AA ′ shown in FIG.
  • FIG. 17B is a cross-sectional view taken along the line BB ′ shown in FIG.
  • FIG. 17C is a cross-sectional view taken along the line CC ′ shown in FIG.
  • the transistor 100 of the third embodiment will be described with reference to FIGS. Components similar to those of the transistor 100 of Embodiment 1 shown in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof is omitted.
  • a part of the gate bus bar 31 is configured by air bridge wiring. More specifically, the gate finger 32 and the gate fingers 32 2, 32 3 parts 33 2 connected between a site 33 4 for connecting the gate fingers 32 4, 32 5 which are adjacent to each other, adjacent to each other adjacent to each other 6, and 32 7 sites 33 5 connecting between each of the gate fingers 32 8, 32 9 parts 33 7 connecting between adjacent is constituted by an air-bridge interconnection with each other.
  • the remaining part of the gate bus bar 31 constitutes a microstrip line.
  • the source electrode 5 is composed of a pair of electrodes 5i and 5j.
  • One electrode 5 i is electrically connected to the metal layer 2 through a via 11 i penetrating the dielectric substrate 1.
  • the other electrode 5j is electrically connected to the metal layer 2 by a via 11j penetrating the dielectric substrate 1.
  • the vias 11 i and 11 j are arranged in the half part of the dielectric substrate 1 on the drain terminal 7 side.
  • the source electrode 5 has portions 51 1 to 51 6 arranged in parallel to the gate fingers 32 1 to 32 10 and the drain fingers 42 1 to 42 5 .
  • the source electrode 5 is disposed between each gate air bridge and the dielectric substrate 1, that is, between each of the portions 33 2 , 33 4 , 33 5 , and 33 7 of the gate bus bar 31 and the dielectric substrate 1.
  • the region 52 2 , 52 4 , 52 5 , 52 7 is formed.
  • the dielectric substrate 1, the metal layer 2, the gate electrode 3, the drain electrode 4, the source electrode 5, the gate terminal 6 and the drain terminal 7 constitute the main part of the transistor 100.
  • the operation of the transistor 100 according to Embodiment 3 is the same as that described in Embodiment 1, description thereof is omitted.
  • the effect of the transistor 100 according to the third embodiment is the same as that described with reference to FIGS. 6 and 7 in the first embodiment, and thus illustration and description thereof are omitted.
  • the gate bus bar 31 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire gate bus bar 31. That is, the gate bus bar 31 may have the same shape as the gate bus bar 31 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5, part 52 2, 52 4 shown in FIG. 15, 52 5, 52 7 may be then formed by the shape removed.
  • the transistor 100 of the third embodiment is provided on the metal layer 2 provided on the back surface portion of the dielectric substrate 1 and on the front surface portion of the dielectric substrate 1, and includes the gate bus bar 31 and the gate bus bar 31.
  • the gate electrode 3 having a plurality of gate fingers 32 1 to 32 10 that are electrically connected to each other by the above, and vias 11 i and 11 j that are provided on the surface portion of the dielectric substrate 1 and penetrate the dielectric substrate 1.
  • a part of the gate bus bar 31 (parts 33 2 , 33 4 , 33 5 , 33 7 ) are configured by air bridge wiring, and the source electrode 5 is electrically connected to the metal layer 2 by the air bridge wiring.
  • Part of the source electrode 5 (parts 52 2 , 52 4 , 52 5 , 52 7 ) is disposed between the bridge wiring and the dielectric substrate 1. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the gate air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.
  • the transistor 100 of the third embodiment is provided on the metal layer 2 provided on the back surface of the dielectric substrate 1 and on the front surface of the dielectric substrate 1, and is electrically connected to each other by the drain bus bar 41 and the drain bus bar 41.
  • the drain electrode 4 having a plurality of connected drain fingers 42 1 to 42 5 and a metal layer by vias 11 i and 11 j that are provided on the surface of the dielectric substrate 1 and penetrate the dielectric substrate 1. 2 and a source electrode 5 electrically connected to each other, and a part of the drain bus bar 41 (parts 43 1 to 43 4 ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric substrate 1 are connected to each other.
  • a part of the source electrode 5 (parts 53 1 to 53 4 ) is disposed between them.
  • FIG. 18A is a plan view showing a gate electrode according to Embodiment 4 of the present invention.
  • FIG. 18B is a plan view showing the drain electrode according to Embodiment 4 of the present invention.
  • FIG. 19A is a cross-sectional view along the line AA ′ shown in FIG. 18A.
  • FIG. 19B is a cross-sectional view taken along line BB ′ shown in FIG. 18B.
  • FIG. 20 is a plan view showing a source electrode according to Embodiment 4 of the present invention.
  • FIG. 21 is a plan view showing a main part of a transistor according to Embodiment 4 of the present invention.
  • 22A is a cross-sectional view taken along line AA ′ shown in FIG. 22B is a cross-sectional view taken along the line BB ′ shown in FIG. 22C is a cross-sectional view taken along the line CC ′ shown in FIG.
  • the transistor 100 of the fourth embodiment will be described with reference to FIGS. Components similar to those of the transistor 100 of Embodiment 1 shown in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof is omitted.
  • the source electrode 5 is composed of a pair of electrodes 5k and 5l.
  • One electrode 5k is electrically connected to the metal layer 2 by vias 11k and 12k penetrating the dielectric substrate 1.
  • the other electrode 5 l is electrically connected to the metal layer 2 by vias 11 l and 12 l penetrating the dielectric substrate 1.
  • the vias 11k and 11l are arranged in a half portion on the gate terminal 6 side of the dielectric substrate 1.
  • the vias 12k and 12l are arranged in a half part on the dielectric substrate 1 on the drain terminal 7 side.
  • the dielectric substrate 1, the metal layer 2, the gate electrode 3, the drain electrode 4, the source electrode 5, the gate terminal 6 and the drain terminal 7 constitute the main part of the transistor 100.
  • the operation of the transistor 100 according to the fourth embodiment is the same as that described in the first embodiment, description thereof is omitted. Further, the effect of the transistor 100 according to the fourth embodiment is the same as that described with reference to FIGS. 6 and 7 in the first embodiment, and thus illustration and description thereof are omitted.
  • the gate bus bar 31 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire gate bus bar 31. That is, the gate bus bar 31 may have the same shape as the gate bus bar 31 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5 may have a shape formed by removing the portions 52 1 to 52 8 shown in FIG.
  • the drain bus bar 41 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire drain bus bar 41. That is, the drain bus bar 41 may have the same shape as the drain bus bar 41 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5 may have a shape formed by removing the portions 53 1 to 53 4 shown in FIG.
  • the transistor 100 according to the fourth embodiment is provided on the metal layer 2 provided on the back surface portion of the dielectric substrate 1 and on the front surface portion of the dielectric substrate 1, and includes the gate bus bar 31 and the gate bus bar 31.
  • the gate electrode 3 having a plurality of gate fingers 32 1 to 32 10 that are electrically connected to each other by the above and vias 11k, 11l that are provided on the surface portion of the dielectric substrate 1 and penetrate the dielectric substrate 1.
  • part of the gate bus bar 31 (region 33 1-33 8) is constituted by an air bridge wiring, the air bridge wiring And part of the source electrode 5 (parts 52 1 to 52 8 ) are disposed between the dielectric substrate 1 and the dielectric substrate 1.
  • the transistor 100 according to the fourth embodiment is provided on the metal layer 2 provided on the back surface of the dielectric substrate 1 and on the front surface of the dielectric substrate 1, and is electrically connected to each other by the drain bus bar 41 and the drain bus bar 41.
  • a source electrode 5 electrically connected to the metal layer 2 and a part of the drain bus bar 41 (parts 43 1 to 43 4 ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric A part of the source electrode 5 (parts 53 1 to 53 4 ) is disposed between the substrate 1 and the substrate 1.
  • the transistor of the present invention can be used, for example, for amplifying a high frequency signal in a radio communication device or a radar device.

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Abstract

This transistor (100) is provided with: a metal layer (2) disposed on a rear surface portion of a dielectric substrate (1); a gate electrode (3) disposed on a surface portion of the dielectric substrate (1), and having a gate bus bar (31) and a plurality of gate fingers (321-3210) electrically connected to each other by the gate bus bar (31); and a source electrode (5) which is disposed on the surface portion of the dielectric substrate (1) and electrically connected to the metal layer (2) by vias (11a, 11b) that pass through the dielectric substrate (1), wherein a portion of the gate bus bar (31) is configured from an air bridge wire, and a portion of the source electrode (5) is disposed between said air bridge wire and the dielectric substrate (1).

Description

トランジスタTransistor
 本発明は、トランジスタに関するものであり、特に高周波用のトランジスタに関する。 The present invention relates to a transistor, and more particularly to a high-frequency transistor.
 従来、無線通信装置又はレーダ装置などにおいて、高周波信号の増幅にトランジスタが用いられている。具体的には、例えば、ソース接地型の電界効果トランジスタ(Field Effect Transistor,FET)が用いられている。特許文献1には、略櫛型のゲート電極と略櫛型のドレイン電極とが互いに噛み合うように配置されたFET、いわゆる「マルチフィンガー型」のFETが開示されている。 Conventionally, a transistor is used to amplify a high-frequency signal in a wireless communication device or a radar device. Specifically, for example, a source-grounded field effect transistor (Field Effect Transistor, FET) is used. Patent Document 1 discloses an FET in which a substantially comb-shaped gate electrode and a substantially comb-shaped drain electrode are arranged so as to mesh with each other, a so-called “multi-finger type” FET.
特開2008-109227号公報JP 2008-109227 A
 マルチフィンガー型のFET(以下「マルチフィンガーFET」という。)におけるゲート電極は、1本以上のゲートバスバーと、このゲートバスバーに対して略垂直に設けられた複数本のゲートフィンガーとを有している。また、マルチフィンガーFETにおけるドレイン電極は、1本以上のドレインバスバーと、このドレインバスバーに対して略垂直に設けられた複数本のドレインフィンガーとを有している。ゲート電極及びドレイン電極は誘電体基板の表面部に設けられており、誘電体基板の裏面部には金属層が設けられている。この金属層は電気的に接地されている。 A gate electrode in a multi-finger type FET (hereinafter referred to as “multi-finger FET”) has at least one gate bus bar and a plurality of gate fingers provided substantially perpendicular to the gate bus bar. Yes. Further, the drain electrode in the multi-finger FET has one or more drain bus bars and a plurality of drain fingers provided substantially perpendicular to the drain bus bars. The gate electrode and the drain electrode are provided on the front surface portion of the dielectric substrate, and a metal layer is provided on the back surface portion of the dielectric substrate. This metal layer is electrically grounded.
 すなわち、従来のマルチフィンガーFETにおいては、ゲートバスバーによりマイクロストリップ線路が構成されており、かつ、ドレインバスバーによりマイクロストリップ線路が構成されている。これらのマイクロストリップ線路を高周波信号が伝搬するとき、誘電体基板内に電磁界が発生するため、誘電正接に応じた誘電損失が生ずる。この誘電損失により、トランジスタの利得、出力電力及び効率が低下する問題があった。 That is, in the conventional multi-finger FET, a microstrip line is constituted by the gate bus bar, and a microstrip line is constituted by the drain bus bar. When a high-frequency signal propagates through these microstrip lines, an electromagnetic field is generated in the dielectric substrate, so that a dielectric loss corresponding to the dielectric loss tangent occurs. Due to this dielectric loss, there is a problem that the gain, output power and efficiency of the transistor are lowered.
 本発明は、上記のような課題を解決するためになされたものであり、高利得、高出力電力かつ高効率なトランジスタを提供することを目的とする。 The present invention has been made to solve the above-described problems, and an object thereof is to provide a transistor having high gain, high output power, and high efficiency.
 本発明のトランジスタは、誘電体基板の裏面部に設けられた金属層と、誘電体基板の表面部に設けられており、ゲートバスバーとゲートバスバーにより互いに電気的に接続された複数本のゲートフィンガーとを有するゲート電極と、誘電体基板の表面部に設けられており、誘電体基板を貫通したビアにより金属層と電気的に接続されたソース電極とを備え、ゲートバスバーの一部がエアブリッジ配線により構成されており、当該エアブリッジ配線と誘電体基板との間にソース電極の一部が配置されているものである。 The transistor of the present invention includes a metal layer provided on the back surface of the dielectric substrate, and a plurality of gate fingers provided on the front surface of the dielectric substrate and electrically connected to each other by the gate bus bar. And a source electrode electrically connected to the metal layer by a via penetrating the dielectric substrate, and a part of the gate bus bar is an air bridge It is constituted by wiring, and a part of the source electrode is arranged between the air bridge wiring and the dielectric substrate.
 本発明のトランジスタは、誘電体基板の裏面部に設けられた金属層と、誘電体基板の表面部に設けられており、ドレインバスバーとドレインバスバーにより互いに電気的に接続された複数本のドレインフィンガーとを有するドレイン電極と、誘電体基板の表面部に設けられており、誘電体基板を貫通したビアにより金属層と電気的に接続されたソース電極とを備え、ドレインバスバーの一部がエアブリッジ配線により構成されており、当該エアブリッジ配線と誘電体基板との間にソース電極の一部が配置されているものである。 The transistor of the present invention includes a metal layer provided on the back surface of the dielectric substrate and a plurality of drain fingers provided on the front surface of the dielectric substrate and electrically connected to each other by the drain bus bar and the drain bus bar. And a source electrode electrically connected to the metal layer by a via penetrating the dielectric substrate, and a part of the drain bus bar is an air bridge It is constituted by wiring, and a part of the source electrode is arranged between the air bridge wiring and the dielectric substrate.
 本発明によれば、上記のように構成したので、高利得、高出力電力かつ高効率なトランジスタを得ることができる。 According to the present invention, since it is configured as described above, a transistor with high gain, high output power, and high efficiency can be obtained.
図1Aは、本発明の実施の形態1に係るゲート電極を示す平面図である。図1Bは、本発明の実施の形態1に係るドレイン電極を示す平面図である。FIG. 1A is a plan view showing a gate electrode according to Embodiment 1 of the present invention. FIG. 1B is a plan view showing the drain electrode according to Embodiment 1 of the present invention. 図2Aは、図1Aに示すA-A’線に沿う断面図である。図2Bは、図1Bに示すB-B’線に沿う断面図である。2A is a cross-sectional view taken along line A-A ′ shown in FIG. 1A. 2B is a cross-sectional view taken along line B-B ′ shown in FIG. 1B. 本発明の実施の形態1に係るソース電極を示す平面図である。It is a top view which shows the source electrode which concerns on Embodiment 1 of this invention. 本発明の実施の形態1に係るトランジスタの要部を示す平面図である。It is a top view which shows the principal part of the transistor which concerns on Embodiment 1 of this invention. 図5Aは、図4に示すA-A’線に沿う断面図である。図5Bは、図4に示すB-B’線に沿う断面図である。図5Cは、図4に示すC-C’線に沿う断面図である。FIG. 5A is a cross-sectional view taken along line A-A ′ shown in FIG. FIG. 5B is a cross-sectional view taken along line B-B ′ shown in FIG. FIG. 5C is a cross-sectional view taken along line C-C ′ shown in FIG. 本発明の実施の形態1に係るトランジスタとの比較対象となるトランジスタの要部を示す平面図である。It is a top view which shows the principal part of the transistor used as the comparison object with the transistor which concerns on Embodiment 1 of this invention. 図7Aは、図6に示すC-C’線に沿う断面図である。図7Bは、図4に示すC-C’線に沿う断面図である。FIG. 7A is a cross-sectional view taken along line C-C ′ shown in FIG. FIG. 7B is a cross-sectional view taken along line C-C ′ shown in FIG. 図8Aは、本発明の実施の形態2に係るゲート電極を示す平面図である。図8Bは、本発明の実施の形態2に係るドレイン電極を示す平面図である。FIG. 8A is a plan view showing a gate electrode according to Embodiment 2 of the present invention. FIG. 8B is a plan view showing the drain electrode according to Embodiment 2 of the present invention. 図9Aは、図8Aに示すA-A’線に沿う断面図である。図9Bは、図8Bに示すB-B’線に沿う断面図である。FIG. 9A is a cross-sectional view taken along line A-A ′ shown in FIG. 8A. FIG. 9B is a cross-sectional view taken along line B-B ′ shown in FIG. 8B. 本発明の実施の形態2に係るソース電極を示す平面図である。It is a top view which shows the source electrode which concerns on Embodiment 2 of this invention. 本発明の実施の形態2に係るトランジスタの要部を示す平面図である。It is a top view which shows the principal part of the transistor which concerns on Embodiment 2 of this invention. 図12Aは、図11に示すA-A’線に沿う断面図である。図12Bは、図11に示すB-B’線に沿う断面図である。図12Cは、図11に示すC-C’線に沿う断面図である。12A is a cross-sectional view taken along line A-A ′ shown in FIG. 12B is a cross-sectional view taken along line B-B ′ shown in FIG. 12C is a cross-sectional view taken along line C-C ′ shown in FIG. 図13Aは、本発明の実施の形態3に係るゲート電極を示す平面図である。図13Bは、本発明の実施の形態3に係るドレイン電極を示す平面図である。FIG. 13A is a plan view showing a gate electrode according to Embodiment 3 of the present invention. FIG. 13B is a plan view showing the drain electrode according to Embodiment 3 of the present invention. 図14Aは、図13Aに示すA-A’線に沿う断面図である。図14Bは、図13Bに示すB-B’線に沿う断面図である。14A is a cross-sectional view taken along line A-A ′ shown in FIG. 13A. 14B is a cross-sectional view taken along line B-B ′ shown in FIG. 13B. 本発明の実施の形態3に係るソース電極を示す平面図である。It is a top view which shows the source electrode which concerns on Embodiment 3 of this invention. 本発明の実施の形態3に係るトランジスタの要部を示す平面図である。It is a top view which shows the principal part of the transistor which concerns on Embodiment 3 of this invention. 図17Aは、図16に示すA-A’線に沿う断面図である。図17Bは、図16に示すB-B’線に沿う断面図である。図17Cは、図16に示すC-C’線に沿う断面図である。FIG. 17A is a cross-sectional view along the line A-A ′ shown in FIG. 16. FIG. 17B is a cross-sectional view along the line B-B ′ shown in FIG. 16. FIG. 17C is a cross-sectional view taken along line C-C ′ shown in FIG. 図18Aは、本発明の実施の形態4に係るゲート電極を示す平面図である。図18Bは、本発明の実施の形態4に係るドレイン電極を示す平面図である。FIG. 18A is a plan view showing a gate electrode according to Embodiment 4 of the present invention. FIG. 18B is a plan view showing the drain electrode according to Embodiment 4 of the present invention. 図19Aは、図18Aに示すA-A’線に沿う断面図である。図19Bは、図18Bに示すB-B’線に沿う断面図である。FIG. 19A is a cross-sectional view taken along line A-A ′ shown in FIG. 18A. FIG. 19B is a cross-sectional view taken along line B-B ′ shown in FIG. 18B. 本発明の実施の形態4に係るソース電極を示す平面図である。It is a top view which shows the source electrode which concerns on Embodiment 4 of this invention. 本発明の実施の形態4に係るトランジスタの要部を示す平面図である。It is a top view which shows the principal part of the transistor which concerns on Embodiment 4 of this invention. 図22Aは、図21に示すA-A’線に沿う断面図である。図22Bは、図21に示すB-B’線に沿う断面図である。図22Cは、図21に示すC-C’線に沿う断面図である。22A is a cross-sectional view taken along line A-A ′ shown in FIG. 22B is a cross-sectional view taken along line B-B ′ shown in FIG. 22C is a cross-sectional view taken along line C-C ′ shown in FIG.
 以下、この発明をより詳細に説明するために、この発明を実施するための形態について、添付の図面に従って説明する。 Hereinafter, in order to explain the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.
実施の形態1.
 図1Aは、本発明の実施の形態1に係るゲート電極を示す平面図である。図1Bは、本発明の実施の形態1に係るドレイン電極を示す平面図である。図2Aは、図1Aに示すA-A’線に沿う断面図である。図2Bは、図1Bに示すB-B’線に沿う断面図である。図3は、本発明の実施の形態1に係るソース電極を示す平面図である。図4は、本発明の実施の形態1に係るトランジスタの要部を示す平面図である。図5Aは、図4に示すA-A’線に沿う断面図である。図5Bは、図4に示すB-B’線に沿う断面図である。図5Cは、図4に示すC-C’線に沿う断面図である。図1~図5を参照して、実施の形態1のトランジスタ100について説明する。
Embodiment 1 FIG.
FIG. 1A is a plan view showing a gate electrode according to Embodiment 1 of the present invention. FIG. 1B is a plan view showing the drain electrode according to Embodiment 1 of the present invention. 2A is a cross-sectional view taken along line AA ′ shown in FIG. 1A. 2B is a cross-sectional view taken along line BB ′ shown in FIG. 1B. FIG. 3 is a plan view showing the source electrode according to Embodiment 1 of the present invention. FIG. 4 is a plan view showing the main part of the transistor according to Embodiment 1 of the present invention. FIG. 5A is a cross-sectional view taken along line AA ′ shown in FIG. 5B is a cross-sectional view taken along the line BB ′ shown in FIG. FIG. 5C is a cross-sectional view taken along the line CC ′ shown in FIG. With reference to FIGS. 1 to 5, the transistor 100 of Embodiment 1 will be described.
 図中、1は誘電体基板である。誘電体基板1の裏面部には、電気的に接地された金属層2が設けられている。誘電体基板1の表面部には、ゲート電極3、ドレイン電極4及びソース電極5が設けられている。 In the figure, 1 is a dielectric substrate. An electrically grounded metal layer 2 is provided on the back surface of the dielectric substrate 1. A gate electrode 3, a drain electrode 4, and a source electrode 5 are provided on the surface portion of the dielectric substrate 1.
 ゲート電極3は、1本のゲートバスバー31と、ゲートバスバー31に対して略垂直に設けられた10本のゲートフィンガー32~3210とを有している。これにより、ゲート電極3の外形は略櫛型である。ゲートフィンガー32~3210は、ゲートバスバー31により互いに電気的に接続されている。また、ゲートフィンガー32~3210の各々は、ゲートバスバー31を介してゲート端子6と電気的に接続されている。 The gate electrode 3 has one gate bus bar 31 and ten gate fingers 32 1 to 32 10 provided substantially perpendicular to the gate bus bar 31. Thereby, the outer shape of the gate electrode 3 is substantially comb-shaped. The gate fingers 32 1 to 32 10 are electrically connected to each other by a gate bus bar 31. Each of the gate fingers 32 1 to 32 10 is electrically connected to the gate terminal 6 via the gate bus bar 31.
 ドレイン電極4は、1本のドレインバスバー41と、ドレインバスバー41に対して略垂直に設けられた5本のドレインフィンガー42~42とを有している。これにより、ドレイン電極4の外形は略櫛型である。ドレインフィンガー42~42は、ドレインバスバー41により互いに電気的に接続されている。また、ドレインフィンガー42~42の各々は、ドレインバスバー41を介してドレイン端子7と電気的に接続されている。 The drain electrode 4 has one drain bus bar 41 and five drain fingers 42 1 to 42 5 provided substantially perpendicular to the drain bus bar 41. Thereby, the external shape of the drain electrode 4 is substantially comb-shaped. Drain finger 42 1-42 5 are electrically connected to each other by the drain bus bar 41. Further, each of the drain finger 42 1-42 5 are drain terminals 7 electrically connected via a drain bus bar 41.
 ゲート電極3及びドレイン電極4は、ゲートフィンガー32~3210とドレインフィンガー42~42とが噛み合うように互いに対向配置されている。より具体的には、互いに隣接するゲートフィンガー32,32間にドレインフィンガー42が配置され、互いに隣接するゲートフィンガー32,32間にドレインフィンガー42が配置され、互いに隣接するゲートフィンガー32,32間にドレインフィンガー42が配置され、互いに隣接するゲートフィンガー32,32間にドレインフィンガー42が配置され、互いに隣接するゲートフィンガー32,3210間にドレインフィンガー42が配置されている。すなわち、トランジスタ100はマルチフィンガー型である。 The gate electrode 3 and the drain electrode 4 are arranged to face each other so that the gate fingers 32 1 to 32 10 and the drain fingers 42 1 to 42 5 are engaged with each other. More specifically, the drain finger 42 1 is disposed between the gate fingers 32 1, 32 2 adjacent to each other, the drain finger 42 2 is disposed between the gate fingers 32 3, 32 4 adjacent to each other, gate adjacent to each other a drain finger 42 3 disposed fingers 32 5, 32 between 6, the drain finger 42 4 is disposed between the gate fingers 32 7, 32 8 which are adjacent to each other, the drain finger between the gate fingers 32 9, 32 10 that are adjacent to each other 42 5 is arranged. That is, the transistor 100 is a multi-finger type.
 ここで、図5Aに示す如く、ゲートバスバー31の一部はエアブリッジ配線により構成されている。より具体的には、互いに隣接するゲートフィンガー32,32間を接続する部位33と、互いに隣接するゲートフィンガー32,32間を接続する部位33と、互いに隣接するゲートフィンガー32,32間を接続する部位33と、互いに隣接するゲートフィンガー32,32間を接続する部位33と、互いに隣接するゲートフィンガー32,32間を接続する部位33と、互いに隣接するゲートフィンガー32,32間を接続する部位33と、互いに隣接するゲートフィンガー32,32間を接続する部位33と、互いに隣接するゲートフィンガー32,3210間を接続する部位33との各々がエアブリッジ配線により構成されている。 Here, as shown to FIG. 5A, a part of gate bus-bar 31 is comprised by the air bridge wiring. More specifically, the gate finger 32 and the gate fingers 32 1, 32 parts 33 1 connecting between 2 and portion 33 2 for connecting the gate fingers 32 2, 32 3 which are adjacent to each other, adjacent to each other adjacent to each other 3, and 32 4 sites 33 3 which connects a portion 33 4 for connecting the gate fingers 32 4, 32 5 which are adjacent to each other, the portion 33 5 for connecting the gate fingers 32 6, 32 7 adjacent to each other , A portion 33 6 connecting the gate fingers 32 7 and 32 8 adjacent to each other, a portion 33 7 connecting the gate fingers 32 8 and 32 9 adjacent to each other, and between the gate fingers 32 9 and 32 10 adjacent to each other each of the sites 33 8 for connecting is formed by an air-bridge wiring.
 以下、ゲートバスバー31のうちのエアブリッジ配線により構成された部位33~33を「ゲートエアブリッジ」ということがある。なお、ゲートバスバー31のうちの残余の部位はマイクロストリップ線路を構成している。 Hereinafter, the portion 33 1-33 8 constituted by an air bridge line of the gate bus bar 31 may be referred to as "gate air bridge". The remaining part of the gate bus bar 31 constitutes a microstrip line.
 また、図5Bに示す如く、ドレインバスバー41の一部はエアブリッジ配線により構成されている。より具体的には、互いに隣接するドレインフィンガー42,42間を接続する部位43と、互いに隣接するドレインフィンガー42,42間を接続する部位43と、互いに隣接するドレインフィンガー42,42間を接続する部位43と、互いに隣接するドレインフィンガー42,42間を接続する部位43との各々がエアブリッジ配線により構成されている。 Further, as shown in FIG. 5B, a part of the drain bus bar 41 is constituted by an air bridge wiring. Drain finger 42 More specifically, a portion 43 1 that connects between the drain finger 42 1, 42 2 adjacent to each other, the portion 43 2 which connects between the drain finger 42 2, 42 3 adjacent to each other, adjacent to each other 3, and 42 4 sites 43 3 which connects the, each of the drain finger 42 4, 42 5 parts 43 4 for connecting the adjacent is constituted by an air-bridge interconnection with each other.
 以下、ドレインバスバー41のうちのエアブリッジ配線により構成された部位43~43を「ドレインエアブリッジ」ということがある。なお、ドレインバスバー41のうちの残余の部位はマイクロストリップ線路を構成している。 Hereinafter, the portions 43 1 to 43 4 constituted by the air bridge wiring in the drain bus bar 41 may be referred to as “drain air bridge”. The remaining part of the drain bus bar 41 constitutes a microstrip line.
 ソース電極5は、一対の電極5a,5bにより構成されている。一方の電極5aは、誘電体基板1を貫通したビア11aにより金属層2と電気的に接続されている。他方の電極5bは、誘電体基板1を貫通したビア11bにより金属層2と電気的に接続されている。ビア11a,11bは、誘電体基板1におけるゲート端子6側の半部に配置されている。すなわち、ソース電極5は電気的に接地されており、トランジスタ100はソース接地型である。 The source electrode 5 is composed of a pair of electrodes 5a and 5b. One electrode 5 a is electrically connected to the metal layer 2 by a via 11 a penetrating the dielectric substrate 1. The other electrode 5 b is electrically connected to the metal layer 2 by a via 11 b that penetrates the dielectric substrate 1. The vias 11a and 11b are arranged in the half portion on the gate terminal 6 side of the dielectric substrate 1. That is, the source electrode 5 is electrically grounded, and the transistor 100 is a grounded source type.
 ソース電極5は、ゲートフィンガー32~3210及びドレインフィンガー42~42に対して並設された部位51~51を有している。より具体的には、ソース電極5は、ゲートバスバー31の一端部に設けられたゲートフィンガー32よりも外側に配置された部位51と、互いに隣接するゲートフィンガー32,32間に配置された部位51と、互いに隣接するゲートフィンガー32,32間に配置された部位51と、互いに隣接するゲートフィンガー32,32間に配置された部位51と、互いに隣接するゲートフィンガー32,32間に配置された部位51と、ゲートバスバー31の他端部に設けられたゲートフィンガー3210よりも外側に配置された部位51とを有している。 The source electrode 5 has portions 51 1 to 51 6 arranged in parallel to the gate fingers 32 1 to 32 10 and the drain fingers 42 1 to 42 5 . More specifically, the source electrode 5 is disposed between a portion 51 1 disposed outside the gate finger 32 1 provided at one end of the gate bus bar 31 and the gate fingers 32 2 and 32 3 adjacent to each other. a portion 51 2 which is, the gate finger 32 4, 32 5 parts 51 3 disposed between the mutually adjacent gate fingers 32 6, 32 7 sites 51 4 disposed between the adjacent, adjacent the gate fingers 32 8, 32 parts 51 5 disposed between 9 and a portion 51 6 arranged outside the gate fingers 32 10 provided on the other end of the gate bus bar 31.
 また、ソース電極5は、ゲートエアブリッジの各々と誘電体基板1との間、すなわちゲートバスバー31の部位33~33の各々と誘電体基板1との間に配置された部位52~52を有している。さらに、ソース電極5は、ドレインエアブリッジの各々と誘電体基板1との間、すなわちドレインバスバー41の部位43~43の各々と誘電体基板1との間に配置された部位53~53を有している。 The source electrode 5, between each a dielectric substrate 1 of a gate air bridge, i.e. arranged site 52 1 between each dielectric substrate 1 site 33 1 to 33 8 of the gate bus bar 31 It has a 52 8. Further, the source electrode 5, between each a dielectric substrate 1 of the drain air bridges, i.e. arranged site 53 1 between each dielectric substrate 1 site 43 1-43 4 of the drain bus bar 41 and a 53 4.
 誘電体基板1、金属層2、ゲート電極3、ドレイン電極4、ソース電極5、ゲート端子6及びドレイン端子7により、トランジスタ100の要部が構成されている。 The dielectric substrate 1, the metal layer 2, the gate electrode 3, the drain electrode 4, the source electrode 5, the gate terminal 6 and the drain terminal 7 constitute the main part of the transistor 100.
 次に、トランジスタ100の動作について、高周波信号を増幅する動作を中心に説明する。まず、ゲート端子6に高周波信号が入力される。入力された高周波信号は、ゲートバスバー31を介してゲートフィンガー32~3210の各々に分配される。次いで、ドレインフィンガー42~42の各々から、増幅された高周波信号が出力される。これらの高周波信号は、ドレインバスバー41により合成されて、ドレイン端子7に出力される。 Next, the operation of the transistor 100 will be described focusing on the operation of amplifying a high frequency signal. First, a high frequency signal is input to the gate terminal 6. The input high frequency signal is distributed to each of the gate fingers 32 1 to 32 10 via the gate bus bar 31. Then, from each of the drain finger 42 1-42 5, amplified radio frequency signal is output. These high frequency signals are combined by the drain bus bar 41 and output to the drain terminal 7.
 次に、図6及び図7を参照して、トランジスタ100の効果について説明する。図6は、実施の形態1に係るトランジスタ100との比較対象となるトランジスタ100’の要部を示す平面図である。図7Aは、図6に示すC-C’線に沿う断面図、すなわちトランジスタ100’の断面図である。図7Bは、図4に示すC-C’線に沿う断面図、すなわちトランジスタ100の断面図である。 Next, the effect of the transistor 100 will be described with reference to FIGS. FIG. 6 is a plan view showing a main part of a transistor 100 ′ to be compared with the transistor 100 according to the first embodiment. FIG. 7A is a cross-sectional view taken along line C-C ′ shown in FIG. 6, that is, a cross-sectional view of the transistor 100 ′. FIG. 7B is a cross-sectional view taken along the line C-C ′ shown in FIG. 4, that is, a cross-sectional view of the transistor 100.
 図6及び図7Aに示す如く、誘電体基板1’の裏面部には電気的に接地された金属層2’が設けられており、誘電体基板1’の表面部にはゲート電極3’及びドレイン電極4’が設けられている。図6及び図7Aにおいて、ソース電極は図示を省略している。 As shown in FIGS. 6 and 7A, an electrically grounded metal layer 2 ′ is provided on the back surface of the dielectric substrate 1 ′, and the gate electrode 3 ′ and the surface of the dielectric substrate 1 ′ are provided. A drain electrode 4 'is provided. 6 and 7A, the source electrode is not shown.
 ゲート電極3’は1本のゲートバスバー31’と10本のゲートフィンガー32’~3210’とを有しており、ゲートフィンガー32’~3210’の各々はゲートバスバー31’を介してゲート端子6’と電気的に接続されている。ドレイン電極4’は1本のドレインバスバー41’と5本のドレインフィンガー42’~42’とを有しており、ドレインフィンガー42’~42’の各々はドレインバスバー41’を介してドレイン端子7’と電気的に接続されている。 The gate electrode 3 'is one gate bus bar 31' has a gate finger 32 first ten and '~ 32 10' and each of the gate fingers 32 1 'to 32 10' through the gate bus bar 31 ' Are electrically connected to the gate terminal 6 '. A drain electrode 4 'is one of the drain bus bar 41' has a five drain finger 42 1 'to 42 5' and each of the drain finger 42 1 '~ 42 5' is via the drain bus bar 41 ' Are electrically connected to the drain terminal 7 '.
 ここで、ゲートバスバー31’はエアブリッジ配線を有しておらず、ゲートバスバー31’の略全体がマイクロストリップ線路を構成している。また、ドレインバスバー41’はエアブリッジ配線を有しておらず、ドレインバスバー41’の略全体がマイクロストリップ線路を構成している。  Here, the gate bus bar 31 'does not have an air bridge wiring, and substantially the entire gate bus bar 31' constitutes a microstrip line. Further, the drain bus bar 41 ′ does not have an air bridge wiring, and substantially the entire drain bus bar 41 ′ constitutes a microstrip line. *
 トランジスタ100’のゲートバスバー31’において、高周波信号はマイクロトリップモードにて伝送される。当該高周波信号に対応する電磁界は、ゲートバスバー31’と金属層2’間に生ずる。図7Aに示す6本の矢印A1’は、ゲートバスバー31’を伝搬する高周波信号の電力に対応する電気力線を示している。図7Aに示す如く、電気力線A1’の始端はゲートバスバー31’であり、電気力線A1’の終端は電気的に接地された金属層2’である。すなわち、電気力線A1’は誘電体基板1’内を通過している。誘電体基板1’は有限のコンダクタンスを有しており、有限の誘電正接を有するため、この誘電正接に応じた誘電損失が生ずる。この誘電損失により、トランジスタ100’の利得、出力電力及び効率が低下する。 In the gate bus bar 31 ′ of the transistor 100 ′, the high frequency signal is transmitted in the micro trip mode. An electromagnetic field corresponding to the high-frequency signal is generated between the gate bus bar 31 'and the metal layer 2'. Six arrows A1 'shown in FIG. 7A indicate electric lines of force corresponding to the power of the high-frequency signal propagating through the gate bus bar 31'. As shown in FIG. 7A, the electric force lines A1 'start at the gate bus bar 31', and the electric lines A1 'end at the electrically grounded metal layer 2'. That is, the electric lines of force A1 'pass through the dielectric substrate 1'. Since the dielectric substrate 1 'has a finite conductance and a finite dielectric loss tangent, a dielectric loss corresponding to the dielectric loss tangent occurs. This dielectric loss reduces the gain, output power and efficiency of transistor 100 '.
 これに対して、実施の形態1のトランジスタ100は、ゲートバスバー31の一部がエアブリッジ配線により構成されており、このエアブリッジ配線と誘電体基板1との間にソース電極5の一部が配置されている。図7Bに示す6本の矢印A1は、ゲートエアブリッジを伝搬する高周波信号の電力に対応する電気力線を示している。図7Bに示す如く、電気力線A1の始端はゲートバスバー31(部位33)であり、電気力線A1の終端は電気的に接地されたソース電極5(部位52)である。すなわち、電気力線A1は、誘電体基板1内を通過せずに空気中を通過している。これにより、誘電体基板1の誘電正接による誘電損失が生ずるのを防ぐことができる。 On the other hand, in the transistor 100 of the first embodiment, a part of the gate bus bar 31 is configured by an air bridge wiring, and a part of the source electrode 5 is interposed between the air bridge wiring and the dielectric substrate 1. Has been placed. The six arrows A1 shown in FIG. 7B indicate electric lines of force corresponding to the power of the high-frequency signal propagating through the gate air bridge. As shown in FIG. 7B, the beginning of the electric power line A1 denotes a gate bus bar 31 (region 33 2), the end of the electric line of force A1 is the source electrode 5 which is electrically grounded (sites 52 2). That is, the electric lines of force A1 do not pass through the dielectric substrate 1 but pass through the air. Thereby, it is possible to prevent the dielectric loss due to the dielectric loss tangent of the dielectric substrate 1 from occurring.
 また、トランジスタ100’のドレインバスバー41’において、高周波信号はマイクロトリップモードにて伝送される。当該高周波信号に対応する電磁界は、ドレインバスバー41’と金属層2’間に生ずる。図7Aに示す6本の矢印A2’は、ドレインバスバー41’を伝搬する高周波信号の電力に対応する電気力線を示している。図7Aに示す如く、電気力線A2’の始端はドレインバスバー41’であり、電気力線A2’の終端は電気的に接地された金属層2’である。すなわち、電気力線A2’は誘電体基板1’内を通過している。誘電体基板1’は有限のコンダクタンスを有しており、有限の誘電正接を有しているため、この誘電正接に応じた誘電損失が生ずる。この誘電損失により、トランジスタ100’の利得、出力電力及び効率が低下する。 Further, the high frequency signal is transmitted in the micro trip mode in the drain bus bar 41 ′ of the transistor 100 ′. An electromagnetic field corresponding to the high-frequency signal is generated between the drain bus bar 41 'and the metal layer 2'. Six arrows A2 'shown in FIG. 7A indicate electric lines of force corresponding to the power of the high-frequency signal propagating through the drain bus bar 41'. As shown in FIG. 7A, the electric force line A2 'starts at the drain bus bar 41', and the electric force line A2 'ends at the electrically grounded metal layer 2'. That is, the electric lines of force A2 'pass through the dielectric substrate 1'. Since the dielectric substrate 1 'has a finite conductance and a finite dielectric tangent, a dielectric loss corresponding to the dielectric tangent occurs. This dielectric loss reduces the gain, output power and efficiency of transistor 100 '.
 これに対して、実施の形態1のトランジスタ100は、ドレインバスバー41の一部がエアブリッジ配線により構成されており、このエアブリッジ配線と誘電体基板1との間にソース電極5の一部が配置されている。図7Bに示す6本の矢印A2は、ドレインエアブリッジを伝搬する高周波信号の電力に対応する電気力線を示している。図7Bに示す如く、電気力線A2の始端はドレインバスバー41(部位43)であり、電気力線A2の終端は電気的に接地されたソース電極5(部位53)である。すなわち、電気力線A2は、誘電体基板1内を通過せずに空気中を通過している。これにより、誘電体基板1の誘電正接による誘電損失が生ずるのを防ぐことができる。 On the other hand, in the transistor 100 of the first embodiment, a part of the drain bus bar 41 is configured by an air bridge wiring, and a part of the source electrode 5 is interposed between the air bridge wiring and the dielectric substrate 1. Has been placed. The six arrows A2 shown in FIG. 7B indicate electric lines of force corresponding to the power of the high-frequency signal propagating through the drain air bridge. As shown in FIG. 7B, the starting end of the electric force line A2 is the drain bus bar 41 (part 43 1 ), and the end of the electric line of force A2 is the electrically grounded source electrode 5 (part 53 1 ). That is, the electric lines of force A2 do not pass through the dielectric substrate 1 but pass through the air. Thereby, it is possible to prevent the dielectric loss due to the dielectric loss tangent of the dielectric substrate 1 from occurring.
 なお、実施の形態1のトランジスタ100において、ドレインバスバー41がエアブリッジ配線を有さず、ドレインバスバー41の略全体によりマイクロストリップ線路が構成されたものであっても良い。すなわち、ドレインバスバー41が図6及び図7Aに示すドレインバスバー41’と同様の形状を有するものであっても良い。この場合、ソース電極5は、図3に示す部位53~53を除去してなる形状であっても良い。 In the transistor 100 of the first embodiment, the drain bus bar 41 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire drain bus bar 41. That is, the drain bus bar 41 may have the same shape as the drain bus bar 41 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5 may have a shape obtained by removing the portions 53 1 to 53 4 shown in FIG.
 また、ゲートバスバー31の本数は1本以上であれば良く、1本に限定されるものではない。ゲートフィンガー32~3210の本数は複数本であれば良く、10本に限定されるものではない。 Further, the number of gate bus bars 31 may be one or more, and is not limited to one. The number of gate fingers 32 1 to 32 10 may be plural, and is not limited to ten.
 また、ドレインバスバー41の本数は1本以上であれば良く、1本に限定されるものではない。ドレインフィンガー42~42の本数は複数本であれば良く、5本に限定されるものではない。 The number of drain bus bars 41 may be one or more, and is not limited to one. The number of drain fingers 42 1 to 42 5 may be a plurality, and is not limited to five.
 以上のように、実施の形態1のトランジスタ100は、誘電体基板1の裏面部に設けられた金属層2と、誘電体基板1の表面部に設けられており、ゲートバスバー31とゲートバスバー31により互いに電気的に接続された複数本のゲートフィンガー32~3210とを有するゲート電極3と、誘電体基板1の表面部に設けられており、誘電体基板1を貫通したビア11a,11bにより金属層2と電気的に接続されたソース電極5とを備え、ゲートバスバー31の一部(部位33~33)がエアブリッジ配線により構成されており、当該エアブリッジ配線と誘電体基板1との間にソース電極5の一部(部位52~52)が配置されている。これにより、ゲートエアブリッジにおいて誘電体基板1による誘電損失が生ずるのを防ぐことができるため、高利得、高出力電力かつ高効率なトランジスタ100を得ることができる。 As described above, the transistor 100 of the first embodiment is provided on the metal layer 2 provided on the back surface portion of the dielectric substrate 1 and on the front surface portion of the dielectric substrate 1, and includes the gate bus bar 31 and the gate bus bar 31. The gate electrode 3 having a plurality of gate fingers 32 1 to 32 10 that are electrically connected to each other by the above, and vias 11 a and 11 b that are provided on the surface portion of the dielectric substrate 1 and penetrate the dielectric substrate 1. And a source electrode 5 electrically connected to the metal layer 2, and a part of the gate bus bar 31 (parts 33 1 to 33 8 ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric substrate A part (parts 52 1 to 52 8 ) of the source electrode 5 is disposed between the source electrode 5 and the source electrode 5. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the gate air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.
 また、実施の形態1のトランジスタ100は、誘電体基板1の裏面部に設けられた金属層2と、誘電体基板1の表面部に設けられており、ドレインバスバー41とドレインバスバー41により互いに電気的に接続された複数本のドレインフィンガー42~42とを有するドレイン電極4と、誘電体基板1の表面部に設けられており、誘電体基板1を貫通したビア11a,11bにより金属層2と電気的に接続されたソース電極5とを備え、ドレインバスバー41の一部(部位43~43)がエアブリッジ配線により構成されており、当該エアブリッジ配線と誘電体基板1との間にソース電極5の一部(部位53~53)が配置されている。これにより、ドレインエアブリッジにおいて誘電体基板1による誘電損失が生ずるのを防ぐことができるため、高利得、高出力電力かつ高効率なトランジスタ100を得ることができる。 The transistor 100 of the first embodiment is provided on the metal layer 2 provided on the back surface of the dielectric substrate 1 and on the front surface of the dielectric substrate 1, and is electrically connected to each other by the drain bus bar 41 and the drain bus bar 41. The drain electrode 4 having a plurality of connected drain fingers 42 1 to 42 5 and a metal layer formed by vias 11 a and 11 b penetrating the dielectric substrate 1 are provided on the surface of the dielectric substrate 1. 2 and a source electrode 5 electrically connected to each other, and a part of the drain bus bar 41 (parts 43 1 to 43 4 ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric substrate 1 are connected to each other. part of the source electrode 5 (sites 53 1-53 4) is disposed between. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the drain air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.
実施の形態2.
 図8Aは、本発明の実施の形態2に係るゲート電極を示す平面図である。図8Bは、本発明の実施の形態2に係るドレイン電極を示す平面図である。図9Aは、図8Aに示すA-A’線に沿う断面図である。図9Bは、図8Bに示すB-B’線に沿う断面図である。図10は、本発明の実施の形態2に係るソース電極を示す平面図である。図11は、本発明の実施の形態2に係るトランジスタの要部を示す平面図である。図12Aは、図11に示すA-A’線に沿う断面図である。図12Bは、図11に示すB-B’線に沿う断面図である。図12Cは、図11に示すC-C’線に沿う断面図である。
Embodiment 2. FIG.
FIG. 8A is a plan view showing a gate electrode according to Embodiment 2 of the present invention. FIG. 8B is a plan view showing the drain electrode according to Embodiment 2 of the present invention. FIG. 9A is a cross-sectional view taken along line AA ′ shown in FIG. 8A. FIG. 9B is a cross-sectional view taken along line BB ′ shown in FIG. 8B. FIG. 10 is a plan view showing a source electrode according to Embodiment 2 of the present invention. FIG. 11 is a plan view showing a main part of a transistor according to Embodiment 2 of the present invention. 12A is a cross-sectional view taken along line AA ′ shown in FIG. 12B is a cross-sectional view taken along the line BB ′ shown in FIG. 12C is a cross-sectional view taken along the line CC ′ shown in FIG.
 図8~図12を参照して、実施の形態2のトランジスタ100について説明する。なお、図1~図5に示す実施の形態1のトランジスタ100と同様の構成部材には同一符号を付して説明を省略する。 The transistor 100 of the second embodiment will be described with reference to FIGS. Components similar to those of the transistor 100 of Embodiment 1 shown in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof is omitted.
 図12Aに示す如く、ゲートバスバー31の一部はエアブリッジ配線により構成されている。より具体的には、互いに隣接するゲートフィンガー32,32間を接続する部位33と、互いに隣接するゲートフィンガー32,32間を接続する部位33と、互いに隣接するゲートフィンガー32,32間を接続する部位33と、互いに隣接するゲートフィンガー32,32間を接続する部位33との各々がエアブリッジ配線により構成されている。なお、ゲートバスバー31のうちの残余の部位はマイクロストリップ線路を構成している。 As shown in FIG. 12A, a part of the gate bus bar 31 is configured by air bridge wiring. More specifically, the gate finger 32 and the gate fingers 32 2, 32 3 parts 33 2 connected between a site 33 4 for connecting the gate fingers 32 4, 32 5 which are adjacent to each other, adjacent to each other adjacent to each other 6, and 32 7 sites 33 5 connecting between each of the gate fingers 32 8, 32 9 parts 33 7 connecting between adjacent is constituted by an air-bridge interconnection with each other. The remaining part of the gate bus bar 31 constitutes a microstrip line.
 ソース電極5は、略長方形状の6個の電極5c~5hにより構成されている。電極5c~5hは、誘電体基板1を貫通したビア11c~11hにより、それぞれ金属層2と電気的に接続されている。 The source electrode 5 is composed of six substantially rectangular electrodes 5c to 5h. The electrodes 5c to 5h are electrically connected to the metal layer 2 through vias 11c to 11h penetrating the dielectric substrate 1, respectively.
 ソース電極5は、ゲートフィンガー32~3210及びドレインフィンガー42~42に対して並設された部位51~51を有している。これらの部位51~51は、電極5c~5hに1個ずつ設けられている。 The source electrode 5 has portions 51 1 to 51 6 arranged in parallel to the gate fingers 32 1 to 32 10 and the drain fingers 42 1 to 42 5 . These sites 51 1-51 6 are provided one on electrodes 5c ~ 5h.
 ここで、ビア11c~11hは、これらの部位51~51の中央部にそれぞれ配置されている。このため、6個のビア11c~11hのうちの4個のビア11d~11gは、ゲートフィンガー32~3210のうちの互いに隣接するゲートフィンガー間に配置され、かつ、ドレインフィンガー42~42のうちの互いに隣接するドレインフィンガー間に配置されている。 Here, the via 11c ~ 11h are respectively arranged in the center of these sites 51 1-51 6. For this reason, the four vias 11d to 11g among the six vias 11c to 11h are arranged between the adjacent gate fingers of the gate fingers 32 2 to 32 10 , and the drain fingers 42 1 to 42 are provided. 5 between the adjacent drain fingers.
 より具体的には、ビア11dは互いに隣接するゲートフィンガー32,32間に配置され、ビア11eは互いに隣接するゲートフィンガー32,32間に配置され、ビア11fは互いに隣接するゲートフィンガー32,32間に配置され、ビア11gは互いに隣接するゲートフィンガー32,32間に配置されている。また、ビア11dは互いに隣接するドレインフィンガー42,42間に配置され、ビア11eは互いに隣接するドレインフィンガー42,42間に配置され、ビア11fは互いに隣接するドレインフィンガー42,42間に配置され、ビア11gは互いに隣接するドレインフィンガー42,42間に配置されている。 More specifically, the via 11d is disposed between the gate fingers 32 2, 32 3 which are adjacent to each other, via 11e is disposed between the gate fingers 32 4, 32 5 which are adjacent to each other, the gate fingers via 11f adjacent to each other 32 6, 32 are disposed between 7, vias 11g is disposed between the gate fingers 32 8, 32 9 adjacent to each other. The via 11d is disposed between the drain fingers 42 1 and 42 2 adjacent to each other, the via 11e is disposed between the drain fingers 42 2 and 42 3 adjacent to each other, and the via 11f is disposed adjacent to the drain fingers 42 3 and 42. 4 , the via 11 g is disposed between the drain fingers 42 4 and 4 5 adjacent to each other.
 また、ソース電極5は、ゲートエアブリッジの各々と誘電体基板1との間、すなわちゲートバスバー31の部位33,33,33,33の各々と誘電体基板1との間に配置された部位52,52,52,52を有している。これらの部位52,52,52,52は、互いに並設された6個の電極5c~5hのうちの両端に配置された電極5c,5hを除く4個の電極5d~5gに1個ずつ設けられている。 The source electrode 5 is disposed between each gate air bridge and the dielectric substrate 1, that is, between each of the portions 33 2 , 33 4 , 33 5 , and 33 7 of the gate bus bar 31 and the dielectric substrate 1. The region 52 2 , 52 4 , 52 5 , 52 7 is formed. These portions 52 2 , 52 4 , 52 5 , and 52 7 are connected to the four electrodes 5d to 5g excluding the electrodes 5c and 5h arranged at both ends of the six electrodes 5c to 5h arranged in parallel to each other. One by one.
 さらに、ソース電極5は、ドレインエアブリッジの各々と誘電体基板1との間、すなわちドレインバスバー41の部位43~43の各々と誘電体基板1との間に配置された部位53~53を有している。これらの部位53~53は、互いに並設された6個の電極5c~5hのうちの両端に配置された電極5c,5hを除く4個の電極5d~5gに1個ずつ設けられている。 Further, the source electrode 5, between each a dielectric substrate 1 of the drain air bridges, i.e. arranged site 53 1 between each dielectric substrate 1 site 43 1-43 4 of the drain bus bar 41 and a 53 4. Each of these portions 53 1 to 53 4 is provided on each of the four electrodes 5d to 5g excluding the electrodes 5c and 5h arranged at both ends of the six electrodes 5c to 5h arranged in parallel to each other. Yes.
 誘電体基板1、金属層2、ゲート電極3、ドレイン電極4、ソース電極5、ゲート端子6及びドレイン端子7により、トランジスタ100の要部が構成されている。 The dielectric substrate 1, the metal layer 2, the gate electrode 3, the drain electrode 4, the source electrode 5, the gate terminal 6 and the drain terminal 7 constitute the main part of the transistor 100.
 実施の形態2に係るトランジスタ100の動作は、実施の形態1にて説明したものと同様であるため、説明を省略する。また、実施の形態2に係るトランジスタ100の効果は、実施の形態1にて図6及び図7を参照して説明したものと同様であるため、図示及び説明を省略する。 Since the operation of the transistor 100 according to the second embodiment is the same as that described in the first embodiment, description thereof is omitted. The effect of the transistor 100 according to the second embodiment is the same as that described with reference to FIGS. 6 and 7 in the first embodiment, and thus illustration and description thereof are omitted.
 なお、実施の形態2のトランジスタ100において、ゲートバスバー31がエアブリッジ配線を有さず、ゲートバスバー31の略全体によりマイクロストリップ線路が構成されたものであっても良い。すなわち、ゲートバスバー31が図6及び図7Aに示すゲートバスバー31’と同様の形状を有するものであっても良い。この場合、ソース電極5は、図10に示す部位52,52,52,52を除去してなる形状であっても良い。または、実施の形態2のトランジスタ100において、ドレインバスバー41がエアブリッジ配線を有さず、ドレインバスバー41の略全体によりマイクロストリップ線路が構成されたものであっても良い。すなわち、ドレインバスバー41が図6及び図7Aに示すドレインバスバー41’と同様の形状を有するものであっても良い。この場合、ソース電極5は、図10に示す部位53~53を除去してなる形状であっても良い。 In the transistor 100 of the second embodiment, the gate bus bar 31 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire gate bus bar 31. That is, the gate bus bar 31 may have the same shape as the gate bus bar 31 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5, part 52 2, 52 4 shown in FIG. 10, 52 5, 52 7 may be then formed by the shape removed. Alternatively, in the transistor 100 of the second embodiment, the drain bus bar 41 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire drain bus bar 41. That is, the drain bus bar 41 may have the same shape as the drain bus bar 41 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5 may have a shape formed by removing the portions 53 1 to 53 4 shown in FIG.
 また、ソース電極5を構成する電極5c~5hの個数は、ゲートフィンガー32~3210の本数及びドレインフィンガー42~42の本数に応じた個数であれば良く、6個に限定されるものではない。 Further, the number of electrodes 5c to 5h constituting the source electrode 5 may be a number corresponding to the number of gate fingers 32 1 to 32 10 and the number of drain fingers 42 1 to 42 5 , and is limited to six. It is not a thing.
 以上のように、実施の形態2のトランジスタ100は、誘電体基板1の裏面部に設けられた金属層2と、誘電体基板1の表面部に設けられており、ゲートバスバー31とゲートバスバー31により互いに電気的に接続された複数本のゲートフィンガー32~3210とを有するゲート電極3と、誘電体基板1の表面部に設けられており、誘電体基板1を貫通したビア11c~11hにより金属層2と電気的に接続されたソース電極5とを備え、ゲートバスバー31の一部(部位33,33,33,33)がエアブリッジ配線により構成されており、当該エアブリッジ配線と誘電体基板1との間にソース電極5の一部(部位52,52,52,52)が配置されている。これにより、ゲートエアブリッジにおいて誘電体基板1による誘電損失が生ずるのを防ぐことができるため、高利得、高出力電力かつ高効率なトランジスタ100を得ることができる。 As described above, the transistor 100 according to the second embodiment is provided on the metal layer 2 provided on the back surface portion of the dielectric substrate 1 and on the front surface portion of the dielectric substrate 1, and includes the gate bus bar 31 and the gate bus bar 31. The gate electrode 3 having a plurality of gate fingers 32 1 to 32 10 that are electrically connected to each other by the above, and vias 11c to 11h that are provided on the surface portion of the dielectric substrate 1 and penetrate the dielectric substrate 1 And a part of the gate bus bar 31 (parts 33 2 , 33 4 , 33 5 , 33 7 ) are configured by air bridge wiring, and the source electrode 5 is electrically connected to the metal layer 2 by the air bridge wiring. Part of the source electrode 5 (parts 52 2 , 52 4 , 52 5 , 52 7 ) is disposed between the bridge wiring and the dielectric substrate 1. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the gate air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.
 また、ビア11d~11gは互いに隣接するゲートフィンガー間に配置されている。これにより、ソース電極5の面積を小さくすることができるため、トランジスタ100を小型にすることができる。 Further, the vias 11d to 11g are arranged between the gate fingers adjacent to each other. Accordingly, since the area of the source electrode 5 can be reduced, the transistor 100 can be reduced in size.
 また、実施の形態2のトランジスタ100は、誘電体基板1の裏面部に設けられた金属層2と、誘電体基板1の表面部に設けられており、ドレインバスバー41とドレインバスバー41により互いに電気的に接続された複数本のドレインフィンガー42~42とを有するドレイン電極4と、誘電体基板1の表面部に設けられており、誘電体基板1を貫通したビア11c~11hにより金属層2と電気的に接続されたソース電極5とを備え、ドレインバスバー41の一部(部位43~43)がエアブリッジ配線により構成されており、当該エアブリッジ配線と誘電体基板1との間にソース電極5の一部(部位53~53)が配置されている。これにより、ドレインエアブリッジにおいて誘電体基板1による誘電損失が生ずるのを防ぐことができるため、高利得、高出力電力かつ高効率なトランジスタ100を得ることができる。 The transistor 100 of the second embodiment is provided on the metal layer 2 provided on the back surface of the dielectric substrate 1 and on the front surface of the dielectric substrate 1, and is electrically connected to each other by the drain bus bar 41 and the drain bus bar 41. The drain electrode 4 having a plurality of connected drain fingers 42 1 to 42 5 and a metal layer formed on the surface of the dielectric substrate 1 and vias 11c to 11h penetrating the dielectric substrate 1 2 and a source electrode 5 electrically connected to each other, and a part of the drain bus bar 41 (parts 43 1 to 43 4 ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric substrate 1 are connected to each other. A part of the source electrode 5 (parts 53 1 to 53 4 ) is disposed between them. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the drain air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.
 また、ビア11d~11gは互いに隣接するドレインフィンガー間に配置されている。これにより、ソース電極5の面積を小さくすることができるため、トランジスタ100を小型にすることができる。 Also, the vias 11d to 11g are arranged between the drain fingers adjacent to each other. Accordingly, since the area of the source electrode 5 can be reduced, the transistor 100 can be reduced in size.
実施の形態3.
 図13Aは、本発明の実施の形態3に係るゲート電極を示す平面図である。図13Bは、本発明の実施の形態3に係るドレイン電極を示す平面図である。図14Aは、図13Aに示すA-A’線に沿う断面図である。図14Bは、図13Bに示すB-B’線に沿う断面図である。図15は、本発明の実施の形態3に係るソース電極を示す平面図である。図16は、本発明の実施の形態3に係るトランジスタの要部を示す平面図である。図17Aは、図16に示すA-A’線に沿う断面図である。図17Bは、図16に示すB-B’線に沿う断面図である。図17Cは、図16に示すC-C’線に沿う断面図である。
Embodiment 3 FIG.
FIG. 13A is a plan view showing a gate electrode according to Embodiment 3 of the present invention. FIG. 13B is a plan view showing the drain electrode according to Embodiment 3 of the present invention. 14A is a cross-sectional view taken along line AA ′ shown in FIG. 13A. 14B is a cross-sectional view taken along line BB ′ shown in FIG. 13B. FIG. 15 is a plan view showing a source electrode according to Embodiment 3 of the present invention. FIG. 16 is a plan view showing a main part of a transistor according to Embodiment 3 of the present invention. 17A is a cross-sectional view taken along line AA ′ shown in FIG. FIG. 17B is a cross-sectional view taken along the line BB ′ shown in FIG. FIG. 17C is a cross-sectional view taken along the line CC ′ shown in FIG.
 図13~図17を参照して、実施の形態3のトランジスタ100について説明する。なお、図1~図5に示す実施の形態1のトランジスタ100と同様の構成部材には同一符号を付して説明を省略する。 The transistor 100 of the third embodiment will be described with reference to FIGS. Components similar to those of the transistor 100 of Embodiment 1 shown in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof is omitted.
 図17Aに示す如く、ゲートバスバー31の一部はエアブリッジ配線により構成されている。より具体的には、互いに隣接するゲートフィンガー32,32間を接続する部位33と、互いに隣接するゲートフィンガー32,32間を接続する部位33と、互いに隣接するゲートフィンガー32,32間を接続する部位33と、互いに隣接するゲートフィンガー32,32間を接続する部位33との各々がエアブリッジ配線により構成されている。なお、ゲートバスバー31のうちの残余の部位はマイクロストリップ線路を構成している。 As shown in FIG. 17A, a part of the gate bus bar 31 is configured by air bridge wiring. More specifically, the gate finger 32 and the gate fingers 32 2, 32 3 parts 33 2 connected between a site 33 4 for connecting the gate fingers 32 4, 32 5 which are adjacent to each other, adjacent to each other adjacent to each other 6, and 32 7 sites 33 5 connecting between each of the gate fingers 32 8, 32 9 parts 33 7 connecting between adjacent is constituted by an air-bridge interconnection with each other. The remaining part of the gate bus bar 31 constitutes a microstrip line.
 ソース電極5は、一対の電極5i,5jにより構成されている。一方の電極5iは、誘電体基板1を貫通したビア11iにより金属層2と電気的に接続されている。他方の電極5jは、誘電体基板1を貫通したビア11jにより金属層2と電気的に接続されている。ビア11i,11jは、誘電体基板1におけるドレイン端子7側の半部に配置されている。 The source electrode 5 is composed of a pair of electrodes 5i and 5j. One electrode 5 i is electrically connected to the metal layer 2 through a via 11 i penetrating the dielectric substrate 1. The other electrode 5j is electrically connected to the metal layer 2 by a via 11j penetrating the dielectric substrate 1. The vias 11 i and 11 j are arranged in the half part of the dielectric substrate 1 on the drain terminal 7 side.
 ソース電極5は、ゲートフィンガー32~3210及びドレインフィンガー42~42に対して並設された部位51~51を有している。また、ソース電極5は、ゲートエアブリッジの各々と誘電体基板1との間、すなわちゲートバスバー31の部位33,33,33,33の各々と誘電体基板1との間に配置された部位52,52,52,52を有している。さらに、ソース電極5は、ドレインエアブリッジの各々と誘電体基板1との間、すなわちドレインバスバー41の部位43~43の各々と誘電体基板1との間に配置された部位53~53を有している。 The source electrode 5 has portions 51 1 to 51 6 arranged in parallel to the gate fingers 32 1 to 32 10 and the drain fingers 42 1 to 42 5 . The source electrode 5 is disposed between each gate air bridge and the dielectric substrate 1, that is, between each of the portions 33 2 , 33 4 , 33 5 , and 33 7 of the gate bus bar 31 and the dielectric substrate 1. The region 52 2 , 52 4 , 52 5 , 52 7 is formed. Further, the source electrode 5, between each a dielectric substrate 1 of the drain air bridges, i.e. arranged site 53 1 between each dielectric substrate 1 site 43 1-43 4 of the drain bus bar 41 and a 53 4.
 誘電体基板1、金属層2、ゲート電極3、ドレイン電極4、ソース電極5、ゲート端子6及びドレイン端子7により、トランジスタ100の要部が構成されている。 The dielectric substrate 1, the metal layer 2, the gate electrode 3, the drain electrode 4, the source electrode 5, the gate terminal 6 and the drain terminal 7 constitute the main part of the transistor 100.
 実施の形態3に係るトランジスタ100の動作は、実施の形態1にて説明したものと同様であるため、説明を省略する。また、実施の形態3に係るトランジスタ100の効果は、実施の形態1にて図6及び図7を参照して説明したものと同様であるため、図示及び説明を省略する。 Since the operation of the transistor 100 according to Embodiment 3 is the same as that described in Embodiment 1, description thereof is omitted. The effect of the transistor 100 according to the third embodiment is the same as that described with reference to FIGS. 6 and 7 in the first embodiment, and thus illustration and description thereof are omitted.
 なお、実施の形態3のトランジスタ100において、ゲートバスバー31がエアブリッジ配線を有さず、ゲートバスバー31の略全体によりマイクロストリップ線路が構成されたものであっても良い。すなわち、ゲートバスバー31が図6及び図7Aに示すゲートバスバー31’と同様の形状を有するものであっても良い。この場合、ソース電極5は、図15に示す部位52,52,52,52を除去してなる形状であっても良い。 In the transistor 100 of the third embodiment, the gate bus bar 31 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire gate bus bar 31. That is, the gate bus bar 31 may have the same shape as the gate bus bar 31 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5, part 52 2, 52 4 shown in FIG. 15, 52 5, 52 7 may be then formed by the shape removed.
 以上のように、実施の形態3のトランジスタ100は、誘電体基板1の裏面部に設けられた金属層2と、誘電体基板1の表面部に設けられており、ゲートバスバー31とゲートバスバー31により互いに電気的に接続された複数本のゲートフィンガー32~3210とを有するゲート電極3と、誘電体基板1の表面部に設けられており、誘電体基板1を貫通したビア11i,11jにより金属層2と電気的に接続されたソース電極5とを備え、ゲートバスバー31の一部(部位33,33,33,33)がエアブリッジ配線により構成されており、当該エアブリッジ配線と誘電体基板1との間にソース電極5の一部(部位52,52,52,52)が配置されている。これにより、ゲートエアブリッジにおいて誘電体基板1による誘電損失が生ずるのを防ぐことができるため、高利得、高出力電力かつ高効率なトランジスタ100を得ることができる。 As described above, the transistor 100 of the third embodiment is provided on the metal layer 2 provided on the back surface portion of the dielectric substrate 1 and on the front surface portion of the dielectric substrate 1, and includes the gate bus bar 31 and the gate bus bar 31. The gate electrode 3 having a plurality of gate fingers 32 1 to 32 10 that are electrically connected to each other by the above, and vias 11 i and 11 j that are provided on the surface portion of the dielectric substrate 1 and penetrate the dielectric substrate 1. And a part of the gate bus bar 31 (parts 33 2 , 33 4 , 33 5 , 33 7 ) are configured by air bridge wiring, and the source electrode 5 is electrically connected to the metal layer 2 by the air bridge wiring. Part of the source electrode 5 (parts 52 2 , 52 4 , 52 5 , 52 7 ) is disposed between the bridge wiring and the dielectric substrate 1. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the gate air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.
 また、実施の形態3のトランジスタ100は、誘電体基板1の裏面部に設けられた金属層2と、誘電体基板1の表面部に設けられており、ドレインバスバー41とドレインバスバー41により互いに電気的に接続された複数本のドレインフィンガー42~42とを有するドレイン電極4と、誘電体基板1の表面部に設けられており、誘電体基板1を貫通したビア11i,11jにより金属層2と電気的に接続されたソース電極5とを備え、ドレインバスバー41の一部(部位43~43)がエアブリッジ配線により構成されており、当該エアブリッジ配線と誘電体基板1との間にソース電極5の一部(部位53~53)が配置されている。これにより、ドレインエアブリッジにおいて誘電体基板1による誘電損失が生ずるのを防ぐことができるため、高利得、高出力電力かつ高効率なトランジスタ100を得ることができる。 The transistor 100 of the third embodiment is provided on the metal layer 2 provided on the back surface of the dielectric substrate 1 and on the front surface of the dielectric substrate 1, and is electrically connected to each other by the drain bus bar 41 and the drain bus bar 41. The drain electrode 4 having a plurality of connected drain fingers 42 1 to 42 5 and a metal layer by vias 11 i and 11 j that are provided on the surface of the dielectric substrate 1 and penetrate the dielectric substrate 1. 2 and a source electrode 5 electrically connected to each other, and a part of the drain bus bar 41 (parts 43 1 to 43 4 ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric substrate 1 are connected to each other. A part of the source electrode 5 (parts 53 1 to 53 4 ) is disposed between them. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the drain air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.
実施の形態4.
 図18Aは、本発明の実施の形態4に係るゲート電極を示す平面図である。図18Bは、本発明の実施の形態4に係るドレイン電極を示す平面図である。図19Aは、図18Aに示すA-A’線に沿う断面図である。図19Bは、図18Bに示すB-B’線に沿う断面図である。図20は、本発明の実施の形態4に係るソース電極を示す平面図である。図21は、本発明の実施の形態4に係るトランジスタの要部を示す平面図である。図22Aは、図21に示すA-A’線に沿う断面図である。図22Bは、図21に示すB-B’線に沿う断面図である。図22Cは、図21に示すC-C’線に沿う断面図である。
Embodiment 4 FIG.
FIG. 18A is a plan view showing a gate electrode according to Embodiment 4 of the present invention. FIG. 18B is a plan view showing the drain electrode according to Embodiment 4 of the present invention. FIG. 19A is a cross-sectional view along the line AA ′ shown in FIG. 18A. FIG. 19B is a cross-sectional view taken along line BB ′ shown in FIG. 18B. FIG. 20 is a plan view showing a source electrode according to Embodiment 4 of the present invention. FIG. 21 is a plan view showing a main part of a transistor according to Embodiment 4 of the present invention. 22A is a cross-sectional view taken along line AA ′ shown in FIG. 22B is a cross-sectional view taken along the line BB ′ shown in FIG. 22C is a cross-sectional view taken along the line CC ′ shown in FIG.
 図18~図22を参照して、実施の形態4のトランジスタ100について説明する。なお、図1~図5に示す実施の形態1のトランジスタ100と同様の構成部材には同一符号を付して説明を省略する。 The transistor 100 of the fourth embodiment will be described with reference to FIGS. Components similar to those of the transistor 100 of Embodiment 1 shown in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof is omitted.
 ソース電極5は、一対の電極5k,5lにより構成されている。一方の電極5kは、誘電体基板1を貫通したビア11k,12kにより金属層2と電気的に接続されている。他方の電極5lは、誘電体基板1を貫通したビア11l,12lにより金属層2と電気的に接続されている。ビア11k,11lは、誘電体基板1におけるゲート端子6側の半部に配置されている。ビア12k,12lは、誘電体基板1におけるドレイン端子7側の半部に配置されている。 The source electrode 5 is composed of a pair of electrodes 5k and 5l. One electrode 5k is electrically connected to the metal layer 2 by vias 11k and 12k penetrating the dielectric substrate 1. The other electrode 5 l is electrically connected to the metal layer 2 by vias 11 l and 12 l penetrating the dielectric substrate 1. The vias 11k and 11l are arranged in a half portion on the gate terminal 6 side of the dielectric substrate 1. The vias 12k and 12l are arranged in a half part on the dielectric substrate 1 on the drain terminal 7 side.
 誘電体基板1、金属層2、ゲート電極3、ドレイン電極4、ソース電極5、ゲート端子6及びドレイン端子7により、トランジスタ100の要部が構成されている。 The dielectric substrate 1, the metal layer 2, the gate electrode 3, the drain electrode 4, the source electrode 5, the gate terminal 6 and the drain terminal 7 constitute the main part of the transistor 100.
 実施の形態4に係るトランジスタ100の動作は、実施の形態1にて説明したものと同様であるため、説明を省略する。また、実施の形態4に係るトランジスタ100の効果は、実施の形態1にて図6及び図7を参照して説明したものと同様であるため、図示及び説明を省略する。 Since the operation of the transistor 100 according to the fourth embodiment is the same as that described in the first embodiment, description thereof is omitted. Further, the effect of the transistor 100 according to the fourth embodiment is the same as that described with reference to FIGS. 6 and 7 in the first embodiment, and thus illustration and description thereof are omitted.
 なお、実施の形態4のトランジスタ100において、ゲートバスバー31がエアブリッジ配線を有さず、ゲートバスバー31の略全体によりマイクロストリップ線路が構成されたものであっても良い。すなわち、ゲートバスバー31が図6及び図7Aに示すゲートバスバー31’と同様の形状を有するものであっても良い。この場合、ソース電極5は、図20に示す部位52~52を除去してなる形状であっても良い。または、実施の形態4のトランジスタ100において、ドレインバスバー41がエアブリッジ配線を有さず、ドレインバスバー41の略全体によりマイクロストリップ線路が構成されたものであっても良い。すなわち、ドレインバスバー41が図6及び図7Aに示すドレインバスバー41’と同様の形状を有するものであっても良い。この場合、ソース電極5は、図20に示す部位53~53を除去してなる形状であっても良い。 In the transistor 100 of the fourth embodiment, the gate bus bar 31 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire gate bus bar 31. That is, the gate bus bar 31 may have the same shape as the gate bus bar 31 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5 may have a shape formed by removing the portions 52 1 to 52 8 shown in FIG. Alternatively, in the transistor 100 of the fourth embodiment, the drain bus bar 41 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire drain bus bar 41. That is, the drain bus bar 41 may have the same shape as the drain bus bar 41 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5 may have a shape formed by removing the portions 53 1 to 53 4 shown in FIG.
 以上のように、実施の形態4のトランジスタ100は、誘電体基板1の裏面部に設けられた金属層2と、誘電体基板1の表面部に設けられており、ゲートバスバー31とゲートバスバー31により互いに電気的に接続された複数本のゲートフィンガー32~3210とを有するゲート電極3と、誘電体基板1の表面部に設けられており、誘電体基板1を貫通したビア11k,11l,12k,12lにより金属層2と電気的に接続されたソース電極5とを備え、ゲートバスバー31の一部(部位33~33)がエアブリッジ配線により構成されており、当該エアブリッジ配線と誘電体基板1との間にソース電極5の一部(部位52~52)が配置されている。これにより、ゲートエアブリッジにおいて誘電体基板1による誘電損失が生ずるのを防ぐことができるため、高利得、高出力電力かつ高効率なトランジスタ100を得ることができる。 As described above, the transistor 100 according to the fourth embodiment is provided on the metal layer 2 provided on the back surface portion of the dielectric substrate 1 and on the front surface portion of the dielectric substrate 1, and includes the gate bus bar 31 and the gate bus bar 31. The gate electrode 3 having a plurality of gate fingers 32 1 to 32 10 that are electrically connected to each other by the above and vias 11k, 11l that are provided on the surface portion of the dielectric substrate 1 and penetrate the dielectric substrate 1. , 12k, and a source electrode 5 connected to the metal layer 2 and the electrically by 12l, part of the gate bus bar 31 (region 33 1-33 8) is constituted by an air bridge wiring, the air bridge wiring And part of the source electrode 5 (parts 52 1 to 52 8 ) are disposed between the dielectric substrate 1 and the dielectric substrate 1. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the gate air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.
 また、実施の形態4のトランジスタ100は、誘電体基板1の裏面部に設けられた金属層2と、誘電体基板1の表面部に設けられており、ドレインバスバー41とドレインバスバー41により互いに電気的に接続された複数本のドレインフィンガー42~42とを有するドレイン電極4と、誘電体基板1の表面部に設けられており、誘電体基板1を貫通したビア11k,11l,12k,12lにより金属層2と電気的に接続されたソース電極5とを備え、ドレインバスバー41の一部(部位43~43)がエアブリッジ配線により構成されており、当該エアブリッジ配線と誘電体基板1との間にソース電極5の一部(部位53~53)が配置されている。これにより、ドレインエアブリッジにおいて誘電体基板1による誘電損失が生ずるのを防ぐことができるため、高利得、高出力電力かつ高効率なトランジスタ100を得ることができる。 The transistor 100 according to the fourth embodiment is provided on the metal layer 2 provided on the back surface of the dielectric substrate 1 and on the front surface of the dielectric substrate 1, and is electrically connected to each other by the drain bus bar 41 and the drain bus bar 41. A drain electrode 4 having a plurality of drain fingers 42 1 to 42 5 connected to each other, and vias 11k, 11l, 12k, which are provided on the surface of the dielectric substrate 1 and penetrate the dielectric substrate 1. 12l is provided with a source electrode 5 electrically connected to the metal layer 2 and a part of the drain bus bar 41 (parts 43 1 to 43 4 ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric A part of the source electrode 5 (parts 53 1 to 53 4 ) is disposed between the substrate 1 and the substrate 1. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the drain air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.
 なお、本願発明はその発明の範囲内において、各実施の形態の自由な組み合わせ、あるいは各実施の形態の任意の構成要素の変形、もしくは各実施の形態において任意の構成要素の省略が可能である。 In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .
 本発明のトランジスタは、例えば、無線通信装置又はレーダ装置における高周波信号の増幅に用いることができる。 The transistor of the present invention can be used, for example, for amplifying a high frequency signal in a radio communication device or a radar device.
 1 誘電体基板、2 金属層、3 ゲート電極、4 ドレイン電極、5 ソース電極、5a,5b,5c,5d,5e,5f,5g,5h,5i,5j,5k,5l 電極、6 ゲート端子、7 ドレイン端子、11a,11b,11c,11d,11e,11f,11g,11h,11i,11j,11k,11l ビア、12k,12l ビア、31 ゲートバスバー、32,32,32,32,32,32,32,32,32,3210 ゲートフィンガー、33,33,33,33,33,33,33,33 部位、41 ドレインバスバー、42,42,42,42,42 ドレインフィンガー、43,43,43,43 部位、51,51,51,51,51,51 部位、52,52,52,52,52,52,52,52 部位、53,53,53,53 部位、100 トランジスタ。 1 dielectric substrate, 2 metal layer, 3 gate electrode, 4 drain electrode, 5 source electrode, 5a, 5b, 5c, 5d, 5e, 5f, 5g, 5h, 5i, 5j, 5k, 5l electrode, 6 gate terminal, 7 drain terminal, 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, 11i, 11j, 11k, 11l via, 12k, 12l via, 31 gate bus bar, 32 1 , 32 2 , 32 3 , 32 4 , 32 5 , 32 6 , 32 7 , 32 8 , 32 9 , 32 10 gate fingers, 33 1 , 33 2 , 33 3 , 33 4 , 33 5 , 33 6 , 33 7 , 33 8 part, 41 drain bus bar, 42 1, 42 2, 42 3, 42 4, 42 5 drain finger, 43 1, 43 2, 43 3, 43 4 sites, 51 1, 51 2, 51 3, 1 4, 51 5, 51 6 sites, 52 1, 52 2, 52 3, 52 4, 52 5, 52 6, 52 7, 52 8 parts, 53 1, 53 2, 53 3, 53 4 sites, 100 transistor .

Claims (8)

  1.  誘電体基板の裏面部に設けられた金属層と、
     前記誘電体基板の表面部に設けられており、ゲートバスバーと前記ゲートバスバーにより互いに電気的に接続された複数本のゲートフィンガーとを有するゲート電極と、
     前記誘電体基板の表面部に設けられており、前記誘電体基板を貫通したビアにより前記金属層と電気的に接続されたソース電極と、を備え、
     前記ゲートバスバーの一部がエアブリッジ配線により構成されており、当該エアブリッジ配線と前記誘電体基板との間に前記ソース電極の一部が配置されている
     ことを特徴とするトランジスタ。
    A metal layer provided on the back surface of the dielectric substrate;
    A gate electrode provided on a surface portion of the dielectric substrate, the gate electrode having a gate bus bar and a plurality of gate fingers electrically connected to each other by the gate bus bar;
    A source electrode provided on a surface portion of the dielectric substrate and electrically connected to the metal layer by a via penetrating the dielectric substrate;
    A part of the gate bus bar is constituted by an air bridge wiring, and a part of the source electrode is disposed between the air bridge wiring and the dielectric substrate.
  2.  前記金属層は電気的に接地されていることを特徴とする請求項1記載のトランジスタ。 2. The transistor according to claim 1, wherein the metal layer is electrically grounded.
  3.  前記ビアは互いに隣接する前記ゲートフィンガー間に配置されていることを特徴とする請求項1記載のトランジスタ。 2. The transistor according to claim 1, wherein the via is disposed between the gate fingers adjacent to each other.
  4.  前記誘電体基板の表面部に設けられており、ドレインバスバーと前記ドレインバスバーにより互いに電気的に接続された複数本のドレインフィンガーとを有するドレイン電極を備え、
     前記ドレインバスバーの一部がエアブリッジ配線により構成されており、当該エアブリッジ配線と前記誘電体基板との間に前記ソース電極の一部が配置されている
     ことを特徴とする請求項1記載のトランジスタ。
    A drain electrode provided on a surface portion of the dielectric substrate and having a drain bus bar and a plurality of drain fingers electrically connected to each other by the drain bus bar;
    The part of the drain bus bar is configured by an air bridge wiring, and a part of the source electrode is disposed between the air bridge wiring and the dielectric substrate. Transistor.
  5.  誘電体基板の裏面部に設けられた金属層と、
     前記誘電体基板の表面部に設けられており、ドレインバスバーと前記ドレインバスバーにより互いに電気的に接続された複数本のドレインフィンガーとを有するドレイン電極と、
     前記誘電体基板の表面部に設けられており、前記誘電体基板を貫通したビアにより前記金属層と電気的に接続されたソース電極と、を備え、
     前記ドレインバスバーの一部がエアブリッジ配線により構成されており、当該エアブリッジ配線と前記誘電体基板との間に前記ソース電極の一部が配置されている
     ことを特徴とするトランジスタ。
    A metal layer provided on the back surface of the dielectric substrate;
    A drain electrode provided on a surface portion of the dielectric substrate and having a drain bus bar and a plurality of drain fingers electrically connected to each other by the drain bus bar;
    A source electrode provided on a surface portion of the dielectric substrate and electrically connected to the metal layer by a via penetrating the dielectric substrate;
    A part of the drain bus bar is constituted by an air bridge wiring, and a part of the source electrode is arranged between the air bridge wiring and the dielectric substrate.
  6.  前記金属層は電気的に接地されていることを特徴とする請求項5記載のトランジスタ。 6. The transistor according to claim 5, wherein the metal layer is electrically grounded.
  7.  前記ビアは互いに隣接する前記ドレインフィンガー間に配置されていることを特徴とする請求項5記載のトランジスタ。 6. The transistor according to claim 5, wherein the via is disposed between the drain fingers adjacent to each other.
  8.  前記誘電体基板の表面部に設けられており、ゲートバスバーと前記ゲートバスバーにより互いに電気的に接続された複数本のゲートフィンガーとを有するゲート電極を備え、
     前記ゲートバスバーの一部がエアブリッジ配線により構成されており、当該エアブリッジ配線と前記誘電体基板との間に前記ソース電極の一部が配置されている
     ことを特徴とする請求項5記載のトランジスタ。
    A gate electrode provided on a surface portion of the dielectric substrate, the gate electrode having a gate bus bar and a plurality of gate fingers electrically connected to each other by the gate bus bar;
    The part of the gate bus bar is configured by an air bridge wiring, and a part of the source electrode is disposed between the air bridge wiring and the dielectric substrate. Transistor.
PCT/JP2017/002280 2017-01-24 2017-01-24 Transistor WO2018138764A1 (en)

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
KR20200062938A (en) * 2018-11-27 2020-06-04 삼성전기주식회사 Semiconductor device having stacked field effect transistors

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JPH0750422A (en) * 1993-08-05 1995-02-21 Nec Corp Semiconductor device
JPH098064A (en) * 1995-06-20 1997-01-10 Siemens Ag Semiconductor device
JP2007081124A (en) * 2005-09-14 2007-03-29 Toshiba Corp Semiconductor device
JP2013183061A (en) * 2012-03-02 2013-09-12 Toshiba Corp Semiconductor device

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Publication number Priority date Publication date Assignee Title
JPH0750422A (en) * 1993-08-05 1995-02-21 Nec Corp Semiconductor device
JPH098064A (en) * 1995-06-20 1997-01-10 Siemens Ag Semiconductor device
JP2007081124A (en) * 2005-09-14 2007-03-29 Toshiba Corp Semiconductor device
JP2013183061A (en) * 2012-03-02 2013-09-12 Toshiba Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200062938A (en) * 2018-11-27 2020-06-04 삼성전기주식회사 Semiconductor device having stacked field effect transistors
KR102149388B1 (en) 2018-11-27 2020-08-28 삼성전기주식회사 Semiconductor device having stacked field effect transistors

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