WO2018138764A1

WO2018138764A1 - Transistor

Info

Publication number: WO2018138764A1
Application number: PCT/JP2017/002280
Authority: WO
Inventors: 純神岡; 山中　宏治; 政毅半谷
Original assignee: 三菱電機株式会社
Priority date: 2017-01-24
Filing date: 2017-01-24
Publication date: 2018-08-02
Also published as: JPWO2018138764A1; JP6246432B1

Abstract

This transistor (100) is provided with: a metal layer (2) disposed on a rear surface portion of a dielectric substrate (1); a gate electrode (3) disposed on a surface portion of the dielectric substrate (1), and having a gate bus bar (31) and a plurality of gate fingers (32₁-32₁₀) electrically connected to each other by the gate bus bar (31); and a source electrode (5) which is disposed on the surface portion of the dielectric substrate (1) and electrically connected to the metal layer (2) by vias (11a, 11b) that pass through the dielectric substrate (1), wherein a portion of the gate bus bar (31) is configured from an air bridge wire, and a portion of the source electrode (5) is disposed between said air bridge wire and the dielectric substrate (1).

Description

Transistor

The present invention relates to a transistor, and more particularly to a high-frequency transistor.

Conventionally, a transistor is used to amplify a high-frequency signal in a wireless communication device or a radar device. Specifically, for example, a source-grounded field effect transistor (Field Effect Transistor, FET) is used. Patent Document 1 discloses an FET in which a substantially comb-shaped gate electrode and a substantially comb-shaped drain electrode are arranged so as to mesh with each other, a so-called “multi-finger type” FET.

JP 2008-109227 A

A gate electrode in a multi-finger type FET (hereinafter referred to as “multi-finger FET”) has at least one gate bus bar and a plurality of gate fingers provided substantially perpendicular to the gate bus bar. Yes. Further, the drain electrode in the multi-finger FET has one or more drain bus bars and a plurality of drain fingers provided substantially perpendicular to the drain bus bars. The gate electrode and the drain electrode are provided on the front surface portion of the dielectric substrate, and a metal layer is provided on the back surface portion of the dielectric substrate. This metal layer is electrically grounded.

That is, in the conventional multi-finger FET, a microstrip line is constituted by the gate bus bar, and a microstrip line is constituted by the drain bus bar. When a high-frequency signal propagates through these microstrip lines, an electromagnetic field is generated in the dielectric substrate, so that a dielectric loss corresponding to the dielectric loss tangent occurs. Due to this dielectric loss, there is a problem that the gain, output power and efficiency of the transistor are lowered.

The present invention has been made to solve the above-described problems, and an object thereof is to provide a transistor having high gain, high output power, and high efficiency.

The transistor of the present invention includes a metal layer provided on the back surface of the dielectric substrate, and a plurality of gate fingers provided on the front surface of the dielectric substrate and electrically connected to each other by the gate bus bar. And a source electrode electrically connected to the metal layer by a via penetrating the dielectric substrate, and a part of the gate bus bar is an air bridge It is constituted by wiring, and a part of the source electrode is arranged between the air bridge wiring and the dielectric substrate.

The transistor of the present invention includes a metal layer provided on the back surface of the dielectric substrate and a plurality of drain fingers provided on the front surface of the dielectric substrate and electrically connected to each other by the drain bus bar and the drain bus bar. And a source electrode electrically connected to the metal layer by a via penetrating the dielectric substrate, and a part of the drain bus bar is an air bridge It is constituted by wiring, and a part of the source electrode is arranged between the air bridge wiring and the dielectric substrate.

According to the present invention, since it is configured as described above, a transistor with high gain, high output power, and high efficiency can be obtained.

FIG. 1A is a plan view showing a gate electrode according to Embodiment 1 of the present invention. FIG. 1B is a plan view showing the drain electrode according to Embodiment 1 of the present invention. 2A is a cross-sectional view taken along line A-A ′ shown in FIG. 1A. 2B is a cross-sectional view taken along line B-B ′ shown in FIG. 1B. It is a top view which shows the source electrode which concerns on Embodiment 1 of this invention. It is a top view which shows the principal part of the transistor which concerns on Embodiment 1 of this invention. FIG. 5A is a cross-sectional view taken along line A-A ′ shown in FIG. FIG. 5B is a cross-sectional view taken along line B-B ′ shown in FIG. FIG. 5C is a cross-sectional view taken along line C-C ′ shown in FIG. It is a top view which shows the principal part of the transistor used as the comparison object with the transistor which concerns on Embodiment 1 of this invention. FIG. 7A is a cross-sectional view taken along line C-C ′ shown in FIG. FIG. 7B is a cross-sectional view taken along line C-C ′ shown in FIG. FIG. 8A is a plan view showing a gate electrode according to Embodiment 2 of the present invention. FIG. 8B is a plan view showing the drain electrode according to Embodiment 2 of the present invention. FIG. 9A is a cross-sectional view taken along line A-A ′ shown in FIG. 8A. FIG. 9B is a cross-sectional view taken along line B-B ′ shown in FIG. 8B. It is a top view which shows the source electrode which concerns on Embodiment 2 of this invention. It is a top view which shows the principal part of the transistor which concerns on Embodiment 2 of this invention. 12A is a cross-sectional view taken along line A-A ′ shown in FIG. 12B is a cross-sectional view taken along line B-B ′ shown in FIG. 12C is a cross-sectional view taken along line C-C ′ shown in FIG. FIG. 13A is a plan view showing a gate electrode according to Embodiment 3 of the present invention. FIG. 13B is a plan view showing the drain electrode according to Embodiment 3 of the present invention. 14A is a cross-sectional view taken along line A-A ′ shown in FIG. 13A. 14B is a cross-sectional view taken along line B-B ′ shown in FIG. 13B. It is a top view which shows the source electrode which concerns on Embodiment 3 of this invention. It is a top view which shows the principal part of the transistor which concerns on Embodiment 3 of this invention. FIG. 17A is a cross-sectional view along the line A-A ′ shown in FIG. 16. FIG. 17B is a cross-sectional view along the line B-B ′ shown in FIG. 16. FIG. 17C is a cross-sectional view taken along line C-C ′ shown in FIG. FIG. 18A is a plan view showing a gate electrode according to Embodiment 4 of the present invention. FIG. 18B is a plan view showing the drain electrode according to Embodiment 4 of the present invention. FIG. 19A is a cross-sectional view taken along line A-A ′ shown in FIG. 18A. FIG. 19B is a cross-sectional view taken along line B-B ′ shown in FIG. 18B. It is a top view which shows the source electrode which concerns on Embodiment 4 of this invention. It is a top view which shows the principal part of the transistor which concerns on Embodiment 4 of this invention. 22A is a cross-sectional view taken along line A-A ′ shown in FIG. 22B is a cross-sectional view taken along line B-B ′ shown in FIG. 22C is a cross-sectional view taken along line C-C ′ shown in FIG.

Hereinafter, in order to explain the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.

Embodiment 1 FIG.
FIG. 1A is a plan view showing a gate electrode according to Embodiment 1 of the present invention. FIG. 1B is a plan view showing the drain electrode according to Embodiment 1 of the present invention. 2A is a cross-sectional view taken along line AA ′ shown in FIG. 1A. 2B is a cross-sectional view taken along line BB ′ shown in FIG. 1B. FIG. 3 is a plan view showing the source electrode according to Embodiment 1 of the present invention. FIG. 4 is a plan view showing the main part of the transistor according to Embodiment 1 of the present invention. FIG. 5A is a cross-sectional view taken along line AA ′ shown in FIG. 5B is a cross-sectional view taken along the line BB ′ shown in FIG. FIG. 5C is a cross-sectional view taken along the line CC ′ shown in FIG. With reference to FIGS. 1 to 5, the transistor 100 of Embodiment 1 will be described.

In the figure, 1 is a dielectric substrate. An electrically grounded metal layer 2 is provided on the back surface of the dielectric substrate 1. A gate electrode 3, a drain electrode 4, and a source electrode 5 are provided on the surface portion of the dielectric substrate 1.

The gate electrode 3 has one gate bus bar 31 and ten gate fingers 32 ₁ to 32 ₁₀ provided substantially perpendicular to the gate bus bar 31. Thereby, the outer shape of the gate electrode 3 is substantially comb-shaped. The gate fingers 32 ₁ to 32 ₁₀ are electrically connected to each other by a gate bus bar 31. Each of the gate fingers 32 ₁ to 32 ₁₀ is electrically connected to the gate terminal 6 via the gate bus bar 31.

The drain electrode 4 has one drain bus bar 41 and five drain fingers 42 ₁ to 42 ₅ provided substantially perpendicular to the drain bus bar 41. Thereby, the external shape of the drain electrode 4 is substantially comb-shaped. Drain finger ₄₂ 1-42 ₅ are electrically connected to each other by the drain bus bar 41. Further, each of the drain finger 42 _1-42 ₅ are drain terminals 7 electrically connected via a drain bus bar 41.

The gate electrode 3 and the drain electrode 4 are arranged to face each other so that the gate fingers 32 ₁ to 32 ₁₀ and the drain fingers 42 ₁ to 42 ₅ are engaged with each other. More specifically, the drain finger 42 ₁ is disposed between the gate fingers ₃₂ 1, 32 ₂ adjacent to each other, the drain finger 42 ₂ is disposed between the

gate fingers

₃₂ 3, 32 ₄ adjacent to each other, gate adjacent to each other a drain finger 42 ₃ disposed

fingers

₃₂ 5, 32 between _6, the drain finger 42 ₄ is disposed between the

gate fingers

₃₂ 7, 32 ₈ which are adjacent to each other, the drain finger between the gate fingers ₃₂ 9, _{32 10} that are adjacent to each other 42 ₅ is arranged. That is, the transistor 100 is a multi-finger type.

Here, as shown to FIG. 5A, a part of gate bus-bar 31 is comprised by the air bridge wiring. More specifically, the gate finger 32 and the gate fingers ₃₂ 1, 32 parts 33 ₁ connecting between ₂ and portion 33 ₂ for connecting the

gate fingers

₃₂ 2, 32 ₃ which are adjacent to each other, adjacent to each other adjacent to each other _3, and 32 ₄ sites 33 ₃ which connects a portion 33 ₄ for connecting the

gate fingers

₃₂ 4, 32 ₅ which are adjacent to each other, the portion 33 ₅ for connecting the

gate fingers

₃₂ 6, 32 ₇ adjacent to each other , A portion 33 ₆ connecting the

gate fingers

32 ₇ and 32 ₈ adjacent to each other, a portion 33 ₇ connecting the

gate fingers

32 ₈ and 32 ₉ adjacent to each other, and between the

gate fingers

32 ₉ and 32 ₁₀ adjacent to each other each of the sites 33 ₈ for connecting is formed by an air-bridge wiring.

Hereinafter, the portion 33 _1-33 ₈ constituted by an air bridge line of the gate bus bar 31 may be referred to as "gate air bridge". The remaining part of the gate bus bar 31 constitutes a microstrip line.

Further, as shown in FIG. 5B, a part of the drain bus bar 41 is constituted by an air bridge wiring. Drain finger 42 More specifically, a portion 43 ₁ that connects between the drain finger ₄₂ 1, 42 ₂ adjacent to each other, the portion 43 ₂ which connects between the drain finger ₄₂ 2, 42 ₃ adjacent to each other, adjacent to each other _3, and 42 ₄ sites 43 ₃ which connects the, each of the drain finger ₄₂ 4, 42 ₅ parts 43 ₄ for connecting the adjacent is constituted by an air-bridge interconnection with each other.

Hereinafter, the portions 43 ₁ to 43 ₄ constituted by the air bridge wiring in the drain bus bar 41 may be referred to as “drain air bridge”. The remaining part of the drain bus bar 41 constitutes a microstrip line.

The source electrode 5 is composed of a pair of

electrodes

5a and 5b. One electrode 5 a is electrically connected to the metal layer 2 by a via 11 a penetrating the dielectric substrate 1. The other electrode 5 b is electrically connected to the metal layer 2 by a via 11 b that penetrates the dielectric substrate 1. The

vias

11a and 11b are arranged in the half portion on the gate terminal 6 side of the dielectric substrate 1. That is, the source electrode 5 is electrically grounded, and the transistor 100 is a grounded source type.

The source electrode 5 has portions 51 ₁ to 51 ₆ arranged in parallel to the gate fingers 32 ₁ to 32 ₁₀ and the drain fingers 42 ₁ to 42 ₅ . More specifically, the source electrode 5 is disposed between a portion 51 ₁ disposed outside the gate finger 32 ₁ provided at one end of the gate bus bar 31 and the

gate fingers

32 ₂ and 32 ₃ adjacent to each other. a portion 51 ₂ which is, the

gate finger

₃₂ 4, 32 ₅ parts 51 ₃ disposed between the mutually

adjacent gate fingers

₃₂ 6, 32 ₇ sites 51 ₄ disposed between the adjacent, adjacent the gate fingers ₃₂ 8, 32 parts 51 ₅ disposed between ₉ and a portion 51 ₆ arranged outside the gate fingers _{32 10} provided on the other end of the gate bus bar 31.

The source electrode 5, between each a dielectric substrate 1 of a gate air bridge, i.e. arranged site 52 ₁ between each dielectric substrate 1 site 33 1 _to 33 ₈ of the gate bus bar 31 It has a 52 _8. Further, the source electrode 5, between each a dielectric substrate 1 of the drain air bridges, i.e. arranged site 53 ₁ between each dielectric substrate 1 site 43 _1-43 ₄ of the drain bus bar 41 and a 53 _4.

The dielectric substrate 1, the metal layer 2, the gate electrode 3, the drain electrode 4, the source electrode 5, the gate terminal 6 and the drain terminal 7 constitute the main part of the transistor 100.

Next, the operation of the transistor 100 will be described focusing on the operation of amplifying a high frequency signal. First, a high frequency signal is input to the gate terminal 6. The input high frequency signal is distributed to each of the gate fingers 32 ₁ to 32 ₁₀ via the gate bus bar 31. Then, from each of the drain finger ₄₂ 1-42 _5, amplified radio frequency signal is output. These high frequency signals are combined by the drain bus bar 41 and output to the drain terminal 7.

Next, the effect of the transistor 100 will be described with reference to FIGS. FIG. 6 is a plan view showing a main part of a transistor 100 ′ to be compared with the transistor 100 according to the first embodiment. FIG. 7A is a cross-sectional view taken along line C-C ′ shown in FIG. 6, that is, a cross-sectional view of the transistor 100 ′. FIG. 7B is a cross-sectional view taken along the line C-C ′ shown in FIG. 4, that is, a cross-sectional view of the transistor 100.

As shown in FIGS. 6 and 7A, an electrically grounded metal layer 2 ′ is provided on the back surface of the dielectric substrate 1 ′, and the gate electrode 3 ′ and the surface of the dielectric substrate 1 ′ are provided. A drain electrode 4 'is provided. 6 and 7A, the source electrode is not shown.

The gate electrode 3 'is one gate bus bar 31' has a gate finger 32 _first ten and '~ _{32 10'} and each of the gate fingers 32 ₁ 'to _{32 10'} through the gate bus bar 31 ' Are electrically connected to the gate terminal 6 '. A drain electrode 4 'is one of the drain bus bar 41' has a five drain finger 42 ₁ 'to 42 _5' and each of the drain finger 42 ₁ '~ 42 _5' is via the drain bus bar 41 ' Are electrically connected to the drain terminal 7 '.

Here, the gate bus bar 31 'does not have an air bridge wiring, and substantially the entire gate bus bar 31' constitutes a microstrip line. Further, the drain bus bar 41 ′ does not have an air bridge wiring, and substantially the entire drain bus bar 41 ′ constitutes a microstrip line. *

In the gate bus bar 31 ′ of the transistor 100 ′, the high frequency signal is transmitted in the micro trip mode. An electromagnetic field corresponding to the high-frequency signal is generated between the gate bus bar 31 'and the metal layer 2'. Six arrows A1 'shown in FIG. 7A indicate electric lines of force corresponding to the power of the high-frequency signal propagating through the gate bus bar 31'. As shown in FIG. 7A, the electric force lines A1 'start at the gate bus bar 31', and the electric lines A1 'end at the electrically grounded metal layer 2'. That is, the electric lines of force A1 'pass through the dielectric substrate 1'. Since the dielectric substrate 1 'has a finite conductance and a finite dielectric loss tangent, a dielectric loss corresponding to the dielectric loss tangent occurs. This dielectric loss reduces the gain, output power and efficiency of transistor 100 '.

On the other hand, in the transistor 100 of the first embodiment, a part of the gate bus bar 31 is configured by an air bridge wiring, and a part of the source electrode 5 is interposed between the air bridge wiring and the dielectric substrate 1. Has been placed. The six arrows A1 shown in FIG. 7B indicate electric lines of force corresponding to the power of the high-frequency signal propagating through the gate air bridge. As shown in FIG. 7B, the beginning of the electric power line A1 denotes a gate bus bar 31 (region 33 _2), the end of the electric line of force A1 is the source electrode 5 which is electrically grounded (sites 52 _2). That is, the electric lines of force A1 do not pass through the dielectric substrate 1 but pass through the air. Thereby, it is possible to prevent the dielectric loss due to the dielectric loss tangent of the dielectric substrate 1 from occurring.

Further, the high frequency signal is transmitted in the micro trip mode in the drain bus bar 41 ′ of the transistor 100 ′. An electromagnetic field corresponding to the high-frequency signal is generated between the drain bus bar 41 'and the metal layer 2'. Six arrows A2 'shown in FIG. 7A indicate electric lines of force corresponding to the power of the high-frequency signal propagating through the drain bus bar 41'. As shown in FIG. 7A, the electric force line A2 'starts at the drain bus bar 41', and the electric force line A2 'ends at the electrically grounded metal layer 2'. That is, the electric lines of force A2 'pass through the dielectric substrate 1'. Since the dielectric substrate 1 'has a finite conductance and a finite dielectric tangent, a dielectric loss corresponding to the dielectric tangent occurs. This dielectric loss reduces the gain, output power and efficiency of transistor 100 '.

On the other hand, in the transistor 100 of the first embodiment, a part of the drain bus bar 41 is configured by an air bridge wiring, and a part of the source electrode 5 is interposed between the air bridge wiring and the dielectric substrate 1. Has been placed. The six arrows A2 shown in FIG. 7B indicate electric lines of force corresponding to the power of the high-frequency signal propagating through the drain air bridge. As shown in FIG. 7B, the starting end of the electric force line A2 is the drain bus bar 41 (part 43 ₁ ), and the end of the electric line of force A2 is the electrically grounded source electrode 5 (part 53 ₁ ). That is, the electric lines of force A2 do not pass through the dielectric substrate 1 but pass through the air. Thereby, it is possible to prevent the dielectric loss due to the dielectric loss tangent of the dielectric substrate 1 from occurring.

In the transistor 100 of the first embodiment, the drain bus bar 41 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire drain bus bar 41. That is, the drain bus bar 41 may have the same shape as the drain bus bar 41 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5 may have a shape obtained by removing the portions 53 ₁ to 53 ₄ shown in FIG.

Further, the number of gate bus bars 31 may be one or more, and is not limited to one. The number of gate fingers 32 ₁ to 32 ₁₀ may be plural, and is not limited to ten.

The number of drain bus bars 41 may be one or more, and is not limited to one. The number of drain fingers 42 ₁ to 42 ₅ may be a plurality, and is not limited to five.

As described above, the transistor 100 of the first embodiment is provided on the metal layer 2 provided on the back surface portion of the dielectric substrate 1 and on the front surface portion of the dielectric substrate 1, and includes the gate bus bar 31 and the gate bus bar 31. The gate electrode 3 having a plurality of gate fingers 32 ₁ to 32 ₁₀ that are electrically connected to each other by the above, and vias 11 a and 11 b that are provided on the surface portion of the dielectric substrate 1 and penetrate the dielectric substrate 1. And a source electrode 5 electrically connected to the metal layer 2, and a part of the gate bus bar 31 (parts 33 ₁ to 33 ₈ ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric substrate A part (parts 52 ₁ to 52 ₈ ) of the source electrode 5 is disposed between the source electrode 5 and the source electrode 5. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the gate air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.

The transistor 100 of the first embodiment is provided on the metal layer 2 provided on the back surface of the dielectric substrate 1 and on the front surface of the dielectric substrate 1, and is electrically connected to each other by the drain bus bar 41 and the drain bus bar 41. The drain electrode 4 having a plurality of connected drain fingers 42 ₁ to 42 ₅ and a metal layer formed by vias 11 a and 11 b penetrating the dielectric substrate 1 are provided on the surface of the dielectric substrate 1. 2 and a source electrode 5 electrically connected to each other, and a part of the drain bus bar 41 (parts 43 ₁ to 43 ₄ ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric substrate 1 are connected to each other. part of the source electrode 5 (sites ₅₃ 1-53 ₄₎ is disposed between. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the drain air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.

Embodiment 2. FIG.
FIG. 8A is a plan view showing a gate electrode according to Embodiment 2 of the present invention. FIG. 8B is a plan view showing the drain electrode according to Embodiment 2 of the present invention. FIG. 9A is a cross-sectional view taken along line AA ′ shown in FIG. 8A. FIG. 9B is a cross-sectional view taken along line BB ′ shown in FIG. 8B. FIG. 10 is a plan view showing a source electrode according to Embodiment 2 of the present invention. FIG. 11 is a plan view showing a main part of a transistor according to Embodiment 2 of the present invention. 12A is a cross-sectional view taken along line AA ′ shown in FIG. 12B is a cross-sectional view taken along the line BB ′ shown in FIG. 12C is a cross-sectional view taken along the line CC ′ shown in FIG.

The transistor 100 of the second embodiment will be described with reference to FIGS. Components similar to those of the transistor 100 of Embodiment 1 shown in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof is omitted.

As shown in FIG. 12A, a part of the gate bus bar 31 is configured by air bridge wiring. More specifically, the gate finger 32 and the

gate fingers

₃₂ 2, 32 ₃ parts 33 ₂ connected between a site 33 ₄ for connecting the

gate fingers

₃₂ 4, 32 ₅ which are adjacent to each other, adjacent to each other adjacent to each other _6, and 32 ₇ sites 33 ₅ connecting between each of the gate fingers ₃₂ 8, 32 ₉ parts 33 ₇ connecting between adjacent is constituted by an air-bridge interconnection with each other. The remaining part of the gate bus bar 31 constitutes a microstrip line.

The source electrode 5 is composed of six substantially rectangular electrodes 5c to 5h. The electrodes 5c to 5h are electrically connected to the metal layer 2 through vias 11c to 11h penetrating the dielectric substrate 1, respectively.

The source electrode 5 has portions 51 ₁ to 51 ₆ arranged in parallel to the gate fingers 32 ₁ to 32 ₁₀ and the drain fingers 42 ₁ to 42 ₅ . These sites ₅₁ 1-51 ₆ are provided one on electrodes 5c ~ 5h.

Here, the via 11c ~ 11h are respectively arranged in the center of these sites ₅₁ 1-51 _6. For this reason, the four vias 11d to 11g among the six vias 11c to 11h are arranged between the adjacent gate fingers of the gate fingers 32 ₂ to 32 ₁₀ , and the drain fingers 42 ₁ to 42 are provided. ₅ between the adjacent drain fingers.

More specifically, the via 11d is disposed between the

gate fingers

₃₂ 2, 32 ₃ which are adjacent to each other, via 11e is disposed between the

gate fingers

₃₂ 4, 32 ₅ which are adjacent to each other, the gate fingers via 11f adjacent to each other 32 _6, 32 are disposed between _7, vias 11g is disposed between the gate fingers ₃₂ 8, 32 ₉ adjacent to each other. The via 11d is disposed between the drain fingers 42 ₁ and 42 ₂ adjacent to each other, the via 11e is disposed between the drain fingers 42 ₂ and 42 ₃ adjacent to each other, and the via 11f is disposed adjacent to the drain fingers 42 ₃ and 42. ₄ , the via 11 g is disposed between the drain fingers 42 ₄ and ₄ ₅ adjacent to each other.

The source electrode 5 is disposed between each gate air bridge and the dielectric substrate 1, that is, between each of the portions 33 ₂ , 33 ₄ , 33 ₅ , and 33 ₇ of the gate bus bar 31 and the dielectric substrate 1. The region 52 ₂ , 52 ₄ , 52 ₅ , 52 ₇ is formed. These portions 52 ₂ , 52 ₄ , 52 ₅ , and 52 ₇ are connected to the four electrodes 5d to 5g excluding the

electrodes

5c and 5h arranged at both ends of the six electrodes 5c to 5h arranged in parallel to each other. One by one.

Further, the source electrode 5, between each a dielectric substrate 1 of the drain air bridges, i.e. arranged site 53 ₁ between each dielectric substrate 1 site 43 _1-43 ₄ of the drain bus bar 41 and a 53 _4. Each of these portions 53 ₁ to 53 ₄ is provided on each of the four electrodes 5d to 5g excluding the

electrodes

5c and 5h arranged at both ends of the six electrodes 5c to 5h arranged in parallel to each other. Yes.

Since the operation of the transistor 100 according to the second embodiment is the same as that described in the first embodiment, description thereof is omitted. The effect of the transistor 100 according to the second embodiment is the same as that described with reference to FIGS. 6 and 7 in the first embodiment, and thus illustration and description thereof are omitted.

In the transistor 100 of the second embodiment, the gate bus bar 31 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire gate bus bar 31. That is, the gate bus bar 31 may have the same shape as the gate bus bar 31 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5, part ₅₂ _2, 52 ₄ shown in FIG. _10, 52 5, 52 ₇ may be then formed by the shape removed. Alternatively, in the transistor 100 of the second embodiment, the drain bus bar 41 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire drain bus bar 41. That is, the drain bus bar 41 may have the same shape as the drain bus bar 41 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5 may have a shape formed by removing the portions 53 ₁ to 53 ₄ shown in FIG.

Further, the number of electrodes 5c to 5h constituting the source electrode 5 may be a number corresponding to the number of gate fingers 32 ₁ to 32 _{10 and} the number of drain fingers 42 ₁ to 42 ₅ , and is limited to six. It is not a thing.

As described above, the transistor 100 according to the second embodiment is provided on the metal layer 2 provided on the back surface portion of the dielectric substrate 1 and on the front surface portion of the dielectric substrate 1, and includes the gate bus bar 31 and the gate bus bar 31. The gate electrode 3 having a plurality of gate fingers 32 ₁ to 32 ₁₀ that are electrically connected to each other by the above, and vias 11c to 11h that are provided on the surface portion of the dielectric substrate 1 and penetrate the dielectric substrate 1 And a part of the gate bus bar 31 (parts 33 ₂ , 33 ₄ , 33 ₅ , 33 ₇ ) are configured by air bridge wiring, and the source electrode 5 is electrically connected to the metal layer 2 by the air bridge wiring. Part of the source electrode 5 (parts 52 ₂ , 52 ₄ , 52 ₅ , 52 ₇ ) is disposed between the bridge wiring and the dielectric substrate 1. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the gate air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.

Further, the vias 11d to 11g are arranged between the gate fingers adjacent to each other. Accordingly, since the area of the source electrode 5 can be reduced, the transistor 100 can be reduced in size.

The transistor 100 of the second embodiment is provided on the metal layer 2 provided on the back surface of the dielectric substrate 1 and on the front surface of the dielectric substrate 1, and is electrically connected to each other by the drain bus bar 41 and the drain bus bar 41. The drain electrode 4 having a plurality of connected drain fingers 42 ₁ to 42 ₅ and a metal layer formed on the surface of the dielectric substrate 1 and vias 11c to 11h penetrating the dielectric substrate 1 2 and a source electrode 5 electrically connected to each other, and a part of the drain bus bar 41 (parts 43 ₁ to 43 ₄ ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric substrate 1 are connected to each other. A part of the source electrode 5 (parts 53 ₁ to 53 ₄ ) is disposed between them. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the drain air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.

Also, the vias 11d to 11g are arranged between the drain fingers adjacent to each other. Accordingly, since the area of the source electrode 5 can be reduced, the transistor 100 can be reduced in size.

Embodiment 3 FIG.
FIG. 13A is a plan view showing a gate electrode according to Embodiment 3 of the present invention. FIG. 13B is a plan view showing the drain electrode according to Embodiment 3 of the present invention. 14A is a cross-sectional view taken along line AA ′ shown in FIG. 13A. 14B is a cross-sectional view taken along line BB ′ shown in FIG. 13B. FIG. 15 is a plan view showing a source electrode according to Embodiment 3 of the present invention. FIG. 16 is a plan view showing a main part of a transistor according to Embodiment 3 of the present invention. 17A is a cross-sectional view taken along line AA ′ shown in FIG. FIG. 17B is a cross-sectional view taken along the line BB ′ shown in FIG. FIG. 17C is a cross-sectional view taken along the line CC ′ shown in FIG.

The transistor 100 of the third embodiment will be described with reference to FIGS. Components similar to those of the transistor 100 of Embodiment 1 shown in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof is omitted.

As shown in FIG. 17A, a part of the gate bus bar 31 is configured by air bridge wiring. More specifically, the gate finger 32 and the

gate fingers

The source electrode 5 is composed of a pair of

electrodes

5i and 5j. One electrode 5 i is electrically connected to the metal layer 2 through a via 11 i penetrating the dielectric substrate 1. The other electrode 5j is electrically connected to the metal layer 2 by a via 11j penetrating the dielectric substrate 1. The

vias

11 i and 11 j are arranged in the half part of the dielectric substrate 1 on the drain terminal 7 side.

The source electrode 5 has portions 51 ₁ to 51 ₆ arranged in parallel to the gate fingers 32 ₁ to 32 ₁₀ and the drain fingers 42 ₁ to 42 ₅ . The source electrode 5 is disposed between each gate air bridge and the dielectric substrate 1, that is, between each of the portions 33 ₂ , 33 ₄ , 33 ₅ , and 33 ₇ of the gate bus bar 31 and the dielectric substrate 1. The region 52 ₂ , 52 ₄ , 52 ₅ , 52 ₇ is formed. Further, the source electrode 5, between each a dielectric substrate 1 of the drain air bridges, i.e. arranged site 53 ₁ between each dielectric substrate 1 site 43 _1-43 ₄ of the drain bus bar 41 and a 53 _4.

Since the operation of the transistor 100 according to Embodiment 3 is the same as that described in Embodiment 1, description thereof is omitted. The effect of the transistor 100 according to the third embodiment is the same as that described with reference to FIGS. 6 and 7 in the first embodiment, and thus illustration and description thereof are omitted.

In the transistor 100 of the third embodiment, the gate bus bar 31 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire gate bus bar 31. That is, the gate bus bar 31 may have the same shape as the gate bus bar 31 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5, part ₅₂ _2, 52 ₄ shown in FIG. _15, 52 5, 52 ₇ may be then formed by the shape removed.

As described above, the transistor 100 of the third embodiment is provided on the metal layer 2 provided on the back surface portion of the dielectric substrate 1 and on the front surface portion of the dielectric substrate 1, and includes the gate bus bar 31 and the gate bus bar 31. The gate electrode 3 having a plurality of gate fingers 32 ₁ to 32 ₁₀ that are electrically connected to each other by the above, and vias 11 i and 11 j that are provided on the surface portion of the dielectric substrate 1 and penetrate the dielectric substrate 1. And a part of the gate bus bar 31 (parts 33 ₂ , 33 ₄ , 33 ₅ , 33 ₇ ) are configured by air bridge wiring, and the source electrode 5 is electrically connected to the metal layer 2 by the air bridge wiring. Part of the source electrode 5 (parts 52 ₂ , 52 ₄ , 52 ₅ , 52 ₇ ) is disposed between the bridge wiring and the dielectric substrate 1. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the gate air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.

The transistor 100 of the third embodiment is provided on the metal layer 2 provided on the back surface of the dielectric substrate 1 and on the front surface of the dielectric substrate 1, and is electrically connected to each other by the drain bus bar 41 and the drain bus bar 41. The drain electrode 4 having a plurality of connected drain fingers 42 ₁ to 42 ₅ and a metal layer by

vias

11 i and 11 j that are provided on the surface of the dielectric substrate 1 and penetrate the dielectric substrate 1. 2 and a source electrode 5 electrically connected to each other, and a part of the drain bus bar 41 (parts 43 ₁ to 43 ₄ ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric substrate 1 are connected to each other. A part of the source electrode 5 (parts 53 ₁ to 53 ₄ ) is disposed between them. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the drain air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.

Embodiment 4 FIG.
FIG. 18A is a plan view showing a gate electrode according to Embodiment 4 of the present invention. FIG. 18B is a plan view showing the drain electrode according to Embodiment 4 of the present invention. FIG. 19A is a cross-sectional view along the line AA ′ shown in FIG. 18A. FIG. 19B is a cross-sectional view taken along line BB ′ shown in FIG. 18B. FIG. 20 is a plan view showing a source electrode according to Embodiment 4 of the present invention. FIG. 21 is a plan view showing a main part of a transistor according to Embodiment 4 of the present invention. 22A is a cross-sectional view taken along line AA ′ shown in FIG. 22B is a cross-sectional view taken along the line BB ′ shown in FIG. 22C is a cross-sectional view taken along the line CC ′ shown in FIG.

The transistor 100 of the fourth embodiment will be described with reference to FIGS. Components similar to those of the transistor 100 of Embodiment 1 shown in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof is omitted.

The source electrode 5 is composed of a pair of electrodes 5k and 5l. One electrode 5k is electrically connected to the metal layer 2 by

vias

11k and 12k penetrating the dielectric substrate 1. The other electrode 5 l is electrically connected to the metal layer 2 by vias 11 l and 12 l penetrating the dielectric substrate 1. The vias 11k and 11l are arranged in a half portion on the gate terminal 6 side of the dielectric substrate 1. The vias 12k and 12l are arranged in a half part on the dielectric substrate 1 on the drain terminal 7 side.

Since the operation of the transistor 100 according to the fourth embodiment is the same as that described in the first embodiment, description thereof is omitted. Further, the effect of the transistor 100 according to the fourth embodiment is the same as that described with reference to FIGS. 6 and 7 in the first embodiment, and thus illustration and description thereof are omitted.

In the transistor 100 of the fourth embodiment, the gate bus bar 31 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire gate bus bar 31. That is, the gate bus bar 31 may have the same shape as the gate bus bar 31 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5 may have a shape formed by removing the portions 52 ₁ to 52 ₈ shown in FIG. Alternatively, in the transistor 100 of the fourth embodiment, the drain bus bar 41 may not have an air bridge wiring, and a microstrip line may be configured by substantially the entire drain bus bar 41. That is, the drain bus bar 41 may have the same shape as the drain bus bar 41 ′ shown in FIGS. 6 and 7A. In this case, the source electrode 5 may have a shape formed by removing the portions 53 ₁ to 53 ₄ shown in FIG.

As described above, the transistor 100 according to the fourth embodiment is provided on the metal layer 2 provided on the back surface portion of the dielectric substrate 1 and on the front surface portion of the dielectric substrate 1, and includes the gate bus bar 31 and the gate bus bar 31. The gate electrode 3 having a plurality of gate fingers 32 ₁ to 32 ₁₀ that are electrically connected to each other by the above and vias 11k, 11l that are provided on the surface portion of the dielectric substrate 1 and penetrate the dielectric substrate 1. , 12k, and a source electrode 5 connected to the metal layer 2 and the electrically by 12l, part of the gate bus bar 31 (region 33 _1-33 ₈₎ is constituted by an air bridge wiring, the air bridge wiring And part of the source electrode 5 (parts 52 ₁ to 52 ₈ ) are disposed between the dielectric substrate 1 and the dielectric substrate 1. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the gate air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.

The transistor 100 according to the fourth embodiment is provided on the metal layer 2 provided on the back surface of the dielectric substrate 1 and on the front surface of the dielectric substrate 1, and is electrically connected to each other by the drain bus bar 41 and the drain bus bar 41. A drain electrode 4 having a plurality of drain fingers 42 ₁ to 42 ₅ connected to each other, and

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11k, 11l, 12k, which are provided on the surface of the dielectric substrate 1 and penetrate the dielectric substrate 1. 12l is provided with a source electrode 5 electrically connected to the metal layer 2 and a part of the drain bus bar 41 (parts 43 ₁ to 43 ₄ ) is constituted by an air bridge wiring, and the air bridge wiring and the dielectric A part of the source electrode 5 (parts 53 ₁ to 53 ₄ ) is disposed between the substrate 1 and the substrate 1. As a result, it is possible to prevent dielectric loss due to the dielectric substrate 1 in the drain air bridge, so that the transistor 100 with high gain, high output power, and high efficiency can be obtained.

In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .

The transistor of the present invention can be used, for example, for amplifying a high frequency signal in a radio communication device or a radar device.

1 dielectric substrate, 2 metal layer, 3 gate electrode, 4 drain electrode, 5 source electrode, 5a, 5b, 5c, 5d, 5e, 5f, 5g, 5h, 5i, 5j, 5k, 5l electrode, 6 gate terminal, 7 drain terminal, 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, 11i, 11j, 11k, 11l via, 12k, 12l via, 31 gate bus bar, 32 ₁ , 32 ₂ , 32 ₃ , 32 ₄ , 32 ₅ , 32 ₆ , 32 ₇ , 32 ₈ , 32 ₉ , 32 ₁₀ gate fingers, 33 ₁ , 33 ₂ , 33 ₃ , 33 ₄ , 33 ₅ , 33 ₆ , 33 ₇ , 33 ₈ part, 41 drain bus bar, 42 _1, ₄₂ _2, 42 _3, 42 4, 42 ₅

drain

_finger, 43 _1, 43 _2, 43 3, 43 ₄ _sites, 51 _1, 51 2, ₅₁ 3, 1 _4, ₅₁ 5, 51 ₆ _sites, 52 _1, ₅₂ _2, 52 _3, 52 _4, 52 5, 52 _6, 52 7, 52 ₈ _parts, 53 _1, 53 _2, 53 3, 53 ₄ sites, 100 transistor .

Claims

A metal layer provided on the back surface of the dielectric substrate;
A gate electrode provided on a surface portion of the dielectric substrate, the gate electrode having a gate bus bar and a plurality of gate fingers electrically connected to each other by the gate bus bar;
A source electrode provided on a surface portion of the dielectric substrate and electrically connected to the metal layer by a via penetrating the dielectric substrate;
A part of the gate bus bar is constituted by an air bridge wiring, and a part of the source electrode is disposed between the air bridge wiring and the dielectric substrate.
2. The transistor according to claim 1, wherein the metal layer is electrically grounded.
2. The transistor according to claim 1, wherein the via is disposed between the gate fingers adjacent to each other.
A drain electrode provided on a surface portion of the dielectric substrate and having a drain bus bar and a plurality of drain fingers electrically connected to each other by the drain bus bar;
The part of the drain bus bar is configured by an air bridge wiring, and a part of the source electrode is disposed between the air bridge wiring and the dielectric substrate. Transistor.
A metal layer provided on the back surface of the dielectric substrate;
A drain electrode provided on a surface portion of the dielectric substrate and having a drain bus bar and a plurality of drain fingers electrically connected to each other by the drain bus bar;
A source electrode provided on a surface portion of the dielectric substrate and electrically connected to the metal layer by a via penetrating the dielectric substrate;
A part of the drain bus bar is constituted by an air bridge wiring, and a part of the source electrode is arranged between the air bridge wiring and the dielectric substrate.
6. The transistor according to claim 5, wherein the metal layer is electrically grounded.
6. The transistor according to claim 5, wherein the via is disposed between the drain fingers adjacent to each other.
A gate electrode provided on a surface portion of the dielectric substrate, the gate electrode having a gate bus bar and a plurality of gate fingers electrically connected to each other by the gate bus bar;
The part of the gate bus bar is configured by an air bridge wiring, and a part of the source electrode is disposed between the air bridge wiring and the dielectric substrate. Transistor.