JP2007081124A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with reduced source inductance, improved heat radiation characteristics, high output, good frequency characteristics and high performance. <P>SOLUTION: A gate electrode 16 formed of a metallic layer forming a Schottky barrier, a source electrode 18 and a drain electrode 11 made of ohmic metal are formed on an operating region 15 of a semiconductor substrate. A region outside the operation region 15 serves as an insulation region. The source electrode 18 is connected with a source electrode pad 10 via a wire 17. Via holes 13 and 14 are simultaneously formed immediately under the source electrode 18 and the source electrode pad 10, and the holes differ in dimensions. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a field effect transistor (FET), and more particularly to a high-power, high-performance FET structure.

  Conventionally, FETs have generally been connected with three wires, gate, source, and drain, using bonding wires when mounting. In connection with bonding wires, the inductance between the source electrode pad and ground is especially in the GHz band. Therefore, the source inductance is reduced by forming a via hole immediately below the source electrode pad instead of connecting the source electrode pad and the ground with a bonding wire. In a high output FET, the gate, source and drain electrodes are generally arranged in a comb shape and connected.

  The source electrode pad connected to the source electrode by wiring is connected to the metal layer provided on the back surface of the semiconductor substrate by a via hole penetrating the semiconductor substrate and grounded. Although the characteristics are improved compared to the bonding method, this structure is grounded through the wiring from the source electrode to the via hole formed in the source electrode pad, so that the millimeter wave band (a frequency of 40 GHz or more) is particularly required. The source inductance is large enough to oscillate in the band. Compared to the source electrode closest to the via hole, the source electrode farthest away tends to oscillate because the source inductance increases due to the difference in the length of the wiring. That is, the source inductance and the oscillation frequency seen from each unit FET composed of a set of source electrode, drain electrode, and gate electrode are also different, and there are several frequencies that can oscillate. For this reason, it is necessary to reduce the source inductance and make the source inductance as seen from each unit FET uniform. Via holes are structures used to reduce the source inductance, but with this structure, the source inductance seen from each source electrode varies as described above, and the source inductance cannot be sufficiently reduced. There is a point. Further, GaAsFET has a high thermal resistance unlike Si, and thus heat dissipation becomes a problem. If the distance to the via hole is long, the heat dissipation becomes worse, and the distance between the FET operation region and the via hole formed in the source electrode pad is not sufficient, so it cannot always be said that the heat dissipation is good (Patent Document 1).

Some have a structure in which via holes are formed directly under each source electrode instead of the source electrode pad in order to reduce the source inductance uniformly. In this structure, the source inductance viewed from each unit FET can be reduced and the variation is small, and so long as it is ideal. However, the upper limit of the design of the source electrode region is satisfied in order to satisfy the characteristics, and there is a problem that a via hole having a free size cannot be arranged.
JP-A-4-29330

  Accordingly, the present invention has been made in view of the above, and an object of the present invention is to provide a high-performance semiconductor device with high output and good frequency characteristics that can reduce source inductance and improve heat dissipation characteristics.

  In order to solve the above problems, a semiconductor device according to the present invention includes a gate electrode formed on a working layer on a compound semiconductor substrate so as to form a Schottky junction, and an operation on the compound semiconductor substrate on both sides of the gate electrode. A source electrode and a drain electrode formed so as to be in ohmic contact with each other; an electrode pad connected to each of these electrodes via a wiring formed on the surface of the compound semiconductor substrate; and A first conductor layer formed on the back surface; a first via hole formed in the compound semiconductor substrate so as to reach the first conductor layer immediately below the source electrode; and the first via hole. A second conductor layer provided so as to connect the source electrode to the first conductor layer, and an electrode pad connected to the source electrode. A second via hole formed in the compound semiconductor substrate so as to reach the first conductor layer, and the electrode pad is provided to connect to the first conductor layer through the third via hole. The second conductor layer is provided.

  According to the present invention, the via hole is formed in the optimum size simultaneously in both the source electrode and the source electrode pad. The via hole formed in the source electrode has the effect of uniformly reducing the heat dissipation and source inductance in the transistor operating region of each FET element, and the via hole formed in the source electrode pad is stable due to a significant reduction in the source inductor of the entire FET To do. As a result, a high-performance semiconductor device with high output and good frequency characteristics can be provided.

  Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 shows the semiconductor device of the present invention as viewed from directly above. FIG. 2 is a cross-sectional view taken along line X-X ′ shown in FIG. As shown in FIG. 2, in the semiconductor device of the present invention, an n-type GaAs operation layer 24 is formed on a semi-insulating GaAs substrate 23 by ion implantation. A first conductor layer 21 (ground conductor layer) is formed on the back surface of the semiconductor substrate 23. A source electrode 18, a drain electrode 11, and a gate electrode 16 are formed on the n-type GaAs crystal layer 24, and the source electrode 18 is connected by a ground conductor layer 21 and a conductor layer 22 to form a via hole 14.

  When viewed from the top in FIG. 1, the gate electrode 16 formed of a metal layer forming a Schottky barrier, and the source electrode 18 and the drain electrode 11 formed of ohmic metal are formed on the operation region 15 of the semiconductor substrate. Has been. The outside of the operating region 15 is an insulating region 25 where no ion implantation is performed.

  The two source electrodes 18 are connected to the three source electrode pads 10 via the wiring 17. Via holes 13 and 14 are formed immediately below the source electrode 18 and immediately below the source electrode pad 10. FIG. 3 shows a top view of an element structure formed by arranging each FET element in a multi-stage comb shape for high output. In this case, a diagram in which the elements of FIG. 1 are arranged in three stages is shown as an example, but generally, how many stages are arranged is determined according to a required output.

  In the GaAsFET, reduction of the ground inductance of the source electrode 18 and improvement of the heat dissipation effect are important for high performance. The via holes 13 and 14 that connect the source electrode 18 and the source electrode pad 10 to the ground conductor layer 21 on the back surface of the semiconductor by the conductor layer 22 can serve both of these roles. The roles are slightly different depending on whether the electrode 18 and the source electrode pad 10 are formed. If an attempt is made to form the via hole 14 directly under the source electrode 18, the electrode area of the source electrode 18 is limited by the electrode width, and therefore a large via hole cannot be formed. If the diameter is small, the ground inductance may not be completely reduced due to the inductance of the via hole 14. However, since the via hole formed immediately below the source electrode 18 is close to the heat source generated in the operation region 15, the heat dissipation can be clearly improved. As described above, the via hole 14 can reduce the source impedance, but it is insufficient to reduce the source impedance over the entire FET. The source electrode pad 10 connected to the source electrode 18 via the wiring 17 is disposed as the outermost electrode of the FET electrode array. The via hole 13 formed immediately below is a large-diameter via hole and has a role of reducing ground inductance. If a large via hole is formed using the source electrode pad 10 as the outermost electrode of the FET electrode array, the source inductance can be reduced along the farthest path that may oscillate, and at the same time, the outer end becomes a short end. Unnecessary radio waves are not emitted and the characteristics can be stabilized.

  As described above, in the semiconductor device according to the present invention, via holes are simultaneously formed in the optimum size in both the source electrode and the source electrode pad. The via hole formed in the source electrode has the effect of uniformly reducing the heat dissipation and source inductance in the transistor operating region of each FET element, and the via hole formed in the source electrode pad is stable due to a significant reduction in the source inductor of the entire FET To do. As a result, a high-performance semiconductor device with high output and good frequency characteristics can be provided.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied without departing from the scope of the invention at the stage of implementation. For example, although the FET has been discussed, this concept is effective even in a normal bipolar transistor.

It is the figure which looked at the semiconductor device in one Example of this invention from the top. It is sectional drawing of the semiconductor device in one Example of this invention. It is the figure which looked at the high output semiconductor device in one Example of this invention from the top.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Source electrode pad 11 ... Drain electrode 12 ... Gate electrode pad 13, 14 ... Via hole 15 ... Operation | movement area 16 ... Gate electrode 17 ... Source wiring 18 ... Source electrode 21 ... 1st conductor layer 22 ... 2nd conductor layer 23 ... Semi-insulating GaAs substrate 24 ... n-type GaAs operating layer 25 ... Insulating region 30 ... Drain electrode pad 31 ... Drain wiring

Claims (2)

  A gate electrode formed so as to form a Schottky junction on an operation layer on the compound semiconductor substrate, and a source electrode and a drain formed so as to be in ohmic contact with the operation layer on the compound semiconductor substrate on both sides of the gate electrode An electrode, an electrode pad connected to each of these electrodes via wiring formed on the surface of the compound semiconductor substrate, a first conductor layer formed on the back surface of the compound semiconductor substrate, and the source electrode A first via hole formed in the compound semiconductor substrate so as to reach the first conductor layer, and the source electrode is connected to the first conductor layer through the first via hole. The second conductor layer provided in this manner and the first semiconductor layer on the compound semiconductor substrate just below the electrode pad connected to the source electrode A second via hole formed in this manner, and a second conductor layer provided so as to connect the electrode pad to the first conductor layer via the third via hole. Semiconductor device.   A plurality of sets of the source electrode, the gate electrode, and the drain electrode are arranged on the operation layer on the compound semiconductor substrate, and the electrode pads connected to the source electrode are arranged on the outer periphery of the electrode arrangement, and 2. The semiconductor device according to claim 1, wherein the operation layer is not provided below the electrode pad.

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