JP5114839B2 - Field effect transistor - Google Patents

Description

  The present invention relates to a field effect transistor, and more particularly to a field effect transistor (FET) suitable for high power operation.

  In high-frequency and high-power FETs, it is necessary to increase the gate width in order to increase the output, and a structure in which the gate, source, and drain electrodes are arranged in a comb shape, that is, a unit field effect transistor composed of these electrodes In general, a structure in which a plurality of them are arranged in parallel is adopted. FIG. 6 shows this comb-shaped electrode structure, and is a plan view showing the essential part of the configuration in a transparent manner. In the figure, a plurality of gate electrodes 502 arranged at a predetermined interval are arranged on an active region 501 formed in advance on a semiconductor wafer, and a source electrode 503 and a drain electrode 504 are alternately arranged between the plurality of gate electrodes 502. Is arranged. Each gate electrode 502 is connected to a gate lead electrode 506 by a bus line 505, and similarly, a source electrode 503 and a drain electrode 504 are gathered and connected to lead electrodes 507 and 508, respectively.

  In general, a field effect transistor (FET) has a relationship between the heat generated by the drain current and the heat dissipated from the front and back surfaces of the transistor when a voltage is applied to the drain and gate electrodes and a drain current flows through the active region. The surface heat distribution is determined. For example, in an FET in which the active region 501 is uniformly arranged with respect to the gate electrode 502 arranged in a comb shape as shown in FIG. 6, the vicinity of the center of the active region becomes high temperature. FIG. 7 shows a profile of this temperature distribution, showing the temperature distribution in the direction along the line aa ′ in FIG. 6, that is, in the direction parallel to the gate electrode 502. This shows that the vicinity of the center of the gate electrode 502 is at a high temperature.

  When such a temperature distribution occurs, there is a problem that breakdown (burnout) and electromigration are likely to be accelerated in the high temperature portion, that is, in the vicinity of the center of the active region, as compared with other relatively low temperature portions. In addition, since the electrical characteristics are also distributed corresponding to the temperature distribution, there are problems that the high frequency characteristics are deteriorated due to the non-uniform operation, and breakdown (burnout) is likely to occur.

  As a technique for solving this problem, Patent Document 1 discloses a structure in which active areas are divided and arranged. FIG. 8 shows this structure, and is a plan view showing the essential part of the structure. In FIG. 8, the electrode arrangement has the same comb-shaped electrode structure as in FIG. 6, and a plurality of gate electrodes 702 arranged at a predetermined interval are arranged, and a source electrode 703 and a drain electrode 704 are arranged between the plurality of gate electrodes 702. Are alternately arranged. Each gate electrode 702 is connected to a gate lead electrode 706 by a bus line 705. Similarly, the source electrode 703 and the drain electrode 704 are collected and connected to lead electrodes 707 and 708, respectively. With respect to such a comb-shaped electrode structure, active regions 701 a and 701 b are divided and formed across a strip-shaped non-conductive region 709 located at the center of the gate electrode 702.

Since the drain current does not flow in the non-conductive region 709 in the center of the gate electrode, that is, there is no heat generation in this region, the temperature distribution along the line aa ′ parallel to the gate electrode 702 is The peak temperature at the center of the electrode 702 is lowered and the distribution is flat. According to Patent Document 1, as described above, the active region is divided and formed across the strip-shaped non-conductive region parallel to the direction in which the transistors are juxtaposed, and the peak temperature at the center of the gate electrode is lowered, thereby It is said that burnout and electromigration associated with existence can be suppressed.
JP-A-5-129604

  However, in this conventional technique, that is, a method of providing a band-shaped non-conductive region as shown in FIG. 8, the unit field effect transistor in the central portion and the end portion of the plurality of unit field effect transistors arranged in parallel are arranged. There is a problem that a temperature difference generated between the unit field effect transistors cannot be reduced. FIG. 10 shows a temperature distribution in the direction parallel to the gate electrode 702 along the lines aa ′, bb ′, and cc ′ when the comb electrode structure shown in FIG. 8 is applied to a field effect transistor using a nitride semiconductor, for example. FIG. The distribution is such that the temperature is high in the central unit field effect transistor (aa ′) and the temperature is low in the unit field effect transistor (cc ′) at the end.

  When the temperature distribution is generated between the different unit field effect transistors in this way, the operation state is different for each unit field effect transistor, and the high frequency characteristics are deteriorated or broken down (burnout) due to the nonuniform operation. ) Is likely to occur.

The field effect transistor (FET) of the present invention includes a plurality of gate electrodes arranged in parallel in a region on a substrate,
An active region having conductivity provided in the one region;
A non-conductive region provided in a central portion in the extending direction of the gate electrode of the active region,
The ratio of the non-conductive region in the extending direction of the gate electrode to the gate electrode is larger in the central portion than in the end portion in the arrangement direction of the gate electrodes.

  The field effect transistor according to the present invention includes a plurality of unit field effect transistors each including a base electrode, a source electrode, and a drain electrode. Further, a part near the center of each unit field effect transistor is a non-conductive region. Since no drain current flows in this non-conductive region, no heat is generated. For this reason, by disposing the non-conductive region largely in a portion where the temperature tends to be high in the field effect transistor having a comb-shaped electrode structure, the peak temperature of the temperature distribution can be lowered and the distribution can be made flat. As a result, an effect of suppressing destruction (burnout) and electromigration that occur locally in the high-temperature part can be obtained.

  In the field effect transistor according to the present invention, the ratio of the non-conductive region in the extending direction of the gate electrode to each gate electrode is larger in the central portion than in the end portion in the arrangement direction of the gate electrodes. That is, for the plurality of unit field effect transistors arranged side by side, the central unit field effect transistor, which tends to become higher in temperature, has a larger non-conductive region and suppresses heat generation, thereby suppressing a rise in temperature. The non-conductive region, which is a non-heat generating region, is made smaller in the unit field effect transistor at the end portion that is hard to be formed. For this reason, the temperature distribution generated between different unit field effect transistors can be reduced, and the uniformity of transistor operation can be improved. As a result, it is possible to obtain an effect that it is possible to suppress high-frequency characteristic deterioration and destruction (burnout) due to non-uniform operation.

  Furthermore, in the field effect transistor according to the present invention, the active region may be provided continuously around the non-conductive region. That is, the length of the non-conductive region provided in one or several unit field effect transistors at both ends is reduced as a result of reducing the non-conductive region in the unit field effect transistors at the end of the plurality of unit field effect transistors arranged in parallel. The thickness is 0 (zero), that is, a structure in which a non-conductive region is not provided for one or several field effect transistors at both ends can be employed. Thereby, the gate width of the field effect transistor can be increased and the RF output can be increased without deteriorating the uniformity of the transistor operation described above. Alternatively, it is possible to reduce the area occupied by the field effect transistor having the gate width for obtaining the necessary RF output.

  According to the present invention, the uniformity of operation is improved by reducing the temperature distribution between different unit field effect transistors in the direction parallel to the gate electrode, and a field effect transistor (FET) excellent in high frequency characteristics and reliability is obtained. Can be provided.

Next, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a plan view illustrating a field effect transistor (FET) according to a first embodiment of the present invention in a perspective view for explaining a planar configuration of an electrode and an active layer portion. FIG. 2 is a plan view of the FET of FIG. It is bb 'sectional drawing.

  As shown in FIGS. 1 and 2, the field effect transistor according to the present embodiment has a plurality of gate electrodes 102 arranged in parallel in one region on the substrate, and conductivity provided in the one region. The active region 101 includes a non-conductive region 109 provided at the center of the active region 101 in the extending direction of the gate electrode 102.

  Specifically, as shown in FIG. 1, the electrode arrangement is preferably a comb electrode structure. That is, in the active region 101, as described above, a plurality of gate electrodes 102 arranged at a predetermined interval are arranged, and source electrodes 103 and drain electrodes 104 are alternately arranged between the plurality of gate electrodes 102. . Each gate electrode 102 is connected to a gate lead electrode 106 by a bus wiring 105, and similarly, the source electrode 103 and the drain electrode 104 are collected and connected to lead electrodes 107 and 108, respectively.

  Further, in the present embodiment, for example, the gate electrode 102 is configured such that the ratio of the non-conductive region 109 in the extending direction of the gate electrode to the gate electrode 102 is larger in the central portion than the end portion in the arrangement direction of the gate electrodes 102 It is made to become small gradually from the center part to the edge part in the arrangement direction of the electrodes 102. In FIG. 1, for example, a non-conductive region 109 is provided in the vicinity of the center of the active region 101 so as to be elliptical, and among the plurality of unit field effect transistors arranged in parallel, the central unit field effect transistor is parallel to the gate electrode 102. The length of the non-conductive region 109 in any direction is increased.

  The non-conductive region 109 near the center of the active region 101 can be easily formed by a manufacturing technique conventionally used for element isolation, such as selective ion implantation or mesa isolation.

  An elliptical non-conductive region 109 provided in the vicinity of the center of the active region 101 corresponds to a region where the temperature is high in a conventional field effect transistor without the non-conductive region 109. That is, by providing the non-conductive region 109 in the region that becomes high temperature in the conventional field effect transistor, heat generation from near the center of the active region 101 is suppressed, so that the peak temperature is reduced and a flat temperature distribution is obtained. become.

  FIG. 3 shows a direction parallel to the gate electrode 102 along the lines aa ′, bb ′, and cc ′ when the comb electrode structure shown in FIGS. 1 and 2 is applied to a field effect transistor using a nitride semiconductor, for example. It is the figure which showed the temperature distribution profile.

  By providing the inactive region 109 in the vicinity of the center of the gate electrode, a flat temperature distribution is obtained in which the peak temperature is reduced in the direction parallel to the gate electrode 102. Further, as a result of increasing the length of the non-conductive region 109 in the direction parallel to the gate electrode 102 in the central unit field effect transistor among a large number of unit field effect transistors arranged in parallel, FIG. The temperature difference between different unit field effect transistors is smaller than the profile shown in FIG.

  Thus, by using the structure of the present invention, the difference in temperature distribution in the direction parallel to the gate electrode and the difference in temperature distribution between different unit field effect transistors can be reduced, and the uniformity of transistor operation can be improved. it can. As a result, the field effect transistor shown in the present embodiment is less susceptible to breakdown (burnout) than the conventional field effect transistor, and thus operates stably even when the operating voltage is increased by 30%, for example. The RF saturation output could be increased by 1 dB.

(Second embodiment)
In the second embodiment of the present invention, the active region is continuously provided around the non-conductive region, so that the unit field effect at the end of the active region with respect to the plurality of unit field effect transistors arranged in parallel is provided. As a result of making the non-conductive region smaller as the transistor, the length of the non-conductive region provided in one or several unit field effect transistors at both ends is 0 (zero), that is, one or several field effect transistors at both ends In this case, the non-conductive region is not provided.

  FIG. 4 is a plan view showing the field effect transistor (FET) of the second embodiment in a transparent manner for explaining the planar configuration of the electrode and the active layer portion.

  As shown in FIG. 4, the electrode arrangement is preferably a comb electrode structure as described in the first embodiment. That is, in the active region 301, a plurality of gate electrodes 302 arranged at a predetermined interval are arranged, and a source electrode 303 and a drain electrode 304 are alternately arranged between the plurality of gate electrodes 302. Each gate electrode 302 is connected to a gate lead electrode 306 by a bus wiring 305, and similarly, a source electrode 303 and a drain electrode 304 are collected and connected to lead electrodes 307 and 308, respectively.

  In the present embodiment, as in the first embodiment, the ratio of the non-conductive region 309 in the gate electrode extending direction to the gate electrode 302 is more central than the end in the arrangement direction of the gate electrodes 302. For example, it gradually decreases from the center to the end in the arrangement direction of the gate electrodes 302. In FIG. 4, for example, a non-conductive region 309 is provided in the vicinity of the center of the active region 301 so as to be elliptical, and among the plurality of unit field effect transistors arranged in parallel, the central unit field effect transistor is parallel to the gate electrode 302. The length of the non-conductive region 309 in the direction is increased.

  Furthermore, in this embodiment, the active region 301 is continuously provided around the non-conductive region 309, and specifically, the non-conductive region 309 does not overlap the unit field effect transistor at each end. It is like that.

  Similar to the first embodiment, the non-conductive region 309 near the center of the active region 301 can be easily formed by a manufacturing technique conventionally used for element isolation, such as selective ion implantation or mesa isolation.

  In this embodiment, as in the first embodiment, as a result of providing the elliptical inactive region 309, the temperature distribution between the direction parallel to the gate electrode and between different unit field effect transistors is reduced, and the transistor operation is reduced. Uniformity can be improved.

  On the other hand, in the present embodiment, the non-conductive region 309 is prevented from overlapping the unit field effect transistors located at both ends of the plurality of unit field effect transistors arranged in parallel as compared with the first embodiment. Is different. Thereby, the non-active region 309 is smaller than that in the first embodiment, and a portion that effectively functions as a transistor, that is, a so-called gate width can be made larger than that in the first embodiment. As a result, although the temperature of the entire transistor rises due to an increase in the active region that is a heat generation region (however, the temperature distribution is flat), the RF output can be improved due to the increase in the gate width. Alternatively, it is possible to reduce the area occupied by the field effect transistor having the gate width for obtaining the necessary RF output.

  In this embodiment, as an aspect in which the active region is continuously provided around the non-conductive region, the unit field-effect transistors that prevent the non-conductive region 309 from overlapping each other are provided one at each end. However, the present invention is not limited to this, and the non-conductive region may not overlap the several unit field effect transistors at both ends.

(Third embodiment)
In the first embodiment and the second embodiment, an aspect in which the gate electrode is gradually reduced from the central portion to the end in the arrangement direction of the gate electrodes, for example, the shape of the non-conductive region provided near the center of the active region is an ellipse. As long as the proportion of the non-conductive region in the extending direction of the gate electrode with respect to each gate electrode is larger in the central portion than in the end portion in the arrangement direction of the gate electrodes. However, the present invention is not limited to this.

  Therefore, in the present embodiment, a mode will be described in which the inactive area is not divided into one elliptical area but is divided into a plurality of areas.

FIG. 5 is a plan view illustrating a field effect transistor (FET) according to a third embodiment of the present invention, which is seen through in order to explain a planar configuration of an electrode and an active layer portion.
As shown in FIG. 5, the electrode arrangement is preferably a comb electrode structure as described in the first and second embodiments. That is, in the active region 401, a plurality of gate electrodes 402 arranged at a predetermined interval are arranged, and source electrodes 403 and drain electrodes 404 are alternately arranged between the plurality of gate electrodes 402. Each gate electrode 402 is connected to a gate lead electrode 406 by a bus wiring 405, and similarly, a source electrode 403 and a drain electrode 404 are collected and connected to lead electrodes 407 and 408, respectively.

  In the present embodiment, the ratio of the non-conductive region 409 in the extending direction of the gate electrode to each gate electrode 402 is larger in the central portion than in the end portion in the arrangement direction of the gate electrodes 402. Are constituted by rectangular non-conductive regions 409a, 409b, 409c divided into three. Specifically, as shown in FIG. 5, the non-conductive regions 409a, 409b, and 409c are arranged in parallel in the extending direction of the gate electrode 402, and the central non-conductive region 409a overlaps all the unit field effect transistors. As described above, the adjacent non-conductive regions 409b and 409c are formed so as not to overlap the two unit field effect transistors at both ends of the juxtaposed field effect transistors.

  Thus, even if the shape and number of non-conductive regions are changed, the ratio of the non-conductive region 409 in the gate electrode extending direction to each gate electrode 402 is more central than the end in the arrangement direction of the gate electrodes 402. As in the first and second embodiments, the difference in temperature distribution in the direction parallel to the gate electrode and the difference in temperature distribution between different unit field effect transistors are reduced, and the transistor operation is uniform. The effect that it can improve property is acquired.

  In the embodiment described above, the shape of the non-conductive region is not limited to these, and among the many unit field effect transistors arranged in parallel, the central unit field effect transistor has a direction parallel to the gate electrode. If the non-conductive region is arranged so that the length of the non-conductive region becomes longer, the effect of the present invention can be obtained. As shapes other than the said embodiment, a rhombus, a polygon, etc. are mentioned, for example.

  As described above, the first effect in these embodiments is that the peak temperature of the field distribution of the field effect transistor having the comb-shaped electrode structure can be lowered and the distribution can be made flat. Thus, the effect of suppressing the breakdown (burnout) and electromigration that occur in the substrate can be obtained.

  The second effect is that, in a field effect transistor having a comb-shaped electrode structure, the temperature distribution generated between different unit field effect transistors can be reduced, and the uniformity of transistor operation can be improved. The effect that the accompanying high frequency characteristic deterioration and destruction (burnout) can be suppressed is acquired.

  The third effect is that the gate width of the field effect transistor can be increased and the RF output can be increased without impairing the first and second effects, or a gate width field effect transistor that obtains the necessary RF output. The area occupied by can be reduced.

  Note that examples of utilizing the field effect transistor according to the present invention include a semiconductor device using a nitride-based semiconductor material, such as a microwave transistor constituting a wireless communication system such as a mobile phone, satellite communication, and WLAN.

It is a top view seeing through the field effect transistor (FET) of a first embodiment of the present invention. It is bb 'sectional drawing of FET of FIG. It is a figure which shows the temperature distribution profile along the aa ', bb', and cc 'line | wire of FIG. It is a top view seeing through the field effect transistor of a second embodiment of the present invention. It is a top view seeing through the field effect transistor of a third embodiment of the present invention. It is a top view which sees through and shows the common field effect transistor of a prior art example. It is a figure which shows the temperature distribution profile along the aa 'line of FIG. It is a top view which sees through and shows the other field effect transistor of a prior art example. It is a figure which shows the temperature distribution profile along the aa 'line of FIG. It is a figure which shows the temperature distribution profile along the aa ', bb', and cc 'line | wire of FIG.

Explanation of symbols

101, 301, 401, 501, 701 Active region 102, 302, 402, 502, 702 Gate electrode 103, 303, 403, 503, 703 Source electrode 104, 304, 404, 504, 704 Drain electrode 105, 305, 405, 505, 705 Bus wiring 106, 306, 406, 506, 706 Gate extraction electrodes 107, 307, 407, 507, 707 Source extraction electrodes 108, 308, 408, 508, 708 Drain extraction electrodes 309, 409, 509, 709 Region 409a, 409b, 409c Non-conductive region

Claims (2)

A plurality of gate electrodes arranged in parallel in a region on the substrate;
An active region having a conductivity by the al located to one region are impurity-doped,
It said active area is provided et al is in the extending direction central portion of the gate electrode of, and a non-conductive region where an impurity is not doped,
The proportion of the non-conductive region in the extending direction of the gate electrode to each gate electrode, rather large in the central portion than the end in the arrangement direction of the gate electrode,
The field effect transistor , wherein the active region is provided continuously around the non-conductive region . The field effect transistor according to claim 1.
The field effect transistor according to claim 1, wherein a ratio of the non-conductive region in the extending direction of the gate electrode to each gate electrode gradually decreases from a central portion to an end portion in the arrangement direction of the gate electrodes.

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