WO2018133057A1 - 晶圆级芯片的封装方法及封装体 - Google Patents

晶圆级芯片的封装方法及封装体 Download PDF

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Publication number
WO2018133057A1
WO2018133057A1 PCT/CN2017/072039 CN2017072039W WO2018133057A1 WO 2018133057 A1 WO2018133057 A1 WO 2018133057A1 CN 2017072039 W CN2017072039 W CN 2017072039W WO 2018133057 A1 WO2018133057 A1 WO 2018133057A1
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layer
wafer
level chip
wafer level
packaging
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PCT/CN2017/072039
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English (en)
French (fr)
Inventor
吴宝全
龙卫
柳玉平
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深圳市汇顶科技股份有限公司
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Priority to CN201780000046.5A priority Critical patent/CN107078068B/zh
Priority to PCT/CN2017/072039 priority patent/WO2018133057A1/zh
Publication of WO2018133057A1 publication Critical patent/WO2018133057A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor

Definitions

  • the technical solution disclosed in the present application relates to the field of semiconductor technology, and in particular, to a package method and a package of a wafer level chip.
  • the technical solution disclosed in the present application can at least solve the following technical problem: how to balance the requirements of package volume and package strength.
  • One or more embodiments of the present application disclose a method of packaging a wafer level chip, including: bonding a wafer to a support carrier; reducing a thickness of the wafer; Etching the dicing groove on the back surface; adhering an insulating layer on the back surface of the wafer and the dicing groove; adding a metal layer on the bottom of the insulating layer and the dicing groove; removing the scribe groove a metal layer on the bottom; a protective layer adhered on the remaining metal layer and the bottom of the dicing groove; the protective layer is processed to obtain an adhesive hole, and the bottom of the adhesive hole is exposed The metal layer; a solder ball is adhered to the metal layer at the bottom of the adhesion hole.
  • the attaching the wafer to the support carrier includes: adhering a cover layer on a wiring surface of the wafer; and adhering the support carrier to the cover layer.
  • the cover layer is plastic coated or coated or sprayed using a wafer level; the cover layer is baked and destressed.
  • adhering the support carrier to the cover layer includes: applying an organic colloid-based adhesive on the support carrier and/or the cover layer; The carrier is attached to the cover layer.
  • the reducing the thickness of the wafer is specifically: grinding the back surface of the wafer.
  • the method before the insulating layer and the bottom of the dicing groove are added with a metal layer, the method further includes: processing the bottom of the dicing groove to remove the bottom portion thereof The insulating layer and the silicon dioxide layer of the wafer expose the pad or the redistribution layer.
  • adding a metal layer to the insulating layer and the bottom of the dicing groove is specifically: depositing or plating a metal layer on the bottom of the insulating layer and the dicing groove.
  • the method before the dicing trench is etched on the back side of the wafer, the method further includes: performing photolithographic development and dry etching on the back side of the wafer.
  • the scribe groove is a trapezoidal groove.
  • the processing the bottom of the dicing groove includes performing photolithographic development and dry etching.
  • the heat shrinkage property of the insulating layer is consistent with the heat shrinkage property of the protective layer.
  • adhering the solder ball on the metal layer at the bottom of the adhesion hole includes: embedding the solder ball into the solder using a solder printing process or a solder ball falling ball process Bonding the metal layer at the bottom of the hole; soldering the solder ball to the adhesion using a 260 ° C high temperature reflow soldering process The metal layer at the bottom of the hole.
  • the method further includes: cutting a region where the dicing groove is located; and removing the support carrier to obtain a package of a single wafer-level chip.
  • One or more embodiments of the present application disclose a package of a wafer level chip, the package of the wafer level chip comprising: a single crystal silicon layer, a silicon dioxide layer, a pad, a cap layer, and an insulating layer a metal layer, a protective layer, and at least one solder ball; wherein the silicon dioxide layer is adjacent to the single crystal silicon layer; the pad is disposed in the silicon dioxide layer and is in contact with the metal layer The cover layer is adhered to the silicon dioxide layer; the insulating layer is adhered to the single crystal silicon layer; the metal layer is adhered to the insulating layer and the silicon dioxide Outside the layer; the protective layer is adhered to the outside of the metal layer; the at least one solder ball is welded to the metal layer through the protective layer.
  • the single crystal silicon layer has a thickness of 100 to 300 ⁇ m; and the cover layer has a thickness of 10 to 40 ⁇ m.
  • the material of the cover layer has a high dielectric constant.
  • the cover layer is made of silicon dioxide or aluminum oxide or ceramic zirconia.
  • the package of the wafer level chip further includes a redistribution layer; the redistribution layer is disposed in the cover layer and is in contact with the pad and the metal layer .
  • the package method of the wafer level chip is compatible with a part of a single TSV (Through Silicon Vias) packaging method, and thus can be applied under the existing process equipment conditions.
  • the packaging method of any of the above wafer level chips can save the substrate packaging step and the plastic package relative to the substrate packaging step and the molding step based on the single TSV packaging method.
  • the steps increase the production cost while increasing the efficiency of the generation.
  • the package of the wafer level chip obtained by the packaging method of any of the above wafer level chips increases the mechanical structural strength and balances the package volume and the package strength under the premise that the thickness is maintained at 0.2 to 0.25 mm. Can fully meet the needs of wafer level chip applications.
  • FIG. 1 is a schematic diagram of a step 101 of a method for packaging a wafer level chip according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of a method 102 of a method for packaging a wafer level chip according to an embodiment of the present application
  • FIG. 3 is a schematic diagram of a step 103 of a method of packaging a wafer level chip according to an embodiment of the present application
  • FIG. 4 is a schematic diagram of a method 104 of a method for packaging a wafer level chip according to an embodiment of the present application
  • FIG. 5 is a schematic diagram of a method 105 of a method for packaging a wafer level chip according to an embodiment of the present application
  • FIG. 6 is a schematic diagram of a method 106 of a method for packaging a wafer level chip according to an embodiment of the present application
  • FIG. 7 is a schematic diagram of a step 107 of a method of packaging a wafer level chip according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a method 108 of a method of packaging a wafer level chip according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a step 109 of a method of packaging a wafer level chip according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a step 110 of a method of packaging a wafer level chip according to an embodiment of the present application
  • FIG. 11 is a schematic diagram showing a step 111 of a method of packaging a wafer level chip according to an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a step 112 of a method of packaging a wafer level chip according to an embodiment of the present application
  • FIG. 13 is a schematic diagram of a package of a wafer level chip in another embodiment of the present application.
  • FIG. 14 is a schematic diagram of a package of a wafer level chip in still another embodiment of the present application.
  • the method for packaging a wafer level chip in the embodiment of the present application includes three stages, wherein the first stage mainly completes the bonding of the wafer and the support carrier and reduces the thickness of the wafer.
  • FIG. 1 is a schematic diagram of a method 101 of a method for packaging a wafer level chip according to an embodiment of the present application.
  • Step 101 Adhering the cover layer 201 on the wiring surface 1 of the wafer.
  • the wafer includes a single crystal silicon layer 101 and a silicon dioxide layer 102, and the cover layer 201 is adhered to the silicon dioxide layer 102.
  • the adhering the cover layer 201 on the wiring surface of the wafer includes: using a wafer level molding or coating or spraying the cover layer 201; baking the cover layer 201 And stress relief treatment.
  • the cover layer 201 is made of a material having a high dielectric constant and a high mechanical structural strength, such as silica, alumina, and ceramic zirconia.
  • the particle size of the material of the cover layer 201 can be a single digit micron. Since the cover layer 201 is made of a material having a high dielectric constant and a high mechanical structural strength, the cover layer 201 can also be satisfactorily satisfied while enhancing the mechanical structural strength of the package of the wafer level chip. The performance requirements of the wafer level chip itself.
  • FIG. 2 is a schematic diagram of a method 102 of a method for packaging a wafer level chip according to an embodiment of the present application.
  • Step 102 Adhering the support carrier 202 to the cover layer 201.
  • adhering the support carrier 202 to the cover layer 201 includes: applying an organic colloid-based adhesive on the support carrier 202 and/or the cover layer 201;
  • the support carrier 202 is attached to the cover layer 202.
  • the support carrier 202 may be a glass piece or a silicon plate or a metal plate.
  • FIG. 3 it is a schematic diagram of a step 103 of a method for packaging a wafer level chip according to an embodiment of the present application.
  • Step 103 Grinding the back side of the wafer.
  • the wafer has an overall thickness of typically 700 ⁇ m prior to grinding. After the back surface of the wafer is polished (that is, the single crystal silicon layer 101 is polished), the thickness of the single crystal silicon layer 101 is reduced to 100 to 300 ⁇ m. Grinding the back side of the wafer facilitates reducing the overall thickness of the wafer.
  • the second stage of the packaging method of the wafer level chip in the embodiment of the present application mainly completes the fabrication of the conductive line with the metal layer and the solder ball as the main structure, so that the pad or the rewiring layer of the wafer level chip can be externally connected. Circuit.
  • FIG. 4 it is a schematic diagram of a method 104 of a method for packaging a wafer level chip according to an embodiment of the present application.
  • Step 104 etching the scribe groove 3 on the back side of the wafer.
  • the method before etching the dicing trench 3 on the back side of the wafer, the method further comprises: performing photolithographic development and dry etching on the back side of the wafer.
  • the scriber groove 3 is a trapezoidal groove.
  • the area of the dicing trench may be predetermined, which region should include the pad 103 or a partial region where the redistribution layer 104 is located.
  • Step 104 mainly etches the single crystal silicon layer 101.
  • FIG. 5 it is a schematic diagram of a method 105 of a method for packaging a wafer level chip according to an embodiment of the present application.
  • Step 105 Adhering an insulating layer 203 on the back surface of the wafer and the scribe groove 3.
  • the material of the insulating layer 203 may be an inorganic insulating material or an organic insulating material, and the thickness thereof is controlled to be 10 to 100 ⁇ m.
  • FIG. 6 a schematic diagram of a method 106 of a method for packaging a wafer level chip according to an embodiment of the present application is shown.
  • Step 106 processing the bottom of the dicing groove 3 to remove the insulating layer 203 at the bottom and the silicon dioxide layer 102 of the wafer, so that the pad 103 or the redistribution layer 104 is exposed.
  • the processing of the bottom of the dicing groove 3 includes photolithographic development and dry etching, or directly cutting the bottom of the dicing groove 3.
  • the portion may be removed
  • the pad 103 or the redistribution layer 104 is divided.
  • a portion of the cover layer 201 may also be removed during processing of the bottom of the scribe groove 3.
  • FIG. 7 a schematic diagram of a method 107 of a method for packaging a wafer level chip according to an embodiment of the present application is shown.
  • Step 107 Add a metal layer 204 to the insulating layer 203 and the bottom of the scribe groove 3.
  • Adding the metal layer 204 to the bottom of the insulating layer 203 and the dicing trench 3 is specifically: depositing or plating a metal layer 204 on the bottom of the insulating layer 203 and the dicing trench 3.
  • the metal layer 204 should be in operative contact with the pad 103 or the redistribution layer 104.
  • FIG. 8 it is a schematic diagram of a method 108 of a package method of a wafer level chip according to an embodiment of the present application.
  • Step 108 Removing the metal layer 204 at the bottom of the scribe groove 3.
  • Removing the metal layer 204 at the bottom of the dicing trench 3 not only defines the metal trace of the metal layer 204, but also forms an interrupted region of the metal layer 204, such that the protective layer 205 in step 109
  • the interrupted region of the metal layer 204 can be covered to protect the metal layer 204 from insulation.
  • Processing techniques for removing the metal layer 204 at the bottom of the dicing trench 3 include, but are not limited to, photolithography and etching.
  • FIG. 9 is a schematic diagram of a step 109 of a method of packaging a wafer level chip according to an embodiment of the present application.
  • Step 109 Adhering a protective layer 205 on the remaining metal layer 204 and at the bottom of the dicing groove 3.
  • the protective layer 205 uses materials that are consistent with the materials used for the insulating layer 203.
  • the protective layer 205 uses materials that are inconsistent with the materials used for the insulating layer 203, but which have consistent heat shrink properties. According to this, it is possible to prevent the package of the wafer level chip from being cracked due to uneven shrinkage.
  • FIG. 10 it is a schematic diagram of a step 110 of a method of packaging a wafer level chip according to an embodiment of the present application.
  • Step 110 The protective layer 205 is processed to obtain an adhesion hole 4, and the bottom of the adhesion hole 4 is the exposed metal layer 204.
  • the processing of the protective layer 205 to obtain the adhesion holes 4 includes, but is not limited to, photolithography and development.
  • FIG. 11 it is a schematic diagram of a step 111 of a method of packaging a wafer level chip according to an embodiment of the present application.
  • Step 111 A solder ball 206 is adhered to the metal layer 204 at the bottom of the adhesion hole 4.
  • adhering the solder balls 206 on the metal layer 204 at the bottom of the adhesion holes 4 includes embedding the solder balls 206 into a solder using a solder printing process or a solder ball drop process.
  • the metal layer 204 of the bottom of the adhesion hole 4; the metal ball 204 of the solder ball 206 and the bottom of the adhesion hole 4 is soldered using a 260 ° C high temperature reflow soldering process.
  • the solder ball 206 forms a circuit with the metal layer 204 and the pad 103 or the redistribution layer 104 as an electrical interconnection point between the package of the wafer level chip and the outside.
  • the third stage of the packaging method of the wafer level chip in the embodiment of the present application mainly completes the single chip cutting of the wafer level chip package.
  • FIG. 12 it is a schematic diagram of a method 112 of a method for packaging a wafer level chip according to an embodiment of the present application.
  • Step 112 cutting the region where the scribe groove 3 is located; removing the support carrier 202 to obtain a package of a single wafer-level chip.
  • the protective layer 205 and the cover layer 201 are required to be penetrated, and the support carrier 202 is partially cut.
  • the above wafer level chip packaging method is compatible with a part of the single TSV package method [BGA (Ball Grid Array) or LGA (Land) in the pad of the single TSV package method Grid Array (contact array package) layout, so it can be applied under the process equipment conditions of the single TSV package method.
  • the packaging method of any of the above wafer level chips can save the production cost increased by the substrate packaging step and the molding step, and the generation is improved. s efficiency.
  • the package of the wafer level chip obtained by the packaging method of any of the above wafer level chips increases the mechanical structural strength and balances the package volume and the package strength under the premise that the thickness is maintained at 0.2 to 0.25 mm. Can fully meet the needs of wafer level chip applications.
  • FIG. 13 a schematic diagram of a package of a wafer level chip in another embodiment of the present application.
  • the package of the wafer level chip is obtained by a packaging method of any one of the above wafer level chips, which may be, but is not limited to, a package of a fingerprint identification chip.
  • the package of the wafer level chip includes: a single crystal silicon layer 10, a silicon dioxide layer 20, a pad 30, a cap layer 40, an insulating layer 50, a metal layer 60, a protective layer 70, and at least one solder ball 80;
  • the silicon dioxide layer 20 is adjacent to the single crystal silicon layer 10; the pad 30 is disposed in the silicon dioxide layer 20, in contact with the metal layer 60; the cover layer 40 is The silicon dioxide layer 20 is adhered together; the insulating layer 50 is adhered to the single crystal silicon layer 10; the metal layer 60 is adhered to the insulating layer 50 and the silicon dioxide layer 20
  • the protective layer 70 is adhered to the outside of the metal layer 60; the at least one solder ball 80 is soldered to the metal layer 60 through the protective layer 70.
  • the single crystal silicon layer 10 has a thickness of 100 to 300 ⁇ m; and the cover layer 40 has a thickness of 10 to 40 ⁇ m.
  • the material of the cover layer 40 has a high dielectric constant and a high mechanical structural strength.
  • the cover layer 40 is made of silicon dioxide or aluminum oxide or ceramic zirconia.
  • the solder ball 80 forms an electrical circuit with the metal layer 60 and the pad 30 as an electrical interconnection point between the package of the wafer level chip and the outside.
  • the cover layer 40 is made of a material having a high dielectric constant and a high mechanical strength. Therefore, the cover layer 40 can well meet the performance requirements of the wafer level chip itself while enhancing the mechanical structural strength of the package of the wafer level chip.
  • FIG. 14 a schematic diagram of a package of a wafer level chip in still another embodiment of the present application.
  • the package of the wafer level chip is obtained by a packaging method of any one of the above wafer level chips, which may be, but is not limited to, a package of a fingerprint identification chip.
  • the package of the wafer level chip includes: a single crystal silicon layer 100, a silicon dioxide layer 200, a pad 300, a redistribution layer 400, a cover layer 500, an insulating layer 600, a metal layer 700, a protective layer 800, and at least one a solder ball 900; wherein the silicon dioxide layer 200 is adjacent to the single crystal silicon layer 100; the pad 300 is disposed in the silicon dioxide layer 20 to form an electrical circuit with the redistribution layer 400; The redistribution layer 400 is disposed in the capping layer 500 and is in contact with the pad 300 and the metal layer 700; the capping layer 500 is adhered to the silicon dioxide layer 200; An insulating layer 600 is adhered to the single crystal silicon layer 100; the metal layer 700 is adhered to the outside of the insulating layer 600 and the silicon dioxide layer 200; the protective layer 800 is adhered to the metal Outside the layer 700; the at least one solder ball 900 is soldered to the metal layer 700 through the protective layer 800.
  • the solder ball 900 forms an electrical circuit with the metal layer 700 and the redistribution layer 400 as an electrical interconnection point of the package of the wafer level chip.
  • the pad 300 in the above embodiment forms an electrical circuit with the metal layer 700 through the redistribution layer 400.
  • the contact of the redistribution layer 400 with the metal layer 700 is more reliable, while also facilitating protection of the pad 300 during the packaging process of the wafer level chip.

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Abstract

一种晶圆级芯片的封装方法及封装体，涉及半导体技术领域。所述方法包括：将晶圆片与支撑载体（202）贴合；减小所述晶圆片的厚度；在所述晶圆片的背面蚀刻划片槽（3）；在所述晶圆片的背面以及所述划片槽（2）内粘附绝缘层（203）；在所述绝缘层（203）以及所述划片槽（2）的底部添加金属层（204）；去除所述划片槽（3）的底部的所述金属层（204）；在剩余的所述金属层（204）上以及所述划片槽（3）的底部粘附保护层（205）；对所述保护层（205）进行加工得到粘附孔（4），所述粘附孔（4）的底部为外露的所述金属层（204）；在所述粘附孔（4）的底部的所述金属层（204）上粘附锡球（206）。能够获得相对较薄的晶圆级芯片的封装体，增加了其机械结构强度，平衡了封装体积和封装强度的要求。

Description

晶圆级芯片的封装方法及封装体 技术领域
本申请公开的技术方案涉及半导体技术领域，尤其涉及晶圆级芯片的封装方法及封装体。
背景技术
当前，业界对指纹芯片的封装既要求体积尽可能的轻薄，同时又要保证封装后的强度。而这两个要求的实现在一定程度上是互相矛盾的。
发明内容
本申请公开的技术方案至少能够解决以下技术问题：如何平衡封装体积和封装强度的要求。
本申请的一个或者多个实施例公开了一种晶圆级芯片的封装方法，包括：将晶圆片与支撑载体贴合；减小所述晶圆片的厚度；在所述晶圆片的背面蚀刻划片槽；在所述晶圆片的背面以及所述划片槽内粘附绝缘层；在所述绝缘层以及所述划片槽的底部添加金属层；去除所述划片槽的底部的所述金属层；在剩余的所述金属层上以及所述划片槽的底部粘附保护层；对所述保护层进行加工得到粘附孔，所述粘附孔的底部为外露的所述金属层；在所述粘附孔的底部的所述金属层上粘附锡球。
在本申请的一个或者多个实施例中，所述将晶圆片与支撑载体贴合包括：在晶圆片的线路面粘附覆盖层；在所述覆盖层粘附支撑载体。
在本申请的一个或者多个实施例中，使用晶圆级塑封或者涂布或者喷涂所述覆盖层；对所述覆盖层进行烘烤和去应力处理。
在本申请的一个或者多个实施例中，在所述覆盖层粘附支撑载体包括：在所述支撑载体和/或所述覆盖层上涂布有机胶体类的粘合剂；将所述支撑载体与所述覆盖层贴合。
在本申请的一个或者多个实施例中，所述减小所述晶圆片的厚度具体为：研磨所述晶圆片的背面。
在本申请的一个或者多个实施例中，在所述绝缘层以及所述划片槽的底部增加金属层之前，所述方法还包括：对所述划片槽的底部进行加工，去除其底部的所述绝缘层和所述晶圆片的二氧化硅层，使得焊盘或者重布线层露出。
在本申请的一个或者多个实施例中，在所述绝缘层以及所述划片槽的底部增加金属层具体为：在所述绝缘层以及所述划片槽的底部沉积或者电镀金属层。
在本申请的一个或者多个实施例中，在所述晶圆片的背面蚀刻划片槽之前，所述方法还包括：对所述晶圆片的背面进行光刻显影和干法蚀刻。
在本申请的一个或者多个实施例中，所述划片槽为梯形槽。
在本申请的一个或者多个实施例中，所述对所述划片槽的底部进行加工包括进行光刻显影和干法蚀刻。
在本申请的一个或者多个实施例中，所述绝缘层的热收缩性能与所述保护层的热收缩性能一致。
在本申请的一个或者多个实施例中，在所述粘附孔的底部的所述金属层上粘附锡球包括：使用焊锡印刷工艺或锡球落球工艺将所述锡球嵌入至所述粘附孔的底部的所述金属层；使用260℃高温回流焊接工艺焊接所述锡球与所述粘附 孔的底部的所述金属层。
在本申请的一个或者多个实施例中，所述方法还包括：对所述划片槽所在的区域进行切割；去除所述支撑载体后得到单颗的晶圆级芯片的封装体。
本申请的一个或者多个实施例公开了一种晶圆级芯片的封装体，所述晶圆级芯片的封装体包括：单晶硅层、二氧化硅层、焊盘、覆盖层、绝缘层、金属层、保护层以及至少一个锡球；其中，所述二氧化硅层与所述单晶硅层相邻；所述焊盘设置在所述二氧化硅层内，与所述金属层接触；所述覆盖层与所述二氧化硅层粘附在一起；所述绝缘层与所述单晶硅层粘附在一起；所述金属层粘附在所述绝缘层与所述二氧化硅层外；所述保护层粘附在所述金属层外；所述至少一个锡球穿过所述保护层与所述金属层焊接在一起。
在本申请的一个或者多个实施例中，所述单晶硅层的厚度为100～300μm；所述覆盖层的厚度为10～40μm。
在本申请的一个或者多个实施例中，所述覆盖层的材质具有高介电常数。
在本申请的一个或者多个实施例中，所述覆盖层的材质为二氧化硅或三氧化二铝或陶瓷类氧化锆。
在本申请的一个或者多个实施例中，所述晶圆级芯片的封装体还包括重布线层；所述重布线层设置在所述覆盖层内，且与所述焊盘以及金属层接触。
与现有技术相比，本申请公开的技术方案主要有以下有益效果：
在本申请的实施例中，所述晶圆级芯片的封装方法兼容了部分的单体TSV(Through Silicon Vias，硅通孔)封装方法，因而在现有的工艺设备条件下就可以进行应用。相对于在单体TSV封装方法的基础上增加基板封装步骤和塑封步骤而言，上述任意一种晶圆级芯片的封装方法能够节省因基板封装步骤和塑封 步骤增加的生产成本，同时提高了生成的效率。通过上述任意一种晶圆级芯片的封装方法获得的晶圆级芯片的封装体在厚度维持在0.2～0.25mm的前提下，增加了其机械结构强度，平衡了封装体积和封装强度的要求，能够充分满足晶圆级芯片应用领域的需求。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。
图1为本申请一实施例中晶圆级芯片的封装方法步骤101的示意图；
图2为本申请一实施例中晶圆级芯片的封装方法步骤102的示意图；
图3为本申请一实施例中晶圆级芯片的封装方法步骤103的示意图；
图4为本申请一实施例中晶圆级芯片的封装方法步骤104的示意图；
图5为本申请一实施例中晶圆级芯片的封装方法步骤105的示意图；
图6为本申请一实施例中晶圆级芯片的封装方法步骤106的示意图；
图7为本申请一实施例中晶圆级芯片的封装方法步骤107的示意图；
图8为本申请一实施例中晶圆级芯片的封装方法步骤108的示意图；
图9为本申请一实施例中晶圆级芯片的封装方法步骤109的示意图；
图10为本申请一实施例中晶圆级芯片的封装方法步骤110的示意图；
图11为本申请一实施例中晶圆级芯片的封装方法步骤111的示意图；
图12为本申请一实施例中晶圆级芯片的封装方法步骤112的示意图；
图13为本申请的另一实施例中晶圆级芯片的封装体的示意图；
图14为本申请的又一实施例中晶圆级芯片的封装体的示意图；
101-单晶硅层、102-二氧化硅层、103-焊盘、104-重布线层、201-覆盖层、202-支撑载体、203-绝缘层、204-金属层、205-保护层、206-锡球、1-线路面、2-晶圆片的背面、3-划片槽、4-粘附孔、5-切割槽、10-单晶硅层、20-二氧化硅层、30-焊盘、40-覆盖层、50-绝缘层、60-金属层、70-保护层、80-锡球、100-单晶硅层、200-二氧化硅层、300-焊盘、400-重布线层、500-覆盖层、600-绝缘层、700-金属层、800-保护层、900-锡球。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
本申请实施例中的晶圆级芯片的封装方法包括三个阶段，其中第一阶段主要完成晶圆片与支持载体的贴合以及减小晶圆片的厚度。
本申请实施例中的晶圆级芯片的封装方法的第一阶段包括但不限于以下内容：
参考图1，为本申请一实施例中晶圆级芯片的封装方法步骤101的示意图。
步骤101：在晶圆片的线路面1粘附覆盖层201。
其中，所述晶圆片包括单晶硅层101和二氧化硅层102，所述覆盖层201粘附在所述二氧化硅层102上。
在本申请的一些实施例中，所述在晶圆片的线路面粘附覆盖层201包括：使用晶圆级塑封或者涂布或者喷涂所述覆盖层201；对所述覆盖层201进行烘烤和去应力处理。
所述覆盖层201使用具有高介电常数和高机械结构强度的材质制成，例如二氧化硅、三氧化二铝以及陶瓷类氧化锆等。制作所述覆盖层201的材质的颗粒度可以为个位数微米的等级。由于所述覆盖层201使用具有高介电常数和高机械结构强度的材质制成，所以所述覆盖层201在增强晶圆级芯片的封装体的机械结构强度的同时，也能很好的满足晶圆级芯片本身的性能需求。
参考图2，为本申请一实施例中晶圆级芯片的封装方法步骤102的示意图。
步骤102：在所述覆盖层201粘附支撑载体202。
在本申请的一些实施例中，在所述覆盖层201粘附支撑载体202包括：在所述支撑载体202和/或所述覆盖层201上涂布有机胶体类的粘合剂；将所述支撑载体202与所述覆盖层202贴合。其中，所述支撑载体202可以是玻璃片或硅片或金属板。
参考图3，为本申请一实施例中晶圆级芯片的封装方法步骤103的示意图。
步骤103：研磨所述晶圆片的背面。
所述晶圆片在研磨之前，整体厚度一般达到700μm。研磨所述晶圆片的背面(也即研磨所述单晶硅层101)后，所述单晶硅层101的厚度减小至100～300μm。研磨所述晶圆片的背面有利于减小晶圆片的整体厚度。
本申请实施例中的晶圆级芯片的封装方法的第二阶段主要完成以金属层、锡球为主要结构的导电线路的制作，使得晶圆级芯片的焊盘或者重布线层能够接入外部电路。
本申请实施例中的晶圆级芯片的封装方法的第二阶段包括但不限于以下内容：
参考图4，为本申请一实施例中晶圆级芯片的封装方法步骤104的示意图。
步骤104：在所述晶圆片的背面蚀刻划片槽3。
在本申请的一些实施例中，在所述晶圆片的背面蚀刻划片槽3之前，所述方法还包括：对所述晶圆片的背面进行光刻显影和干法蚀刻。
在本申请的一些实施例中，所述划片槽3为梯形槽。在所述晶圆片的背面蚀刻划片槽3时，可以预先给定划片槽的区域，该区域应当包含焊盘103或者重布线层104所在的部分区域。步骤104主要蚀刻所述单晶硅层101。
参考图5，为本申请一实施例中晶圆级芯片的封装方法步骤105的示意图。
步骤105：在所述晶圆片的背面以及所述划片槽3内粘附绝缘层203。
在本申请的一些实施例中，所述绝缘层203的材质可以是无机类绝缘材料或有机类绝缘材料，其厚度控制在10～100μm。
参考图6，为本申请一实施例中晶圆级芯片的封装方法步骤106的示意图。
步骤106：对所述划片槽3的底部进行加工，去除其底部的所述绝缘层203和所述晶圆片的二氧化硅层102，使得焊盘103或者重布线层104露出。
在本申请的一些实施例中，所述对所述划片槽3的底部进行加工包括进行光刻显影和干法蚀刻，或者直接对所述划片槽3的底部进行切割。为了使得所述焊盘103或者所述重布线层104的露出部分不超过必要的范围，可以去除部 分的所述焊盘103或者所述重布线层104。对所述划片槽3的底部进行加工的过程中还可以去除部分的所述覆盖层201。
参考图7，为本申请一实施例中晶圆级芯片的封装方法步骤107的示意图。
步骤107：在所述绝缘层203以及所述划片槽3的底部添加金属层204。
在所述绝缘层203以及所述划片槽3的底部增加金属层204具体为：在所述绝缘层203以及所述划片槽3的底部沉积或者电镀金属层204。
所述金属层204应当与所述焊盘103或者所述重布线层104有效接触。
参考图8，为本申请一实施例中晶圆级芯片的封装方法步骤108的示意图。
步骤108：去除所述划片槽3底部的所述金属层204。
去除所述划片槽3底部的所述金属层204，不仅可以定义出所述金属层204的金属线路，而且可以形成所述金属层204的中断区域，使得步骤109中的所述保护层205能够覆盖到所述金属层204的中断区域，对所述金属层204起到绝缘保护的作用。去除所述划片槽3底部的所述金属层204的加工工艺包括但不限于光刻和蚀刻。
参考图9，为本申请一实施例中晶圆级芯片的封装方法步骤109的示意图。
步骤109：在剩余的所述金属层204上以及所述划片槽3的底部粘附保护层205。
在本申请的一些实施例中，保护层205使用的材料与绝缘层203使用的材料一致。
在另一些实施例中，保护层205使用的材料与绝缘层203使用的材料不一致，但二者的热收缩性能一致。据此，能够防止晶圆级芯片的封装体因收缩不均而开裂。
参考图10，为本申请一实施例中晶圆级芯片的封装方法步骤110的示意图。
步骤110：对所述保护层205进行加工得到粘附孔4，所述粘附孔4的底部为外露的所述金属层204。对所述保护层205进行加工得到粘附孔4的加工工艺包括但不限于光刻和显影。
参考图11，为本申请一实施例中晶圆级芯片的封装方法步骤111的示意图。
步骤111：在所述粘附孔4的底部的所述金属层204上粘附锡球206。
在本申请的一些实施例中，在所述粘附孔4的底部的所述金属层204上粘附锡球206包括：使用焊锡印刷工艺或锡球落球工艺将所述锡球206嵌入至所述粘附孔4的底部的所述金属层204；使用260℃高温回流焊接工艺焊接所述锡球206与所述粘附孔4的底部的所述金属层204。所述锡球206与所述金属层204以及所述焊盘103或者所述重布线层104形成电路，作为晶圆级芯片的封装体与外界的电气互联点。
本申请实施例中的晶圆级芯片的封装方法的第三阶段主要完成晶圆级芯片封装体的单体切割。
本申请实施例中的晶圆级芯片的封装方法的第三阶段包括但不限于以下内容：
参考图12，为本申请一实施例中晶圆级芯片的封装方法步骤112的示意图。
步骤112：对所述划片槽3所在的区域进行切割；去除所述支撑载体202后得到单颗的晶圆级芯片的封装体。对所述划片槽3所在的区域进行切割时，需贯穿所述保护层205和所述覆盖层201，并部分切割所述支撑载体202。
上述晶圆级芯片的封装方法，兼容了部分的单体TSV封装方法【在单体TSV封装方法中的焊盘采用BGA(Ball Grid Array，焊球阵列封装)或者LGA(Land  grid Array，触点阵列封装)布局】，因而在单体TSV封装方法的工艺设备条件下就可以进行应用。相对于在单体TSV封装方法的基础上增加基板封装步骤和塑封步骤而言，上述任意一种晶圆级芯片的封装方法能够节省因基板封装步骤和塑封步骤增加的生产成本，同时提高了生成的效率。通过上述任意一种晶圆级芯片的封装方法获得的晶圆级芯片的封装体在厚度维持在0.2～0.25mm的前提下，增加了其机械结构强度，平衡了封装体积和封装强度的要求，能够充分满足晶圆级芯片应用领域的需求。
参考图13，为本申请的另一实施例中晶圆级芯片的封装体的示意图。所述晶圆级芯片的封装体通过上述任意一种晶圆级芯片的封装方法获得，其可以但不限于是指纹识别芯片的封装体。
所述晶圆级芯片的封装体包括：单晶硅层10、二氧化硅层20、焊盘30、覆盖层40、绝缘层50、金属层60、保护层70以及至少一个锡球80；其中，所述二氧化硅层20与所述单晶硅层10相邻；所述焊盘30设置在所述二氧化硅层20内，与所述金属层60接触；所述覆盖层40与所述二氧化硅层20粘附在一起；所述绝缘层50与所述单晶硅层10粘附在一起；所述金属层60粘附在所述绝缘层50与所述二氧化硅层20外；所述保护层70粘附在所述金属层60外；所述至少一个锡球80穿过所述保护层70与所述金属层60焊接在一起。
在本申请的一些实施例中，所述单晶硅层10的厚度为100～300μm；所述覆盖层40的厚度为10～40μm。所述覆盖层40的材质具有高介电常数和高机械结构强度。所述覆盖层40的材质为二氧化硅或三氧化二铝或陶瓷类氧化锆。
所述锡球80与所述金属层60以及所述焊盘30形成电路，作为所述晶圆级芯片的封装体与外界的电气互联点。
上述实施例中，所述覆盖层40采用高介电常数和高机械结构强度的材质制 成，因而所述覆盖层40在增强晶圆级芯片的封装体的机械结构强度的同时，也能很好的满足晶圆级芯片本身的性能需求。
参考图14，为本申请的又一实施例中晶圆级芯片的封装体的示意图。所述晶圆级芯片的封装体通过上述任意一种晶圆级芯片的封装方法获得，其可以但不限于是指纹识别芯片的封装体。
所述晶圆级芯片的封装体包括：单晶硅层100、二氧化硅层200、焊盘300、重布线层400、覆盖层500、绝缘层600、金属层700、保护层800以及至少一个锡球900；其中，所述二氧化硅层200与所述单晶硅层100相邻；所述焊盘300设置在所述二氧化硅层20内，与所述重布线层400形成电路；所述重布线层400设置在所述覆盖层500内，且与所述焊盘300以及所述金属层700接触；所述覆盖层500与所述二氧化硅层200粘附在一起；所述绝缘层600与所述单晶硅层100粘附在一起；所述金属层700粘附在所述绝缘层600与所述二氧化硅层200外；所述保护层800粘附在所述金属层700外；所述至少一个锡球900穿过所述保护层800与所述金属层700焊接在一起。
所述锡球900与所述金属层700以及所述重布线层400形成电路，作为所述晶圆级芯片的封装体的电气互联点。
上述实施例中的所述焊盘300通过所述重布线层400与所述金属层700形成电路。所述重布线层400与所述金属层700的接触更为可靠，同时也有利于在晶圆级芯片的封装过程中保护所述焊盘300。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制。尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解，其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换。而这些修改或者替换，并不使相应技术方案的 本质脱离本申请各实施例技术方案的精神和范围。

Claims (18)

  1. 一种晶圆级芯片的封装方法，其特征在于，包括：
    将晶圆片与支撑载体贴合；
    减小所述晶圆片的厚度；
    在所述晶圆片的背面蚀刻划片槽；
    在所述晶圆片的背面以及所述划片槽内粘附绝缘层；
    在所述绝缘层以及所述划片槽的底部添加金属层；
    去除所述划片槽的底部的所述金属层；
    在剩余的所述金属层上以及所述划片槽的底部粘附保护层；
    对所述保护层进行加工得到粘附孔，所述粘附孔的底部为外露的所述金属层；
    在所述粘附孔的底部的所述金属层上粘附锡球。
  2. 根据权利要求1所述晶圆级芯片的封装方法，其特征在于，所述将晶圆片与支撑载体贴合包括：
    在晶圆片的线路面粘附覆盖层；
    在所述覆盖层粘附支撑载体。
  3. 根据权利要求2所述晶圆级芯片的封装方法，其特征在于，在晶圆片的线路面粘附覆盖层包括：
    使用晶圆级塑封或者涂布或者喷涂所述覆盖层；
    对所述覆盖层进行烘烤和去应力处理。
  4. 根据权利要求2所述晶圆级芯片的封装方法，其特征在于，在所述覆盖层粘附支撑载体包括：
    在所述支撑载体和/或所述覆盖层上涂布有机胶体类的粘合剂；
    将所述支撑载体与所述覆盖层贴合。
  5. 根据权利要求1所述晶圆级芯片的封装方法，其特征在于，所述减小所述晶圆片的厚度具体为：研磨所述晶圆片的背面。
  6. 根据权利要求1所述晶圆级芯片的封装方法，其特征在于，在所述绝缘层以及所述划片槽的底部增加金属层之前，所述方法还包括：对所述划片槽的底部进行加工，去除其底部的所述绝缘层和所述晶圆片的二氧化硅层，使得焊盘或者重布线层露出。
  7. 根据权利要求1所述晶圆级芯片的封装方法，其特征在于，在所述绝缘层以及所述划片槽的底部增加金属层具体为：在所述绝缘层以及所述划片槽的底部沉积或者电镀金属层。
  8. 根据权利要求1所述晶圆级芯片的封装方法，其特征在于，在所述晶圆片的背面蚀刻划片槽之前，所述方法还包括：
    对所述晶圆片的背面进行光刻显影和干法蚀刻。
  9. 根据权利要求1所述晶圆级芯片的封装方法，其特征在于，所述划片槽为梯形槽。
  10. 根据权利要求1所述晶圆级芯片的封装方法，其特征在于，所述对所述划片槽的底部进行加工包括进行光刻显影和干法蚀刻。
  11. 根据权利要求1所述晶圆级芯片的封装方法，其特征在于，所述绝缘层的热收缩性能与所述保护层的热收缩性能一致。
  12. 根据权利要求1所述晶圆级芯片的封装方法，其特征在于，在所述粘附孔的底部的所述金属层上粘附锡球包括：
    使用焊锡印刷工艺或锡球落球工艺将所述锡球嵌入至所述粘附孔的底部的所述金属层；
    使用260℃高温回流焊接工艺焊接所述锡球与所述粘附孔的底部的所述金属层。
  13. 根据权利要求1-12任意一项所述晶圆级芯片的封装方法，其特征在于，所述方法还包括：
    对所述划片槽所在的区域进行切割；
    去除所述支撑载体后得到单颗的晶圆级芯片的封装体。
  14. 一种晶圆级芯片的封装体，其特征在于，包括：
    单晶硅层(10)、二氧化硅层(20)、焊盘(30)、覆盖层(40)、绝缘层(50)、金属层(60)、保护层(70)以及至少一个锡球(80)；
    其中，所述二氧化硅层(20)与所述单晶硅层(10)相邻；
    所述焊盘(30)设置在所述二氧化硅层(20)内，与所述金属层(60)接触；
    所述覆盖层(40)与所述二氧化硅层(20)粘附在一起；
    所述绝缘层(50)与所述单晶硅层(10)粘附在一起；
    所述金属层(60)粘附在所述绝缘层(50)与所述二氧化硅层(20)外；
    所述保护层(70)粘附在所述金属层(60)外；
    所述至少一个锡球(80)穿过所述保护层(70)与所述金属层(60)焊接在一起。
  15. 根据权利要求14所述晶圆级芯片的封装体，其特征在于：
    所述单晶硅层(10)的厚度为100～300μm；
    所述覆盖层(40)的厚度为10～40μm。
  16. 根据权利要求14所述晶圆级芯片的封装体，其特征在于，所述覆盖层(40)的材质具有高介电常数。
  17. 根据权利要求16所述晶圆级芯片的封装体，其特征在于，所述覆盖层(40)的材质为二氧化硅或三氧化二铝或陶瓷类氧化锆。
  18. 根据权利要求14-17任意一项所述晶圆级芯片的封装体，其特征在于，还包括重布线层(400)；
    所述重布线层(400)设置在所述覆盖层(500)内，且与所述焊盘(300)以及金属层(700)接触。
PCT/CN2017/072039 2017-01-22 2017-01-22 晶圆级芯片的封装方法及封装体 WO2018133057A1 (zh)

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