TW201714258A - 半導體封裝結構 - Google Patents

半導體封裝結構 Download PDF

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TW201714258A
TW201714258A TW105128082A TW105128082A TW201714258A TW 201714258 A TW201714258 A TW 201714258A TW 105128082 A TW105128082 A TW 105128082A TW 105128082 A TW105128082 A TW 105128082A TW 201714258 A TW201714258 A TW 201714258A
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semiconductor package
package structure
molding compound
semiconductor
layer
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TWI626717B (zh
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劉乃瑋
林子閎
彭逸軒
蕭景文
黃偉哲
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聯發科技股份有限公司
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Abstract

本發明提供了一種半導體封裝結構。該結構包括：一模塑料，具有一切割道區域。一半導體晶粒，設置在該模塑料中並且被該切割道區域圍繞。該半導體晶粒具有一第一表面與一相對於該第一表面的第二表面。該結構進一步包括：一重分佈層(RDL)結構，設置在該半導體晶粒的該第一表面上並且覆蓋該模塑料。該RDL結構具有對齊該切割道區域的開口。

Description

半導體封裝結構
本發明涉及半導體封裝結構，特別係涉及一種具有高可靠性的扇出晶圓級封裝結構。
近年來，由於電子產品已變得具有越來越多的功能並且尺寸已按比例縮小，因此希望半導體設備的製造商將更多的設備形成於單塊半導體晶圓上，從而可以使得含有這些設備的電子產品更加緊湊。作為對此種希望的響應，已經發展了PoP(Package-on-Package，封裝上封裝)技術和WLP(Wafer Level Package，晶圓級封裝)技術。PoP技術使得兩個或者更多的封裝能夠使用他們之間的標准界面來安裝(即堆疊)在彼此的頂上，使得能夠在他們之間路由信號。此種方式允許電子產品具有更高的元件密度，電子產品諸如為行動電話、個人數位助理(Personal Digital Assistant，PDA)及數位相機。另外，在WLP中，晶粒可以與封裝具有相同的尺寸。
但是，在利用PoP及/或WLP技術來製造半導體封裝的同時，可能出現一些問題。例如，在執行切割(dicing)製程以產生單個的封裝結構時，在封裝結構中形成的含有聚合物的互連層(有時也被稱為RDL(Redistribution Layer，重分佈層))可能會污染機械鋸(mechanical saw)，並且該切割也 可能導致互連層破裂。因此，增加了製造成本。另外，在半導體封裝的製造中，用於晶粒附著的結合力不足以及模塑料與模塑料中的通孔之間的附著力較差會降低半導體封裝結構的可靠性、良品率及生產量。
如此，期望一種創新的半導體封裝結構。
因此，本發明之主要目的即在於提供一種半導體封裝結構，可以提高其可靠性。
根據本發明至少一個實施例的一種半導體封裝結構，包括：一模塑料，具有一切割道區域；一半導體晶粒，設置在該模塑料中並且該切割道區域圍繞該半導體晶粒，其中，該半導體晶粒具有一第一表面與和一相對於該第一表面的第二表面；以及一重分佈層結構，設置在該半導體晶粒的該第一表面上並且覆蓋該模塑料，其中該重分佈層結構具有對齊該切割道區域的第一開口。
上述半導體封裝結構，其重分佈層結構具有對齊切割道區域的開口，因此該開口可以防止重分佈層結構在執行切割製程時破裂，從而提高半導體封裝結構的可靠性。
10、20、30、40、50、60、70‧‧‧半導體封裝結構
122、203‧‧‧導電結構
100‧‧‧模塑料
200‧‧‧半導體晶粒
102、202‧‧‧RDL結構
L‧‧‧切割道區域
W‧‧‧寬度
200a‧‧‧第一表面
200b‧‧‧第二表面
201‧‧‧接墊
205‧‧‧鈍化層
102b‧‧‧導電線路
102a‧‧‧金屬間介電層
103、203‧‧‧開口
203a‧‧‧底部
120‧‧‧被動元件
104‧‧‧通孔
106、206‧‧‧黏合層
206a、306a‧‧‧板狀部
206b、306b‧‧‧壁部
110‧‧‧第一保護層
108‧‧‧第二保護層
105‧‧‧焊料
H‧‧‧高度
130‧‧‧阻擋層
通過閱讀接下來的詳細描述以及參考所附的圖示的例子可以更加完整地理解本發明，其中：第1圖至第7圖分別為根據本發明不同實施例的半導體封裝結構的橫截面示意圖。
以下描述為實現本發明的較佳預期模式。該描述僅係出於說明本發明一般原理的目的，而不應視為限制。本發明的範圍可參考所附的申請專利範圍來確定。
參考特定實施例及確定的圖式來描述本發明，但是本發明不限制於此，並且本發明僅由申請專利範圍來限定。描述的圖式僅是示意圖而非限制。在圖式中，出於說明目的而誇大了某些元件的尺寸，並且某些元件的尺寸並非按比例繪制。圖示中的尺寸及相對尺寸不對應本發明實踐中的真實尺寸。
第1圖為根據本發明一些實施例的一半導體封裝結構10的橫截面示意圖。在一些實施例中，該半導體封裝結構10為一晶圓級半導體封裝結構，例如一扇出晶圓級半導體封裝結構。在一實施例中，該扇出晶圓級半導體封裝結構可以包括：一系統單晶片(System On Chip，SOC)封裝結構和一垂直地堆疊於其上的動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)封裝結構(未示出)。
參考第1圖，該半導體封裝結構安裝於一基底(未示出)上，諸如一印刷電路板(Printed Circuit Board，PCB)，該基底可以由聚丙烯(polypropylene，PP)形成。
在一些實施例中，該基底作為封裝基底並且可以為單層或者多層結構。導電墊及電性耦接至導電墊的導電線路(trace)一般係設置在基底的頂面或者基底中。在此情形中，導電線路可以用於半導體封裝結構10的輸入/輸出 (Input/output，I/O)連接。在一實施例中，半導體封裝結構10係直接安裝於導電線路上。
半導體封裝結構10通過一接合製程安裝於基底上。例如，半導體封裝結構10包括：複數導電結構122，係通過該接合製程安裝於基底上並電性耦接至基底。在一些實施例中，導電結構122包括：導電凸塊(諸如銅凸塊或者焊料凸塊)，導電柱或者導電膏(conductive paste)結構。
在本實施例中，半導體封裝結構10包括：一模塑料100，一半導體晶粒200(諸如一SOC晶粒)，以及一RDL結構102。該模塑料100中具有一切割道區域(dicing lane region)L。在一些實施例中，該模塑料100可以由環氧樹脂、樹脂、可塑聚合物或者類似物形成。該模塑料100可以在實質為液體時應用，然後通過化學反應固化，諸如在環氧樹脂或者樹脂中。在一些其他實施例中，模塑料100可以為紫外(ultraviolet，UV)或者熱固化的聚合物，作為能夠設置在半導體晶粒200周圍的凝膠或者可塑固體來應用該聚合物，接著通過UV或者熱固化製程固化該聚合物。模塑料100可以按照模型(未示出)來固化。
在一些實施例中，半導體晶粒200設置在模塑料100中並且切割道區域L圍繞該半導體晶粒200。該半導體晶粒200具有一第一表面200a與一相對於該第一表面200a的第二表面200b。該第一與第二表面200a、200b可以從該模塑料100中露出。另外，該半導體晶粒200可以包括：接墊201，係電性連接至半導體晶粒200中的電路(未示出)。在一些實 施例中，該半導體晶粒200(諸如SOC晶粒)可以包括：一邏輯晶粒，該邏輯晶粒包括：中央處理單元(Central Processing Unit，CPU)、圖形處理單元(Graphics Processing Unit，GPU)、DRAM控制器或者他們的任意組合。在一些實施例中，半導體晶粒200的接墊201接觸對應的導電結構203(例如導電凸塊、導電柱或者焊膏)，並且導電結構203設置在一鈍化層205中並且位於該第一表面200a上。
在一些實施例中，RDL結構102，也稱為扇出結構，係設置在半導體晶粒200的第一表面200a上(例如通過鈍化層205及導電結構203設置在第一表面200a上)並且覆蓋模塑料100。其中，RDL結構102通過導電結構203連接至半導體晶粒200。
在本實施例中，RDL結構102包括：一條或多條導電線路102b，設置在一金屬間介電(Inter-Metal Dielectric，IMD)層102a中。另外，RDL結構102的IMD層102a具有對齊切割道區域L的一開口103。在一些實施例中，IMD層102a由一有機材料形成，該有機材料包括：聚合物(polymer)基材料或者類似物。例如，IMD層102a可以由光敏材料形成，該光敏材料包括：乾膜光阻(dry film photoresist)或者貼膜(taping film)。在此情形中，通過包含曝光與顯影製程的微影製程來形成開口103。
在本實施例中，開口103穿透RDL結構102，使得開口103露出對應切割道區域L的模塑料100。在一些實施例中，開口103的寬度W大約在1μm(微米)~100μm之間。 此開口103防止RDL結構102在執行切割製程時破裂。另外，開口103也允許機械鋸在執行切割製程時免於接觸RDL結構102的側壁，從而防止來自RDL結構102的聚合物殘留的產生。如此，確保機械鋸不會被聚合物殘留污染。
在本實施例中，半導體封裝結構10進一步包括：一被動元件120，設置在RDL結構102上並且通過其中的導電線路102b電性耦接至該RDL結構102。另外，複數個導電結構122設置在RDL結構102上並且通過其中的導電線路102b電性耦接至RDL結構102。
在一些實施例中，模塑料100包括：一個或複數個通孔104，有時也被稱為穿過封裝的通孔(Through Package Vias，TPV)或者穿過插入層的通孔(Through Interposer Vias，TIV)。在一些實施例中，通孔104可以圍繞半導體晶粒200。另外，通孔104可以由銅形成。
在本實施例中，半導體封裝結構10進一步包括：一黏合層106，一第一保護層110，以及一第二保護層108。該黏合層106(有時也被稱為晶粒粘結膜(die-attach film))用於在半導體封裝結構10的製造期間，使半導體晶粒200附著至載體(未示出)上。在一些實施例中，模塑料100可以圍繞黏合層106。
第一保護層110(也時也被稱為背面膜(back side film，BSF))設置在半導體晶粒200的第二表面200b與模塑料100的上方，使得黏合層106設置在第一保護層110與半導體晶粒200之間。第一保護層110保護半導體晶粒200與模塑 料100免受損傷。第二保護層108設置在半導體晶粒200的第二表面200b與模塑料100的上方，並且位於第一保護層110與黏合層106之間。第二保護層108保護下方的黏合層106在通孔104的形成期間免受損傷。在一些實施例中，第一與第二保護層110、118可分別具有開口，以露出模塑料100中的通孔104。另外，可選的焊料105可以填充這些開口以接觸露出的通孔104，從而有助於用於PoP製造的接合製程。在一些實施例中，在模塑料100中可以不形成通孔。在此情形中，可以移除第二保護層108，使得第一保護層110直接接觸黏合層106。
根據前述實施例，由於RDL結構102具有由微影所定義的開口，以露出對應切割道區域L的模塑料100，因此沒有必要在使用機械鋸的切割製程之前，執行鐳射開槽製程。如此，可以降低製造成本並且可以簡化用於半導體封裝結構的製程。另外，當執行切割製程時，可以消除或者緩解來自含有聚合物(polymer)的RDL結構的聚合物殘留的產生，從而防止機械鋸被污染。另外，由於開口使得RDL結構產生不連續的表面，因此通過減少應力來緩解或者改善半導體封裝結構中的翹曲。
第2圖為根據本發明一些實施例的一半導體封裝結構20的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第1圖已描述了的元件的，出於簡潔而省略。在本實施例中，除了RDL結構202以外，半導體封裝結構20類似於第1圖示出的半導體封裝結構10。RDL結構202 包括：一IMD層102a與一導電線路102b，分別相同或者類似於第1圖所示的IMD層102a及導電線路102b。但是，通過微影在RDL結構202中形成的開口203具有位於RDL結構202中的底部203a。也就是說，開口203不穿透IMD層102a。在本實施例中，對應切割道區域L的開口203的寬度W大約在1μm~100μm之間。
在一些實施例中，可以在模塑料100中不形成通孔104。在此情形中，可以移除第二保護層108，使得第一保護層110直接接觸黏合層106。
根據前述實施例，由於沒有露出對應RDL結構的開口的模塑料，因此可以阻止在半導體封裝結構的製造中使用的化學蝕刻製程所導致的模塑料損失。
類似地，由於RDL結構具有由微影所定義的開口，因此沒有必要在使用機械鋸的切割製程之前，執行鐳射開槽製程。如此，可以降低製造成本並且可以簡化用於半導體封裝結構的製程。另外，可以消除或者緩解聚合物殘留，從而防止機械鋸被污染。由於開口也使得RDL結構產生了不連續的表面，因此通過減少應力可以緩解或者改善半導體封裝結構中的翹曲。
第3圖為根據本發明一些實施例的一半導體封裝結構30的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第1圖已描述了的元件的，出於簡潔而省略。在本實施例中，除了黏合層206以外，半導體封裝結構30類似於第1圖示出的半導體封裝結構10。在本實施例中，黏合 層206為U形。該U形的黏合層206設置在半導體晶粒的第二表面200a上，並且具有一板狀部(plate portion)206a及一壁部(wall portion)206b，其中該壁部206b位於該板狀部206a上並且位於該板狀部206a的邊緣，使得壁部206b覆蓋半導體晶粒200的部分側壁。在一些實施例中，在該板狀部206a上的壁部206b的高度H大約在1μm~20μm之間。也就是說，U形的黏合層206沿半導體晶粒200的側壁延伸的距離大約在1μm~20μm之間。
類似地，模塑料100也圍繞U形的黏合層206。第一保護層110設置在U形的黏合層206和模塑料100的上方。另外，第二保護層108設置在第一保護層110和U形的黏合層206之間。
在本實施例中，通過控制用於使半導體晶粒200通過黏合層(即黏合層206)附著至載體(未示出)的結合力的大小，來調整U形的黏合層206的壁部206b的高度H。也就是說，壁部206b的高度H正比於結合力的大小。
在一些實施例中，RDL結構102可以由RDL結構202(如第2圖所示)替換，以便於具有沒有穿透RDL結構的開口。
第4圖為根據本發明一些實施例的一半導體封裝結構40的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第1圖及第3圖已描述了的元件的，出於簡潔而省略。在本實施例中，半導體封裝結構40類似於第3圖示出的半導體封裝結構30。在本實施例中，在模塑料100中沒 有形成通孔。另外，相比於半導體封裝結構30，移除了位於第一保護層110與半導體晶粒200之間的第二保護層108，使得第一保護層110直接接觸U形的黏合層206並且延伸至完全覆蓋模塑料100的上表面。
在一些實施例中，RDL結構102可以由RDL結構202(如第2圖所示)替換，以便於具有沒有穿透RDL結構的開口。
第5圖為根據本發明一些實施例的一半導體封裝結構50的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第4圖已描述了的元件的，出於簡潔而省略。在本實施例中，除了U形的黏合層306之外，半導體封裝結構50類似於第4圖示出的半導體封裝結構40。在本實施例中，U形的黏合層206的板狀部306a上的壁部306b延伸至完全覆蓋模塑料100的上表面。也就是說，U形的黏合層206沒有被模塑料100圍繞。
在一些實施例中，RDL結構102可以由RDL結構202(如第2圖所示)替換，以便於具有沒有穿透RDL結構的開口。
根據前述的實施例，由於U形的黏合層的壁部部分地覆蓋半導體晶粒的側壁，因此可以消除或者緩解在黏合層的固化期間的晶粒偏移問題。另外，由於施加充足的用於晶粒附著的結合力，以形成U形的黏合層，因此可以降低在執行晶粒附著和接著的平面化之後的晶粒的總厚度變化(Total Thickness Variation，TTV)，如此提高半導體封裝結構的可靠 性、良品率及生產量。
類似地，由於RDL結構具有由微影所定義的開口，因此沒有必要在使用機械鋸的切割製程之前，執行鐳射開槽製程。如此，可以降低製造成本並且可以簡化半導體封裝結構的製程。另外，可以消除或者緩解聚合物殘留，從而防止機械鋸被污染。由於開口也使得RDL結構產生了不連續的表面，因此通過減少應力可以緩解或者改善半導體封裝結構中的翹曲。另外，由於沒有露出對應RDL結構的開口的模塑料，因此可以阻止在半導體封裝結構的製造中使用的化學蝕刻製程所導致的模塑料損失。
第6圖為根據本發明一些實施例的一半導體封裝結構60的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第1圖已描述了的元件的，出於簡潔而省略。在本實施例中，半導體封裝結構60類似於第1圖示出的半導體封裝結構10。在本實施例中，阻擋層(barrier layer)130設置在模塑料100和通孔104之間。阻擋層130提供模塑料100和通孔104之間的充分的黏著，從而阻止模塑料100和通孔104彼此脫層。另外，阻擋層130也阻止通孔104中的金屬原子擴散進模塑料100中。另外，阻擋層130進一步降低或者消除來自通孔104的金屬污跡(metal smear)，該金屬污跡是在執行用於形成通孔104的平面化製程時形成的，從而防止具有微小間距的通孔104之間的橋接。
在一些實施例中，該阻擋層130可以包括：氧化銅(例如CuO,Cu2O，或Cu2O3)。在一些實施例中，阻擋層130 可以包括：氧化鈦(例如TiO)或者氧化鋁(如Al2O3)。在一些實施例中，阻擋層130可以包括：氧化矽(如，SiO或者SiO2)，碳化矽(如SiC)，或者氮氧化矽(如SiOxNy)。在這些情形中，可以由化學氣相沈積(chemical vapor deposition，CVD)、物理氣相沈積(physical vapor deposition，PVD)、電漿沈積、旋轉塗佈、爐內氧化(furnace oxidation)或者其他合適的沈積方式來形成阻擋層130。
在一些實施例中，RDL結構102可以由RDL202(如第2圖所示)替換，以便於具有沒有穿透RDL結構的開口。
在一些實施例中，黏合層106可以由第3圖所示的U形的黏合層206替換，如第7圖所示。
根據前述實施例，由於阻擋層130形成在模塑料100和通孔104之間，因此可以增加半導體封裝結構的可靠性。
類似地，由於U形的黏合層的壁部部分地覆蓋半導體晶粒的側壁，因此可以消除或者緩解在固化黏合層的期間的晶粒偏移問題。另外，由於施加足夠的用於晶粒附著的結合力以形成U形的黏合層，因此可以降低在執行晶粒附著和接著的平面化後的晶粒的總厚度變化(TTV)。因此，可以增加半導體封裝結構的可靠性、良品率和生產量。
另外，由於RDL結構具有由微影所定義的開口，因此沒有必要在使用機械鋸的切割製程之前，執行鐳射開槽製程。如此，可以降低製造成本並且可以簡化用於半導體封裝結構的製程。另外，可以消除或者緩解聚合物殘留，從而防止機 械鋸被污染。由於開口使得RDL結構產生不連續的表面，因此通過減少應力可以緩解或者改善半導體封裝結構中的翹曲。另外，由於沒有露出對應RDL結構的開口的模塑料，因此可以阻止由在半導體封裝結構的製造中使用的化學蝕刻製程所導致的模塑料損失。
以上所述僅為本發明的較佳實施例而已，並不用以限制本發明，凡在本發明的精神和原則之內所作的任何修改、等同替換和改進等，均應包含在本發明的保護範圍之內。
10‧‧‧半導體封裝結構
122、203‧‧‧導電結構
100‧‧‧模塑料
200‧‧‧半導體晶粒
102‧‧‧RDL結構
L‧‧‧切割道區域
W‧‧‧寬度
200a‧‧‧第一表面
200b‧‧‧第二表面
201‧‧‧接墊
205‧‧‧鈍化層
102b‧‧‧導電線路
102a‧‧‧金屬間介電層
103‧‧‧開口
120‧‧‧被動元件
104‧‧‧通孔
106‧‧‧黏合層
110‧‧‧第一保護層
108‧‧‧第二保護層
105‧‧‧焊料

Claims (15)

  1. 一種半導體封裝結構，包括：一模塑料，具有一切割道區域；一半導體晶粒，設置在該模塑料中並且該切割道區域圍繞該半導體晶粒，其中，該半導體晶粒具有一第一表面與和一相對於該第一表面的第二表面；以及一重分佈層結構，設置在該半導體晶粒的該第一表面上並且覆蓋該模塑料，其中該重分佈層結構具有對齊該切割道區域的第一開口。
  2. 如申請專利範圍第1項所述的半導體封裝結構，其中，該第一開口穿透該重分佈層結構，使得通過該第一開口露出對應該切割道區域的該模塑料。
  3. 如申請專利範圍第1項所述的半導體封裝結構，其中，該第一開口具有一位於該重分佈層結構中的底部。
  4. 如申請專利範圍第1項所述的半導體封裝結構，其中，該第一開口的寬度介於1微米~100微米之間。
  5. 如申請專利範圍第1項所述的半導體封裝結構，其中，進一步包括：一黏合層，設置在該半導體晶粒的該第二表面上。
  6. 如申請專利範圍第5項所述的半導體封裝結構，其中，該黏合層為U形並且具有一板狀部及一壁部，該壁部位於該板狀部的邊緣並且該壁部覆蓋該半導體晶粒的部分側壁。
  7. 如申請專利範圍第6項所述的半導體封裝結構，其中，該壁部的高度介於1微米~20微米之間。
  8. 如申請專利範圍第6項所述的半導體封裝結構，其中，該模塑料圍繞該壁部，或者該壁部設置在該模塑料上。
  9. 如申請專利範圍第5項所述的半導體封裝結構，其中，進一步包括：一第一保護層，設置在該半導體晶粒的該第二表面及該模塑料的上方，並且該黏合層位於該第一保護層與該半導體晶粒之間。
  10. 如申請專利範圍第9項所述的半導體封裝結構，其中，進一步包括：通孔，穿過該模塑料並且電性耦接至該重分佈層結構；第二保護層，設置在該第一保護層與該黏合層之間，用於保護該黏合層。
  11. 如申請專利範圍第10項所述的半導體封裝結構，其中，該第一與第二保護層分別具有第二開口，以露出該通孔。
  12. 如申請專利範圍第1項所述的半導體封裝結構，其中，進一步包括：通孔，穿過該模塑料並且電性耦接至該重分佈層結構。
  13. 如申請專利範圍第12項所述的半導體封裝結構，其中，進一步包括：一阻擋層，設置在該模塑料與該通孔之間，用於阻止該模塑料和該通孔彼此脫層。
  14. 如申請專利範圍第13項所述的半導體封裝結構，其中，該阻擋層包括：氧化銅、氧化鈦、氧化鋁、氧化矽、碳化矽或者氮氧化矽。
  15. 如申請專利範圍第1項所述的半導體封裝結構，其中，該 重分佈層結構包括：一光敏材料。
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