CN102832199A - 一种用于铜互连的混合介质抗铜扩散阻挡层及其制造方法 - Google Patents

一种用于铜互连的混合介质抗铜扩散阻挡层及其制造方法 Download PDF

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CN102832199A
CN102832199A CN2012103629213A CN201210362921A CN102832199A CN 102832199 A CN102832199 A CN 102832199A CN 2012103629213 A CN2012103629213 A CN 2012103629213A CN 201210362921 A CN201210362921 A CN 201210362921A CN 102832199 A CN102832199 A CN 102832199A
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copper
layer
oxide
metal
diffusion barrier
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孙清清
房润辰
郑珊
张卫
王鹏飞
周鹏
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Fudan University
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Abstract

本发明属于集成电路制造互连领域，具体涉及一种用于铜互连的混合介质抗铜扩散阻挡层及其制造方法。本发明使用混合介质（氧化层/金属）来作为抗铜扩散阻挡层，首先，可以有效增强金属对铜的抗扩散能力，并有效防止扩散阻挡层被氧化而失效，延长扩散阻挡层的寿命。其次，可以降低互连电路的有效介电常数值，进而使得互连电路整体的RC延迟下降。再次，由于金属与铜具有良好的粘附性和接触，可以在金属表面直接电镀铜而不需要先淀积一层铜籽晶，工艺简单可行，有望在未来铜互连的抗扩散阻挡层的制造中得到应用。

Description

一种用于铜互连的混合介质抗铜扩散阻挡层及其制造方法
技术领域
本发明属于集成电路制造互连领域，具体涉及一种用于铜互连的混合介质（氧化层/金属）抗铜扩散阻挡层及其制造方法。
背景技术
铜互连技术是指在半导体集成电路互连层的制作中采用铜金属材料取代传统铝金属互连材料的新型半导体制造工艺技术。传统的铜互连结构如图1所示，包括在半导体基底10上形成的低介电常数介质层11，在低介电常数介质层11中形成有互连通孔，覆盖所述互连通孔的底壁和侧壁形成有抗铜扩散阻挡层12，在所述互连通孔内所述抗铜扩散阻挡层12之上形成有铜金属互连线13，在铜金属互连线13之上还形成有氮化硅薄膜作为刻蚀阻挡层以及同一层铜互连线的绝缘。.如上所述，在电镀铜金属之前，需先淀积一层抗铜扩散阻挡层以阻止铜扩散进入到介质当中，以防止漏电等一些列问题的发生。
由于半导体器件工艺技术节点越来越小，导致整个电路对时序的要求越来越高，迫切需要新技术来减小互连本身带来的RC（R指电阻，C指电容）延迟，从根本上来说即需要减小互连当中绝缘层的有效介电常数值。从90纳米到现在的22纳米工艺技术节点，为了减小互连电路的影响，已引入了超低介电常数介质（ULK）作为电路的绝缘层，然而要保持整个电路的介电常数在一个很低的水平却是很难的。
目前一般使用物理汽相沉积（PVD）工艺来淀积扩散阻挡层，生长好的扩散阻挡层的一致性和致密性比较差，当暴露在空气中或暴露在含氧气体中的时候，容易被氧化而逐渐失效，而且，PVD工艺淀积的扩散阻挡层在制备好之后需要进行热退火才能具有良好的接触，然后退火会给已经制作好的器件带来热损伤以及负面影响，同时，在扩散阻挡层生长好之后，仍然需要在表面先淀积一层铜籽晶才能进行金属铜的电镀，工艺过程复杂。
发明内容
本发明的目的在于提出一种新型的扩散阻挡层，在简化工艺过程的同时还可以增强扩散阻挡层的性能。
为达到本发明的上述目的，本发明提出了一种用于铜互连的抗铜扩散阻挡层，包括：
在半导体基底上形成的低介电常数介质层；
在所述低介电常数介质层中形成的互连通孔；
在所述互连通孔的侧壁以及所述低介电常数介质层之上形成的氧化层；
覆盖所述氧化层与所述互连通孔的底壁形成的金属层；
所述氧化层与所述金属层形成氧化层/金属混合介质抗铜扩散阻挡层。
同时，本发明还提出了上述用于铜互连的抗铜扩散阻挡层的制造方法，具体包括：
在提供的半导体基底表面淀积一层低介电常数介质层；
在所述低介电常数介质层之上旋涂光刻胶并光刻定义出互连通孔的位置；
刻蚀所述低介电常数介质层形成互连通孔；剥除光刻胶；
覆盖所形成的互连通孔的底壁、侧壁以及所述低介电常数介质层的表面生长一层薄的氧化层；
对所形成的氧化层进行回刻以去除在所述互连通孔底部的所述氧化层；
覆盖剩余的氧化层以及互连通孔的底壁淀积一金属层，所形成的金属层与氧化层构成氧化层/金属混合介质抗铜扩散阻挡层。
如上所述的用于铜互连的抗铜扩散阻挡层的制造方法，所述的氧化层可以为硅碳氮（SiCN）、氮化硅(Si3N4)、氮氧化铝（AlON）、或者为氧化铝（Al2O3）、氧化钽（Ta2O5）、、氧化铪（HfO2）等金属氧化物。
如上所述的用于铜互连的抗铜扩散阻挡层的制造方法，所述的金属层可以为钴（Co）、钌(Ru)、钽（Ta）、钨（W）、钼（Mo）、钛（Ti）、铜（Cu）等单质金属，也可以、氮化钽（TaN）、氮化钛（TiN）、或者为氮化钼（MoN）等金属氮化物。
本发明使用混合介质（氧化层/金属）来作为抗铜扩散阻挡层，具有已下优点：
首先，可以有效增强金属对铜的抗扩散能力，并有效防止扩散阻挡层被氧化而失效，延长扩散阻挡层的寿命。
其次，可以降低互连电路的有效介电常数值，进而使得互连电路整体的RC延迟下降。
再次，由于金属与铜具有良好的粘附性和接触，可以在金属表面直接电镀铜而不需要先淀积一层铜籽晶，工艺简单可行，有望在未来铜互连的抗扩散阻挡层的制造中得到应用。
附图说明
图1为传统技术的铜互连结构的截面图。
图2为本发明所提出的混合介质抗铜扩散阻挡层的一个实施例的截面图。
图3-图10为在前道铜互连中用生长SiCN/Ru混合介质抗铜扩散阻挡层的一个实施例的工艺流程图。
具体实施方式
下面结合附图与具体实施方式对本发明作进一步详细的说明，在图中，为了方便说明，放大或缩小了层和区域的厚度，所示大小并不代表实际尺寸。尽管这些图并不能完全准确的反映出器件的实际尺寸，但是它们还是完整的反映了区域和组成结构之间的相互位置，特别是组成结构之间的上下和相邻关系。
图2为本发明所提出的混合介质抗铜扩散阻挡层的一个实施例的截面图。如图2所示，在半导体基底200之上形成有低介电常数介质层201，在低介电常数介质层201形成有互连通孔。在互连通孔的侧壁以及低介电常数介质层201之上形成有氧化层202，覆盖氧化层202以及互连通孔的底壁形成有一金属层203，氧化层202与金属层203形成氧化层/金属混合介质抗铜扩散阻挡层。
氧化层202可以为SiCN、Si3N4、AlON，也可以为Al2O3、Ta2O5、HfO2等金属氧化物。金属层203可以为Co、Ru、 Ta、W、Mo、Ti、Cu等单质金属，也可以为TaN、TiN或者为MoN等金属氮化物。
本发明所提出的用于铜互连的氧化层/金属混合介质抗铜扩散阻挡层可以应用于不同的铜互连结构中，以下所叙述的是本发明所公开的在前道铜互连中生长氧化层/金属混合介质抗铜扩散阻挡层的一个实施例。
如图2所示，首先在提供的半导体基底200的表面生长低介电常数介质层201，之后在低介电常数介质层201之上旋涂光刻胶301并掩模、曝光、显影定义出互连通孔的位置。
所述半导体基底200的材质可以是单晶硅、多晶硅、非晶硅中的一种，也可以是绝缘体上的硅结构或硅上外延层结构。在所述半导体基底200中形成有半导体器件（未示出），例如具有栅极、源极和漏极的金属氧化物半导体器件。所述半导体基底200中还可以形成有金属互连结构（未示出），如铜的通孔或者互连线。
所述低介电常数介质层201可以是二氧化硅、硼硅玻璃、磷硅玻璃、硼磷硅玻璃等，也可以为超低介电常数介质，比如为多孔SiCOH（掺碳的氧化物）介质。
接下来，刻蚀掉没有被光刻胶保护的低介电常数介质层形成互连通孔，剥除光刻胶301后如图3所示。
接下来，在所形成的互连通孔的底壁、侧壁以及低介电常数介质层201的表面生长一层约2纳米厚的氧化层202，如图4所示。然后，采用反应离子刻蚀（RIE）的方法对氧化层202进行回刻，刻蚀掉位于互连通孔底壁上的氧化层，以保证关键尺寸，如图5所示。
氧化层202可以为SiCN、Si3N4、AlON、Al2O3、Ta2O5或者为HfO2。以上所述金属层的生长方法都是业界所熟知的，以生长SiCN氧化层为例，将形成互连通孔后的器件放入300℃的反应腔体内，使用TDMAS （〔N(CH[RD3])[RD2]RD3]SiH ）和氢气（H2）分别作为前驱体和氧化剂，用等离子体增强化学气相沉积（PECVD）方法在互连通孔的底壁、侧壁以及低介电常数介质层201的表面生长一层约2纳米厚的SiCN氧化层。
接下来，采用原子层淀积的方法覆盖氧化层202以及互连通孔的底壁生长一层约1纳米厚的金属层203，如图6所示。
金属层203可以为Co、Ru、 Ta、W、Mo、Ti、Cu、TaN、TiN或者为MoN。以上所述金属层的生长方法也是业界所熟知的，以生长钌金属层为例。将钌源IMBCHRu[（η6-1-异丙基-4-甲基苯）（η4??-环己-1,3-二烯）钌（O）]加热至120℃，使用IMNCHRu和氧气（O2）分别作为前驱体和氧化剂，在300℃的反应腔体内，采用原子层淀积的方法覆盖氧化层202以及互连通孔的底壁生长一层约1纳米厚的钌金属层。
接下来，在互连通孔中电镀铜金属204，如图7所示。
接下来，对铜金属进行化学机械抛光，以去除多余的铜金属、抗铜扩散阻挡层和低介电常数介质层，如图8所示。
最后，利用PECVD工艺使用硅烷（SiH4）和氨气（NH3）为反应气体生长一层氮化硅刻蚀阻挡层205，如图9所示。
如上所述，在不偏离本发明精神和范围的情况下，还可以构成许多有很大差别的实施例。应当理解，除了如所附的权利要求所限定的，本发明不限于在说明书中所述的具体实例。

Claims (10)

1. 一种用于铜互连的抗铜扩散阻挡层，包括：在半导体基底上形成的低介电常数介质层；在所述低介电常数介质层中形成的互连通孔；其特征在于，
在所述互连通孔的侧壁以及所述低介电常数介质层之上形成的氧化层；
覆盖所述氧化层与所述互连通孔的底壁形成的金属层；
所述氧化层与所述金属层形成氧化层和金属混合介质抗铜扩散阻挡层。
2. 如权利要求1所述的用于铜互连的抗铜扩散阻挡层，其特征在于，所述的氧化层为硅碳氮、氮化硅或者为金属的氧化物及氮氧化物。
3. 如权利要求1所述的用于铜互连的抗铜扩散阻挡层，其特征在于，所述的金属层可以为单质金属或金属氮化物。
4. 如权利要求2所述的用于铜互连的抗铜扩散阻挡层，其特征在于，所述金属的氧化物及氮氧化物为氧化铝、氮氧化铝、氧化钽或者氧化铪。
5. 如权利要求3所述的用于铜互连的抗铜扩散阻挡层，其特征在于，所述的金属层为钴、钌、钽、钨、钼、钛、铜、氮化钽、氮化钛或者为氮化钼。
6. 一种如权利要求1所述的用于铜互连的抗铜扩散阻挡层的制造方法，包括：
在提供的半导体基底表面淀积一层低介电常数介质层；刻蚀所述低介电常数介质层形成互连通孔；覆盖所形成的互连通孔的底壁、侧壁以及所述低介电常数介质层的表面生长一层薄的氧化层；
对所形成的氧化层进行回刻以去除在所述互连通孔底部的所述氧化层；
覆盖剩余的氧化层以及互连通孔的底壁淀积一金属层，所形成的金属层与氧化层构成氧化层和金属混合介质抗铜扩散阻挡层。
7. 如权利要求6所述的用于铜互连的抗铜扩散阻挡层，其特征在于，所述的氧化层为硅碳氮、氮化硅或者为金属的氧化物及氮氧化物。
8. 如权利要求6所述的用于铜互连的抗铜扩散阻挡层，其特征在于，所述的金属层可以为单质金属或金属氮化物。
9. 如权利要求7所述的用于铜互连的抗铜扩散阻挡层，其特征在于，所述金属的氧化物及氮氧化物为氧化铝、氮氧化铝、氧化钽或者氧化铪。
10. 如权利要求8所述的用于铜互连的抗铜扩散阻挡层，其特征在于，所述的金属层为钴、钌、钽、钨、钼、钛、铜、氮化钽、氮化钛或者为氮化钼。
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