WO2018126509A1 - Ffs模式的阵列基板及其制作方法 - Google Patents

Ffs模式的阵列基板及其制作方法 Download PDF

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Publication number
WO2018126509A1
WO2018126509A1 PCT/CN2017/073337 CN2017073337W WO2018126509A1 WO 2018126509 A1 WO2018126509 A1 WO 2018126509A1 CN 2017073337 W CN2017073337 W CN 2017073337W WO 2018126509 A1 WO2018126509 A1 WO 2018126509A1
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WO
WIPO (PCT)
Prior art keywords
layer
common electrode
array substrate
metal layer
ffs mode
Prior art date
Application number
PCT/CN2017/073337
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English (en)
French (fr)
Inventor
甘启明
Original Assignee
深圳市华星光电技术有限公司
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Priority to US15/513,916 priority Critical patent/US20180239204A1/en
Publication of WO2018126509A1 publication Critical patent/WO2018126509A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background

Definitions

  • the present invention relates to the field of liquid crystal panels, and in particular to an array substrate of an FFS mode and a method of fabricating the same.
  • Fringe Field Switch is a fringe field liquid crystal display mode, referred to as FFS mode.
  • the FFS mode liquid crystal panel has the advantages of high light transmittance, wide viewing angle, and the like, and is widely used in the field of wide viewing angle liquid crystal display technology.
  • the edge electric field is formed by the common electrode and the pixel electrode to realize the control of the liquid crystal to achieve the display screen.
  • the common electrode is a monolithic electrode layer, and the potential of the pixel electrode is independently controlled by the data line, and the potential of the common electrode is independently controlled by an external circuit.
  • the invention provides an FFS mode array substrate and a manufacturing method thereof, so as to solve the technical problem that a common voltage signal on a common electrode in an array substrate of the existing FFS mode is different.
  • the present invention provides an array substrate of an FFS mode, comprising a plurality of scan lines, a plurality of data lines, and a common electrode, further comprising a plurality of conductive strips, the conductive strips being disposed between the scan lines and the common electrodes And being in a different layer from the data line, the conductive strip is electrically connected to the common electrode for conducting an electrical signal of the common electrode.
  • the FFS mode array substrate further includes a dielectric layer disposed between the data line and the conductive strip for insulation separation The data line and the conductive strip.
  • the FFS mode array substrate further includes a flat layer, the flat layer is disposed on the conductive strip, and the common electrode is disposed on the flat layer, wherein A via hole is disposed on the flat layer, and the common electrode is electrically connected to the conductive strip through the via hole.
  • the conductive strips are disposed corresponding to the scan lines.
  • the length of the electrical conductor is the same as the length of the scanning line.
  • the number of the conductive strips is the same as the number of the scan lines.
  • the material of the conductive strip comprises aluminum, copper or molybdenum.
  • the present invention further provides an array substrate of an FFS mode, comprising a plurality of scan lines, a plurality of data lines, and a common electrode, further comprising a plurality of conductive strips, the conductive strips being disposed between the scan lines and the common electrodes And electrically connected to the common electrode for conducting an electrical signal of the common electrode.
  • the conductive strips are in the same layer and insulated from the data lines.
  • the array substrate further includes a dielectric layer and a flat layer, the dielectric layer and the flat layer are disposed on the data line and the conductive strip, and the common electrode is placed a via hole is disposed in the dielectric layer and the planar layer, and the conductive strip is electrically connected to the common electrode through the via hole.
  • the via hole includes two via holes corresponding to both end portions of the conductive strip, and the conductive strip passes through the two through holes and the common The electrodes are electrically connected.
  • the conductive strips are disposed corresponding to the scan lines.
  • the material of the conductive strip comprises aluminum, copper or molybdenum.
  • the shape of the conductive strip includes a rectangle or the middle of the conductive strip is rectangular, and the two ends are semi-circular.
  • the material of the conductive strip is the same as the material of the data line, and the conductive strip is formed simultaneously with the data line.
  • the invention further provides a method for fabricating an array substrate of an FFS mode, which comprises:
  • the conductive strip is disposed between the scan line and the common electrode, and is electrically connected to the common electrode.
  • the second metal layer and the third metal layer are the same layer, and the second metal layer, the third metal layer and the common electrode layer are formed on the insulating layer to Forming a plurality of data lines, a plurality of conductive strips, and a common electrode, respectively, including:
  • a common electrode layer is formed on the first planar layer to form a common electrode.
  • the sequentially forming the first dielectric layer and the first planar layer on the second metal layer and the third metal layer include:
  • first planar layer on the first dielectric layer and forming a second sub-via on the first planar layer through a second photomask, wherein the first sub-via and the second sub-pass
  • the hole forms a first via
  • the common electrode layer is electrically connected to the conductive strip through the first via.
  • the second metal layer and the third metal layer are different layers, and the second metal layer, the third metal layer and the common electrode layer are formed on the insulating layer to Forming a plurality of data lines, a plurality of conductive strips, and a common electrode, respectively, including:
  • a common electrode layer is formed on the second planar layer to form a common electrode, wherein the common electrode is electrically connected to the conductive strip through the second via.
  • the fabricating the third metal layer on the second dielectric layer to form a plurality of the conductive strips includes: in the dielectric layer and the scan line The third metal layer is formed at a corresponding position to form a plurality of the conductive strips.
  • the invention provides an array substrate of an FFS mode and a manufacturing method thereof.
  • the FFS mode array substrate is provided with a conductive strip between the scan line and the common electrode, and the conductive strip is electrically connected to the common electrode, and the conductive strip is used to conduct an electrical signal of the common electrode, so that The electrical signals on the common electrode in the array substrate of the FFS mode are kept consistent, and the display effect of the liquid crystal panel to which the array substrate is applied is improved.
  • FIG. 1 is a flowchart of a method for fabricating an array substrate of an FFS mode according to an embodiment of the present invention
  • step S11 is a schematic structural view of step S11 in the method for fabricating the array substrate shown in FIG. 1;
  • step S12 is a schematic structural view of step S12 in the method for fabricating the array substrate shown in FIG. 1;
  • step S13 is a schematic diagram showing a specific process of step S13 in the method for fabricating the array substrate shown in FIG. 1;
  • FIG. 8 are schematic diagrams showing a manufacturing process of the method for fabricating the array substrate shown in FIG. 4;
  • FIG. 9 is a schematic top plan view of the array substrate of FIG. 7;
  • FIG. 10 is still another schematic flowchart of step S13 in the method for fabricating the array substrate shown in FIG. 1;
  • FIG. 11 is a schematic structural view of an array substrate fabricated by the method for fabricating the array substrate shown in FIG. 10.
  • FIGS. 2, 3, 5 to 9, and 11 structurally similar elements are denoted by the same reference numerals.
  • This embodiment provides a method for fabricating an array substrate in an FFS mode, as shown in FIG. 1 to FIG.
  • the method includes the following steps:
  • Step S11 forming a first metal layer on the substrate to form a plurality of scan lines
  • the substrate 10 may be a glass substrate for supporting purposes while carrying various devices on the array substrate.
  • a first metal layer is formed on the substrate 10 by a process such as physical deposition to form a plurality of scanning lines 20, as shown in FIG.
  • FIG. 2 only a section of any one of the scanning lines in the direction perpendicular to the substrate 10 is shown. It can be understood that the plurality of scanning lines 20 are spaced apart.
  • the material of the first metal layer, that is, the plurality of scanning lines 20 may be metal such as molybdenum (MO), aluminum (Al) or copper (Cu), and is not specifically limited herein.
  • MO molybdenum
  • Al aluminum
  • Cu copper
  • Step S12 forming an insulating layer on the first metal layer
  • an insulating layer 30 is formed on the first metal layer by a plasma enhanced chemical vapor deposition process, as shown in FIG.
  • Step S13 forming a second metal layer, a third metal layer, and a common electrode layer on the insulating layer to form a plurality of data lines, a plurality of conductive strips, and a common electrode, respectively; wherein the conductive strip is placed in the scan A wire is electrically connected to the common electrode and to the common electrode.
  • the second metal layer and the third metal layer are the same layer.
  • the second metal layer and the third metal layer are simultaneously formed, that is, a plurality of data lines and a plurality of conductive strips are simultaneously formed, so that the second metal layer and the plurality of conductive strips are simultaneously formed. The time for fabricating the array substrate without increasing the complexity of fabricating the array substrate.
  • FIG. 4 is a schematic diagram of a specific process of step S13 in FIG. Step S13 specifically includes the following steps:
  • Step S131 forming a second metal layer and a third metal layer on the insulating layer to form a plurality of data lines and a plurality of conductive strips, wherein the data lines are insulated from the conductive strips;
  • a second metal layer and a third metal layer are simultaneously formed on the insulating layer 30 by a physical vapor deposition method or the like to form a plurality of data lines 40 and conductive strips 50, as shown in FIG.
  • the plurality of data lines 40 are arranged at intervals.
  • the plurality of data lines 40 are vertically disposed, that is, perpendicular to the paper surface direction
  • the plurality of scanning lines 20 are horizontally disposed, that is, parallel to the paper surface direction.
  • the plurality of data lines 40 and the plurality of scan lines 20 are insulated from each other to form a plurality of sub-pixel units.
  • Each data line 40 is used to connect sub-pixel units in the same column, and each scan line 20 is used to connect sub-pixel units in the same row.
  • the third metal layer is disposed at a position where the scanning line 20 corresponds to each other, that is, a plurality of conductive strips 50 are disposed directly above the scanning line 20.
  • the conductive strips 50 are made of the same material as the plurality of data lines 40, that is, metals such as MO, Al, or Cu.
  • the conductive strip 50 may also be different from the material of the plurality of data lines 40.
  • the data line 40 is made of MO metal
  • the conductive strip 50 is made of AL metal.
  • the width of the conductive strip 50 may be the same as the width of the scan line 20 such that the conductive strip 50 just covers directly above the scan line 20.
  • the conductive strips 50 are insulated from the data lines 40. Specifically, both ends of the electrical conductor 50 are spaced apart from the data lines 40 on both sides.
  • Step S132 sequentially fabricating a first dielectric layer and a first planar layer on the second metal layer and the third metal layer;
  • the first dielectric layer 60 is generally formed on the second metal layer and the third metal layer, and passes through the first light.
  • the cover forms a first sub-via 61 on the first dielectric layer 60, as shown in FIG.
  • the first sub-via 61 is a vertically transparent hole.
  • the conductive strip 50 can be seen through the first sub-via 61 as viewed in a direction perpendicular to the substrate 10.
  • a first planar layer 70 is formed on the first dielectric layer 60, as shown in FIG.
  • the second sub-via 71 is formed on the first flat layer 70 by the second mask.
  • the second sub-via 71 corresponds to the first sub-via 61, and the second sub-via 71 and the first sub-via 61 constitute the first via 90, as shown in FIG.
  • FIG. 9 is a schematic top plan view of the array substrate shown in FIG. 7.
  • the plurality of data lines 40 and the plurality of scan lines 20 are interleaved to form a plurality of sub-pixel units 140.
  • a thin film transistor, a pixel electrode, and the like included in the sub-pixel unit 140 are not shown in FIG.
  • the array substrate shown in FIG. 9 is the insulating layer 30, the first dielectric layer 60, and the first A top view of the planar layer 70, but retaining the first via 90.
  • the insulating layer 30, the first dielectric layer 60, and the first planar layer 70 are omitted in FIG. 9, those skilled in the art can easily obtain the insulating layer 30, the first dielectric layer according to the description of the foregoing fabrication method.
  • Step S133 forming a common electrode layer on the first flat layer to form a common electrode.
  • a common electrode layer is formed on the first planarization layer 70 by a vapor deposition method or the like to form a common electrode 80, as shown in FIG.
  • the common electrode 80 is a transparent electrode, such as an indium tin oxide electrode.
  • the common electrode 80 When the common electrode 80 is fabricated, the common electrode 80 needs to cover the sidewall of the first via 90 and the conductive strip 50 that leaks through the first via 90, so that the common electrode 80 can pass through the first via 90 and conduct electricity. Strip 50 is electrically connected.
  • the common electrode 80 can conduct an electrical signal by means of the conductive strip 50. Since the conductive strip 50 is made of a metal material, its resistivity is much smaller than that of the indium tin oxide. The difference in electrical signals throughout the entire common electrode 80 is greatly reduced and has good uniformity.
  • the common electrode 80 is electrically contacted with the conductive strip 50 through the two first vias 90. It can be understood that in other embodiments, the number of the first vias 90 is not limited. For two, there can be more, and no specific restrictions are made here.
  • the plurality of first via holes may be disposed in the same row, or may be arranged in multiple rows.
  • the number of the first via holes 90 is four, four A via 90 can be arranged in two rows and two columns.
  • the manner in which the common electrode 80 is electrically connected to the conductive strip 50 is not limited to the via connection.
  • the via connection is not used, the dielectric layer 60 and the flat layer 70 do not need to be formed through the mask.
  • the two first vias 90 respectively correspond to the two ends of the conductive strip 50.
  • the first via 90 may also correspond to other portions of the conductive strip 50, and do not do this. Specific restrictions.
  • the conductive strips 50 may also be in different layers from the data lines 40, ie, the second metal layer and the third metal layer are not the same layer.
  • the specific flowchart of step S13 is as shown in FIG.
  • Step S13 includes the following steps:
  • Step S134 forming a second metal layer on the insulating layer to form a plurality of data lines
  • a second metal layer is formed on the insulating layer 30 by a physical vapor deposition method or the like to form a plurality of data lines 40.
  • Step S135 forming a second dielectric layer on the second metal layer
  • a second dielectric layer 110 is formed over the second metal layer to insulate the data lines 40 from other conductive structures.
  • Step S136 forming a third metal layer on the second dielectric layer to form a plurality of conductive strips
  • a plurality of conductive strips 50 are formed on the second dielectric layer 110 by a process such as physical vapor deposition.
  • the conductive strip 50 corresponds to the position of the scan line 20, and the length of the conductive strip 50 may be smaller or smaller than the distance between the data lines 40 on the left and right sides of the sub-pixel unit.
  • the length of the conductive strips 50 can also be the same as the length of the entire row of scan lines 20, that is, the plurality of sub-pixel units of the same row share the same conductive strip 50. For example, if there are M rows of scan lines 20 in the array substrate, then there are corresponding M conductive strips 50 corresponding to the M rows of scan lines, as shown in FIG.
  • Step S137 forming a second planar layer on the third metal layer, and forming a second via hole on the second planar layer through a third photomask;
  • the second flat layer 120 is formed on the third metal layer while the second via 130 is formed on the second flat layer 120 through the third mask.
  • the number of the second via holes 130 is two, that is, each of the sub-pixel units corresponds to two second via holes 130 . It can be understood that when the same row of sub-pixel units share the same conductive strip 50, the number of the second via holes 130 corresponding to each sub-pixel unit may be one, or one second is disposed for each sub-pixel unit.
  • the via 130 is for electrically connecting the common electrode 80 to the conductive strip 50.
  • the number and arrangement of the second via holes 130 are not limited to the above, and may be set according to parameters such as the size of the actual array substrate, and are not specifically limited herein.
  • Step S138 forming a common electrode layer on the second planar layer to form a common electrode, wherein the common electrode is electrically connected to the conductive strip through the second via.
  • the common electrode layer is formed by a physical vapor deposition method or the like to form the common electrode 80, and the common electrode 80 is electrically connected to the conductive strip through the second via 130.
  • a conductive strip is formed on the array substrate, so that the common electrode can be transmitted to the electrical signal by the conductive strip, thereby reducing the voltage difference between the common electrodes and maintaining the voltage of the common electrode. Uniformity makes the FFS mode liquid crystal panel to which the array substrate is applied has a better display effect.
  • the embodiment provides an array substrate of an FFS mode, which is fabricated by using the method for fabricating the array substrate provided by the embodiment of the invention.
  • the array substrate includes a substrate 10 , a plurality of scan lines 20 , a plurality of data lines 40 , a common electrode 80 , and a plurality of conductive strips 50 .
  • the array substrate In the array substrate, a plurality of scanning lines 20 are spaced apart from each other on the substrate 10. In order to prevent the scan line 20 and the data line 40 from being electrically connected, in the embodiment, the array substrate further includes an insulating layer 30 covering the plurality of strips. Above the scan line 20.
  • a plurality of data lines 40 are spaced apart on the insulating layer 30. It can be understood that, in the array substrate shown in FIG. 8, the plurality of data lines 40 are vertically disposed, that is, perpendicular to the paper surface direction, and the plurality of scanning lines 20 are horizontally disposed, that is, parallel to the paper surface direction.
  • the plurality of data lines 40 and the plurality of scan lines 20 are insulated from each other to form a plurality of sub-pixel units.
  • Each data line 40 is used to connect sub-pixel units in the same column, and each scan line 20 is used to connect sub-pixel units in the same row.
  • the material of the plurality of scan lines 20 and the plurality of data lines 40 may be metal such as MO, Al, or Cu, and the materials of the plurality of scan lines 20 and the plurality of data lines 40 may be the same or different. There are no specific restrictions here.
  • a plurality of conductive strips 50 are disposed directly above the scan lines 20 corresponding to the sub-pixel units.
  • the width of the conductive strip 50 may be the same as the width of the scanning line 20, or may be slightly smaller or slightly larger than the width of the scanning line 20.
  • the shape of the conductive strip 50 is a regular rectangle. It can be understood that the conductive strip 50 can also have other shapes, such as a rectangle in the middle of the conductive strip 50, and a semicircular structure at both ends of the rectangle. Etc., no specific restrictions are made here.
  • the conductive strips 50 can be fabricated simultaneously with the plurality of data lines 40. At this time, the conductive strips 50 are in the same layer as the plurality of data lines 40, and the conductive strips 50 are insulated from the data lines 40 on both sides. Separated.
  • the conductive strip 50 may be the same material as the data line 40, that is, a metal such as MO, Al or Cu.
  • the conductive strips 50 may be different from the material of the data lines 40.
  • the conductive strips 50 are made of MO metal, and the data lines 40 are made of Al metal.
  • the array substrate further includes a first dielectric layer 60 and a first planar layer 70.
  • the first dielectric layer 60 and the first planar layer 70 are sequentially disposed on the conductive strips 50 and the plurality of data lines 40.
  • a common electrode 80 is disposed on the first planar layer 70, at which time the conductive strip 50 will be placed between the scan line 20 and the common electrode 80.
  • the common electrode 80 is a transparent electrode such as indium tin oxide.
  • the first dielectric layer 60 and the first flat layer 70 in the embodiment are provided with via holes 90, and the conductive strips 50 are electrically connected to the common electrode 80 through the vias 90. .
  • the number of the via holes 90 is two, and the two via holes 90 respectively correspond to the two end portions of the bus bar 50, and the bus bar 50 passes through the two via holes 90 and the common The electrodes are electrically connected.
  • the common electrode 80 can conduct an electrical signal by means of the conductive strip 50. Since the conductive strip 50 is made of a metal material, its resistivity is much smaller than that of the indium tin oxide. The difference in electrical signals throughout the entire common electrode 80 is greatly reduced and has good uniformity.
  • the conductive strips 50 may also be in the same layer as the plurality of data lines 40, as shown in FIG.
  • the second dielectric layer 110 is disposed on the data line 40.
  • the conductive strip 50 is placed on the second dielectric layer 110 and corresponds to the scan line 20.
  • the flat layer 120 is disposed on the conductive strip 50, and the via layer 130 is provided with a via 130.
  • the common electrode 80 is disposed on the flat layer 120 and is electrically connected to the conductive strip 50 through the via 130.
  • the length of the conductive strips 50 may be less than or less than the distance between the data lines 40 on the left and right sides of the sub-pixel unit.
  • the length of the conductive strips 50 can also be the same as the length of the entire row of scan lines 20, that is, the plurality of sub-pixel units of the same row share the same conductive strip 50. For example, if there are M rows of scan lines 20 in the array substrate, then there are corresponding M conductive strips 50 corresponding to the M rows of scan lines.
  • each sub-pixel unit corresponds to two via holes 130. It can be understood that when the same row of sub-pixel units share the same conductive strip 50, the number of vias 130 corresponding to each sub-pixel unit may be one, or one via 130 may be disposed for each sub-pixel unit. It is used to electrically connect the common electrode 80 to the bus bar 50.
  • the number and arrangement of the vias 130 are not limited to the above, and may be set according to parameters such as the size of the actual array substrate, and are not specifically limited herein.
  • the array substrate of the FFS mode provided in this embodiment is provided with a conductive strip between the scan line and the common electrode, and the conductive strip is electrically connected to the common electrode. After the common electrode is applied with an electrical signal, the common electrode can be electrically connected by the conductive strip. The electrical signal is transmitted to reduce the difference between the voltages of the common electrode, and the uniformity of the voltage across the common electrode is maintained, so that the FFS mode liquid crystal panel using the array substrate has better display effect.

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Abstract

一种FFS模式的阵列基板及其制作方法。该阵列基板包括多条扫描线（20）、多条数据线（40）以及公共电极（80），还包括多个导电条（50），导电条（50）设置于扫描线（20）与公共电极（80）之间，且与公共电极（80）电连接，用于传导公共电极（80）的电信号。该阵列基板可以使得公共电极（80）上的电信号保持一致，提高应用该阵列基板的液晶面板的显示效果。

Description

FFS模式的阵列基板及其制作方法 技术领域
本发明涉及液晶面板技术领域，特别是涉及一种FFS模式的阵列基板及其制作方法。
 背景技术
边缘场开关（Fringe Field Switching，简称FFS）是一种边缘场液晶显示模式，简称FFS模式。FFS模式液晶面板具有光透过率高、视角广等优点，被广泛应用在广视角液晶显示技术领域。在FFS模式液晶面板中，通过公共电极与像素电极形成边缘电场来实现对液晶控制从而达到显示画面的目的。公共电极为一整块电极层，像素电极的电位通过数据线来独立控制，公共电极的电位通过外部电路独立控制。
然而，对于大尺寸的FFS模式液晶面板而言，由于公共电极的电阻率较高，即氧化铟锡的电阻率较高，容易引起公共电极的公共电极信号延迟，使得液晶面板各处的公共电压产生差异，影响显示画面质量。
故，有必要提供一种FFS模式的阵列基板及其制作方法，以解决现有技术所存在的问题。
 技术问题
本发明提供一种FFS模式的阵列基板及其制作方法，以解决现有的FFS模式的阵列基板中公共电极上的公共电压信号存在差异的技术问题。
 技术解决方案
本发明提供一种FFS模式的阵列基板，包括多条扫描线、多条数据线以及公共电极，其还包括多个导电条，所述导电条置于所述扫描线与所述公共电极之间，且与所述数据线处于不同层，所述导电条与所述公共电极电连接，用于传导所述公共电极的电信号。
在本发明所述的FFS模式的阵列基板中，所述FFS模式的阵列基板还包括介电层，所述介电层置于所述数据线与所述导电条之间，用于绝缘隔开所述数据线与所述导电条。
在本发明所述的FFS模式的阵列基板中，所述FFS模式的阵列基板还包括平坦层，所述平坦层置于所述导电条上，所述公共电极置于所述平坦层上，其中，所述平坦层上设有过孔，所述公共电极通过所述过孔与所述导电条电连接。
在本发明所述的FFS模式的阵列基板中，所述导电条与所述扫描线正对应设置。
在本发明所述的FFS模式的阵列基板中，所述导电体的长度与所述扫描线的长度相同。
在本发明所述的FFS模式的阵列基板中，所述导电条的个数与所述扫描线的个数相同。
在本发明所述的FFS模式的阵列基板中，所述导电条的材质包括铝、铜或钼。
本发明提供还一种FFS模式的阵列基板，包括多条扫描线、多条数据线以及公共电极，还包括多个导电条，所述导电条设置于所述扫描线与所述公共电极之间，且与所述公共电极电连接，用于传导所述公共电极的电信号。
在本发明所述FFS模式的阵列基板中，所述导电条与所述数据线处于同一层且绝缘隔开。
在本发明所述FFS模式的阵列基板中，所述阵列基板还包括介电层和平坦层，所述介电层和平坦层置于所述数据线和导电条上，所述公共电极置于所述平坦层上；所述介电层和平坦层中设有过孔，所述导电条通过所述过孔与所述公共电极电连接。
在本发明所述FFS模式的阵列基板中，所述过孔包括与所述导电条的两个端部相对应的两个过孔，所述导电条通过两个所述过孔与所述公共电极电连接。
在本发明所述FFS模式的阵列基板中，所述导电条与所述扫描线正对应设置。
在本发明所述FFS模式的阵列基板中，所述导电条的材质包括铝、铜或钼。
在本发明所述FFS模式的阵列基板中，所述导电条的形状包括长方形或者所述导电条的中间为长方形、两个端部为半圆形结构。
在本发明所述FFS模式的阵列基板中，所述导电条的材质与所述数据线的材质相同，且所述导电条与所述数据线同时成型。
本发明又提供一种FFS模式的阵列基板的制作方法，其包括：
在基板上制作第一金属层以形成多条扫描线；
在所述第一金属层上制作绝缘层；
在所述绝缘层上制作第二金属层、第三金属层和公共电极层以分别形成多条数据线、多个导电条和公共电极；
其中，所述导电条置于所述扫描线与所述公共电极之间，且与所述公共电极电连接。
在本发明所述的制作方法中，所述第二金属层和所述第三金属层为同一层，所述在所述绝缘层上制作第二金属层、第三金属层和公共电极层以分别形成多条数据线、多个导电条和公共电极，包括：
在所述绝缘层上制作第二金属层和第三金属层以形成多条数据线和多条导电条，其中，所述数据线与所述导电条绝缘隔开设置；
在所述第二金属层和第三金属层上依次制作第一介电层和第一平坦层；
在所述第一平坦层上制作公共电极层以形成公共电极。
在本发明所述的制作方法中，所述在所述第二金属层和第三金属层上依次制作第一介电层和第一平坦层包括：
在所述第二金属层和第三金属层上形成第一介电层，并通过第一道光罩在所述第一介电层上形成第一子过孔；
在所述第一介电层上形成第一平坦层，并通过第二道光罩在所述第一平坦层上形成第二子过孔，其中，所述第一子过孔和第二子过孔形成第一过孔，所述公共电极层通过所述第一过孔与所述导电条电连接。
在本发明所述的制作方法中，所述第二金属层和所述第三金属层为不同层，所述在所述绝缘层上制作第二金属层、第三金属层和公共电极层以分别形成多条数据线、多个导电条和公共电极，包括：
在所述绝缘层上制作第二金属层以形成多条数据线；
在所述第二金属层上制作第二介电层；
在所述第二介电层上制作第三金属层以形成多条导电条；
在所述第三金属层上制作第二平坦层，并通过第三道光罩在所述第二平坦层上形成第二过孔；
在所述第二平坦层上制作公共电极层以形成公共电极，其中，所述公共电极通过所述第二过孔与所述导电条电连接。
在本发明所述的制作方法中，所述在所述第二介电层上制作所述第三金属层以形成多条所述导电条包括：在所述介电层中与所述扫描线正对应的位置处制作所述第三金属层以形成多条所述导电条。
 有益效果
本发明提供一种FFS模式的阵列基板及其制作方法。该FFS模式的阵列基板通过在所述扫描线与所述公共电极之间设置导电条，且所述导电条与所述公共电极电连接，利用导电条来传导所述公共电极的电信号，使得FFS模式的阵列基板中公共电极上的电信号保持一致，提高应用该阵列基板的液晶面板的显示效果。
 附图说明
图1为本发明实施例中FFS模式的阵列基板的制作方法的流程图；
图2为图1所示阵列基板制作方法中步骤S11的结构示意图；
图3为图1所示阵列基板制作方法中步骤S12的结构示意图；
图4为图1所示阵列基板制作方法中步骤S13的具体流程示意图；
图5至图8为图4所示阵列基板制作方法的制作过程示意图；
图9为图7中阵列基板的俯视结构示意图；
图10为图1所示阵列基板制作方法中步骤S13的又一具体流程示意图；
图11为图10所示阵列基板制作方法制作的阵列基板的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图2、图3、图5至图9、图11中，结构相似的单元是以相同标号表示。
本实施例提供一种FFS模式的阵列基板的制作方法，请参见图1至图11所示。该方法包括以下步骤：
步骤S11：在基板上制作第一金属层以形成多条扫描线；
基板10可以为玻璃基板，用于起到支撑的作用，同时承载阵列基板上的各个器件。采用物理沉积法等工艺在基板10上制作第一金属层以形成多条扫描线20，如图2所示。
在图2中，仅仅示出了任意一条扫描线沿垂直于基板10方向的截面。可以理解的是，多条扫描线20间隔设置。
第一金属层，即多条扫描线20的材质可以为钼（MO）、铝（Al）或者铜（Cu）等金属，在此不做具体限制。
步骤S12：在所述第一金属层上制作绝缘层；
在制作完第一金属层20后，为了防止第一金属层和第二金属层电性接触，采用等离子体增强化学气相沉积工艺在第一金属层上制作绝缘层30，如图3所示。
步骤S13：在所述绝缘层上制作第二金属层、第三金属层和公共电极层以分别形成多条数据线、多个导电条和公共电极；其中，所述导电条置于所述扫描线与所述公共电极之间，且与所述公共电极电连接。
在本实施例中，第二金属层和第三金属层为同一层，此时第二金属层和第三金属层同时制作，即多条数据线和多个导电条同时形成，这样可以不增加制作阵列基板的时间，同时又不增加制作阵列基板的复杂度。
请参见图4所示，图4为图1中步骤S13的具体流程示意图。步骤S13具体包括以下几个步骤：
步骤S131：在所述绝缘层上制作第二金属层和第三金属层以形成多条数据线和多条导电条，其中，所述数据线与所述导电条绝缘隔开设置；
在制作完绝缘层30后，采用物理气相沉积法等工艺在绝缘层30上同时制作第二金属层和第三金属层以形成多条数据线40和导电条50，如图5所示。
可以理解的是，多条数据线40为间隔设置。一般情况下，多条数据线40为竖直设置，即垂直于纸面方向，多条扫描线20水平设置，即平行于纸面方向。这样多条数据线40和多条扫描线20相互绝缘交错形成多个子像素单元。每条数据线40用于连接处于同一列的子像素单元，每条扫描线20用于连接处于同一行的子像素单元。
在图5中，两条数据线40之间为子像素单元所在区域。为了避免影响子像素单元的开口率，第三金属层设置在扫描线20正对应的位置，即多条导电条50设置在扫描线20的正上方。
在本实施例中，导电条50与多条数据线40的材质相同，即均为MO、Al或者Cu等金属。当然，导电条50也可以与多条数据线40的材质不相同，例如，数据线40采用MO金属，而导电条50采用AL金属。
导电条50的宽度可以与扫描线20的宽度相同，以使得导电条50正好覆盖在扫描线20的正上方。
为了避免引起信号串扰，导电条50与数据线40处于绝缘隔开。具体地，导电体50的两个端部与两侧的数据线40间隔设置。
步骤S132：在所述第二金属层和第三金属层上依次制作第一介电层和第一平坦层；
在制作形成数据线40和导电条50后，为了使得数据线40与其他导电结构绝缘，一般会在第二金属层和第三金属层上制作第一介电层60，并通过第一道光罩在第一介电层60上形成第一子过孔61，如图6所示。
该第一子过孔61为上下通透的孔，从垂直于基板10方向上看，通过第一子过孔61可以看到导电条50。
在制作完上述结构后，阵列基板表面会凹凸不平，为了可以平坦化阵列基板表面，需在第一介电层60上制作第一平坦层70，如图7所示。
在制作第一平坦层70时，通过第二道光罩在第一平坦层70上形成第二子过孔71。
其中，第二子过孔71与第一子过孔61正对应，第二子过孔71和第一子过孔61组成第一过孔90，如图8所示。
请参见图9所示，图9为图7中所示的阵列基板的俯视结构示意图。多条数据线40和多条扫描线20交错形成多个子像素单元140。图9中并未示出子像素单元140包括的薄膜晶体管、像素电极等器件。
为了清晰地表现扫描线20、数据线40、导电条50和第一过孔90之间的位置关系，图9中示出的阵列基板为去掉绝缘层30、第一介电层60和第一平坦层70的俯视图，但保留了第一过孔90。
虽然图9中省略了绝缘层30、第一介电层60和第一平坦层70，但是根据前述制作方法的描述，本领域的技术人员可以很容易地得到包含将绝缘层30、第一介电层60和第一平坦层70的阵列基板的俯视图。
步骤S133：在所述第一平坦层上制作公共电极层以形成公共电极。
在制作完第一平坦层70后，在第一平坦层70上采用气相沉积法等工艺制作公共电极层以形成公共电极80，如图8所示。
在本实施例中，公共电极80为透明电极，如采用氧化铟锡电极。
在制作公共电极80时，公共电极80需要覆盖在第一过孔90的侧壁以及通过第一过孔90暴漏的导电条50上，这样公共电极80就可以通过第一过孔90与导电条50电连接。
当大屏液晶面板的控制电路向公共电极80输入电信号时，公共电极80可以借助导电条50传导电信号，由于导电条50采用金属材质，其电阻率远小于氧化铟锡的电阻率，使得整块公共电极80上各处的电信号差异大大减小，具有良好的均一性。
在本实施例的每个子像素单元中，公共电极80通过两个第一过孔90与导电条50电接触，可以理解的是，在其他实施例中，第一过孔90的个数不局限于两个，可以为更多个，在此不做具体限制。
当第一过孔的个数为大于两个时，多个第一过孔可以同排设置，也可以多排设置，如，当第一过孔90的个数为4个时，4个第一过孔90可以排成两行两列的形状。
需要说明的是，公共电极80与导电条50电连接的方式不局限于过孔连接，当不采用过孔连接时，介电层60和平坦层70上不需要通过光罩制作子过孔。
在本实施例中，两个第一过孔90分别对应了导电条50的两个端部，在其他实施例中，第一过孔90也可以对应导电条50的其他部分，在此不做具体限制。
在一实施例中，导电条50也可以与数据线40处于不同层，即第二金属层和第三金属层不为同一层。此时步骤S13的具体流程图如图10所示。
步骤S13包括以下几个步骤：
步骤S134：在所述绝缘层上制作第二金属层以形成多条数据线；
如图11所示，在绝缘层30上采用物理气相沉积法等工艺制作第二金属层以形成多条数据线40。
步骤S135：在所述第二金属层上制作第二介电层；
在第二金属层上制作第二介电层110，用以使得数据线40与其他导电结构绝缘。
步骤S136：在所述第二介电层上制作第三金属层以形成多条导电条；
在第二介质层110上采用物理气相沉积法等工艺制作多条导电条50。导电条50与扫描线20的位置对应，导电条50的长度可以小于或小于等于子像素单元左右两侧的数据线40之间的距离。
由于导电条50与数据线40处于不同层且相互绝缘，因此，导电条50的长度也可以与整行扫描线20的长度相同，即同一行的多个子像素单元公用同一个导电条50。例如，阵列基板中有M行扫描线20，则对应有M个导电条50与M行扫描线正对应，如图11所示。
步骤S137：在所述第三金属层上制作第二平坦层，并通过第三道光罩在所述第二平坦层上形成第二过孔；
在制作完导电条50后，在第三金属层上制作第二平坦层120，同时通过第三道光罩在第二平坦层120上形成第二过孔130。
在图11中，第二过孔130的个数为两个，即每个子像素单元对应两个第二过孔130。可以理解的是，当同一行子像素单元公用同一个导电条50时，每个子像素单元对应的第二过孔130的个数可以为1个，或者，每间隔一个子像素单元设置一个第二过孔130，用于使得公共电极80与导电条50电连接。
当然，第二过孔130的个数以及设置方式不局限于上述情况，可以根据实际阵列基板的大小等参数进行设置，在此不做具体限制。
步骤S138：在所述第二平坦层上制作公共电极层以形成公共电极，其中，所述公共电极通过所述第二过孔与所述导电条电连接。
在制作完第二平坦层120后，在采用物理气相沉积法等工艺制作公共电极层以形成公共电极80，公共电极80通过第二过孔130与导电条电连接。
本实施例提供的FFS模式的阵列基板的制作方法，在阵列基板上制作导电条，使得公共电极可以借助导电条传到电信号，降低公共电极各处电压的差异，保持公共电极各处电压的均一性，使得应用该阵列基板的FFS模式液晶面板具有更好的显示效果。
本实施例提供一种FFS模式的阵列基板，该阵列基板采用本发明实施例提供的阵列基板的制作方法制作。
请参见图8，该阵列基板包括基板10、多条扫描线20、多条数据线40、公共电极80以及多个导电条50。
在该阵列基板中，多条扫描线20间隔设置在基板10上。由于多条数据线40和多条扫描线20纵横交错，为了防止扫描线20和数据线40电性接触，在本实施例中，阵列基板还包括绝缘层30，该绝缘层30覆盖在多条扫描线20的上方。
多条数据线40间隔设置在绝缘层30上。可以理解的是，在图8所示的阵列基板中，多条数据线40为竖直设置，即垂直于纸面方向，多条扫描线20水平设置，即平行于纸面方向。这样多条数据线40和多条扫描线20相互绝缘交错形成多个子像素单元。每条数据线40用于连接处于同一列的子像素单元，每条扫描线20用于连接处于同一行的子像素单元。
在本实施例中，多条扫描线20和多条数据线40的材质可以为MO、Al或者Cu等金属，且多条扫描线20和多条数据线40的材质可以相同，也可以不相同，在此不做具体限制。
为了避免影响子像素单元的开口率，多条导电条50设置在子像素单元对应的扫描线20的正上方。导电条50的宽度可以与扫描线20的宽度相同，也可以比扫描线20的宽度略小或略大均可。
在本实施例中，导电条50的形状为规则的长方形，可以理解的是，导电条50也可以为其他形状，如导电条50的中间为长方形，长方形的两个端部为半圆型结构等等，在此不做具体限制。
为了不增加制作整个阵列基板的时间，导电条50可以与多条数据线40同时制作，此时导电条50与多条数据线40处于同一层，且导电条50与两侧的数据线40绝缘隔开。
另外，导电条50可以与数据线40的材质相同，即均为MO、Al或者Cu等金属。导电条50可以与数据线40的材质不相同，例如导电条50为MO金属，数据线40为Al金属。
在本实施例中，阵列基板还包括第一介电层60和第一平坦层70，第一介电层60和第一平坦层70依次置于导电条50、多条数据线40上。在第一平坦层70上设置公共电极80，此时，导电条50将置于扫描线20与公共电极80之间。
在本实施例中，公共电极80为氧化铟锡等透明电极。
为了可以使得导电条50与公共电极80电连接，本实施例中的第一介电层60与第一平坦层70上设有过孔90，导电条50通过过孔90与公共电极80电连接。
在图8所示的阵列基板中，过孔90的个数为两个，且两个过孔90分别与导电条50的两个端部相对应，导电条50通过两个过孔90与公共电极电连接。
当大屏液晶面板的控制电路向公共电极80输入电信号时，公共电极80可以借助导电条50传导电信号，由于导电条50采用金属材质，其电阻率远小于氧化铟锡的电阻率，使得整块公共电极80上各处的电信号差异大大减小，具有良好的均一性。
在一实施例中，导电条50也可以与多条数据线40不处于同一层，如图11所示。
在图11所示的阵列基板中，第二介电层110设置在数据线40上。导电条50置于第二介电层110上，且与扫描线20正对应。平坦层120设置在导电条50上，且平坦层120上设有过孔130。公共电极80设置在平坦层120上，且通过过孔130与导电条50电连接。
在该实施例中，导电条50的长度可以小于或小于等于子像素单元左右两侧的数据线40之间的距离。
由于导电条50与数据线40处于不同层且相互绝缘，因此，导电条50的长度也可以与整行扫描线20的长度相同，即同一行的多个子像素单元公用同一个导电条50。例如，阵列基板中有M行扫描线20，则对应有M个导电条50与M行扫描线正对应。
另外，在图11所示的阵列基板中，每个子像素单元对应两个过孔130。可以理解的是，当同一行子像素单元公用同一个导电条50时，每个子像素单元对应的过孔130的个数可以为1个，或者，每间隔一个子像素单元设置一个过孔130，用于使得公共电极80与导电条50电连接。
当然，过孔130的个数以及设置方式不局限于上述情况，可以根据实际阵列基板的大小等参数进行设置，在此不做具体限制。
本实施例提供的FFS模式的阵列基板，其通过在扫描线与公共电极之间设置导电条，且该导电条与公共电极电连接，当公共电极被施加电信号后，公共电极可以借助导电条传到电信号，降低公共电极各处电压的差异，保持公共电极各处电压的均一性，使得应用该阵列基板的FFS模式液晶面板具有更好的显示效果。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种FFS模式的阵列基板，包括多条扫描线、多条数据线以及公共电极，其还包括多个导电条，所述导电条置于所述扫描线与所述公共电极之间，且与所述数据线处于不同层，所述导电条与所述公共电极电连接，用于传导所述公共电极的电信号。
  2. 根据权利要求1所述的FFS模式的阵列基板，其中所述FFS模式的阵列基板还包括介电层，所述介电层置于所述数据线与所述导电条之间，用于绝缘隔开所述数据线与所述导电条。
  3. 根据权利要求2所述的FFS模式的阵列基板，其中所述FFS模式的阵列基板还包括平坦层，所述平坦层置于所述导电条上，所述公共电极置于所述平坦层上，其中，所述平坦层上设有过孔，所述公共电极通过所述过孔与所述导电条电连接。
  4. 根据权利要求1所述的FFS模式的阵列基板，其中所述导电条与所述扫描线正对应设置。
  5. 根据权利要求4所述的FFS模式的阵列基板，其中所述导电体的长度与所述扫描线的长度相同。
  6. 根据权利要求5所述的FFS模式的阵列基板，其中所述导电条的个数与所述扫描线的个数相同。
  7. 根据权利要求1所述的FFS模式的阵列基板，其中所述导电条的材质包括铝、铜或钼。
  8. 一种FFS模式的阵列基板，包括多条扫描线、多条数据线以及公共电极，其还包括多个导电条，所述导电条设置于所述扫描线与所述公共电极之间，且与所述公共电极电连接，用于传导所述公共电极的电信号。
  9. 根据权利要求8所述的FFS模式的阵列基板，其中所述导电条与所述数据线处于同一层且绝缘隔开。
  10. 根据权利要求9所述的FFS模式的阵列基板，其中所述阵列基板还包括介电层和平坦层，所述介电层和平坦层置于所述数据线和导电条上，所述公共电极置于所述平坦层上；所述介电层和平坦层中设有过孔，所述导电条通过所述过孔与所述公共电极电连接。
  11. 根据权利要求10所述的FFS模式的阵列基板，其中所述过孔包括与所述导电条的两个端部相对应的两个过孔，所述导电条通过两个所述过孔与所述公共电极电连接。
  12. 根据权利要求8所述的FFS模式的阵列基板，其中所述导电条与所述扫描线正对应设置。
  13. 根据权利要求8所述的FFS模式的阵列基板，其中所述导电条的材质包括铝、铜或钼。
  14. 根据权利要求11所述的FFS模式的阵列基板，其中所述导电条的形状包括长方形或者所述导电条的中间为长方形、两个端部为半圆形结构。
  15. 根据权利要求9所述的FFS模式的阵列基板，其中所述导电条的材质与所述数据线的材质相同，且所述导电条与所述数据线同时成型。
  16. 一种FFS模式的阵列基板的制作方法，其包括：
    在基板上制作第一金属层以形成多条扫描线；
    在所述第一金属层上制作绝缘层；
    在所述绝缘层上制作第二金属层、第三金属层和公共电极层以分别形成多条数据线、多个导电条和公共电极；
    其中，所述导电条置于所述扫描线与所述公共电极之间，且与所述公共电极电连接。
  17. 根据权利要求16所述的制作方法，其中所述第二金属层和所述第三金属层为同一层，所述在所述绝缘层上制作第二金属层、第三金属层和公共电极层以分别形成多条数据线、多个导电条和公共电极，包括：
    在所述绝缘层上制作所述第二金属层和第三金属层以形成多条所述数据线和多条所述导电条，其中，所述数据线与所述导电条绝缘隔开设置；
    在所述第二金属层和第三金属层上依次制作第一介电层和第一平坦层；
    在所述第一平坦层上制作所述公共电极层以形成所述公共电极。
  18. 根据权利要求17所述的制作方法，其中所述在所述第二金属层和第三金属层上依次制作第一介电层和第一平坦层包括：
    在所述第二金属层和第三金属层上形成所述第一介电层，并通过第一道光罩在所述第一介电层上形成第一子过孔；
    在所述第一介电层上形成所述第一平坦层，并通过第二道光罩在所述第一平坦层上形成第二子过孔，其中，所述第一子过孔和第二子过孔形成第一过孔，所述公共电极通过所述第一过孔与所述导电条电连接。
  19. 根据权利要求16所述的制作方法，其中所述第二金属层和所述第三金属层为不同层，所述在所述绝缘层上制作第二金属层、第三金属层和公共电极层以分别形成多条数据线、多个导电条和公共电极，包括：
    在所述绝缘层上制作所述第二金属层以形成多条所述数据线；
    在所述第二金属层上制作第二介电层；
    在所述第二介电层上制作所述第三金属层以形成多条所述导电条；
    在所述第三金属层上制作第二平坦层，并通过第三道光罩在所述第二平坦层上形成第二过孔；
    在所述第二平坦层上制作所述公共电极层以形成所述公共电极，其中，所述公共电极通过所述第二过孔与所述导电条电连接。
  20. 根据权利要求19所述的制作方法，其中所述在所述第二介电层上制作所述第三金属层以形成多条所述导电条包括：在所述介电层中与所述扫描线正对应的位置处制作所述第三金属层以形成多条所述导电条。
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