WO2018097102A1 - 窒化物半導体基板とその製造方法および半導体デバイス - Google Patents
窒化物半導体基板とその製造方法および半導体デバイス Download PDFInfo
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- WO2018097102A1 WO2018097102A1 PCT/JP2017/041686 JP2017041686W WO2018097102A1 WO 2018097102 A1 WO2018097102 A1 WO 2018097102A1 JP 2017041686 W JP2017041686 W JP 2017041686W WO 2018097102 A1 WO2018097102 A1 WO 2018097102A1
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- nitride semiconductor
- semiconductor substrate
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- nitride
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- 150000004767 nitrides Chemical class 0.000 title claims abstract description 267
- 239000004065 semiconductor Substances 0.000 title claims abstract description 233
- 239000000758 substrate Substances 0.000 title claims abstract description 185
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 42
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- 238000000034 method Methods 0.000 claims abstract description 42
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- H01S5/00—Semiconductor lasers
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- H01S5/00—Semiconductor lasers
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- H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
- H01S5/323—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/32308—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm
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Definitions
- the present invention relates to a nitride semiconductor substrate having a reduced surface dislocation density, a manufacturing method thereof, and a semiconductor device manufactured using the nitride semiconductor substrate.
- LEDs Light Emitting Diodes
- LDs Laser Diodes
- LEDs are used for various display devices, mobile phones and other liquid crystal display backlights, white illumination, etc.
- LDs are used as Blu-ray Disc light sources for high-definition video recording and playback, optical communications, CDs, DVDs, etc. It has been.
- MMIC monolithic microwave integrated circuit
- HEMT High Electron Mobility Transistor: high-electron mobility transistor
- SBD Schottky barrier diodes
- the semiconductor elements constituting these devices are manufactured using a nitride semiconductor substrate on which a nitride semiconductor layer such as gallium nitride (GaN) is formed.
- a nitride semiconductor substrate As such a nitride semiconductor substrate, a nitride semiconductor bulk substrate cut directly from a bulk single crystal nitride, a single crystal nitride is grown on a substrate such as sapphire, and then the substrate is removed.
- characteristics such as the internal quantum efficiency of the LED and the oscillation performance of the LD, and the lifetime are related to the dislocation density (TDD) of the surface of the nitride semiconductor substrate.
- TDD dislocation density
- Such a nitride semiconductor substrate having a low dislocation density can be obtained by a method of directly producing the above-described nitride semiconductor bulk substrate, but the process is complicated and requires a great deal of cost. Thus, the price is 50 to 60 times higher than the case of manufacturing a nitride semiconductor substrate. For this reason, there is a strong demand for a technique for manufacturing a nitride semiconductor substrate that can provide a low-dislocation density nitride semiconductor substrate at low cost using an inexpensive sapphire base material or the like.
- a nitride semiconductor substrate is formed by forming a nitride semiconductor thin film on a base material such as sapphire by using a metal-organic chemical vapor deposition (MOCVD) method or the like, it is obtained.
- MOCVD metal-organic chemical vapor deposition
- the dislocation density of the nitride semiconductor substrate is on the order of 10 8 to 10 10 cm ⁇ 2 , and it is known that the obtained nitride semiconductor substrate cannot obtain designed characteristics and lifetime.
- a nitride buffer layer is formed on the sapphire substrate, and then amorphous silicon oxide (a- A selective growth (SAG) mask is formed using SiO 2 ), and a method of lateral epitaxy of a nitride semiconductor layer on the selective growth mask (ELOG: epitaxial lateral overgrowth) is performed.
- SAG selective growth
- ELOG epitaxial lateral overgrowth
- this method requires the substrate to be taken out of the growth apparatus when forming the selective growth mask, which complicates the process and reduces the production efficiency.
- the low dislocation density region is formed by the pattern of the selective growth mask, the low dislocation density region is scattered on the substrate, and the area cannot be increased. It is difficult to increase the size of the semiconductor substrate.
- JP 2010-199620 A Japanese Patent Laid-Open No. 2015-095585
- the present invention provides a manufacturing technique of a nitride semiconductor substrate capable of manufacturing a nitride semiconductor substrate having a sufficiently reduced dislocation density in a large area even on an inexpensive base material such as sapphire. Let it be an issue.
- the present inventor has succeeded in producing a red light emitting diode using Eu-doped GaN (Eu-doped GaN layer) as a light emitting layer for the first time in the world.
- a doping material is formed on a sapphire substrate.
- the dislocation density is reduced in an undoped GaN layer (ud-GaN layer) not doped with GaN and a GaN layer (Eu-doped GaN layer) doped with Eu as a doping material in order. I found out.
- the Eu addition amount in the Eu-added GaN layer is about 1 atomic%, specifically, even if the impurity level is as small as 0.01 to 2 atomic%,
- the surprising result is that the dislocation density is drastically reduced, and a low-dislocation-density nitride semiconductor substrate suitable for the production of a high-performance, long-life semiconductor device with a dislocation density of 10 6 cm ⁇ 2 or less is obtained. Obtained.
- the threading dislocation from the sapphire base material is not bent to reach the surface when passing through the Eu-added GaN layer, and is produced on the sapphire base material. It has been found that the dislocation density is drastically reduced in spite of being a nitride semiconductor substrate.
- the dislocation density decreases in proportion to the increase in the thickness of the Eu-added GaN layer stacked on the ud-GaN layer, and the total thickness is as thin as 3 ⁇ m or less.
- a nitride semiconductor substrate having a sufficiently low dislocation density can be provided.
- the nitride semiconductor layer is a superlattice nitride semiconductor layer with a plurality of stacking times, even if the thickness of the Eu-added GaN layer is about 1/10 of the ud-GaN layer thickness, The inventors have found that the dislocation density decreases in proportion to the increase in the number of laminations. It has been found that by using such a superlattice structure, it is possible to provide a nitride semiconductor substrate having a sufficiently low dislocation density while having a total thickness of 3 ⁇ m or less.
- the ud-GaN layer and the Eu-added GaN layer can be stacked on the entire surface of the sapphire substrate, unlike the ELOG method, the area of the nitride semiconductor layer can be increased. The size of the physical semiconductor substrate can be increased.
- the reason why the threading dislocation from the sapphire substrate is not bent in the Eu-doped GaN layer and reaches the surface by forming such a laminated structure, and the reason why the dislocation density is lowered is estimated as follows.
- GaN is used as a nitride and Eu is used as an additive element.
- nitride so-called GaN-based nitrides such as AlN and InN other than GaN (including mixed crystals such as InGaN and AlGaN) are included.
- the additive element is not limited to Eu, and a nitride semiconductor substrate having a sufficiently reduced dislocation density is provided as long as it is a rare earth element that generically refers to Sc, Y, and lanthanoid elements from La to Lu. be able to.
- SiC or Si may be used as the base material, or thin GaN may be used as the base material. Since SiC is inexpensive and has high thermal conductivity and excellent heat dissipation, a nitride semiconductor substrate suitable for manufacturing a high-power semiconductor device can be provided at low cost. Since Si can easily obtain a large-sized base material, it is possible to provide an enlarged nitride semiconductor substrate. Further, by using GaN having a small thickness as a base material, a GaN bulk substrate can be provided at a low cost.
- the nitride semiconductor layer is alternately used by using two or more nitride layers having different local strains.
- the structure laminated on the substrate at least a part of the dislocations from the substrate side is bent and can be eliminated before reaching the surface.
- the dislocation density on the surface of the nitride semiconductor layer is lowered to the order of 10 6 cm ⁇ 2 or less, which is suitable for the production of a high-performance, long-life semiconductor device. .
- the removed nitride semiconductor layer can be used as a nitride semiconductor bulk substrate.
- the inventions described in claims 1 to 14 are based on the above findings, and the invention described in claim 1
- a nitride semiconductor substrate having a nitride semiconductor layer formed on a substrate The nitride semiconductor layer is An undoped nitride layer to which no doping material is added; and It is formed by laminating a rare earth element-added nitride layer to which a rare earth element is added as a doping material,
- the nitride semiconductor substrate is characterized in that a dislocation density on the surface of the nitride semiconductor layer is 10 6 cm -2 or less.
- Claim 2 is 2.
- the invention according to claim 3 The nitride semiconductor substrate according to claim 1, wherein the rare earth element is Eu.
- the invention according to claim 4 4.
- the invention according to claim 5 The number of laminations of the undoped nitride layer and the rare earth element-added nitride layer is one,
- the undoped nitride layer has a thickness of 0.1 to 50 nm, 5.
- the invention according to claim 6 The undoped nitride layer and the rare earth element-added nitride layer are laminated a plurality of times, and the nitride semiconductor layer is formed by a superlattice structure,
- the undoped nitride layer has a thickness of 0.1 to 50 nm
- the invention according to claim 7 The nitride semiconductor substrate according to claim 6, wherein the number of lamination is 2 to 300.
- the invention according to claim 8 is 8.
- the invention according to claim 9 is 9.
- the invention according to claim 10 is A nitride semiconductor substrate having a nitride semiconductor layer formed on a substrate,
- the nitride semiconductor layer has a structure in which two or more nitride layers having different local strains are alternately stacked,
- the nitride semiconductor substrate is characterized in that a dislocation density on the surface of the nitride semiconductor layer is 10 6 cm -2 or less.
- the invention according to claim 11 is The dislocation from the base material side is bent in the alternately laminated structure of the nitride semiconductor layer and disappears before reaching the surface. This is a nitride semiconductor substrate.
- the invention according to claim 12 is The nitride semiconductor substrate according to claim 10 or 11, wherein the nitride semiconductor layer is formed as a nitride semiconductor bulk substrate by being removed from the base material.
- the above-described nitride semiconductor substrate according to the present invention is a nitride semiconductor substrate having a sufficiently low dislocation density, it can be suitably used not only for light-emitting devices but also for high-frequency devices and high-power devices. .
- the invention according to claim 13 is A semiconductor device manufactured using the nitride semiconductor substrate according to any one of claims 1 to 12.
- the invention as set forth in claim 14 The semiconductor device according to claim 13, wherein the semiconductor device is any one of a light emitting device, a high frequency device, and a high output device.
- the nitride semiconductor substrate according to the present invention described above is a doping material using a metal organic vapor phase epitaxial method (OMVPE method) at a temperature of 900 to 1200 ° C. in a series of steps without being taken out from the reaction vessel in the middle.
- OMVPE method metal organic vapor phase epitaxial method
- the nitride layer When growing the nitride layer, if the growth temperature is increased, pits (holes) due to dislocations penetrating to the surface increase, and the dislocation density cannot be sufficiently reduced. On the other hand, when the temperature is lowered, the pits are reduced and the dislocation density can be sufficiently reduced.
- the growth temperature of the nitride layer is set to 900 to 1100 ° C.
- the nitride semiconductor substrate can be manufactured with a sufficiently reduced dislocation density.
- the formation of the undoped nitride layer and the rare earth element-added nitride layer can be performed by whether or not Eu is added during the growth of the GaN crystal, and thus can be performed in a series of steps without being taken out from the reaction vessel.
- a large-sized nitride semiconductor substrate can be manufactured at high cost with high production efficiency.
- the invention according to claim 15 is A method for manufacturing a nitride semiconductor substrate in which a nitride semiconductor layer is formed on a substrate, Growing GaN, InN, AlN, or a mixed crystal of any two or more thereof on a substrate to form an undoped nitride layer to which no doping material is added; On the undoped nitride layer, GaN, InN, AlN, or a mixed crystal of any two or more thereof is used as a base material, and a rare earth element is added as a doping material so as to replace Ga, In, or Al.
- a step of forming a rare earth element-added nitride layer is performed by a series of forming steps using a metal organic vapor phase epitaxial method under a temperature condition of 900 to 1200 ° C. without being taken out from a reaction vessel. Is the method.
- the invention of claim 16 is Forming the undoped nitride layer; Forming the rare earth element-added nitride layer, 16.
- a nitride semiconductor substrate having a sufficiently low dislocation density while having a total thickness of 3 ⁇ m or less by repeatedly forming a nitride semiconductor layer having a superlattice structure. it can.
- the invention according to claim 17 17.
- Eu has an atomic radius suitable for suppressing the propagation of dislocations by generating distortion in the surroundings even when substituted with Ga among the lanthanoid rare earth elements, the surface dislocations can be efficiently formed. Density can be reduced.
- Eu is preferable as a doping material because Eu compounds are easily available.
- the invention according to claim 18 Eu is determined by any one of Eu ⁇ N [Si (CH 3 ) 3 ] 2 ⁇ 3 , Eu (C 11 H 19 O 2 ) 3 , Eu [C 5 (CH 3 ) 4 (C 3 H 7 )] 2.
- Eu [C 5 (CH 3 ) 5 ] 2 , Eu [C 5 (CH 3 ) 4 H] 2 , Eu ⁇ N [Si (CH 3 ) 3 ] 2 ⁇ 3 , Eu (C 5 H 7 O 2 ) 3 , Eu (C 11 H 19 O 2 ) 3 , Eu [C 5 (CH 3 ) 4 (C 3 H 7 )] 2 and the like can be mentioned.
- Eu ⁇ N [Si (CH 3) 3] 2 ⁇ 3 and Eu (C 11 H 19 O 2 ) 3, Eu [C 5 (CH 3) 4 (C 3 H 7)] 2 is the reactor Since the vapor pressure at is high, efficient addition can be performed.
- the invention according to claim 20 provides 20.
- the nitride semiconductor layer can be used as a nitride semiconductor bulk substrate by removing the nitride semiconductor layer formed on the substrate from the substrate.
- the manufacturing technique of the nitride semiconductor substrate which can manufacture the nitride semiconductor substrate by which the dislocation density was fully reduced can be manufactured in a large area is provided. be able to.
- FIG. 1 is a schematic diagram showing a configuration of a nitride semiconductor substrate according to an embodiment of the present invention. It is a TEM image of the nitride semiconductor substrate which concerns on one embodiment of this invention. It is an AFM image of the surface of the nitride semiconductor substrate which concerns on one embodiment of this invention. It is an AFM image of the surface of the Eu addition GaN layer in the nitride semiconductor substrate concerning one embodiment of the present invention. It is the TEM image which observed the cross section of the nitride semiconductor substrate which concerns on one embodiment of this invention from the specific direction. It is a schematic diagram which shows the structure of the nitride semiconductor substrate which concerns on other embodiment of this invention.
- the present invention will be described based on embodiments.
- sapphire is used as the base material
- GaN layer is used as the nitride semiconductor layer
- Eu is used as the rare earth element to be added.
- the invention is not limited thereto.
- an undoped nitride layer (ud-GaN layer) and a rare earth element-added nitride layer (Eu) to which Eu is added as a rare earth element are formed on a sapphire substrate.
- a nitride semiconductor substrate in which a nitride semiconductor layer is formed by laminating an additional GaN layer one layer at a time will be described.
- FIG. 1 is a schematic diagram showing a configuration of a nitride semiconductor substrate according to the present embodiment.
- 1 is a nitride semiconductor substrate
- 10 is a sapphire substrate
- 20 is a nitride semiconductor layer in which a ud-GaN layer 21 and an Eu-added GaN layer 22 are laminated once as a pair.
- the nitride semiconductor substrate according to the present embodiment may be used for manufacturing a semiconductor device as a template with a nitride semiconductor layer formed on a sapphire base.
- the nitride semiconductor layer is a buffer ( In order to function as a buffer layer, the nitride semiconductor layer may be expressed as a buffer layer.
- the crack by the lattice constant difference (lattice mismatch) of the sapphire base material 10 and GaN is produced.
- the distance between the LT-GaN layer 30 grown at a low temperature of about 475 ° C. and the sapphire substrate 10 and the nitride semiconductor layer (buffer layer) 20 is increased to suppress the influence of dislocation.
- the ud-GaN layer 40 is formed in advance.
- a nitride semiconductor substrate manufacturing method is formed by laminating a ud-GaN layer 21 having a thickness of 10 nm and an Eu-doped GaN layer 22 having a thickness of 300 nm. An example in which 1 is manufactured will be described in detail.
- LT-GaN having a growth rate of 1.3 ⁇ m / h and a thickness of about 30 nm on a sapphire substrate 10 under conditions of a growth temperature of 475 ° C. and a pressure of 100 kPa using a metal organic vapor phase epitaxy method (OMVPE method).
- OMVPE method metal organic vapor phase epitaxy method
- the layer 30 was formed, and then the ud-GaN layer 40 having a thickness of about 2 ⁇ m was formed on the LT-GaN layer 30 under the conditions of a growth temperature of 1150 ° C. and a pressure of 100 kPa at a growth rate of 0.8 ⁇ m / h.
- an O-added GaN layer 22 having a thickness of 300 nm and a growth rate of 0.8 ⁇ m / h was formed on the ud-GaN layer 40 under the conditions of a growth temperature of 960 ° C. and a pressure of 100 kPa using the OMVPE method.
- an OMVPE method was used to form a ud-GaN layer 21 having a thickness of 10 nm and a growth rate of 0.8 ⁇ m / h on the Eu-doped GaN layer 22 under the conditions of a growth temperature of 960 ° C. and a pressure of 100 kPa.
- the Eu-doped GaN layer 22 and the ud-GaN layer 21 were laminated one by one, thereby forming the nitride semiconductor layer 20 and completing the manufacture of the nitride semiconductor substrate 1.
- trimethylgallium (TMGa) was used as the Ga raw material, and the supply amount was 0.55 sccm. Then, ammonia (NH 3 ) was used as the N raw material, and the supply amount was 4.0 slm. Further, Eu [C 5 (CH 3 ) 4 (C 3 H 7 )] 2 bubbled with a carrier gas (hydrogen gas: H 2 ) was used as the Eu organic raw material, and the supply amount was 1.5 slm (supply temperature) : 115 ° C.).
- the Eu raw material supply temperature is kept at a sufficiently high temperature of 115 to 135 ° C by changing the piping valve of the OMVPE device from the normal specification (heat-resistant temperature 80 to 100 ° C) to the high temperature special specification.
- a sufficient amount of Eu can be supplied to the reaction tube.
- each layer was formed in a series of steps so that the sample was not taken out from the reaction tube and the growth was not interrupted.
- FIG. 2 is a TEM image of the nitride semiconductor substrate.
- FIG. 2 shows that in this nitride semiconductor substrate, dislocations generated in the ud-GaN layer formed on the lowermost sapphire base are propagated toward the surface. However, among these dislocations, the dislocation reaches the surface in the part surrounded by the dark one-dot chain line on the right side, but the dislocation appears on the surface in the part surrounded by the light one-dot chain line on the left side. By the time it reaches, it has disappeared in the nitride semiconductor layer (buffer layer) in which the ud-GaN layer and the Eu-added GaN layer are stacked. From this result, according to the present embodiment, it can be confirmed that the dislocation density can be reduced in the nitride semiconductor substrate.
- FIG. 3 is an AFM image of the surface of the nitride semiconductor substrate, (a) is the surface of the ud-GaN layer before the formation of the nitride semiconductor layer (buffer layer), and (b) is after the formation of the nitride semiconductor layer (buffer layer). The surface of the nitride semiconductor layer (buffer layer) is shown.
- the dislocation density can be reduced in the nitride semiconductor substrate according to the present embodiment.
- the reason for the smaller pit diameter is that the pit diameter formed in the GaN layer is related to the growth temperature, and the upper Eu-doped GaN layer was grown at a low temperature of 960 ° C. This is probably because the diameter of the pit has been reduced. When the pit diameter is reduced and the pit is blocked, the dislocation density is further reduced.
- the state of dislocations appearing on the surface was observed by AFM in the same manner as described above.
- FIG. 4 is an AFM image of the surface of the Eu-doped GaN layer with each thickness.
- A is the result at a thickness of 100 nm
- (b) is the thickness at 300 nm
- (c) is the result at a thickness of 900 nm.
- the pits decrease as indicated by the one-dot chain circle, and almost disappear at a thickness of 900 nm.
- the growth and annihilation of the mixed dislocation is controlled by the nitride semiconductor layer (buffer layer).
- the dislocation density can be reduced as the thickness of the Eu-doped GaN layer stacked on the ud-GaN layer increases.
- the Eu-added GaN layer becomes too thick, there is a difference in thermal expansion coefficient between sapphire, which is a base material, and GaN, which is a nitride semiconductor layer, and warpage occurs at the interface between sapphire and the nitride semiconductor layer. There is a risk that it cannot be used as a physical semiconductor substrate.
- the ud-GaN layer and the Eu-added GaN layer are alternately stacked on the sapphire substrate a plurality of times, and a plurality of pairs of the ud-GaN layer and the Eu-added GaN layer are stacked.
- a nitride semiconductor layer having a superlattice structure a nitride semiconductor substrate having a sufficiently reduced dislocation density is manufactured even if it is thin.
- FIG. 6 is a schematic diagram showing the configuration of the nitride semiconductor substrate according to the present embodiment.
- the reference numerals in FIG. 6 are the same as those in FIG. 1 except that the number of nitride semiconductor substrates is two.
- the nitride semiconductor layer 20 includes the Eu-added GaN layer 22 and the ud-GaN layer 21 alternately stacked a plurality of times.
- the structure is the same as that of the nitride semiconductor substrate according to the first embodiment except that the ud-GaN layer 21 is formed as the outermost layer from the viewpoint of suppressing oxidation.
- the ud-GaN layer 21 is formed by repeatedly forming the ud-GaN layer 21 and the Eu-doped GaN layer 22.
- the method is the same as that of the nitride semiconductor substrate manufacturing method according to the first embodiment except that a plurality of pairs of the GaN layer 22 and the Eu-added GaN layer 22 are stacked.
- the formation of each layer was performed in a series of steps so as not to interrupt the growth without taking out the sample from the reaction tube on the way.
- FIG. 7 is an AFM image of the surface of the nitride semiconductor substrate.
- FIG. 7 is compared with FIG. 4C, which is an AFM image of the surface of a nitride semiconductor substrate in which an Eu-doped GaN layer having a thickness of 900 nm is laminated once, the total thickness of 480 nm (the topmost ud-GaN layer is It can be seen that the dislocation density is further reduced although the thickness is about half that of FIG.
- FIG. 8 shows a cross-sectional TEM image of the nitride semiconductor substrate manufactured by stacking 40 pairs in Experiment B.
- the dislocation density is on the order of 10 6 cm ⁇ 2 even in 13 pairs with the smallest number of pairs, and the dislocation density decreases as the number of pairs increases.
- Dislocation 1 there are two dislocations, Dislocation 1 and Dislocation 2.
- Dislocation 1 After entering the nitride semiconductor layer (buffer layer), it converges and disappears.
- Dislocation 2 although it has not disappeared, the size of the dislocation decreases as it passes through the pair. Also from this result, it can be understood that the dislocation density is further decreased in Experiment C in which the number of pairs is further increased to 70 pairs in Table 1 and FIG.
- the above result satisfies the dislocation density (10 6 cm ⁇ 2 order) required for manufacturing a vertical power transistor using a blue laser pickup or Si or SiC. It can be seen that the nitride semiconductor substrate according to the embodiment can be used for manufacturing a blue laser for a pickup and a vertical power transistor used for Blu-Ray even though it is formed on a sapphire substrate.
- dislocation density is reduced as the number of pairs increases, by reducing the further dislocation density further increase the number of pairs, 10 4 that is required for a blue laser for writing to be used in the Blu-Ray It is expected that a cm ⁇ 2 order can be achieved.
- nitriding that enables the manufacture of a high-quality nitride semiconductor using an inexpensive sapphire substrate or the like.
- a physical semiconductor substrate can be provided. Further, since the nitride layer can be formed on the entire surface of the substrate, the area can be increased and the utility is excellent.
- nitride semiconductor bulk substrate can be obtained, so that there is a possibility that the use of the nitride semiconductor substrate for semiconductor devices can be further expanded.
- Nitride semiconductor substrate 1
- Sapphire substrate 2
- Nitride semiconductor layer (buffer layer) 21
- Eu-doped GaN layer 30
- LT-GaN layer 40 ud-GaN layer
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Abstract
Description
基材上に窒化物半導体層が形成された窒化物半導体基板であって、
前記窒化物半導体層が、
ドーピング材料が添加されていないアンドープ窒化物層と、
ドーピング材料として希土類元素が添加された希土類元素添加窒化物層とが積層されて形成されており、
前記窒化物半導体層の表面における転位密度が106cm-2オーダー以下であることを特徴とする窒化物半導体基板である。
前記窒化物半導体層における窒化物が、GaN、InN、AlN、またはこれらのいずれか2つ以上の混晶であることを特徴とする請求項1に記載の窒化物半導体基板である。
前記希土類元素が、Euであることを特徴とする請求項1または請求項2に記載の窒化物半導体基板である。
前記Euの添加量が、0.01~2原子%であることを特徴とする請求項3に記載の窒化物半導体基板である。
前記アンドープ窒化物層と前記希土類元素添加窒化物層との積層回数が1回であり、
前記アンドープ窒化物層の厚みが0.1~50nm、
前記希土類元素添加窒化物層の厚みが0.1~2000nmであることを特徴とする請求項1ないし請求項4のいずれか1項に記載の窒化物半導体基板である。
前記アンドープ窒化物層と、前記希土類元素添加窒化物層とが複数回積層されて、超格子構造によって前記窒化物半導体層が形成されており、
前記アンドープ窒化物層の厚みが0.1~50nm、
前記希土類元素添加窒化物層の厚みが0.1~200nmであることを特徴とする請求項1ないし請求項4のいずれか1項に記載の窒化物半導体基板である。
積層回数が2~300回であることを特徴とする請求項6に記載の窒化物半導体基板である。
総厚が3μm以下であることを特徴とする請求項1ないし請求項7のいずれか1項に記載の窒化物半導体基板である。
前記基材がサファイア、SiC、Si、GaNのいずれかであることを特徴とする請求項1ないし請求項8のいずれか1項に記載の窒化物半導体基板である。
基材上に窒化物半導体層が形成された窒化物半導体基板であって、
前記窒化物半導体層が、局所的な歪が異なる2以上の窒化物層が交互に積層された構造を有しており、
前記窒化物半導体層の表面における転位密度が106cm-2オーダー以下であることを特徴とする窒化物半導体基板である。
基材側からの転位の少なくとも一部が、前記窒化物半導体層の前記交互に積層された構造において曲げられて、表面に到達するまでに消滅していることを特徴とする請求項10に記載の窒化物半導体基板である。
前記窒化物半導体層が、前記基材から取り外されて窒化物半導体バルク基板として形成されていることを特徴とする請求項10または請求項11に記載の窒化物半導体基板である。
請求項1ないし請求項12のいずれか1項に記載の窒化物半導体基板を用いて作製されていることを特徴とする半導体デバイスである。
発光デバイス、高周波デバイス、高出力デバイスのいずれかであることを特徴とする請求項13に記載の半導体デバイスである。
基材上に窒化物半導体層が形成された窒化物半導体基板の製造方法であって、
基材上にGaN、InN、AlN、またはこれらのいずれか2つ以上の混晶を成長させて、ドーピング材料が添加されていないアンドープ窒化物層を形成する工程と、
前記アンドープ窒化物層の上に、GaN、InN、AlN、またはこれらのいずれか2つ以上の混晶を母体材料とし、ドーピング材料として希土類元素をGa、InあるいはAlと置換するように添加することにより、希土類元素添加窒化物層を形成する工程とを備えており、
前記2つの工程を、有機金属気相エピタキシャル法を用いて、900~1200℃の温度条件の下で、反応容器から取り出すことなく一連の形成工程によって行うことを特徴とする窒化物半導体基板の製造方法である。
前記アンドープ窒化物層を形成する工程と、
前記希土類元素添加窒化物層を形成する工程とを、
交互に、複数回繰り返し行うことを特徴とする請求項15に記載の窒化物半導体基板の製造方法である。
前記希土類元素として、Euを用いることを特徴とする請求項15または請求項16に記載の窒化物半導体基板の製造方法である。
Euを、Eu{N[Si(CH3)3]2}3、Eu(C11H19O2)3、Eu[C5(CH3)4(C3H7)]2のいずれかにより供給することを特徴とする請求項17に記載の窒化物半導体基板の製造方法である。
前記基材として、サファイア、SiC、Si、GaNのいずれかを用いることを特徴とする請求項15ないし請求項18のいずれか1項に記載の窒化物半導体基板の製造方法である。
さらに、基材上に形成された窒化物半導体層を前記基材から取り外して、窒化物半導体バルク基板とする工程を備えていることを特徴とする請求項15ないし請求項19のいずれか1項に記載の窒化物半導体基板の製造方法である。
本実施の形態においては、サファイア基材上に、アンドープ窒化物層(ud-GaN層)と、希土類元素としてEuが添加された希土類元素添加窒化物層(Eu添加GaN層)とが1層ずつ積層されて、窒化物半導体層が形成された窒化物半導体基板について説明する。
最初に本実施の形態に係る窒化物半導体基板の基本的な構成について説明する。図1は、本実施の形態に係る窒化物半導体基板の構成を示す模式図である。図1において、1は窒化物半導体基板、10はサファイア基材、20はud-GaN層21およびEu添加GaN層22をペアとして1回積層した窒化物半導体層である。
次に、本実施の形態に係る窒化物半導体基板の製造方法について、厚み10nmのud-GaN層21および厚み300nmのEu添加GaN層22を積層して窒化物半導体基板1を製造した例を挙げて、具体的に説明する。
(1)TEM画像に基づく評価
上記で得られた窒化物半導体基板の表面における転位密度について、まず、透過型電子顕微鏡(TEM)を用いて断面を観察して、転位密度の低減効果について評価した。
次に、窒化物半導体層(バッファー層)の形成の前後において表面に現われた転位の様子を原子間力顕微鏡(AFM)により観察して、転位密度の低減効果について評価した。なお、観察は1μm四方の同じ箇所で行った。
本発明者は、さらに、Eu添加GaN層の厚みと転位密度との関係について評価するために、上記と同様にして、厚み10nmのud-GaN層上に、Eu添加GaN層を厚み900nmまで成長させ、厚みが転位密度にどのように影響するのか評価した。
ここで、本実施の形態における転位密度の伝播について、図5を用いて説明する。なお、図5は、上記で作製された窒化物半導体基板の断面を特定の方向、具体的には、上向きg=[002]およびg=[110]方向から観察したTEM画像であり、それぞれを上下に配置して示している。
以上のように、本実施に形態においては、安価なサファイア基材上に、ud-GaN層とEu添加GaN層を適切な厚みで1回積層するという簡便な方法で、106cm-2オーダー以下という十分に低転位密度の窒化物半導体基板を得ることができるため、高性能、長寿命の半導体デバイスを安価に提供するという近年の要請に好適に応えることができる。
上記した第1の実施の形態においては、ud-GaN層の上に積層されるEu添加GaN層の厚みの増加に合わせて転位密度を低減させることができるが、Eu添加GaN層が厚くなり過ぎると、基材であるサファイアと窒化物半導体層のGaNとでは熱膨張係数に差があるためサファイアと窒化物半導体層との界面に反りが発生して、窒化物半導体基板として使用できなくなる恐れがある。
最初に本実施の形態に係る窒化物半導体基板の基本的な構成について説明する。図6は、本実施の形態に係る窒化物半導体基板の構成を示す模式図である。なお、図6における符号は窒化物半導体基板が2である以外は図1と同様である。図6より分かるように、本実施の形態においては、窒化物半導体層20が、Eu添加GaN層22とud-GaN層21を交互に複数回積層されており、また、Eu添加GaN層22の酸化を抑制するという観点から最表層にud-GaN層21が形成されている点を除いては、第1の実施の形態に係る窒化物半導体基板と同様の構成となっている。
そして、本実施の形態に係る窒化物半導体基板2の製造方法についても、ud-GaN層21とEu添加GaN層22の形成を繰り返しながら行って、ud-GaN層21とEu添加GaN層22の複数ペアを積層することを除いては、第1の実施の形態に係る窒化物半導体基板の製造方法と同様である。なお、本実施の形態においても、各層の形成は、途中で試料を反応管より取り出すことなく、成長の中断がないように一連の工程で行った。
(1)AFM画像に基づく評価
上記した窒化物半導体基板の製造方法を用い、厚み10nmのud-GaN層21および厚み1nmのEu添加GaN層22を、交互に40回(40ペア)積層して作製された窒化物半導体基板2の転位密度について、第1の実施の形態と同様に、AFM画像に基づいて転位密度の低減効果を評価した。
次に、ペア数(積層回数)の転位密度低減への影響を調べるために、上記した窒化物半導体基板の製造方法を用い、厚み10nmのud-GaN層21および厚み3nmのEu添加GaN層22を交互に積層して、ペア数(積層回数)を13(実験A)、40(実験B)、70(実験C)と変えた3種類の窒化物半導体層が形成された窒化物半導体基板2について、それぞれ転位密度を測定した。
10 サファイア基材
20 窒化物半導体層(バッファー層)
21 ud-GaN層
22 Eu添加GaN層
30 LT-GaN層
40 ud-GaN層
Claims (20)
- 基材上に窒化物半導体層が形成された窒化物半導体基板であって、
前記窒化物半導体層が、
ドーピング材料が添加されていないアンドープ窒化物層と、
ドーピング材料として希土類元素が添加された希土類元素添加窒化物層とが積層されて形成されており、
前記窒化物半導体層の表面における転位密度が106cm-2オーダー以下であることを特徴とする窒化物半導体基板。 - 前記窒化物半導体層における窒化物が、GaN、InN、AlN、またはこれらのいずれか2つ以上の混晶であることを特徴とする請求項1に記載の窒化物半導体基板。
- 前記希土類元素が、Euであることを特徴とする請求項1または請求項2に記載の窒化物半導体基板。
- 前記Euの添加量が、0.01~2原子%であることを特徴とする請求項3に記載の窒化物半導体基板。
- 前記アンドープ窒化物層と前記希土類元素添加窒化物層との積層回数が1回であり、
前記アンドープ窒化物層の厚みが0.1~50nm、
前記希土類元素添加窒化物層の厚みが0.1~2000nmであることを特徴とする請求項1ないし請求項4のいずれか1項に記載の窒化物半導体基板。 - 前記アンドープ窒化物層と、前記希土類元素添加窒化物層とが複数回積層されて、超格子構造によって前記窒化物半導体層が形成されており、
前記アンドープ窒化物層の厚みが0.1~50nm、
前記希土類元素添加窒化物層の厚みが0.1~200nmであることを特徴とする請求項1ないし請求項4のいずれか1項に記載の窒化物半導体基板。 - 積層回数が2~300回であることを特徴とする請求項6に記載の窒化物半導体基板。
- 総厚が3μm以下であることを特徴とする請求項1ないし請求項7のいずれか1項に記載の窒化物半導体基板。
- 前記基材がサファイア、SiC、Si、GaNのいずれかであることを特徴とする請求項1ないし請求項8のいずれか1項に記載の窒化物半導体基板。
- 基材上に窒化物半導体層が形成された窒化物半導体基板であって、
前記窒化物半導体層が、局所的な歪が異なる2以上の窒化物層が交互に積層された構造を有しており、
前記窒化物半導体層の表面における転位密度が106cm-2オーダー以下であることを特徴とする窒化物半導体基板。 - 基材側からの転位の少なくとも一部が、前記窒化物半導体層の前記交互に積層された構造において曲げられて、表面に到達するまでに消滅していることを特徴とする請求項10に記載の窒化物半導体基板。
- 前記窒化物半導体層が、前記基材から取り外されて窒化物半導体バルク基板として形成されていることを特徴とする請求項10または請求項11に記載の窒化物半導体基板。
- 請求項1ないし請求項12のいずれか1項に記載の窒化物半導体基板を用いて作製されていることを特徴とする半導体デバイス。
- 発光デバイス、高周波デバイス、高出力デバイスのいずれかであることを特徴とする請求項13に記載の半導体デバイス。
- 基材上に窒化物半導体層が形成された窒化物半導体基板の製造方法であって、
基材上にGaN、InN、AlN、またはこれらのいずれか2つ以上の混晶を成長させて、ドーピング材料が添加されていないアンドープ窒化物層を形成する工程と、
前記アンドープ窒化物層の上に、GaN、InN、AlN、またはこれらのいずれか2つ以上の混晶を母体材料とし、ドーピング材料として希土類元素をGa、InあるいはAlと置換するように添加することにより、希土類元素添加窒化物層を形成する工程とを備えており、
前記2つの工程を、有機金属気相エピタキシャル法を用いて、900~1200℃の温度条件の下で、反応容器から取り出すことなく一連の形成工程によって行うことを特徴とする窒化物半導体基板の製造方法。 - 前記アンドープ窒化物層を形成する工程と、
前記希土類元素添加窒化物層を形成する工程とを、
交互に、複数回繰り返し行うことを特徴とする請求項15に記載の窒化物半導体基板の製造方法。 - 前記希土類元素として、Euを用いることを特徴とする請求項15または請求項16に記載の窒化物半導体基板の製造方法。
- Euを、Eu{N[Si(CH3)3]2}3、Eu(C11H19O2)3、Eu[C5(CH3)4(C3H7)]2のいずれかにより供給することを特徴とする請求項17に記載の窒化物半導体基板の製造方法。
- 前記基材として、サファイア、SiC、Si、GaNのいずれかを用いることを特徴とする請求項15ないし請求項18のいずれか1項に記載の窒化物半導体基板の製造方法。
- さらに、基材上に形成された窒化物半導体層を前記基材から取り外して、窒化物半導体バルク基板とする工程を備えていることを特徴とする請求項15ないし請求項19のいずれか1項に記載の窒化物半導体基板の製造方法。
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JPWO2018097102A1 (ja) | 2019-10-17 |
US20190280156A1 (en) | 2019-09-12 |
EP3546622A4 (en) | 2019-12-04 |
US11133435B2 (en) | 2021-09-28 |
CN110036144A (zh) | 2019-07-19 |
KR20190078654A (ko) | 2019-07-04 |
JP6876337B2 (ja) | 2021-05-26 |
EP3546622A1 (en) | 2019-10-02 |
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