WO2018076679A1 - 一种基于串行Flash控制器接收数据的方法及装置 - Google Patents

一种基于串行Flash控制器接收数据的方法及装置 Download PDF

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Publication number
WO2018076679A1
WO2018076679A1 PCT/CN2017/085779 CN2017085779W WO2018076679A1 WO 2018076679 A1 WO2018076679 A1 WO 2018076679A1 CN 2017085779 W CN2017085779 W CN 2017085779W WO 2018076679 A1 WO2018076679 A1 WO 2018076679A1
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delay
sampling
value
input data
unit
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PCT/CN2017/085779
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English (en)
French (fr)
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张康
张亚国
杨沛
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深圳市中兴微电子技术有限公司
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Priority to EP17863311.1A priority Critical patent/EP3534270A4/en
Publication of WO2018076679A1 publication Critical patent/WO2018076679A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller

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  • the present invention relates to the field of communications, and in particular, to a method and apparatus for receiving data based on a serial flash controller, and a computer storage medium.
  • the serial flash controller has a serial output clock and a serial input clock.
  • the flash controller outputs data to the flash chip by a serial output clock signal, and the flash controller samples the flash chip input with a serial input clock signal. data.
  • the delays on the line are the same, reaching the Flash chip almost simultaneously; and the data and serial input clock transmitted to the serial flash controller by the Flash chip.
  • the delay between the two is large on the line, and the serial input clock is smaller than the input data.
  • the margin of half cycle can only satisfy the correctly sampled data under low frequency conditions.
  • serial flash control An error occurred in the sampling of the data. It can be seen that the serial flash controller has a low serial clock frequency when receiving data from the flash chip, and it is difficult to meet higher speed data transmission.
  • embodiments of the present invention are directed to a method and apparatus for receiving data based on a serial flash controller, and a computer storage medium, which can improve data transmission speed between a serial flash controller and a flash chip.
  • an embodiment of the present invention provides a method for receiving data based on a serial flash controller, where the method includes:
  • the serial flash controller When the serial flash controller receives the input data sent by the flash memory chip, acquires a value of the sampling selection register, and determines a sampling delay time according to the value of the sampling selection register and the second working clock signal; the second working clock The signal is the working clock signal of the serial flash controller;
  • sampling start time is to start sampling the input data sent by the Flash chip by using the second working clock signal as a sampling signal. time.
  • the method further includes:
  • the frequency of the first working clock signal is less than the frequency of the second working clock signal.
  • the method further includes:
  • the value of the sample selection register is adjusted according to the sampling delay period coefficient.
  • the method further includes:
  • the delay coefficient is determined according to the delay of the input data and the delay precision of the clock buffer
  • the method when the input data is received from the Flash chip in the multiplex mode, before the value of the sample selection register is obtained, for each input data, the method further includes:
  • the arrival time of the input data is adjusted according to the delay buffer size.
  • an embodiment of the present invention further provides an apparatus for receiving data based on a serial flash controller, where the apparatus includes: a sampling delay unit, a sampling selection unit, and a sampling unit;
  • the sampling delay unit is configured to acquire a value of the sampling selection unit when the serial flash controller receives the input data sent by the flash memory chip, and determine a sampling delay according to the value of the sampling selection unit and the second working clock signal.
  • the second working clock signal is an operating clock signal of the serial flash controller;
  • the sampling unit is configured to perform sampling according to the sampling delay time to adjust the sampling start time to receive the input data, wherein the sampling start time is started by using the second working clock signal as a sampling signal The moment when the input data sent by the flash chip is sampled.
  • the device further includes: a sending unit,
  • the apparatus further includes: a delay sampling parameter configuration unit, configured to:
  • the value of the sampling selection unit is adjusted according to the sampling delay period coefficient.
  • the apparatus further includes: a delay buffer unit, a clock buffer unit, a clock buffer selection unit, and a data delay selection unit;
  • the delay buffer unit is configured to:
  • the device further includes: a delay buffer parameter configuration unit, configured to:
  • the delay coefficient is determined according to the delay size of the input data and the delay precision of the clock buffer unit;
  • the sampling delay unit, the sampling selection unit, the sampling unit, the transmitting unit, the delay sampling parameter configuration unit, the delay buffer unit, the clock buffer unit, the clock buffer selection unit, the data delay selection unit, and the delay buffer parameter configuration unit When performing processing, it can be implemented by a central processing unit (CPU), a digital signal processor (DSP), or a field-programmable gate array (FPGA).
  • CPU central processing unit
  • DSP digital signal processor
  • FPGA field-programmable gate array
  • Embodiments of the present invention also provide a computer storage medium storing computer executable instructions configured to perform the above method of receiving data based on a serial flash controller.
  • the method for receiving data based on the serial flash controller in the embodiment of the present invention when the serial flash controller receives the input data sent by the flash flash chip, acquires the value of the sampling selection register, according to the value of the sampling selection register and the The second working clock signal determines a sampling delay time; the second working clock signal is an operating clock signal of the serial flash controller; The delay time adjustment sampling start time is sampled to receive the input data; wherein the sampling start time is a time at which the input data sent by the Flash chip is started by using the second working clock signal as a sampling signal.
  • the serial input clock signal is cancelled, the input data is sampled by the working clock signal of the serial flash controller, and the sampling delay is performed at the beginning of sampling, while increasing the frequency of sampling the input data by the serial flash controller. It can receive stable input data, thereby increasing the rate at which the flash controller receives the input data of the flash chip, and speeds up the data transmission between the serial flash controller and the flash chip.
  • FIG. 1 is a schematic flowchart of a method for receiving data based on a serial flash controller according to Embodiment 1 of the present invention
  • FIG. 2 is a schematic structural diagram of an 8-level delay buffer selection unit according to Embodiment 2 of the present invention.
  • FIG. 3 is a schematic structural diagram of a delay buffer unit including a 32-level delay buffer selection unit according to Embodiment 2 of the present invention
  • FIG. 4 is a schematic structural diagram of an apparatus for receiving data based on a serial flash controller according to Embodiment 3 of the present invention.
  • FIG. 5 is a schematic structural diagram of another apparatus for receiving data based on a serial flash controller according to Embodiment 3 of the present invention.
  • FIG. 6 is a schematic structural diagram of a connection between QSPI and Flash according to Embodiment 4 of the present invention.
  • a first embodiment of the present invention provides a method for receiving data based on a serial flash controller. As shown in FIG. 1, the method includes:
  • serial flash controller receives the input data sent by the flash flash chip, Obtaining a value of the sampling selection register, determining a sampling delay time according to the value of the sampling selection register and the second working clock signal; the second working clock signal is an operating clock signal of the serial flash controller;
  • the method further includes: transmitting a preset first working clock signal to the flash memory chip; wherein the frequency of the first working clock signal is less than the frequency of the second working clock signal.
  • the serial flash controller Before the serial flash controller receives the input data output by the flash chip from the flash chip, the serial flash controller sends a first working clock signal to the flash chip, and when the flash chip sends data to the serial flash controller, the received data is received.
  • the first operational clock signal outputs data to the serial flash controller for the operational clock signal.
  • the serial flash controller sets the period or frequency of the first working clock signal, it can refer to its own working clock signal: the second working clock signal, the period of the first working clock signal is greater than the period of the second working clock signal, That is, the frequency of the first working clock signal is smaller than the frequency of the second working clock signal.
  • the frequency of the second working clock signal is 100 MHz
  • the frequency of the first working clock signal is 50 MHz.
  • the frequency of the first working clock signal in the embodiment of the present invention is greater than the frequency of the working clock signal of the flash chip in the prior art, so that the frequency of the output data of the flash chip is increased.
  • the serial flash controller When the serial flash controller receives the input data sent by the flash chip, before sampling the received data with the second clock signal, it is necessary to determine the sampling start time and obtain the value of the sampling selection register; according to the sampling selection register a value and the second operational clock signal determine a sampling delay time;
  • the sampling selection register is used to determine the number of cycles that need to be delayed at the sampling start time
  • the value of the sampling selection register is used as the number of cycles of the sampling delay
  • the sampling delay time is determined by using the second working clock signal as the delay clock. The sampling start time is delayed.
  • the sampling delay period coefficient is used as the value of the sampling selection register, and the sampling time is controlled by the value of the sampling selection register, so that the sampling start time relatively delays the delay time of the input data.
  • the sampling delay time is determined to be 2*10 ns, that is, 20 ns, and the sampling starts. The time is delayed by 20ns.
  • the value of the sampling selection register is determined according to the delay of the input data.
  • the specific details are: determining a sampling delay period coefficient according to the second working clock signal and the delay of the input data; The time period coefficient adjusts the value of the sample select register.
  • the timing of starting the sampling is adjusted according to the delay of the input data and the period during which the current serial flash controller receives the input data, that is, the period of the second working clock signal.
  • the user can configure the value of the sampling selection register according to the delay of the data received by the serial flash controller according to actual needs, so that when sampling, directly obtain the value of the sampling selection register to adjust the sampling start. time.
  • the method further includes: according to the delay of the input data and the delay precision of the clock buffer. Determining a delay coefficient; determining a value of a clock buffer selection register and a value of a data delay selection register according to the delay coefficient.
  • the method Before receiving the input data, before acquiring the value of the sampling selection register, for each input data, the method further includes: obtaining a value of the clock buffer selection register, a value of the data delay selection register; and selecting a register according to the clock buffer a value, a value of the data delay selection register, and a delay precision of the clock buffer to determine a delay buffer size of the input data;
  • the time buffer size adjusts the arrival time of the input data.
  • the input of the clock buffer selection register and the data delay selection register are respectively added and then multiplied to obtain a delay coefficient, which represents that the clock buffer needs to be delayed.
  • the number of cycles is multiplied by the delay coefficient of the clock buffer to obtain the delay buffer size of the data, and the time when the transmitted data reaches the serial flash controller is buffered.
  • the value range of the data delay selection register and the clock buffer selection register is determined according to the number of bits of the register. For example, when the data delay selection register is a 5-bit register, the value ranges from 0 to 31, and the clock buffer is selected. When the register is a 3-bit register, its value ranges from 0-7.
  • the delay coefficient may be a value obtained by multiplying the value of the data delay selection register and the value of the clock buffer selection register by 1 respectively, and the data delay selection register is a 5-bit register and the clock buffer selection register is a 3-bit register.
  • the delay buffer of the input data is The size is (6+1)*(1+1)*50ps is 14*50ps. That is, for the input data received by the channel, a delay of 14*50 ps is delayed, and the time for the data to reach the serial flash control is delayed by 14*50 ps.
  • the value of the register starts from 0. Therefore, the number of output stages of the actually set register is greater than the value of the register, for example: A register with a bit width of 3, when the value of the register is 0, indicates that the output level of the register is 1.
  • the setting or adjustment of the value of each register can be preset by the user,
  • the setting of the body is determined according to the delay amount of the received data of the way and the delay precision of the clock buffer, and the delay coefficient is determined according to the delay amount of the data and the delay precision of the clock buffer, and the clock buffer selection register is further determined.
  • the value and data delay select the value of the register. For example, when the delay coefficient is 14, the value of the clock buffer selection register can be set to 6, and the data delay selection register is 1, the delay coefficient is (6+1)*. (1+1).
  • the delay buffer size of the input data before reaching the serial flash controller is controlled by the modification of the values of the clock buffer selection register and the data delay selection register.
  • the delay buffer adjustment may not be performed.
  • sampling start time is adjusted according to the sampling delay time to perform sampling to receive the input data.
  • the sampling start time is an input that is sent to the Flash chip by using the second working clock signal as a sampling signal. The moment when the data is sampled.
  • the timing at which the serial flash controller starts sampling the input data is adjusted, and the input data is sampled from the sampling start time to receive the data transmitted by the flash chip.
  • the determined delay time includes a delay of the flash chip when the data is outputted, and a delay that exists when the data is transmitted through the connection between the flash chip and the serial flash controller; the delay of the input data It can also include Flash chip output delay, wiring, PAD and delay buffering.
  • the sampling start time of the data received by the serial flash controller is adjusted.
  • the serial flash controller takes the delay into consideration when receiving the input data, and obtains stable stability.
  • the input data avoids the situation where the target data sampled when starting sampling data has not reached the serial flash controller.
  • the sampling start time is adjusted, so that the sampling is obtained at the time of sampling. The data is valid input data.
  • a method for receiving data based on a serial flash controller provided by an embodiment of the present invention is described by taking QSPI as an example.
  • QSPI is an extension of the SPI interface, and is a serial flash controller that supports NorFlash operation. And NandFlash operation.
  • the bit width of the clock buffer selection register described is 3 bits, which can be expressed as clkbufsel[2:0]
  • the bit width of the data delay selection register is 5 bits, which can be expressed as datdlysel[4:0 ]
  • the sample select register has a bit width of 3 bits and can be expressed as samplesel[2:0].
  • the eight clock buffers clkbuf are concatenated into a clkbuf chain, and the clkbufsel register is set to select which level of output from the 8-level delay buffer selection register, and the delay range is 1-8 clock buffers.
  • 32 qspi_clkbuf units are connected in series to form a link, and the datdlysel register is set to select which level of qspi_clkbuf output from the 32-level qspi_clkbuf selection unit, in the range of 1-32.
  • the value of the qspi_clkbuf unit for each level is determined by the clkbufsel register. The value ranges from 0 to 7.
  • the delay coefficient is calculated as (datdlysel+1)*(clkbufsel+1).
  • the delay range of each input data is 1-256 clock buffers.
  • the delay precision of each clock buffer clkbuf is 50ps
  • the maximum delay of qspi_clkbuf is 8*50ps
  • the delay of each input data of QSPI is adjusted to overcome the problem that the output data of the Flash chip cannot reach QSPI at the same time.
  • clkbufsel has a value of 3 ⁇ b001 and datdlysel has a value of 5 ⁇ b00111, where 3 ⁇ b001 represents a binary value with a bit width of 3 and a value of 5 represents a binary value with a bit width of 5 and a value of 7.
  • the input data of QSPI will increase the delay of (1+1)*(7+1)*50ps or 16*50ps.
  • QSPI uses the working clock to sample data, and the samplesel register controls the time at which the delay sampling starts.
  • the delay range is 0-7 working clock cycles. Assume that the operating clock frequency of QSPI is 100MHz, the clock period is 10ns, the serial output clock frequency is 50MHz, the output data of the flash chip takes about 8ns, the data is transmitted to the QSPI via the connection, etc. It takes about 5ns, and the delay is about 13ns in total. Set to 3 ⁇ b010 to sample stable input data.
  • the delay of the input data is 13 ns
  • the clock period of the QSPI operating clock is 10 ns.
  • the input data is not received within 10 ns of the first cycle, and the data is received at the 3 ns of the second cycle.
  • Set samplesel to 2 perform a delay of 2 sampling periods, and start sampling at the beginning of the third sampling period.
  • the embodiment of the present invention further provides a data receiving by using a serial flash controller.
  • the device includes: a sampling delay unit 401, a sampling selection unit 402, and a sampling unit 403, where
  • the sampling delay unit 401 is configured to: when the serial flash controller receives the input data sent by the flash memory chip, acquire the value of the sampling selecting unit 402, and determine the sampling delay according to the value of the sampling selecting unit and the second working clock signal.
  • the second working clock signal is an operating clock signal of the serial flash controller;
  • the sampling unit 403 is configured to perform sampling according to the sampling delay time to adjust the sampling start time to receive the input data, where the sampling start time is to start the pair of flashes by using the second working clock signal as a sampling signal The moment when the input data sent by the chip is sampled.
  • the device further includes: a sending unit 404, configured to send a preset first working clock signal to the flash memory chip; wherein, the frequency of the second working clock signal is greater than the first working clock The frequency of the signal.
  • a sending unit 404 configured to send a preset first working clock signal to the flash memory chip; wherein, the frequency of the second working clock signal is greater than the first working clock The frequency of the signal.
  • the device further includes: a delayed sampling parameter configuration unit 405 configured to:
  • the apparatus further includes: a delay buffer unit 406, a clock buffer unit 407, a clock buffer selection unit 408, and a data delay selection unit 409; the delay buffer unit 406 is configured to: when in the multiplex mode When receiving the input data from the flash chip, before acquiring the value of the sample selection register, for each input data, the value of the clock buffer selection unit 408, the value of the data delay selection unit 409 is obtained; according to the value of the clock buffer selection unit 408 The value of the data delay selecting unit 409 and the delay precision of the clock buffer unit 407 determine the delay buffer size of the input data; and adjust the arrival time of the input data according to the delay buffer size.
  • the device further includes: a delay buffer parameter configuration unit 410 configured to:
  • the delay coefficient is determined according to the delay size of the input data and the delay precision of the clock buffer unit 407; the value of the clock buffer selection unit 408 and the value of the data delay unit 409 are determined according to the delay coefficient. .
  • the clock buffer unit 407 can be implemented by a clock buffer
  • the sample selection unit 402, the clock buffer selection unit 408, and the data delay selection unit 409 can be respectively implemented by a register, which respectively correspond to the sampling selection register in the first embodiment.
  • a clock buffer selection register and a data delay selection register may be formed into a register unit, and a sampling selection register, a clock buffer selection register, and a clock buffer selection register are set in the register unit.
  • Data delay select register may be the same functional unit configured by the processor.
  • the QSPI of the four-wire transmission mode is taken as an example to describe a device for receiving data based on the serial flash controller of the delay buffer unit.
  • the four data input transmission lines between the QSPI and the Flash chip can be dat_in0, dat_in1, dat_in2, and dat_in3, respectively.
  • the description of the four-way data input is within the protection scope of the embodiment of the present invention.
  • the four-way data input may also be: dat_in1, dat_in2, dat_in3, and dat_in4.
  • the four input data transmission lines are respectively buffered by the corresponding data reception delay selection unit, that is, qspi_rxdatdly1, qspi_rxdatdly2, qspi_rxdatdly3, qspi_rxdatdly4, wherein the QSPI delay buffer selection unit qspi_rxdatdly is composed of qspi_rxdatdly1, qspi_rxdatdly2, qspi_rxdatdly3, qspi_rxdatdly4.
  • the data outputted by the flash chip is input to the control logic unit of QSPI through the qspi_rxdatdly delay buffer unit, the clock buffer selection register clkbufsel, the data delay selection register datdlysel, and the sample selection register samplesel are located in the register unit.
  • Reg unit the software can be configured through the APB interface.
  • the register unit reg unit is different from the clock of the control logic unit control logic, and the register value is passed to the control logic unit via the sync unit sync unit.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • the serial flash controller when the serial flash controller receives the input data sent by the flash memory chip, the value of the sampling selection register is obtained, according to the value of the sampling selection register.
  • the second working clock signal determines a sampling delay time; the second working clock signal is an operating clock signal of the serial flash controller; and the sampling start time is adjusted according to the sampling delay time to perform sampling to receive the input data;
  • the sampling start time is a time at which the input data sent by the Flash chip is started by using the second working clock signal as a sampling signal.
  • the serial input clock signal is cancelled, the input data is sampled by the working clock signal of the serial flash controller, and the sampling delay is performed at the beginning of sampling, while increasing the frequency of sampling the input data by the serial flash controller. It can receive stable input data, thereby increasing the rate at which the flash controller receives the input data of the flash chip, and speeds up the data transmission between the serial flash controller and the flash chip.

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Abstract

一种基于串行Flash控制器接收数据的方法、装置和计算机存储介质，该方法包括：当串行Flash控制器接收到闪存Flash芯片发送的输入数据时，获取采样选择寄存器的值，根据所述采样选择寄存器的值和第二工作时钟信号确定采样延时时间；所述第二工作时钟信号为串行Flash控制器的工作时钟信号（101）；根据所述采样延时时间调整采样开始时刻进行采样以接收所述输入数据；其中，所述采样开始时刻为以第二工作时钟信号为采样信号开始对所述Flash芯片发送的输入数据进行采样的时刻（102）。

Description

一种基于串行Flash控制器接收数据的方法及装置
相关申请的交叉引用
本申请基于申请号为201610934188.6、申请日为2016年10月31日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及通信领域，尤其涉及一种基于串行Flash控制器接收数据的方法及装置、计算机存储介质。
背景技术
目前，串行Flash控制器存在串行输出时钟和串行输入时钟，其中，Flash控制器以串行输出时钟信号将数据输出至Flash芯片，Flash控制器以串行输入时钟信号采样Flash芯片输入的数据。对于Flash控制器传输到Flash芯片的数据和串行输出时钟，二者经过线路上的延时相同，几乎同时到达Flash芯片；而对于Flash芯片传输到串行Flash控制器的数据和串行输入时钟，二者经过线路上的延时差异较大，串行输入时钟比输入数据的延时小。在Flash芯片下降沿发送数据，Flash控制器上升沿采样数据的情况下，半个周期的余量仅能满足低频条件下正确采样数据，对于更高频率的串行时钟来说，串行Flash控制器数据采样会发生错误。可见，串行Flash控制器从Flash芯片接收数据时的串行时钟频率较低，难以满足更高速度的数据传输。
因此，亟需一种基于串行Flash控制器接收数据的技术方案，以能够提高串行Flash控制器和Flash芯片之间的数据传输速度。
发明内容
有鉴于此，本发明实施例希望提供一种基于串行Flash控制器接收数据的方法及装置、计算机存储介质，能够提高串行Flash控制器和Flash芯片之间的数据传输速度。
本发明实施例的技术方案是这样实现的：
一方面，本发明实施例提供一种基于串行Flash控制器接收数据的方法，所述方法包括：
当串行Flash控制器接收到闪存Flash芯片发送的输入数据时，获取采样选择寄存器的值，根据所述采样选择寄存器的值和第二工作时钟信号确定采样延时时间；所述第二工作时钟信号为串行Flash控制器的工作时钟信号；
根据所述采样延时时间调整采样开始时刻进行采样以接收所述输入数据；其中，所述采样开始时刻为以第二工作时钟信号为采样信号开始对所述Flash芯片发送的输入数据进行采样的时刻。
在上述方案中，所述方法还包括：
发送预设的第一工作时钟信号至闪存Flash芯片；
其中，所述第一工作时钟信号的频率小于所述第二工作时钟信号的频率。
在上述方案中，所述方法还包括：
根据所述第二工作时钟信号和所述输入数据的延时大小确定采样延时周期系数；
根据所述采样延时周期系数调整采样选择寄存器的值。
在上述方案中，对于每一路输入数据，所述方法还包括：
根据输入数据的延时大小和时钟缓冲器的延时精度确定延时系数；
根据所述延时系数确定时钟缓冲选择寄存器的值和数据延时选择寄存 器的值。
在上述方案中，当以多路传输模式从所述Flash芯片接收输入数据时，获取采样选择寄存器的值之前，对于每一路输入数据，所述方法还包括：
获取时钟缓冲选择寄存器的值、数据延时选择寄存器的值；
根据所述时钟缓冲选择寄存器的值、所述数据延时选择寄存器的值和时钟缓冲器的延时精度确定输入数据的延时缓冲大小；
根据所述延时缓冲大小调整输入数据的达到时间。
一方面，本发明实施例还提供一种基于串行Flash控制器接收数据的装置，所述装置包括：采样延时单元、采样选择单元和采样单元；其中，
所述采样延时单元，配置为当串行Flash控制器接收到闪存Flash芯片发送的输入数据时，获取采样选择单元的值，根据所述采样选择单元的值和第二工作时钟信号确定采样延时时间；所述第二工作时钟信号为串行Flash控制器的工作时钟信号；
所述采样单元，配置为根据所述采样延时时间调整采样开始时刻进行采样以接收所述输入数据；其中，所述采样开始时刻为以所述第二工作时钟信号为采样信号开始对所述Flash芯片发送的输入数据进行采样的时刻。
在上述方案中，所述装置还包括：发送单元，
配置为发送预设的第一工作时钟信号至闪存Flash芯片；其中，所述第二工作时钟信号的频率大于所述第一工作时钟信号的频率。
在上述方案中，所述装置还包括：延时采样参数配置单元，配置为：
根据所述第二工作时钟信号和所述输入数据的延时大小确定采样延时周期系数；
根据所述采样延时周期系数调整所述采样选择单元的值。
在上述方案中，所述装置还包括：延时缓冲单元、时钟缓冲单元、时钟缓冲选择单元和数据延时选择单元；
其中，所述延时缓冲单元配置为：
当以多路传输模式从所述Flash芯片接收输入数据时，获取采样选择寄存器的值之前，对于每一路输入数据，获取时钟缓冲选择单元的值、数据延时选择单元的值；
根据所述时钟缓冲选择单元的值、所述数据延时选择单元的值和时钟缓冲单元的延时精度确定输入数据的延时缓冲大小；根据所述延时缓冲大小调整输入数据的到达时间。
在上述方案中，所述装置还包括：延时缓冲参数配置单元，配置为：
对于每一路输入数据，根据输入数据的延时大小和所述时钟缓冲单元的延时精度确定延时系数；
根据所述延时系数确定所述时钟缓冲选择单元的值和所述数据延时选择单元的值。
所述采样延时单元、采样选择单元、采样单元、发送单元、延时采样参数配置单元、延时缓冲单元、时钟缓冲单元、时钟缓冲选择单元、数据延时选择单元、延时缓冲参数配置单元在执行处理时，可以采用中央处理器(CPU，Central Processing Unit)、数字信号处理器(DSP，Digital Singnal Processor)或可编程逻辑阵列(FPGA，Field－Programmable Gate Array)实现。
本发明实施例还提供一种计算机存储介质，其中存储有计算机可执行指令，该计算机可执行指令配置执行上述基于串行Flash控制器接收数据的方法。
本发明实施例的基于串行Flash控制器接收数据的方案，当串行Flash控制器接收到闪存Flash芯片发送的输入数据时，获取采样选择寄存器的值，根据所述采样选择寄存器的值和第二工作时钟信号确定采样延时时间；所述第二工作时钟信号为串行Flash控制器的工作时钟信号；根据所述采样 延时时间调整采样开始时刻进行采样以接收所述输入数据；其中，所述采样开始时刻为以所述第二工作时钟信号为采样信号开始对所述Flash芯片发送的输入数据进行采样的时刻。如此，取消串行输入时钟信号，通过串行Flash控制器的工作时钟信号进行输入数据的采样，并在采样开始时，进行采样延时，在提高串行Flash控制器采样输入数据的频率的同时，能够接收到稳定的输入数据，从而提高Flash控制器接收Flash芯片的输入数据的速率，加快串行Flash控制器和Flash芯片之间的数据传输速度。
附图说明
图1为本发明实施例一提供的一种基于串行Flash控制器接收数据的方法的流程示意图；
图2为本发明实施例二提供的8级延时缓冲选择单元的结构示意图；
图3为本发明实施例二提供的包括32级延时缓冲选择单元的延时缓冲单元的结构示意图；
图4为本发明实施例三提供的一种基于串行Flash控制器接收数据的装置的结构示意图；
图5为本发明实施例三提供的另一种基于串行Flash控制器接收数据的装置的结构示意图；
图6为本发明实施例四QSPI与Flash连接结构示意图。
具体实施方式
下面结合附图对技术方案的实施作进一步的详细描述。
实施例一
本发明实施例一提供一种基于串行Flash控制器接收数据的方法，如图1所示，所述方法包括：
S101、当串行Flash控制器接收到闪存Flash芯片发送的输入数据时， 获取采样选择寄存器的值，根据所述采样选择寄存器的值和第二工作时钟信号确定采样延时时间；所述第二工作时钟信号为串行Flash控制器的工作时钟信号；
这里，所述方法还包括：发送预设的第一工作时钟信号至闪存Flash芯片；其中，所述第一工作时钟信号的频率小于所述第二工作时钟信号的频率。
当串行Flash控制器从Flash芯片接收Flash芯片输出的输入数据之前，串行Flash控制器向Flash芯片发送第一工作时钟信号，当Flash芯片向串行Flash控制器发送数据时，以接收到的第一工作时钟信号为工作时钟信号向串行Flash控制器输出数据。
这里，串行Flash控制器设置第一工作时钟信号的周期或频率时，可参考其自身的工作时钟信号：第二工作时钟信号，第一工作时钟信号的周期大于第二工作时钟信号的周期，即第一工作时钟信号的频率小于第二工作时钟信号的频率，比如：第二工作时钟信号的频率为100MHz，第一工作时钟信号的频率为50MHz。
这里需要说明的是，本发明实施例中的第一工作时钟信号的频率大于现有技术中的Flash芯片的工作时钟信号的频率，从而使得Flash芯片输出数据的频率提高。
当串行Flash控制器接收到Flash芯片发送的输入数据时，以第二时钟信号对接收到的数据进行采样之前，需确定采样开始时刻，获取采样选择寄存器的值；根据所述采样选择寄存器的值和所述第二工作时钟信号确定采样延时时间；
这里，采样选择寄存器用于确定采样开始时刻需要延时的周期数，以采样选择寄存器的值作为采样延时的周期数，以第二工作时钟信号为延时时钟来确定采样延时时间，将采样开始时刻进行延时。
这里，通过调整采样选择寄存器的值，将采样延时周期系数作为采样选择寄存器的值，通过采样选择存器的值来控制采样时间，使得采样开始的时刻相对延时了输入数据的延时大小，以接收稳定的输入数据。比如：当输入数据到达串行Flash控制器时，获取的采样选择寄存器的值为2，第二工作时钟信号的周期为10ns，则确定采样延时时间为2*10ns，即20ns，将采样开始时刻延迟了20ns。
其中，采样选择寄存器的值根据输入数据的延时大小进行确定，具体细节为：根据所述第二工作时钟信号和所述输入数据的延时大小确定采样延时周期系数；根据所述采样延时周期系数调整采样选择寄存器的值。当确定输入数据的延时大小后，根据输入数据的延时大小和当前串行Flash控制器接收输入数据时进行采样的周期即第二工作时钟信号的周期来调整开始采样的时刻，具体细节为：根据第二工作时钟信号的周期和输入数据的延时大小确定表征采样延时周期数的采样延时周期系数；通过采样延时周期系数控制采样选择寄存器的值来调整采样开始时刻。在实际应用中，用户可根据实际需要提前根据串行Flash控制器接收的数据的延时大小对采样选择寄存器的值进行配置，从而在进行采样时，直接获取采样选择寄存器的值来调整采样开始时刻。
这里，当串行Flash控制器以多路传输模式从所述Flash芯片接收输入数据时，对于每一路输入数据，所述方法还包括：根据输入数据的延时大小和时钟缓冲器的延时精度确定延时系数；根据所述延时系数确定时钟缓冲选择寄存器的值和数据延时选择寄存器的值。
当接收输入数据时，获取采样选择寄存器的值之前，对于每一路输入数据，所述方法还包括：获取时钟缓冲选择寄存器的值、数据延时选择寄存器的值；根据所述时钟缓冲选择寄存器的值、所述数据延时选择寄存器的值和时钟缓冲器的延时精度确定输入数据的延时缓冲大小；根据所述延 时缓冲大小调整输入数据的到达时间。
这里，当通过多路线路进行数据传输时，通过对每一路输入数据进行延时调整，使得Flash芯片的多路输入数据能够同时到达串行Flash控制器，每一路输入数据到达串行Flash控制器的时间保持一致，得到避免了一路输入数据已经到达而其他路输入数据还未到达的情况。
这里，对于每一级数据延时选择寄存器的输入都设置有时钟缓冲选择寄存器和数据延时选择寄存器的值分别加1后相乘得到延时系数，该延时系数表征时钟缓冲器需要延时的周期数，将延时系数与时钟缓冲器的延时精度相乘后得到该路数据的延时缓冲大小，将该路传输数据到达串行Flash控制器的时间进行了延时缓冲。
具体的，数据延时选择寄存器和时钟缓冲选择寄存器的取值范围根据寄存器的位数来确定，比如：数据延时选择寄存器为5位寄存器时，其取值范围为0-31，时钟缓冲选择寄存器为3位寄存器时，其取值范围为0-7。这里，延时系数可为数据延时选择寄存器的值和时钟缓冲选择寄存器的值分别加1后相乘得到的值，以数据延时选择寄存器为5位寄存器且时钟缓冲选择寄存器为3位寄存器为例，对于某一路输入数据，该路对应的时钟缓冲选择寄存器的值为6，数据延时选择寄存器为1，时钟缓冲器的延时精度为50ps时，则该路输入数据的延时缓冲大小为(6+1)*(1+1)*50ps为14*50ps。即对于该路接收的输入数据进行14*50ps的延时，将该路数据到达串行Flash控制的时间延迟了14*50ps。
需要说明的是，对于时钟缓冲选择寄存器、数据延时选择寄存器等寄存器而言，寄存器的值从0开始，因此，实际上设置的寄存器的输出级数相对于寄存器的值大1，比如：对于位宽为3的寄存器，当寄存器的值为0时，表示该寄存器的输出级数为1。
这里，对于各寄存器的值的设置或调整，可由用户进行预先设置，具 体的设置根据该路接收数据的延时大小和时钟缓冲器的延时精度来确定，根据数据的延时大小和时钟缓冲器的延时精度确定延时系数，进一步的确定时钟缓冲选择寄存器的值和数据延时选择寄存器的值，比如：当延时系数为14时，可设置时钟缓冲选择寄存器的值为6，数据延时选择寄存器为1，则延时系数为(6+1)*(1+1)。通过时钟缓冲选择寄存器和数据延时选择寄存器的值的修改来控制该路输入数据在到达串行Flash控制器之前的延时缓冲大小。
在实际应用中，当串行Flash控制器为单线传输模式时，则可不进行延时缓冲的调整。
S102、根据所述采样延时时间调整采样开始时刻进行采样以接收所述输入数据；其中，所述采样开始时刻为以所述第二工作时钟信号为采样信号开始对所述Flash芯片发送的输入数据进行采样的时刻。
当确定了延时时间后，对串行Flash控制器的对输入数据开始进行采样的时刻进行调整，从采样开始时刻对输入数据进行采样，从而接收Flash芯片发送的数据。
其中，确定的延时时间包括Flash芯片在输出数据时存在的延时，还包括在通过Flash芯片与串行Flash控制器之间的连线传输数据时存在的延时；输入数据的延时大小也可包括Flash芯片输出延时、连线、PAD和延时缓冲。
在本发明实施例中，对串行Flash控制器接收数据的采样开始时刻进行了调整。Flash芯片的输入数据在到达串行Flash控制器时，存在一定的延时大小，通过对采样开始时刻的调整，使得串行Flash控制器在接收输入数据时，将延时考虑进去，得到稳定的输入数据，避免了开始采样数据时所采样的目标数据还未达到串行Flash控制器的情况发生。并且由于第二工作时钟信号的频率大于第一工作时钟信号的频率，使得每一路输入数据的时序发生变化时，通过对采样开始时刻的调整，使得在采样的时候采样得到 的数据为有效的输入数据。
在本发明实施例中，(1)取消串行Flash控制器串行输入时钟信号，使用工作时钟采样输入数据；(2)对于多线模式，对于每一路输入数据，在串行Flash控制器的串行数据输入端口和Flash芯片数据输出端口之间增加延时缓冲；(3)设置延时时钟周期数，控制串行Flash控制器采样输入数据的时刻。
通过以上技术手段的采用，相对于现有的串行Flash控制器接收数据的技术方案，不仅提高了传输数据的速率，加快了串行Flash控制器和Flash芯片之间的数据传输速度，还解决数据经过PAD和连线等延迟到达Flash控制器而过早采样数据的问题，从而正确采样Flash芯片输出的数据，并能够分别设置每一路输入数据的延时大小，使得Flash芯片输出的数据同时到达串行Flash控制器。
实施例二
在本发明实施例中，以QSPI为例对本发明实施例提供的基于串行Flash控制器接收数据的方法进行说明，QSPI是SPI接口的扩展，作为一种串行Flash控制器，其支持NorFlash操作和NandFlash操作。在本实施例中，进行说明的时钟缓冲选择寄存器的位宽为3位，可以表示为clkbufsel[2:0]，数据延时选择寄存器的位宽为5位，可以表示为datdlysel[4:0]，采样选择寄存器的位宽为3位，可以表示为samplesel[2:0]。
如图2所示，由8个时钟缓冲器clkbuf串联成一个clkbuf链，设置clkbufsel寄存器，选择从8级延时缓冲选择寄存器的哪一级输出，延时范围为1-8个时钟缓冲。
如图3所示，由32个qspi_clkbuf单元串联成一个链路，设置datdlysel寄存器，选择从32级qspi_clkbuf选择单元的哪一级qspi_clkbuf输出，范围为1-32级。这里，对于每一级qspi_clkbuf单元的值由clkbufsel寄存器决 定，其取值范围为0-7。
延时系数的计算公式为(datdlysel+1)*(clkbufsel+1)，通过配置clkbufsel寄存器和datdlysel寄存器，每一路输入数据的延时范围为1-256个时钟缓冲。当每个时钟缓冲器clkbuf的延时精度为50ps，qspi_clkbuf的延时最大值为8*50ps，qspi_rxdatdly的延时最大值为8*50*32＝12800ps。
通过设置clkbufsel寄存器和datdlysel寄存器，调整QSPI每一路输入数据的延时大小，克服Flash芯片输出数据不能同时到达QSPI的问题。假设clkbufsel的值为3`b001，datdlysel的值为5`b00111，其中，3`b001表示位宽为3值为1的二进制数值，5`b00111表示位宽为5值为7的二进制数值。根据延时数值计算公式，则QSPI的某一路输入数据会增加(1+1)*(7+1)*50ps即16*50ps的延时。
这里，对于单线传输模式，不需要配置clkbufsel寄存器和datdlysel寄存器。
Flash芯片输出的数据送入QSPI经过延时调整后，QSPI使用工作时钟采样数据，samplesel寄存器控制延时采样开始的时刻，延时范围为0-7工作时钟周期。假设QSPI的工作时钟频率为100MHz，时钟周期为10ns，串行输出时钟频率为50MHz，Flash芯片输出数据大约需要8ns，数据经过连线等传输到QSPI大约需要5ns，延迟总共约为13ns，则samplesel设置为3`b010才能采样到稳定的输入数据。
这里，输入数据的延时大小为13ns，QSPI的工作时钟的时钟周期为10ns，则在第一个周期10ns内未接收到输入数据，在第二个周期的第3ns时接收到数据，因此，将samplesel设置为2，进行2个采样周期的延时，在第三个采样周期的开始时刻开始进行采样。
实施例三
为实现上述，本发明实施例还提供一种基于串行Flash控制器接收数据 的装置，如图4所示，所述装置包括：采样延时单元401、采样选择单元402和采样单元403，其中，
采样延时单元401，配置为当串行Flash控制器接收到闪存Flash芯片发送的输入数据时，获取采样选择单元402的值，根据所述采样选择单元的值和第二工作时钟信号确定采样延时时间；所述第二工作时钟信号为串行Flash控制器的工作时钟信号；
采样单元403，配置为根据所述采样延时时间调整采样开始时刻进行采样以接收所述输入数据；其中，所述采样开始时刻为以所述第二工作时钟信号为采样信号开始对所述Flash芯片发送的输入数据进行采样的时刻。
如图5所示，所述装置还包括：发送单元404，配置为发送预设的第一工作时钟信号至闪存Flash芯片；其中，所述第二工作时钟信号的频率大于所述第一工作时钟信号的频率。
在本发明实施例中，如图5所示，所述装置还包括：延时采样参数配置单元405，配置为：
根据所述第二工作时钟信号和所述输入数据的延时大小确定采样延时周期系数；根据所述采样延时周期系数调整所述采样选择单元402的值。
如图5所示，所述装置还包括：延时缓冲单元406、时钟缓冲单元407、时钟缓冲选择单元408和数据延时选择单元409；延时缓冲单元406配置为：当以多路传输模式从所述Flash芯片接收输入数据时，获取采样选择寄存器的值之前，对于每一路输入数据，获取时钟缓冲选择单元408的值、数据延时选择单元409的值；根据时钟缓冲选择单元408的值、数据延时选择单元409的值和时钟缓冲单元407的延时精度确定输入数据的延时缓冲大小；根据所述延时缓冲大小调整输入数据的达到时间。
在本实施例中，如图5所示，所述装置还包括：延时缓冲参数配置单元410，配置为：
对于每一路数据，根据输入数据的延时大小和时钟缓冲单元407的延时精度确定延时系数；根据所述延时系数确定所述时钟缓冲选择单元408的值和数据延时单元409的值。
在实际应用中，时钟缓冲单元407可由时钟缓冲器实现，采样选择单元402、时钟缓冲选择单元408和数据延时选择单元409可分别通过一寄存器实现，分别对应为实施例一中的采样选择寄存器、时钟缓冲选择寄存器和数据延时选择寄存器，这里，可将采样选择寄存器、时钟缓冲选择寄存器和数据延时选择寄存器组成一寄存器单元，在该寄存器单元中设置采样选择寄存器、时钟缓冲选择寄存器和数据延时选择寄存器。延时采样参数配置单元405和延时缓冲参数配置单元406可为通过处理器实现配置的同一功能单元。
实施例四
在本发明实施例中，以四线传输模式的QSPI为例，说明增加延时缓冲单元的基于串行Flash控制器接收数据的装置。
如图6所示，QSPI和Flash芯片之间的四路数据输入传输线，如图6所示，可以分别以dat_in0、dat_in1、dat_in2、dat_in3。只要能表示出四路数据输入的描述形式都在本发明实施例的保护范围之内，比如，该四路数据输入，还可以为：dat_in1、dat_in2、dat_in3、dat_in4。这四路输入数据传输线分别通过对应的数据接收延时选择单元进行延时缓冲，即qspi_rxdatdly1、qspi_rxdatdly2、qspi_rxdatdly3、qspi_rxdatdly4，其中，由qspi_rxdatdly1、qspi_rxdatdly2、qspi_rxdatdly3、qspi_rxdatdly4构成了QSPI延时缓冲选择单元qspi_rxdatdly。
如图6所示，Flash芯片输出的数据经过qspi_rxdatdly延时缓冲单元输入QSPI的控制逻辑单元control logic，时钟缓冲选择寄存器clkbufsel、数据延时选择寄存器datdlysel和采样选择寄存器samplesel位于寄存器单元 reg unit，软件可通过APB接口实现寄存器的配置。寄存器单元reg unit和控制逻辑单元control logic的时钟不同，寄存器值经过同步单元sync unit后传入控制逻辑单元中。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
采用本发明实施例，当串行Flash控制器接收到闪存Flash芯片发送的输入数据时，获取采样选择寄存器的值，根据所述采样选择寄存器的值和 第二工作时钟信号确定采样延时时间；所述第二工作时钟信号为串行Flash控制器的工作时钟信号；根据所述采样延时时间调整采样开始时刻进行采样以接收所述输入数据；其中，所述采样开始时刻为以所述第二工作时钟信号为采样信号开始对所述Flash芯片发送的输入数据进行采样的时刻。如此，取消串行输入时钟信号，通过串行Flash控制器的工作时钟信号进行输入数据的采样，并在采样开始时，进行采样延时，在提高串行Flash控制器采样输入数据的频率的同时，能够接收到稳定的输入数据，从而提高Flash控制器接收Flash芯片的输入数据的速率，加快串行Flash控制器和Flash芯片之间的数据传输速度。

Claims (11)

  1. 一种基于串行Flash控制器接收数据的方法，所述方法包括：
    当串行Flash控制器接收到闪存Flash芯片发送的输入数据时，获取采样选择寄存器的值，根据所述采样选择寄存器的值和第二工作时钟信号确定采样延时时间；所述第二工作时钟信号为串行Flash控制器的工作时钟信号；
    根据所述采样延时时间调整采样开始时刻进行采样以接收所述输入数据；其中，所述采样开始时刻为以第二工作时钟信号为采样信号开始对所述Flash芯片发送的输入数据进行采样的时刻。
  2. 根据权利要求1所述的方法，其中，所述方法还包括：
    发送预设的第一工作时钟信号至闪存Flash芯片；
    其中，所述第一工作时钟信号的频率小于所述第二工作时钟信号的频率。
  3. 根据权利要求1所述的方法，其中，所述方法还包括：
    根据所述第二工作时钟信号和所述输入数据的延时大小确定采样延时周期系数；
    根据所述采样延时周期系数调整采样选择寄存器的值。
  4. 根据权利要求1所述的方法，其中，对于每一路输入数据，所述方法还包括：
    根据输入数据的延时大小和时钟缓冲器的延时精度确定延时系数；
    根据所述延时系数确定时钟缓冲选择寄存器的值和数据延时选择寄存器的值。
  5. 根据权利要求4所述的方法，其中，当以多路传输模式从所述Flash芯片接收输入数据时，获取采样选择寄存器的值之前，对于每一路输入数 据，所述方法还包括：
    获取时钟缓冲选择寄存器的值、数据延时选择寄存器的值；
    根据所述时钟缓冲选择寄存器的值、所述数据延时选择寄存器的值和时钟缓冲器的延时精度确定输入数据的延时缓冲大小；
    根据所述延时缓冲大小调整输入数据的达到时间。
  6. 一种基于串行Flash控制器接收数据的装置，所述装置包括：采样延时单元、采样选择单元和采样单元；其中，
    所述采样延时单元，配置为当串行Flash控制器接收到闪存Flash芯片发送的输入数据时，获取采样选择单元的值，根据所述采样选择单元的值和第二工作时钟信号确定采样延时时间；所述第二工作时钟信号为串行Flash控制器的工作时钟信号；
    所述采样单元，配置为根据所述采样延时时间调整采样开始时刻进行采样以接收所述输入数据；其中，所述采样开始时刻为以所述第二工作时钟信号为采样信号开始对所述Flash芯片发送的输入数据进行采样的时刻。
  7. 根据权利要求6所述的装置，其中，所述装置还包括：发送单元，
    配置为发送预设的第一工作时钟信号至闪存Flash芯片；其中，所述第二工作时钟信号的频率大于所述第一工作时钟信号的频率。
  8. 根据权利要求6所述的装置，其中，所述装置还包括：延时采样参数配置单元，配置为：
    根据所述第二工作时钟信号和所述输入数据的延时大小确定采样延时周期系数；
    根据所述采样延时周期系数调整所述采样选择单元的值。
  9. 根据权利要求6所述的装置，其中，所述装置还包括：延时缓冲单元、时钟缓冲单元、时钟缓冲选择单元和数据延时选择单元；
    其中，所述延时缓冲单元配置为：
    当以多路传输模式从所述Flash芯片接收输入数据时，获取采样选择寄存器的值之前，对于每一路输入数据，获取时钟缓冲选择单元的值、数据延时选择单元的值；
    根据所述时钟缓冲选择单元的值、所述数据延时选择单元的值和时钟缓冲单元的延时精度确定输入数据的延时缓冲大小；根据所述延时缓冲大小调整输入数据的到达时间。
  10. 根据权利要求9所述的装置，其中，所述装置还包括：延时缓冲参数配置单元，配置为：
    对于每一路输入数据，根据输入数据的延时大小和所述时钟缓冲单元的延时精度确定延时系数；
    根据所述延时系数确定所述时钟缓冲选择单元的值和所述数据延时选择单元的值。
  11. 一种计算机存储介质，其中存储有计算机可执行指令，该计算机可执行指令配置执行上述权利要求1-5任一项所述的基于串行Flash控制器接收数据的方法。
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