WO2015176475A1 - Fifo数据缓存器及其进行时延控制的方法、计算机存储介质 - Google Patents

Fifo数据缓存器及其进行时延控制的方法、计算机存储介质 Download PDF

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WO2015176475A1
WO2015176475A1 PCT/CN2014/088772 CN2014088772W WO2015176475A1 WO 2015176475 A1 WO2015176475 A1 WO 2015176475A1 CN 2014088772 W CN2014088772 W CN 2014088772W WO 2015176475 A1 WO2015176475 A1 WO 2015176475A1
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data
state
transmission path
buffer
output port
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PCT/CN2014/088772
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English (en)
French (fr)
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汪八零
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深圳市中兴微电子技术有限公司
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Publication of WO2015176475A1 publication Critical patent/WO2015176475A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled

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  • the invention relates to a data buffering technology in an integrated circuit, in particular to a first input first output (FIFO) data buffer and a method for performing the delay control thereof.
  • FIFO first input first output
  • FIFO data buffers are widely used in digital integrated circuit design due to their first-in, first-out, balanced input and output processing rates.
  • the FIFO data buffer includes two parts: a control part and a storage part.
  • the storage portion in the large-capacity FIFO data buffer usually uses a Synchronous Static Random Access Memory (SSRAM) as an internal storage unit.
  • SSRAM Synchronous Static Random Access Memory
  • the SSRAM issues a write enable signal on the previous clock pulse signal, but the data can be written on the latter clock pulse signal; likewise, the read enable signal is issued on the previous clock cycle, but the next clock is generated.
  • the pulse period can read the data; therefore, the SSRAM as the internal memory unit of the FIFO data buffer will cause an increase in delay.
  • the FIFO data buffer implemented by this method has a large delay, when the system uses the FIFO data buffer. When it is sensitive to delay, it will cause the performance of the corresponding system to decrease.
  • embodiments of the present invention are directed to providing a FIFO data buffer and a method thereof for performing delay control, and a computer storage medium.
  • An embodiment of the present invention provides a FIFO data buffer, where the FIFO data buffer includes an input port, an output port, a control unit, a first cache unit, and a second cache unit.
  • the control unit is configured to acquire state information of a current output port of the FIFO data buffer, first data storage state information of the first cache unit, and second data storage state information of the second cache unit And determining a data transmission path according to the obtained status information of the output port, the first data storage status information, and the second data storage status information.
  • the transmission path includes a first transmission path, a second transmission path, a third transmission path, and a fourth transmission path.
  • the FIFO data buffer further includes: a first multiple selection unit and a second multiple selection unit;
  • the first transmission path is sequentially connected by an input port, a second multiple selection unit, and an output port;
  • the second transmission path is sequentially connected by an input port, a first multiple selection unit, a second buffer unit, a second multiple selection unit, and an output port;
  • the third transmission path is sequentially connected by an input port, a first buffer unit, a first multiple selection unit, a second buffer unit, a second multiple selection unit, and an output port;
  • the fourth transmission path is sequentially connected by an input port, a first buffer unit, a second multiple selection unit, and an output port.
  • control unit is configured to:
  • Presetting the delay of the first buffer unit is greater than the delay of the second buffer unit
  • the state of the current output port of the FIFO data buffer is a path state
  • the first data storage state is an empty state
  • the second data storage state is an empty state, determining to transmit data through the first transmission path
  • the first data storage state is an empty state
  • the second data storage state is an empty state, determining to pass the second transmission Path transmission data
  • the first data storage state is a non-empty state
  • the second data storage state is an empty state, determining to transmit data through the third data transmission path
  • the current output port status of the FIFO data buffer is a path state
  • the first data storage state is a non-empty state
  • the previous clock cycle of the current clock cycle has data from the third data transmission path or the fourth transmission.
  • the path reaches the output port, it is determined that the data is transmitted through the fourth data transmission path.
  • the first multiple selection unit and the second multiple selection unit are implemented by using a multiplexer.
  • the first buffer unit is implemented by using a RAM or an SSRAM; and the second buffer unit is implemented by using a register.
  • an embodiment of the present invention further provides a method for delay control of a FIFO data buffer, the method comprising:
  • the FIFO data buffer obtains state information of the current output port, first data storage state information, and second data storage state information; and according to the obtained output port state information, the first data storage state information, and the second data storage state information, Determine the transmission path of the data.
  • the transmission path includes a first transmission path, a second transmission path, a third transmission path, and a fourth transmission path.
  • the FIFO data buffer includes an input port, an output port, a control unit, a first buffer unit, a second buffer unit, a first multiple selection unit, and a second multiple selection unit.
  • the first transmission path is sequentially connected by an input port, a second multiple selection unit, and an output port;
  • the second transmission path is composed of an input port, a first multiple selection unit, a second buffer unit, The second multi-channel selection unit and the output port are sequentially connected;
  • the third transmission path is sequentially connected by an input port, a first buffer unit, a first multiple selection unit, a second buffer unit, a second multiple selection unit, and an output port;
  • the fourth transmission path is sequentially connected by an input port, a first buffer unit, a second multiple selection unit, and an output port.
  • the method further includes: presetting that a delay of the first cache unit is greater than a delay of the second cache unit;
  • the determining, according to the obtained status information of the output port, the first data storage state information, and the second data storage state information, determining a data transmission path including:
  • the first data storage state is an empty state
  • the second data storage state is an empty state
  • the first data storage state is an empty state
  • the second data storage state is an empty state, determining to transmit data through the second transmission path
  • the first data storage state is a non-empty state
  • the second data storage state is an empty state, determining to transmit data through the third data transmission path
  • the first data storage state is a non-empty state, and the data of the previous clock cycle of the current clock cycle has a data from the third data transmission path or the fourth transmission path to the output port. Then, it is determined that the data is transmitted through the fourth data transmission path.
  • Embodiments of the present invention provide a computer storage medium comprising a set of instructions that, when executed, cause at least one processor to perform the method of delay control of the FIFO data buffer described above.
  • the FIFO data buffer obtained by embodiment of the present invention and method and device for performing delay control thereof
  • the computer storage medium, the FIFO data buffer obtains state information of the current output port, the first data storage state information, and the second data storage state information; and according to the obtained output port state information, the first data storage state information, and the second
  • the data stores status information and determines the transmission path of the data.
  • the embodiment of the present invention can select different transmission paths of the data transmission according to the current output port state information, the first data storage state information, and the second data storage state information of the FIFO data buffer, so that the FIFO data buffer can Considering the large-capacity cache and the delay in the data transmission path, the large-capacity cache can be guaranteed while reducing the delay in data transmission.
  • FIG. 1 is a schematic structural diagram of a FIFO data buffer according to an embodiment of the present invention.
  • FIG. 2 is a schematic flowchart of an implementation method of delay control based on a FIFO data buffer according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a FIFO data buffer in scenario 1 according to an embodiment of the present invention.
  • the FIFO data buffer obtains state information of the current output port, the first data storage state information, and the second data storage state information; and according to the obtained output port state information, the first data storage state information, and the The second data stores state information to determine the data transmission path.
  • the embodiment of the present invention provides a FIFO data buffer, where the FIFO data buffer includes an input port and an output port. As shown in FIG. 1 , the FIFO data buffer further includes: a control list. a unit 100, a first cache unit 101, and a second cache unit 102; wherein
  • the control unit 100 is configured to acquire state information of a current output port of the FIFO data buffer, first data storage state information of the first cache unit 101, and second data of the second cache unit 102. And storing state information; determining a data transmission path according to the obtained state information of the output port, the first data storage state information, and the second data storage state information.
  • the status information of the output port includes a path status or a non-path status; the first data storage status information includes an empty status, a non-empty status, or a near full status; and the second data storage status information includes an empty status, a non- Empty state.
  • the transmission path may include four transmission paths: a first transmission path, a second transmission path, a third transmission path, and a fourth transmission path.
  • the FIFO data buffer further includes: a first multiple selection unit 103 and a second multiple selection unit 104;
  • the first multiplex selection unit 103 is configured to select input multiplexed data, and select one channel of data to output to the second cache unit;
  • the second multiple selection unit 104 is connected to the output port and configured to select the input multiple data to output to the output port.
  • first multiplex selection unit 103 and the second multiplex selection unit 104 are only configured to select multiplexed data, there is no delay effect on the transmission of data.
  • the first transmission path is sequentially connected by an input port, a second multiple selection unit 104, and an output port;
  • the second transmission path is sequentially connected by the input port, the first multiple selection unit 103, the second buffer unit 102, the second multiple selection unit 104, and the output port;
  • the third transmission path is sequentially connected by the input port, the first buffer unit 101, the first multiple selection unit 103, the second buffer unit 102, the second multiple selection unit 104, and the output port;
  • the fourth transmission path is sequentially connected by the input port, the first buffer unit 101, the second multiplexing unit 104, and the output port.
  • control unit 100 is further configured to control the first buffer unit 101, the second buffer unit 102, the first multiple selection unit 103, and the second multiple selection unit 104 to cooperate. To complete the control of each transmission path during data transmission; wherein the execution of each functional unit is triggered by the rising or falling edge of the clock pulse.
  • the delay of the first buffer unit 101 is preset to be greater than the delay of the second buffer unit 102. Therefore, the four transmission paths have different delays due to different transmission paths, and can simultaneously balance the data when transmitting data. The capacity is delayed, so that the data processing rate between the sender device and the sink device is matched.
  • the working principle of the FIFO data buffer is as follows:
  • the initial states of the first buffer unit 101 and the second buffer unit 102 are all set to an empty state
  • Manner 1 When data is transmitted, if the current state of the output port is the path state, the first data storage state is the empty state, and the second data storage state is the empty state, it is determined that the data is transmitted through the first transmission path.
  • the FIFO data buffer is triggered to receive the data sent by the transmitting device from the input port of the clock, and if the state of the output port at this time is the path state, the first data storage
  • the data is transmitted through the first transmission path, that is, the data received from the input port is transmitted to the output device through the output port without buffering, so that Data 0 delay transmission to the output device, suitable for scenarios sensitive to transmission delay, can be reduced
  • the data transmission delay between the input device and the output device is reduced, thereby improving the performance of the system.
  • Manner 2 If the current state of the output port is the non-path state, the first data storage state is an empty state, and the second data storage state is an empty state, determining to transmit data through the second transmission path.
  • the FIFO data buffer is triggered to receive the data sent by the transmitting device from the input port, and if the state of the output port at this time is the non-path state, the first data storage
  • the data is transmitted through the second transmission path, that is, since the delay of the first buffer unit 101 is greater than the delay of the second buffer unit 102,
  • the data received from the input port is first stored in the second buffer unit 102 having a relatively small delay.
  • the control unit 100 changes the state of the output port to the path state. At this time, the data in the second buffer unit 102 is first transmitted to the output port, which can reduce the data transmission process. The delay in the middle.
  • the state of the output port is a non-path state, and the data is first stored in the second buffer unit 102. If the output port status is still non-path state at the current time, the The transferred data is stored in the first buffer unit 101, and when the state of the output port is changed to the path state, the data in the second buffer unit 102 is first transmitted to the output port, so that the design of the FIFO data buffer conforms to the advanced first.
  • the design principle is
  • Manner 3 If the current state of the output port is a non-path state, the first data storage state is a non-empty state, and the second data storage state is an empty state, determining to transmit data through the third data transmission path.
  • the FIFO data buffer is triggered to receive the data sent by the transmitting device from the input port, and if the state of the output port is the non-path state, the first data storage state.
  • the first cache unit 101 is in a non-empty state.
  • the data in the first buffer unit 102 is moved to the second buffer unit 102, and when the state of the output port is changed to the path state, the data in the second buffer unit 102 is transmitted to the output port.
  • the fourth mode if the current state of the output port is the path state, the first data storage state is a non-empty state, and the data of the previous clock cycle of the current clock cycle arrives from the third data transmission path or the fourth transmission path.
  • the output port determines that data is transmitted through the fourth data transmission path.
  • the FIFO data buffer is triggered to receive data sent by the transmitting device from the input port. If the state of the output port is the path state, the first data storage state is In the non-empty state, the data in the first buffer unit 101 is directly transmitted to the output port, which can reduce the delay in the data transmission process.
  • the second buffer unit 102 with a small delay is used to buffer data, and when the state of the output port is changed to the path state, the data in the second buffer unit 102 can be directly output to the output port. It is to improve the response speed to the output port, thus reducing the response delay.
  • the first buffer unit 101 can be implemented by using a large-capacity RAM or SSRAM.
  • the minimum delay is two pulse periods.
  • the second buffer unit 102 can be implemented by a register.
  • the minimum delay is one pulse period;
  • the first multiplexing unit 103 and the The second multiplex selection unit 104 can be implemented with a multiplexer. Since the multiplexer is only configured to select multiplexed data, there is no delay effect on the transmission of data.
  • the data transmission delay corresponding to the first transmission path is 0 pulse periods
  • the second transmission path Corresponding data transmission delay is at least one pulse period
  • the data transmission delay corresponding to the third transmission path is at least three pulse periods
  • the data transmission delay corresponding to the fourth data transmission path is at least two pulses cycle.
  • the embodiment of the present invention further provides a method for performing delay control based on a FIFO data buffer. Since the principle and device of the method for solving the problem are similar, the implementation process and implementation principles of the method can be seen. The implementation process and implementation principle descriptions of the foregoing devices are not repeated here.
  • a method for performing delay control based on a FIFO data buffer includes:
  • Step S201 The FIFO data buffer acquires its current output port state information, first data storage state information, and second data storage state information.
  • Step S202 Determine a data transmission path according to the acquired output port state information, the first data storage state information, and the second data storage state information.
  • the transmission path includes a first transmission path, a second transmission path, a third transmission path, and a fourth transmission path.
  • the first transmission path is input
  • the second transmission path is sequentially connected by the input port, the first multiple selection unit, the second buffer unit, the second multiple selection unit, and the output port;
  • the third transmission path is sequentially connected by the input port, the first buffer unit, the first multiple selection unit, the second buffer unit, the second multiple selection unit, and the output port;
  • the fourth transmission path is input port, the first buffer The unit, the second multiple selection unit, and the output port are sequentially connected.
  • the delay of the first buffer unit is preset to be greater than the delay of the second cache unit
  • the specific implementation manner of determining the data transmission path is as follows:
  • the first data storage state is an empty state
  • the second data storage state is an empty state
  • the first data storage state is an empty state
  • the second data storage state is an empty state, determining to transmit data through the second transmission path
  • the first data storage state is a non-empty state
  • the second data storage state is an empty state, determining to transmit data through the third data transmission path
  • the first data storage state is a non-empty state, and the data of the previous clock cycle of the current clock cycle has a data from the third data transmission path or the fourth transmission path to the output port. Then, it is determined that the data is transmitted through the fourth data transmission path.
  • the FIFO data buffer obtains state information of the current output port, the first data storage state information, and the second data storage state information; and according to the obtained output port state information, the first data storage state information, and the The second data stores state information to determine the data transmission path.
  • the embodiment of the present invention can select different transmission paths of the data transmission according to the current output port state information, the first data storage state information, and the second data storage state information of the FIFO data buffer, so that the FIFO data buffer can Considering the large-capacity cache and the delay in the data transmission path, the large-capacity cache can be guaranteed while reducing the delay in data transmission.
  • the flow of the delay control of the FIFO data buffer in the embodiment of the present invention is described in detail in the following example.
  • the data processing and traffic condition evaluation of the device requires at least one FIFO data cache device with a depth of 1024 and a bit width of 64 to be sent to the sender device.
  • the sent data is buffered to achieve processing rate matching between the transmitting device and the receiving device.
  • the FIFO data buffer includes: one SSRAM, one register tempreg, and two multiplexers MUX. -0 and MUX-1, a controller Ctrl; where
  • the SSRAM, the scratchpad tempreg, the two multiplexers MUX-0 and MUX-1 form the data path of the FIFO data buffer, and the controller Ctrl serves as the control path for the FIFO data buffer.
  • the SSRAM specification is 1024 ⁇ 64, that is, the depth is 1024 and the bit width is 64.
  • MUX-0 is a 64-bit three-choice multiplexer, which selects which routing controller Ctrl sel0 control signal to control;
  • Temporeg is a 64-bit D flip-flop with an enable.
  • the enable signal is tempreg_we, and tempreg can only cache a 64-bit data.
  • MUX-1 is a 64-bit 3-to-1 multiplexer, specifically selecting the sel1 control signal of the routing controller Ctrl for control;
  • connection relationship of SSRAM, MUX-0, tempreg, MUX-1, input port and output port is shown in Figure 4.
  • the input data is from the input port to the output port.
  • the delay of the first transmission path is zero, the delay of the second transmission path is at least one pulse period, the delay corresponding to the third transmission path is at least three pulse periods, and the delay corresponding to the fourth transmission path is at least Two pulse periods.
  • the controller Ctrl is used as a controller of the FIFO data buffer to complete the control of the data transmission path, the receiving handshake control of the input data, and the sending handshake control of the output data.
  • the input information of the controller Ctrl includes:
  • the output information of the controller Ctrl includes:
  • the input data sent to the transmitting device can accept the status indication signal o_din_ready;
  • the working principle of the FIFO data buffer is as follows:
  • the FIFO data buffer is triggered to receive the data sent by the transmitting device from the input port, and if the output device can receive the data according to the i_dout_ready signal, the output port is controlled.
  • the path state a state of the path state; and determining, according to the cfifo_empty signal, that the first data storage state of the SSRAM is an empty state, and determining that the second data storage state of the D flip-flop is an empty state according to the tempreg_valid signal, determining to transmit data through the first transmission path, That is, the data received from the input port is transmitted to the output device through the output port without buffering, so that the data can be transmitted to the output device with zero delay, which is suitable for the scenario where the transmission delay is sensitive.
  • the data transfer speed between the input device and the output device improves the performance of the system.
  • the FIFO data buffer is triggered to receive the data sent by the sending device from the input port, if according to i_dout_ready
  • the signal determines that the output device is incapable of receiving data, and controls the output port state to be a non-path state, and determines that the first data storage state of the SSRAM is empty according to the cfifo_empty signal, and determines the second data storage state of the D flip-flop according to the tempreg_valid signal.
  • the state is empty, it is determined that the data is transmitted through the second transmission path, that is, the received data is first buffered into the D flip-flop, and when the output device can receive the data according to the i_dout_ready signal, when the output port state is changed to the path state At this time, the data of the second buffer in the D flip-flop will be transmitted to the output port through a delay of one pulse period, thereby improving the response speed of the FIFO data buffer to the output port and reducing the response delay.
  • the FIFO data buffer is triggered to receive the data sent by the transmitting device from the input port, and if the output device cannot determine the data according to the i_dout_ready signal, the control output is controlled.
  • the port state is a non-path state, and determining that the first data storage state of the SSRAM is a non-empty state according to the cfifo_aful signal, and determining that the second data storage state is an empty state according to the tempreg_valid signal, determining to transmit data through the third transmission path, that is,
  • the data in the SSRAM is moved to the D flip-flop to directly transfer the temporarily stored data in the D flip-flop to the output port through a pulse period delay when the output port state transitions to the path state, thereby improving the The response speed of the FIFO data buffer to the output port, corresponding to a delay of at least three pulse periods.
  • the FIFO data buffer is triggered to receive the data sent by the transmitting device from the input port, and if the output device can receive the data according to the i_dout_ready signal, the output port is controlled.
  • the state is a path state
  • the first data storage state of the SSRAM is determined to be a non-empty state according to the cfifo_aful signal, and data of the previous clock cycle of the current clock cycle has a data from the third data transmission path or the fourth transmission path to the output port, Then, it is determined that the data is transmitted through the fourth transmission path, that is, the data in the SSRAM does not need to be stored in the D flip-flop, but the data in the SSRAM is directly transmitted to the output port, and the corresponding delay is at least two pulse periods.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

一种先进先出（FIFO）数据缓存器，该FIFO数据缓存器包括：输入端口、输出端口、控制单元（100）、第一缓存单元（101）、第二缓存单元（102）；其中，所述控制单元（100），用于获取自身当前的输出端口的状态信息、所述第一缓存单元（101）的第一数据存储状态信息及所述第二缓存单元（102）的第二数据存储状态信息；根据获取的输出端口的状态信息、第一数据存储状态信息及第二数据存储状态信息，确定数据的传输通路。同时还包括一种基于FIFO数据缓存器进行时延控制的方法及计算机存储介质。

Description

FIFO数据缓存器及其进行时延控制的方法、计算机存储介质 技术领域
本发明涉及集成电路中数据缓存技术，尤其涉及一种先进先出(First Input First Output，FIFO)数据缓存器及其进行时延控制的方法。
背景技术
FIFO数据缓存器由于具备先进先出、平衡输入输出处理速率等特性，在数字集成电路设计中被广泛应用。一般，FIFO数据缓存器包括两部分：控制部分和存储部分。考虑到单位比特资源开销，现有技术中，通常大容量的FIFO数据缓存器中的存储部分都是使用同步静态随机存取存储器(Synchronous Static Random Access Memory，SSRAM)作为内部存储单元。
发明人在实现本发明的过程中，发现现有采用SSRAM作为FIFO数据缓存器的内部存储单元的方案中，至少存在以下缺陷：
根据SSRAM本身的特性，SSRAM在前一时钟脉冲信号发出写使能信号，但是在后一时钟脉冲信号才能写入数据；同样，在前一时钟脉冲周期发出读使能信号，但在后一时钟脉冲周期才能读出数据；因此，SSRAM作为FIFO数据缓存器的内部存储单元将会导致时延的增加，采用这种方法实现的FIFO数据缓存器时延较大，当使用FIFO数据缓存器的系统对时延较敏感时，将导致相应系统性能下降。
发明内容
有鉴于此，本发明实施例期望提供一种FIFO数据缓存器及其进行时延控制的方法、计算机存储介质。
为达到上述目的，本发明实施例的技术方案是这样实现的：
本发明实施例提供了一种FIFO数据缓存器，该FIFO数据缓存器包括输入端口、输出端口，控制单元、第一缓存单元、第二缓存单元；其中，
所述控制单元，配置为获取所述FIFO数据缓存器当前的输出端口的状态信息、所述第一缓存单元的第一数据存储状态信息、以及所述第二缓存单元的第二数据存储状态信息；并根据获得的输出端口的状态信息、第一数据存储状态信息及第二数据存储状态信息，确定数据的传输通路。
上述方案中，所述传输通路包括第一传输通路、第二传输通路、第三传输通路、第四传输通路。
上述方案中，所述FIFO数据缓存器还包括：第一多路选择单元、第二多路选择单元；
所述第一传输通路由输入端口、第二多路选择单元、输出端口依次连接；
所述第二传输通路由输入端口、第一多路选择单元、第二缓存单元、第二多路选择单元、输出端口依次连接；
所述第三传输通路由输入端口、第一缓存单元、第一多路选择单元、第二缓存单元、第二多路选择单元、输出端口依次连接；
所述第四传输通路由输入端口、第一缓存单元、第二多路选择单元、输出端口依次连接。
上述方案中，所述控制单元配置为：
预设所述第一缓存单元的时延大于所述第二缓存单元的时延；
在传输数据时，若所述FIFO数据缓存器当前的输出端口的状态为通路状态，第一数据存储状态为空状态及第二数据存储状态为空状态，则确定通过第一传输通路传输数据；
若所述FIFO数据缓存器当前的输出端口的状态为非通路状态，第一数据存储状态为空状态及第二数据存储状态为空状态，则确定通过第二传输 通路传输数据；
若所述FIFO数据缓存器当前的输出端口状态为非通路状态，第一数据存储状态为非空状态，第二数据存储状态为空状态，则确定通过第三数据传输通路传输数据；
若所述FIFO数据缓存器当前的输出端口的状态为通路状态，第一数据存储状态为非空状态，且当前时钟脉冲周期的前一时钟脉冲周期有数据从第三数据传输通路或者第四传输通路到达输出端口，则确定通过第四数据传输通路传输数据。
上述方案中，所述第一多路选择单元及所述第二多路选择单元采用多路选择器实现。
上述方案中，所述第一缓存单元采用RAM或SSRAM实现；所述第二缓存单元采用寄存器实现。
基于上述的FIFO数据缓存器，本发明实施例还提供了一种FIFO数据缓存器进行时延控制的方法，该方法包括：
FIFO数据缓存器获取自身当前的输出端口的状态信息、第一数据存储状态信息及第二数据存储状态信息；根据获得的输出端口状态信息、第一数据存储状态信息及第二数据存储状态信息，确定数据的传输通路。
上述方案中，所述传输通路包括第一传输通路、第二传输通路、第三传输通路、第四传输通路。
上述方案中，所述FIFO数据缓存器包括输入端口、输出端口、控制单元、第一缓存单元、第二缓存单元、第一多路选择单元和第二多路选择单元；
所述第一传输通路由输入端口、第二多路选择单元、输出端口依次连接；
所述第二传输通路由输入端口、第一多路选择单元、第二缓存单元、 第二多路选择单元、输出端口依次连接；
所述第三传输通路由输入端口、第一缓存单元、第一多路选择单元、第二缓存单元、第二多路选择单元、输出端口依次连接；
所述第四传输通路由输入端口、第一缓存单元、第二多路选择单元、输出端口依次连接。
上述方案中，所述方法还包括：预设所述第一缓存单元的时延大于所述第二缓存单元的时延；
相应地，所述根据获得的输出端口的状态信息、第一数据存储状态信息及第二数据存储状态信息，确定数据的传输通路，包括：
在传输数据时，若自身当前的输出端口的状态为通路状态，第一数据存储状态为空状态及第二数据存储状态为空状态，则确定通过第一传输通路传输数据；
若自身当前的输出端口的状态为非通路状态，第一数据存储状态为空状态及第二数据存储状态为空状态，则确定通过第二传输通路传输数据；
若自身当前的输出端口的状态为非通路状态，第一数据存储状态为非空状态，第二数据存储状态为空状态，则确定通过第三数据传输通路传输数据；
若自身当前的输出端口的状态为通路状态，第一数据存储状态为非空状态，且当前时钟脉冲周期的前一时钟脉冲周期有数据从第三数据传输通路或者第四传输通路到达输出端口，则确定通过第四数据传输通路传输数据。
本发明实施例有提供了一种计算机存储介质，所述计算机存储介质包括一组指令，当执行所述指令时，引起至少一个处理器执行上述的FIFO数据缓存器进行时延控制的方法。
本发明实施例所提供的FIFO数据缓存器及其进行时延控制的方法、计 算机存储介质，FIFO数据缓存器获取自身当前的输出端口的状态信息、第一数据存储状态信息及第二数据存储状态信息；根据获得的输出端口状态信息、第一数据存储状态信息及第二数据存储状态信息，确定数据的传输通路。如此，本发明实施例能根据FIFO数据缓存器当前的输出端口状态信息、第一数据存储状态信息及第二数据存储状态信息，选择数据传输的不同传输通路，以使所述FIFO数据缓存器能够兼顾大容量的缓存及数据传输路径中的时延，进而能在保证大容量缓存的同时降低数据传输中的时延。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为本发明实施例FIFO数据缓存器的组成结构示意图；
图2为本发明实施例基于FIFO数据缓存器进行时延控制的方法的实现流程示意图；
图3为本发明实施例场景一中的FIFO数据缓存器的组成结构示意图。
具体实施方式
本发明实施例中，FIFO数据缓存器获取自身当前的输出端口的状态信息、第一数据存储状态信息及第二数据存储状态信息；根据获得的输出端口状态信息、第一数据存储状态信息及第二数据存储状态信息，确定数据的传输通路。
下面结合附图对本发明具体实施方式作进一步说明。
本发明实施例提出了一种FIFO数据缓存器，所述FIFO数据缓存器包括输入端口、输出端口；如图1所示，该FIFO数据缓存器还包括：控制单 元100、第一缓存单元101、第二缓存单元102；其中，
所述控制单元100，配置为获取所述FIFO数据缓存器当前的输出端口的状态信息、所述第一缓存单元101的第一数据存储状态信息、以及所述第二缓存单元102的第二数据存储状态信息；根据获得的输出端口的状态信息、第一数据存储状态信息及第二数据存储状态信息，确定数据的传输通路。
这里，所述输出端口的状态信息包括通路状态或非通路状态；所述第一数据存储状态信息包括空状态、非空状态或近满状态；所述第二数据存储状态信息包括空状态、非空状态。
这里，所述传输通路可以包括四条传输通路：第一传输通路、第二传输通路、第三传输通路以及第四传输通路。
进一步地，结合图1所示，所述FIFO数据缓存器还包括：第一多路选择单元103、第二多路选择单元104；其中，
所述第一多路选择单元103，配置为对输入的多路数据进行选择，选择出一路数据输出到所述第二缓存单元中；
所述第二多路选择单元104，与输出端口连接，配置为将输入的多路数据选择出一路输出到输出端口。
由于第一多路选择单元103、第二多路选择单元104仅配置为对多路数据进行选择，因此，对数据的传输没有时延影响。
下面对本发明实施例FIFO数据缓冲器中各传输通路的连接关系进行具体说明：
所述第一传输通路由输入端口、第二多路选择单元104、输出端口依次连接；
所述第二传输通路由输入端口、第一多路选择单元103、第二缓存单元102、第二多路选择单元104、输出端口依次连接；
所述第三传输通路由输入端口、第一缓存单元101、第一多路选择单元103、第二缓存单元102、第二多路选择单元104、输出端口依次连接；
所述第四传输通路由输入端口、第一缓存单元101、第二多路选择单元104、输出端口依次连接。
这里，所述控制单元100，还配置为控制所述第一缓存单元101、所述第二缓存单元102、所述第一多路选择单元103、所述第二多路选择单元104进行协作工作，以完成数据传输过程中各个传输通路的控制；其中，各个功能单元的执行均由时钟脉冲的上升沿或下降沿触发。
这里，预设所述第一缓存单元101的时延大于所述第二缓存单元102的时延，因此，四条传输通路由于传输路径的不同对应不同的时延，在传输数据时，能够兼顾缓存容量及时延，从而使发送端设备和接收端设备之间的数据处理速率达到匹配。
本发明实施例中，基于上述FIFO数据缓存器的组成结构及传输通路的连接关系，所述FIFO数据缓存器的工作原理是这样的：
首先，所述第一缓存单元101、第二缓存单元102的初始状态均设置为空状态；
方式一、在传输数据时，若自身当前的输出端口的状态为通路状态，第一数据存储状态为空状态、以及第二数据存储状态为空状态，则确定通过第一传输通路传输数据。
这里，在时钟脉冲信号的上升沿或下降沿到来时刻，触发所述FIFO数据缓存器从自身输入端口接收发送端设备发送的数据，若此时自身输出端口的状态为通路状态、第一数据存储状态为空状态、以及第二数据存储状态为空状态，则选择通过第一传输通路传输数据，即从输入端口接收到的数据无需缓存，直接通过输出端口传输到输出端设备，这样，可以将数据0时延的传输到输出端设备，适用于对传输时延较为敏感的场景下，能够减 少输入端设备与输出端设备之间的数据传输延时，从而提升系统的性能。
方式二、若自身当前的输出端口的状态为非通路状态，第一数据存储状态为空状态、以及第二数据存储状态为空状态，则确定通过第二传输通路传输数据。
这里，在时钟脉冲信号的上升沿或下降沿到来时刻，触发所述FIFO数据缓存器从输入端口接收发送端设备发送的数据，若此时自身输出端口的状态为非通路状态、第一数据存储状态为空状态、以及第二数据存储状态为空状态，则选择通过第二传输通路传输数据，即由于所述第一缓存单元101的时延大于所述第二缓存单元102的时延，因此，从输入端口接收到的数据，会先存入时延相对较小的第二缓存单元102中，当第二缓存单元102存满数据时，从输入端口接收到的数据才会存入第一缓存单元101中；待接收端设备可以接收数据时，所述控制单元100将输出端口状态转变为通路状态，此时首先将第二缓存单元102中的数据传输到输出端口，能够降低数据传输过程中的时延。
需要说明的是，在当前时刻，输出端口的状态为非通路状态，数据首先存入第二缓存单元102中，若在当前时刻的下一时刻，且输出端口状态依然为非通路状态，则将要传输的数据存入第一缓存单元101中，待输出端口状态转变为通路状态时，先将第二缓存单元102中的数据传输到输出端口，以使所述FIFO数据缓存器的设计符合先进先出的设计原则。
方式三、若自身当前的输出端口的状态为非通路状态，第一数据存储状态为非空状态，第二数据存储状态为空状态，则确定通过第三数据传输通路传输数据。
这里，在时钟脉冲信号的上升沿或下降沿到来时刻，触发所述FIFO数据缓存器从输入端口接收发送端设备发送的数据，若此时输出端口的状态为非通路状态，第一数据存储状态为非空状态，则将所述第一缓存单元101 中的数据先搬移到所述第二缓存单元102中，待输出端口状态转变为通路状态时，将第二缓存单元102中的数据传输到输出端口。
方式四、若自身当前的输出端口的状态为通路状态，第一数据存储状态为非空状态，且当前时钟脉冲周期的前一时钟脉冲周期有数据从第三数据传输通路或者第四传输通路到达输出端口，则确定通过第四数据传输通路传输数据。
这里，在时钟脉冲信号的上升沿或下降沿到来时刻，触发所述FIFO数据缓存器从输入端口接收发送端设备发送的数据，若此时输出端口的状态为通路状态，第一数据存储状态为非空状态，则将所述第一缓存单元101中的数据直接传输到输出端口，能够降低数据传输过程中的时延。
本发明的上述实施例中，采用时延较小的第二缓存单元102对数据进行缓存，待输出端口状态转变为通路状态时，可以将第二缓存单元102中的数据直接输出到输出端口，是为了改善对输出端口的响应速度，从而降低响应时延。
在本发明的实际应用中，所述第一缓存单元101可采用大容量的RAM或SSRAM实现，根据RAM或SSRAM自身的特性，数据通过RAM或SSRAM进行传输时，最小时延为两个脉冲周期；所述第二缓存单元102可采用寄存器实现，根据D触发器自身的特性，数据通过D触发器进行传输时，最小时延为一个脉冲周期；所述第一多路选择单元103及所述第二多路选择单元104可采用多路选择器实现，由于多路选择器仅配置为对多路数据进行选择，因此，对数据的传输没有时延影响。基于此，在实际应用中，若再考虑到数据在所述FIFO数据缓存器中的等待时间，则所述第一传输通路对应的数据传输时延为0个脉冲周期，所述第二传输通路对应的数据传输时延为至少一个脉冲周期，第三传输通路对应的数据传输时延为至少三个脉冲周期，第四数据传输通路对应的数据传输时延为至少两个脉冲 周期。
基于相同的技术构思，本发明实施例还提供了一种基于FIFO数据缓存器进行时延控制的方法，由于该方法解决问题的原理与装置相似，因此，方法的实施过程及实施原理均可以参见前述装置的实施过程及实施原理描述，重复之处不再赘述。
如图2所示，本发明实施例提供的基于FIFO数据缓存器进行时延控制的方法，该方法包括：
步骤S201：FIFO数据缓存器获取自身当前的输出端口状态信息、第一数据存储状态信息及第二数据存储状态信息。
步骤S202：根据获取的输出端口状态信息、第一数据存储状态信息及第二数据存储状态信息，确定数据的传输通路。
这里，所述传输通路包括第一传输通路、第二传输通路、第三传输通路、第四传输通路。
当所述FIFO数据缓存器包括输入端口、输出端口、控制单元、第一缓存单元、第二缓存单元、第一多路选择单元和第二多路选择单元时，所述第一传输通路由输入端口、第二多路选择单元、输出端口依次连接；所述第二传输通路由输入端口、第一多路选择单元、第二缓存单元、第二多路选择单元、输出端口依次连接；所述第三传输通路由输入端口、第一缓存单元、第一多路选择单元、第二缓存单元、第二多路选择单元、输出端口依次连接；所述第四传输通路由输入端口、第一缓存单元、第二多路选择单元、输出端口依次连接。
进一步地，预设所述第一缓存单元的时延大于所述第二缓存单元的时延；
相应地，根据获取的输出端口状态信息、第一数据存储状态信息及第二数据存储状态信息，确定数据的传输通路的具体实施方式如下：
在传输数据时，若自身当前的输出端口的状态为通路状态，第一数据存储状态为空状态以及第二数据存储状态为空状态，则确定通过第一传输通路传输数据；
若自身当前的输出端口的状态为非通路状态，第一数据存储状态为空状态以及第二数据存储状态均为空状态，则确定通过第二传输通路传输数据；
若自身当前的输出端口的状态为非通路状态，第一数据存储状态为非空状态及第二数据存储状态为空状态，则确定通过第三数据传输通路传输数据；
若自身当前的输出端口的状态为通路状态，第一数据存储状态为非空状态，且当前时钟脉冲周期的前一时钟脉冲周期有数据从第三数据传输通路或者第四传输通路到达输出端口，则确定通过第四数据传输通路传输数据。
本发明实施例中，FIFO数据缓存器获取自身当前的输出端口的状态信息、第一数据存储状态信息及第二数据存储状态信息；根据获得的输出端口状态信息、第一数据存储状态信息及第二数据存储状态信息，确定数据的传输通路。如此，本发明实施例能根据FIFO数据缓存器当前的输出端口状态信息、第一数据存储状态信息及第二数据存储状态信息，选择数据传输的不同传输通路，以使所述FIFO数据缓存器能够兼顾大容量的缓存及数据传输路径中的时延，进而能在保证大容量缓存的同时降低数据传输中的时延。
为了更清楚地对本发明实施例进行说明，下面以场景一为例，对本发明实施例中的FIFO数据缓存器进行时延控制的流程进行详细描述，该场景一中，根据发送端设备、接收端设备的数据处理和流量情况评估，至少需要一个深度为1024、位宽为64的先进先出的数据缓存设备对发送端设备发 送的数据进行缓存，才能使发送端设备和接收端设备之间达到处理速率匹配，如图3所示，FIFO数据缓存器包括：一个SSRAM、一个暂存器tempreg、两个多路选择器MUX-0和MUX-1，一个控制器Ctrl；其中，
SSRAM、暂存器tempreg、两个多路选择器MUX-0和MUX-1构成FIFO数据缓存器的数据通路，控制器Ctrl作为FIFO数据缓存器的控制通路。
SSRAM规格为1024×64，即深度为1024、位宽为64；
MUX-0为一个64bit的三选一多路选择器，具体选择哪一路由控制器Ctrl的sel0控制信号进行控制；
tempreg是一个64bit带使能端的D触发器，使能控制信号为tempreg_we，tempreg仅能缓存一个64bit的数据。
MUX-1为一个64bit的3选1多路选择器，具体选择那一路由控制器Ctrl的sel1控制信号进行控制；
SSRAM、MUX-0、tempreg、MUX-1、输入端口、输出端口连接关系如图4所示，输入数据从输入端口到输出端口，一共有四条传输通路：
1)第一传输通路：输入端口→MUX-1→输出端口；
2)第二传输通路：输入端口→MUX-0→tempreg→MUX-1→输出端口；
3)第三传输通路：输入端口→cFIFO→MUX-0→tempreg→MUX-1→输出端口；
4)第四传输通路：输入端口→cFIFO→MUX-1→输出端口；
其中，第一传输通路对应时延为零，第二传输通路对应时延为至少一个脉冲周期，第三传输通路对应的时延为至少三个脉冲周期，第四传输通路对应的时延为至少两个脉冲周期。
控制器Ctrl作为FIFO数据缓存器的控制器，完成数据传输通路的控制、输入数据的接收握手控制、输出数据的发送握手控制；其中，控制器Ctrl的输入信息包括：
1)来自发送端设备的输入数据有效指示信号i_din_valid；
2)来自接收端设备的可接收指示信号i_dout_ready；
3)来自SSRAM的空标志信号cfifo_empty；
4)来自SSRAM的近满标志信号cfifo_aful；
5)来自tempreg的是否暂存一个数据的标志寄存器信号tempreg_valid。
控制器Ctrl的输出信息包括：
1)发送给发送端设备的输入数据可接受状态指示信号o_din_ready；
2)发送给接收端设备的输出数据有效指示信号o_dout_valid；
3)发送给SSRAM的写使能信号cfifo_we和读使能信号cfifo_re；
4)发送给MUX-0的选择信号sel0；
5)发送给tempreg的更新使能信号tmpreg_we；
6)发送给MUX-1的选择信号sel1。
本发明实际应用中，基于上述FIFO数据缓存器的组成结构及传输通路的连接关系，所述FIFO数据缓存器的工作原理是这样的：
方式一、在时钟脉冲信号的上升沿或下降沿到来时刻，触发所述FIFO数据缓存器从输入端口接收发送端设备发送的数据，若根据i_dout_ready信号确定输出端设备可以接收数据，则控制输出端口的状态为通路状态；并且根据cfifo_empty信号确定SSRAM的第一数据存储状态为空状态、以及根据tempreg_valid信号确定D触发器的第二数据存储状态为空状态，则确定通过第一传输通路传输数据，即从输入端口接收到的数据无需缓存，直接通过输出端口传输到输出端设备，这样，可以将数据零时延的传输到输出端设备，适用于对传输时延较为敏感的场景下，能够提高输入端设备与输出端设备之间的数据传输速度，从而提升系统的性能。
方式二、在时钟脉冲信号的上升沿或下降沿到来时刻，触发所述FIFO数据缓存器从输入端口接收发送端设备发送的数据，若根据i_dout_ready 信号确定输出端设备不可以接收数据，则控制输出端口状态为非通路状态，并且根据cfifo_empty信号确定SSRAM的第一数据存储状态为空状态、以及根据tempreg_valid信号确定D触发器的第二数据存储状态为空状态，则确定通过第二传输通路传输数据，即先将接收到的数据缓存到D触发器中，在根据i_dout_ready信号确定输出端设备可以接收数据时，将输出端口状态转变为通路状态时，此时D触发器中第二缓存的数据将经过一个脉冲周期的延时传输到输出端口，从而提高了FIFO数据缓存器对输出端口的响应速度，减少了响应时延。
方式三、在时钟脉冲信号的上升沿或下降沿到来时刻，触发所述FIFO数据缓存器从输入端口接收发送端设备发送的数据，若根据i_dout_ready信号确定输出端设备不可以接收数据，则控制输出端口状态为非通路状态，且根据cfifo_aful信号确定SSRAM的第一数据存储状态为非空状态、以及根据tempreg_valid信号确定第二数据存储状态为空状态，则确定通过第三传输通路传输数据，即需要将SSRAM中的数据搬移到D触发器中，以便在输出端口状态转变为通路状态时，直接将D触发器中暂存的数据经过一个脉冲周期的延时传输到输出端口，从而提高了所述FIFO数据缓存器对输出端口的响应速度，对应的时延为至少三个脉冲周期。
方式四、在时钟脉冲信号的上升沿或下降沿到来时刻，触发所述FIFO数据缓存器从输入端口接收发送端设备发送的数据，若根据i_dout_ready信号确定输出端设备可以接收数据，则控制输出端口状态为通路状态，且根据cfifo_aful信号确定SSRAM的第一数据存储状态为非空状态，且当前时钟脉冲周期的前一时钟脉冲周期有数据从第三数据传输通路或者第四传输通路到达输出端口，则确定通过第四传输通路传输数据，即无需将SSRAM中的数据存入D触发器中，而是直接将SSRAM中的数据传输到输出端口，对应的时延为至少两个脉冲周期。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和 修改。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (11)

  1. 一种先进先出FIFO数据缓存器，所述FIFO数据缓存器包括输入端口、输出端口，所述FIFO数据缓存器还包括：控制单元、第一缓存单元、第二缓存单元；其中，
    所述控制单元，配置为获取所述FIFO数据缓存器当前的输出端口的状态信息、所述第一缓存单元的第一数据存储状态信息、以及所述第二缓存单元的第二数据存储状态信息；并根据获得的输出端口的状态信息、第一数据存储状态信息及第二数据存储状态信息，确定数据的传输通路。
  2. 根据权利要求1所述的FIFO数据缓存器，其中，所述传输通路包括第一传输通路、第二传输通路、第三传输通路、第四传输通路。
  3. 根据权利要求2所述的FIFO数据缓存器，其中，所述FIFO数据缓存器还包括：第一多路选择单元、第二多路选择单元；
    所述第一传输通路由输入端口、第二多路选择单元、输出端口依次连接；
    所述第二传输通路由输入端口、第一多路选择单元、第二缓存单元、第二多路选择单元、输出端口依次连接；
    所述第三传输通路由输入端口、第一缓存单元、第一多路选择单元、第二缓存单元、第二多路选择单元、输出端口依次连接；
    所述第四传输通路由输入端口、第一缓存单元、第二多路选择单元、输出端口依次连接。
  4. 根据权利要求2或3所述的FIFO数据缓存器，其中，所述控制单元配置为：
    预设所述第一缓存单元的时延大于所述第二缓存单元的时延；
    在传输数据时，若所述FIFO数据缓存器当前的输出端口的状态为通路状态，第一数据存储状态为空状态及第二数据存储状态为空状态，则确定 通过第一传输通路传输数据；
    若所述FIFO数据缓存器当前的输出端口的状态为非通路状态，第一数据存储状态为空状态及第二数据存储状态为空状态，则确定通过第二传输通路传输数据；
    若所述FIFO数据缓存器当前的输出端口状态为非通路状态，第一数据存储状态为非空状态，第二数据存储状态为空状态，则确定通过第三数据传输通路传输数据；
    若所述FIFO数据缓存器当前的输出端口的状态为通路状态，第一数据存储状态为非空状态，且当前时钟脉冲周期的前一时钟脉冲周期有数据从第三数据传输通路或者第四传输通路到达输出端口，则确定通过第四数据传输通路传输数据。
  5. 根据权利要求3所述的FIFO数据缓存器，其中，所述第一多路选择单元及所述第二多路选择单元采用多路选择器实现。
  6. 根据权利要求1所述的FIFO数据缓存器，其中，所述第一缓存单元采用RAM或SSRAM实现；所述第二缓存单元采用寄存器实现。
  7. 一种FIFO数据缓存器进行时延控制的方法，所述方法包括：
    FIFO数据缓存器获取自身当前的输出端口的状态信息、第一数据存储状态信息及第二数据存储状态信息；
    根据获得的输出端口状态信息、第一数据存储状态信息及第二数据存储状态信息，确定数据的传输通路。
  8. 根据权利要求7所述的方法，其中，所述传输通路包括第一传输通路、第二传输通路、第三传输通路、第四传输通路。
  9. 根据权利要求8所述的方法，其中，所述FIFO数据缓存器包括输入端口、输出端口、控制单元、第一缓存单元、第二缓存单元、第一多路选择单元和第二多路选择单元；
    所述第一传输通路由输入端口、第二多路选择单元、输出端口依次连接；
    所述第二传输通路由输入端口、第一多路选择单元、第二缓存单元、第二多路选择单元、输出端口依次连接；
    所述第三传输通路由输入端口、第一缓存单元、第一多路选择单元、第二缓存单元、第二多路选择单元、输出端口依次连接；
    所述第四传输通路由输入端口、第一缓存单元、第二多路选择单元、输出端口依次连接。
  10. 根据权利要求8或9所述的方法，其中，所述方法还包括：预设所述第一缓存单元的时延大于所述第二缓存单元的时延；
    相应地，所述根据获得的输出端口的状态信息、第一数据存储状态信息及第二数据存储状态信息，确定数据的传输通路，包括：
    在传输数据时，若自身当前的输出端口的状态为通路状态，第一数据存储状态为空状态及第二数据存储状态为空状态，则确定通过第一传输通路传输数据；
    若自身当前的输出端口的状态为非通路状态，第一数据存储状态为空状态及第二数据存储状态为空状态，则确定通过第二传输通路传输数据；
    若自身当前的输出端口的状态为非通路状态，第一数据存储状态为非空状态，第二数据存储状态为空状态，则确定通过第三数据传输通路传输数据；
    若自身当前的输出端口的状态为通路状态，第一数据存储状态为非空状态，且当前时钟脉冲周期的前一时钟脉冲周期有数据从第三数据传输通路或者第四传输通路到达输出端口，则确定通过第四数据传输通路传输数据。
  11. 一种计算机存储介质，所述计算机存储介质包括一组指令，当执 行所述指令时，引起至少一个处理器执行如权利要求7至10任一项所述的FIFO数据缓存器进行时延控制的方法。
PCT/CN2014/088772 2014-05-23 2014-10-16 Fifo数据缓存器及其进行时延控制的方法、计算机存储介质 WO2015176475A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113688074A (zh) * 2021-10-26 2021-11-23 浙江芯昇电子技术有限公司 先进先出数据处理装置及数据处理方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109155798B (zh) * 2016-05-27 2020-08-25 华为技术有限公司 一种异步fifo电路及时延确定方法
CN108958700A (zh) * 2017-05-22 2018-12-07 深圳市中兴微电子技术有限公司 一种先进先出数据缓存器及缓存数据的方法
CN109388370B (zh) * 2017-08-03 2023-06-27 深圳市中兴微电子技术有限公司 一种实现先入先出队列的方法及装置
CN109918043B (zh) * 2019-03-04 2020-12-08 上海熠知电子科技有限公司 一种基于虚拟通道的运算单元共享方法和系统
WO2020252769A1 (zh) * 2019-06-21 2020-12-24 深圳市大疆创新科技有限公司 先入先出存储器的数据存储方法、设备及存储介质
CN111400205B (zh) * 2020-02-29 2022-05-24 华南理工大学 一种先进先出地址轮询缓存读写方法、系统及装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101299647A (zh) * 2008-06-27 2008-11-05 中兴通讯股份有限公司 一种实现sdh业务无损切换的装置和方法
CN101566941A (zh) * 2009-06-03 2009-10-28 北京中星微电子有限公司 一种基于静态存储器的fifo存储单元
CN102497514A (zh) * 2011-12-15 2012-06-13 中国科学院自动化研究所 一种三通道视频转发设备和转发方法
CN103119548A (zh) * 2010-09-23 2013-05-22 马维尔以色列(M.I.S.L.)有限公司 低等待时间先进先出(fifo)缓存

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2536200B1 (fr) * 1982-11-15 1987-01-16 Helen Andre Unite de stockage temporaire de donnees organisee en file d'attente
US7039770B1 (en) * 2002-03-05 2006-05-02 Juniper Networks, Inc. Low latency request dispatcher
CN101308697B (zh) * 2008-07-10 2011-08-24 哈尔滨工业大学 基于sdram的大容量fifo突发缓存器及数据存储方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101299647A (zh) * 2008-06-27 2008-11-05 中兴通讯股份有限公司 一种实现sdh业务无损切换的装置和方法
CN101566941A (zh) * 2009-06-03 2009-10-28 北京中星微电子有限公司 一种基于静态存储器的fifo存储单元
CN103119548A (zh) * 2010-09-23 2013-05-22 马维尔以色列(M.I.S.L.)有限公司 低等待时间先进先出(fifo)缓存
CN102497514A (zh) * 2011-12-15 2012-06-13 中国科学院自动化研究所 一种三通道视频转发设备和转发方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113688074A (zh) * 2021-10-26 2021-11-23 浙江芯昇电子技术有限公司 先进先出数据处理装置及数据处理方法

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