WO2018070111A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2018070111A1
WO2018070111A1 PCT/JP2017/030227 JP2017030227W WO2018070111A1 WO 2018070111 A1 WO2018070111 A1 WO 2018070111A1 JP 2017030227 W JP2017030227 W JP 2017030227W WO 2018070111 A1 WO2018070111 A1 WO 2018070111A1
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WIPO (PCT)
Prior art keywords
film
interlayer insulating
disposed
insulating film
semiconductor device
Prior art date
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Ceased
Application number
PCT/JP2017/030227
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English (en)
French (fr)
Japanese (ja)
Inventor
洋一 芦田
藤原　剛
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Denso Corp
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Denso Corp
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Application filed by Denso Corp filed Critical Denso Corp
Publication of WO2018070111A1 publication Critical patent/WO2018070111A1/ja
Priority to US16/355,917 priority Critical patent/US10916506B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

Definitions

  • a semiconductor device including a semiconductor substrate, an interlayer insulating film, a first hard film, a pad portion, and a surface protective film.
  • the semiconductor substrate has a semiconductor element.
  • the interlayer insulating film is disposed on the semiconductor substrate.
  • the first hard film is disposed on the interlayer insulating film.
  • the pad portion is disposed on the first hard film and forms an electrode of the semiconductor device.
  • a surface protective film made of polyimide is disposed in a region where bonding is not performed in the pad portion.
  • the temperature of the pad may rise due to the operation of the semiconductor element.
  • the electromigration of the pad portion is promoted by the temperature rise.
  • pad portions having different potentials may break through the surface protective film due to electromigration, and there is a possibility that a short circuit may occur between the pad portions.
  • This disclosure is intended to provide a semiconductor device that can suppress a short circuit between pad portions due to electromigration.
  • a semiconductor device includes a semiconductor substrate having a semiconductor element formed on one surface, an interlayer insulating film disposed on one surface of the semiconductor substrate, and disposed in the interlayer insulating film.
  • the wiring layer and the interlayer insulating film are disposed on the opposite side of the semiconductor substrate, the hard film is harder than the interlayer insulating film, and the hard film is disposed on the opposite side of the interlayer insulating film, and the wiring layer is interposed therebetween.
  • a plurality of pads for external connection connected to the semiconductor element, and a surface protective film having electrical insulation and at least disposed in a region facing the pads are provided.
  • the surface protective film is a silicon nitride film or a silicon oxide film.
  • FIG. 1 is a plan view showing a schematic configuration of a semiconductor device according to a first embodiment.
  • FIG. 2 is a cross-sectional view taken along the line II-II in FIG. It is a circuit diagram which shows the circuit for evaluating a semiconductor device.
  • FIG. 4 is a timing chart showing drain voltage, gate voltage, and drain current when a semiconductor device is evaluated using the circuit of FIG. 3.
  • FIG. 4 is a timing chart showing drain voltage, gate voltage, forward voltage, and drain current when a semiconductor device is evaluated using the circuit of FIG. 3. It is a figure which shows the evaluation result of a semiconductor device when a semiconductor device is evaluated using the circuit of FIG. It is sectional drawing which shows schematic structure of the semiconductor device which concerns on 2nd Embodiment.
  • the semiconductor device 10 for example, an IC chip can be adopted.
  • the semiconductor device 10 includes an SOI substrate 12 as a semiconductor substrate, an interlayer insulating film 14, a wiring layer 16, a hard film 18, a pad portion 20, and a surface protective film 22.
  • the semiconductor device 10 has a flat plate shape whose thickness direction is along the Z direction.
  • the semiconductor device 10 has a front surface 10a and a back surface 10b opposite to the front surface 10a.
  • the semiconductor device 10 of the present embodiment is electrically connected to the inductive load 100 and controls the current flowing through the inductive load 100.
  • Inductive load 100 can also be referred to as an L load or an inductance. The control of the inductive load 100 in the semiconductor device 10 will be described in detail below.
  • the semiconductor element 30 is formed on one surface of the SOI substrate 12 opposite to the back surface 10b.
  • the semiconductor element 30 is, for example, an LDMOS (lateral diffusion MOS transistor) or an IGBT (insulated gate bipolar transistor).
  • a plurality of semiconductor elements 30 are formed on the SOI substrate 12.
  • An interlayer insulating film 14 is disposed on one surface of the SOI substrate 12 opposite to the back surface 10b.
  • the hard film 18 does not pass moisture from the outside of the semiconductor device 10 and protects the wiring layer 16 and the SOI substrate 12 from moisture.
  • a pad portion 20 is disposed on the opposite side of the hard film 18 from the interlayer insulating film 14 in the Z direction.
  • the pad unit 20 is an electrode for external connection.
  • the pad portion 20 is electrically connected to the semiconductor element 30 through the wiring layer 16.
  • the pad portion 20 is formed using a metal such as aluminum or an aluminum alloy.
  • the Young's modulus of the pad portion 20 is, for example, about 80 GPa. As described above, the pad portion 20 is disposed on the SOI substrate 12, the wiring layer 16, and the interlayer insulating film 14 via the hard film 18.
  • a contact hole 34 for electrically connecting the pad portion 20 and the third wiring layer 16c is formed in the hard film 18 and the interlayer insulating film 14.
  • the contact hole 34 is formed so as to penetrate the hard film 18 in the Z direction and reach the third wiring layer 16 c with a predetermined depth in the Z direction in the interlayer insulating film 14.
  • the pad portion 20 is also disposed in the contact hole 34 in addition to the surface of the hard film 18 opposite to the interlayer insulating film 14.
  • a plurality of pad portions 20 are arranged in the semiconductor device 10. For example, different voltages are applied to the pad portions 20 arranged at different locations.
  • FIG. 2 as the pad portion 20, a first pad portion 20 a connected to the ground and a second pad portion 20 b connected to the inductive load 100 are shown.
  • the first pad portion 20a and the second pad portion 20b are arranged so as not to contact each other. That is, an area where the pad portion 20 is not formed is provided on the hard film 18.
  • the first pad portion 20a and the second pad portion 20b face each other in the X direction. Therefore, the opposing region Sb is formed between the first pad portion 20a and the second pad portion 20b. As shown in FIG. 1, the opposing region Sb is formed extending in the Y direction.
  • a surface protective film 22 is formed on the opposite side of the pad portion 20 from the hard film 18 in the Z direction.
  • the surface protective film 22 prevents the pad portions 20 from short-circuiting when foreign matter adheres to the surface 10 a of the semiconductor device 10.
  • the surface protective film 22 covers a part of the pad portion 20 and forms a part of the surface 10a.
  • the surface protective film 22 is formed using a material having excellent electrical insulation.
  • Each pad portion 20 has a portion covered with the surface protective film 22 and a portion exposed from the surface protective film 22 and forming a part of the surface 10a.
  • the portion exposed from the surface protective film 22 in the pad portion 20 is connected to the inductive load 100 and the ground by bonding.
  • the region exposed from the surface protective film 22 in the pad portion 20 is referred to as a bonding region Sa.
  • the bonding region Sa overlaps at least a part of the region of the SOI substrate 12 where the semiconductor element 30 is formed. That is, the pad part 20 is an element pad.
  • the stress due to bonding is easily transmitted to the semiconductor element 30.
  • the hard film 18 is disposed between the pad portion 20 and the interlayer insulating film 14, whereby transmission of stress due to bonding to the interlayer insulating film 14 side can be suppressed. That is, the hard film 18 can suppress the stress due to bonding from being transmitted to the semiconductor element 30, and can reduce bonding damage to the semiconductor element 30. Furthermore, it is possible to suppress the occurrence of cracks in the semiconductor device 10.
  • the surface protective film 22 is also disposed in the facing region Sb. A part of the surface protective film 22 is disposed on the entire facing region Sb and is in contact with the pad portion 20 and the hard film 18.
  • the surface protective film 22 has an inner film 22a disposed in contact with the pad portion 20 and an outer film 22b disposed on the opposite side of the inner film 22a from the pad portion 20 in the Z direction.
  • the inner film 22a is a passivation film that is harder than the outer film 22b.
  • the Young's modulus of the inner film 22a is, for example, 50 GPa or more.
  • the Young's modulus of the inner film 22a of this embodiment is, for example, about 240 GPa.
  • the inner film 22a is formed using a silicon oxide film (SiO 2 , SiO) or a silicon nitride film (SiN).
  • the main component of the inner film 22a is a silicon oxide film or a silicon nitride film.
  • the hard film 18 can relieve bonding stress by being disposed between the pad portion 20 and the interlayer insulating film 14, but the electromigration of the pad portion 20 cannot be suppressed because it is not disposed on the pad portion 20.
  • the inner film 22a is a hard film, it is possible to suppress the electromigration from occurring in the pad portion 20. Electromigration is a phenomenon in which a metal is deformed by the movement of ions.
  • the inner film 22a has a thickness of 1.0 ⁇ m or more.
  • an SOI substrate having a plurality of semiconductor elements 30 formed on one surface is prepared.
  • the semiconductor element 30 can be formed by a known method.
  • the wiring layer 16 and the interlayer insulating film 14 are formed on the semiconductor element 30.
  • each wiring layer 16 is formed by depositing aluminum using a sputtering method or the like.
  • the interlayer insulating film 14 is formed using a CVD method or the like.
  • the pad portion 20 is formed on the hard film 18 by depositing aluminum using a sputtering method or the like. Then, the inner film 22a is deposited on the pad portion 20 by using a plasma CVD method or the like. Next, an unnecessary portion of the inner film 22a is removed using a mask so that the bonding region Sa of the pad portion 20 is exposed from the inner film 22a. Then, the outer film 22b is formed on the inner film 22a. Thus, the semiconductor device 10 can be manufactured.
  • one end of the inductive load 100 is connected to the positive electrode of the power source 102, and the other end of the inductive load 100 is connected to the semiconductor device 10. Specifically, the other end of the inductive load 100 is connected to the drain of the semiconductor element 30 via the second pad portion 20b. Further, the source of the semiconductor element 30 is connected to the negative electrode of the power source 102 through the first pad portion 20a. Note that the negative electrode of the power supply 102 is connected to the ground.
  • the pulse signal applied to the gate is Low, and the gate is turned off.
  • Vd represents a drain voltage applied to the semiconductor element 30
  • Vg represents a gate voltage
  • Id represents a drain current.
  • the drain voltage Vd is fixed to Vdd.
  • the drain current Id is 0. That is, no current flows through the semiconductor element 30.
  • the operation of the semiconductor device 10 in the order of the period T1, the period T2, and the period T3 is defined as one revolution.
  • the semiconductor device 10 is operated so that the number of rotations is a plurality of times.
  • FIG. 5 shows the forward voltage Vf of the temperature-sensitive diode installed near the semiconductor element 30 in addition to the drain voltage Vd, the gate voltage Vg, and the drain current Id.
  • the value of the forward voltage Vf indicates the temperature of the semiconductor element 30.
  • the forward voltage Vf has a constant value.
  • the temperature of the semiconductor element 30 rises and the forward voltage Vf decreases.
  • the forward voltage Vf returns to a constant value before the gate is turned off.
  • FIG. 6 shows an evaluation result when the thermal stress acting on the semiconductor device 10 is evaluated by changing the film thickness of the inner film 22a.
  • the square marker of FIG. 6 has shown the value when the pad parts 20 are short-circuited.
  • the triangular marker of FIG. 6 has shown the value when the pad parts 20 do not short-circuit. If the inner layer 22a of the 0 .mu.m, that is, when the inner layer 22a is not formed, the rotation speed is the pad part 20 to each other at about 10 7 times is shorted. Further, even when the inner film 22a is 0.2 ⁇ m, the pad portions 20 are short-circuited at a rotational speed of 10 6 to 10 7 times. In contrast, when the inner membrane 22a of 1.4 ⁇ m, the pad portion 20 to each other in the rotational speed is 109 times is not shorted.
  • the inner film 22a of the present embodiment is a silicon nitride film or a silicon oxide film, it is harder than the polyimide used for the conventional inner film 22a. Further, the inner film 22a is disposed in the facing region Sb between the pad portions 20. According to this, even if the temperature of the pad portion 20 rises due to the operation of the semiconductor element 30, each pad portion 20 is not easily deformed to the facing region Sb side by the hard inner film 22a. That is, the inner film 22a can suppress deformation of the pad portion 20 due to electromigration. Therefore, in the semiconductor device 10, a short circuit between the pad portions 20 due to electromigration can be suppressed.
  • the surface protective film 22 is a single layer.
  • the surface protective film 22 is formed using a silicon oxide film or a silicon nitride film.
  • the surface protective film 22 does not have the outer film 22b excellent in flexibility. Therefore, a silicon oxide film or a silicon nitride film is formed on the pad portion 20 and forms a part of the surface 10a.
  • the semiconductor device 10 may control a current flowing through a resistance load.
  • the semiconductor device 10 has the SOI substrate 12 as the semiconductor substrate.
  • the present invention is not limited to this.
  • An example in which the semiconductor device 10 includes a bulk silicon substrate as a semiconductor substrate may be employed.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
PCT/JP2017/030227 2016-10-14 2017-08-24 半導体装置 Ceased WO2018070111A1 (ja)

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JP2016-202787 2016-10-14
JP2016202787A JP2018064059A (ja) 2016-10-14 2016-10-14 半導体装置

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KR20210133524A (ko) * 2020-04-29 2021-11-08 삼성전자주식회사 배선 구조체 및 이를 포함하는 반도체 패키지
CN111900087B (zh) * 2020-08-31 2022-09-20 华虹半导体(无锡)有限公司 Igbt器件的制造方法

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JPH0766201A (ja) * 1993-08-27 1995-03-10 Matsushita Electric Ind Co Ltd 配線のエレクトロマイグレーション寿命試験用半導体装置及びその製造方法、並びにその試験方法
JPH1154621A (ja) * 1997-08-07 1999-02-26 Sony Corp 半導体装置およびその製造方法
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JP2006005202A (ja) * 2004-06-18 2006-01-05 Nec Electronics Corp 半導体装置
JP2008091454A (ja) * 2006-09-29 2008-04-17 Rohm Co Ltd 半導体装置及び半導体装置の製造方法
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