WO2018000810A1 - 薄膜晶体管及显示装置 - Google Patents

薄膜晶体管及显示装置 Download PDF

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WO2018000810A1
WO2018000810A1 PCT/CN2017/071598 CN2017071598W WO2018000810A1 WO 2018000810 A1 WO2018000810 A1 WO 2018000810A1 CN 2017071598 W CN2017071598 W CN 2017071598W WO 2018000810 A1 WO2018000810 A1 WO 2018000810A1
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Prior art keywords
display device
drain
film transistor
thin film
gate
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English (en)
French (fr)
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雍玮娜
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/500,121 priority Critical patent/US10777646B2/en
Publication of WO2018000810A1 publication Critical patent/WO2018000810A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance

Definitions

  • the present invention relates to the field of display technologies, and in particular to a thin film transistor and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • each sub-pixel is provided with a thin film transistor, so that each sub-pixel can operate independently and is not easily affected by other sub-pixels.
  • a bottom gate structure which is a gate 11, a gate insulating layer 12, a semiconductor layer 13, and a source 14 and a drain in the same layer from bottom to top. Extreme 15.
  • the gate 11 is connected to the scan line 110, and the source 14 is connected to the data line 140.
  • the second metal layer (the layer in which the source 14 and the drain 15 are located) is overlaid on the semiconductor layer.
  • the line widths of the source 14 and the drain 15 are thinner, and in order to reduce the risk of disconnection during the etching, the climbing portion of the drain 15 (ie, the portion covering the edge of the semiconductor layer 13) It tends to increase its local line width.
  • This increases the degree of overlap of the second metal layer with the first metal layer (the layer in which the gate 11 is located), thus increasing the parasitic capacitance between the first metal layer and the second metal layer.
  • the increased parasitic capacitance will result in a greater degree of capacitive coupling effect and signal delay effect, which will affect the display effect of the liquid crystal display and reduce the display quality of the liquid crystal display.
  • An object of the present invention is to provide a thin film transistor and a display device for reducing a first metal layer and a second metal layer The parasitic capacitance between them improves the display quality of the liquid crystal display.
  • the invention provides a thin film transistor comprising:
  • the semiconductor layer has an extension portion, a planar projection of the extension portion beyond an edge of the gate, and the drain covers the extension portion.
  • the drain has a linear structure.
  • the drain includes a climbing portion and a flat portion covering the extended portion of the semiconductor layer.
  • the width of the climbing portion is greater than the width of the tile portion.
  • the source has a horseshoe shape.
  • the source includes an arc portion and two straight portions, and the two straight portions are connected at both ends of the arc portion.
  • the drain is located between two straight portions of the source.
  • the present invention also provides a display device comprising an array substrate, a color filter substrate, and a liquid crystal layer filled between the array substrate and the color filter substrate;
  • a plurality of the above thin film transistors are formed on the array substrate.
  • the display device is a mobile phone or a tablet computer.
  • the display device has a PPI value of 400 or more.
  • the present invention brings about the following advantageous effects:
  • the shape of the semiconductor layer is improved, and an extension portion is added to the semiconductor layer.
  • the planar projection of the extended portion extends beyond the edge of the gate and the drain covers the extended portion. Since the extended portion of the semiconductor layer is located outside the gate, the climbing portion of the drain is prevented from overlapping the gate.
  • the portion where the line width is increased in the drain does not overlap with the gate, thereby reducing the parasitic capacitance between the first metal layer and the second metal layer, thereby weakening the capacitive coupling effect and signal delay.
  • the effect is to improve the display quality of the liquid crystal display.
  • 1 is a schematic plan view of a conventional thin film transistor
  • Figure 2 is a cross-sectional view taken along line A-A of Figure 1;
  • FIG. 3 is a schematic plan view of a thin film transistor according to an embodiment of the present invention.
  • Figure 4 is a cross-sectional view taken along line B-B of Figure 3.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • Embodiments of the present invention provide a thin film transistor that can be applied to a liquid crystal display.
  • the present embodiment uses an amorphous silicon (abbreviated as a-Si) thin film transistor as an example.
  • the thin film transistor includes a gate 21 in order from the bottom to the top, covering the gate 21 .
  • the gate 21 is connected to the scan line 210, and the source 24 is connected to the data line 240.
  • the gate 21 and the scan line 210 are located in the first metal layer, and the source 24, the drain 25 and the data line 240 are located in the second metal layer.
  • the semiconductor layer 23 has an extension portion 231 whose plane projection projects beyond the edge of the gate 21 and the drain 25 covers the extension portion 231.
  • the drain electrode 25 in this embodiment has a linear structure
  • the source electrode 24 has a horseshoe-shaped structure.
  • the source electrode 24 includes an arc portion and two straight portions which are parallel to each other and are respectively connected to both ends of the arc portion.
  • the drain 25 is located between the two straight portions of the source 24 and is also parallel to the two straight portions of the source 24.
  • the source 24 of the horseshoe structure can increase the area of the channel in the thin film transistor, and the thin film transistor has a faster response speed.
  • the drain 25 includes a climbing portion 251 and a flat portion 252.
  • the climbing portion 251 covers the extended portion 231 of the semiconductor layer 23, and the remaining portion of the drain 25 is the tiling portion 252.
  • the width of the climbing portion 251 of the drain 25 is greater than the width of the tile portion 252.
  • the shape of the semiconductor layer 23 is improved, and the extended portion 231 is added to the semiconductor layer 23.
  • the planar projection of the extended portion 231 extends beyond the edge of the gate 21, and the climbing portion 251 of the drain 25 covers the extended portion 231 of the semiconductor layer 23. Since the extension portion 231 of the semiconductor layer 23 is located outside the gate electrode 21, the climbing portion 251 of the drain electrode 25 is prevented from overlapping the gate electrode 21, and the climbing portion 251 of the drain electrode 25 does not overlap the gate electrode 21. .
  • the line width can be increased at the climbing portion 251 of the drain 25, and since the gate portion 21 and the climbing portion 251 of the drain 25 do not overlap, the first metal layer and the second metal layer can be lowered.
  • the parasitic capacitance thus reducing the capacitive coupling effect and signal delay effect, improves the display quality of the liquid crystal display.
  • the capacitive coupling effect refers to: considering a single sub-pixel, in the actual operation of the thin film transistor, the gate 21 applies a high potential to cause electron accumulation in the conductive channel, and the thin film transistor is in an on state. At this time, the data line 240 writes a voltage to the pixel electrode through the source 24 and the drain 25. Then, the potential of the gate 21 is turned from negative to negative, and the thin film transistor enters a closed state. Without considering leakage, the pixel electrode of the thin film transistor maintains the previously written voltage until the next gate 1 is turned on.
  • the signal delay effect refers to: considering the entire sub-pixel array array, during the operation of the liquid crystal display, it is necessary to continuously switch the voltage of each wire, for example, the scanning line 210 is turned on and off, and the data 240 line is positive or negative. The potential is switched, so both the scan line 210 and the data line 240 transmit a square wave voltage.
  • the ideal square wave at the input end of the scan line 210 and the data line 240 the waveform of the square wave undergoes a certain degree of deformation after passing several sub-pixels. When the degree of such deformation is further aggravated, unevenness in brightness, chromaticity, and even display abnormality may occur.
  • the simulation results of the thin film transistor provided by the embodiment of the present invention and the existing thin film transistor are simulated by using simulation software, and the comparison results are as follows:
  • the size of the parasitic capacitance in the conventional thin film transistor is 0.034374 pF
  • the size of the parasitic capacitance in the thin film transistor provided by the embodiment of the present invention is 0.032121 pF.
  • the size of the parasitic capacitance in the thin film transistor provided by the embodiment of the present invention is only 93.4% of that of the prior art.
  • the climbing portion 251 having a large line width in the drain 25 does not overlap with the gate electrode 21, the parasitic capacitance between the first metal layer and the second metal layer can be reduced. Therefore, the capacitive coupling effect and the signal delay effect in the display process are weakened, and the display quality of the liquid crystal display is improved.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the embodiment of the invention provides a display device, which is preferably a display device with a high PPI (Pixels Per Inch) such as a mobile phone or a tablet computer, that is, a display device with a high number of pixels per inch.
  • the display device in this embodiment has a PPI value of 400 or more.
  • the display device provided by the embodiment of the invention includes an array substrate, a color filter substrate, and a liquid crystal layer filled between the array substrate and the color filter substrate.
  • the sub-pixels arranged in an array are formed on the array substrate, and the thin film transistors provided in the first embodiment are disposed in each sub-pixel.
  • the display device provided by the embodiment of the invention has the same technical features as the thin film transistor provided in the first embodiment, so that the same technical problem can be solved and the same technical effect can be achieved.
  • the technical solution provided by the embodiment of the present invention is particularly suitable for a display device with a high PPI value.
  • a display device with a higher PPI value the effect of improving the charging efficiency of the thin film transistor, that is, improving the signal delay, is more obvious.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种薄膜晶体管及显示装置，能够降低第一金属层与第二金属层之间的寄生电容，提高液晶显示器的显示品质。薄膜晶体管包括栅极（21）；覆盖在栅极上的栅极绝缘层（22）；形成于栅极绝缘层上的半导体层（23）；形成于半导体层上的源极（24）和漏极（25）；半导体层具有一延伸部分（231），延伸部分的平面投影超出栅极的边缘，且漏极覆盖延伸部分。

Description

薄膜晶体管及显示装置
本申请要求享有2016年7月1日提交的名称为“薄膜晶体管及显示装置”的中国专利申请CN201610510471.6的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，具体的说，涉及一种薄膜晶体管及显示装置。
背景技术
随着显示技术的发展，薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，简称TFT-LCD)已经成为最为常见的显示装置，是当前平面显示装置的主要品种之一，已经成为了现代IT、视讯产品中重要的显示平台。
其中的薄膜晶体管在有源矩阵显示技术中有着非常重要的作用。具体来说，在主动矩阵式(active matrix)液晶显示器中，每个子像素都配置有一个薄膜晶体管，使得每一个子像素可以独立的运作，且不易受到其他子像素的影响。如图1和图2所示，目前的薄膜晶体管大多采用底栅型结构，自下而上依次为栅极11、栅极绝缘层12、半导体层13，以及位于同一层的源极14和漏极15。其中，栅极11与扫描线110连接，源极14与数据线140连接。在这样结构的薄膜晶体管中，第二金属层(源极14和漏极15所在的图层)覆盖在半导体层之上。
在实际设计中，源极14和漏极15的线宽较细，同时为了降低在蚀刻过程中发生断线的风险，在漏极15的爬坡部分(即覆盖住半导体层13边缘的部分)往往会增加其局部的线宽。这就使得第二金属层与第一金属层(栅极11所在的图层)的交叠程度增大，因此增加了第一金属层与第二金属层之间的寄生电容。而增加的寄生电容会导致更大程度的电容耦合效应与信号延迟效应，这将会影响液晶显示器的显示效果，降低液晶显示器的显示品质。
发明内容
本发明的目的在于提供一种薄膜晶体管及显示装置，以降低第一金属层与第二金属层 之间的寄生电容，提高液晶显示器的显示品质。
本发明提供一种薄膜晶体管，包括：
栅极；
覆盖在所述栅极上的栅极绝缘层；
形成于所述栅极绝缘层上的半导体层；
形成于所述半导体层上的源极和漏极；
所述半导体层具有一延伸部分，所述延伸部分的平面投影超出所述栅极的边缘，且所述漏极覆盖所述延伸部分。
优选的是，所述漏极呈直线形结构。
进一步的是，所述漏极包括爬坡部分和平铺部分，所述爬坡部分覆盖着所述半导体层的延伸部分。
进一步的是，所述爬坡部分的宽度大于所述平铺部分的宽度。
优选的是，所述源极呈马蹄形结构。
进一步的是，所述源极包括一个弧形部分和两个直线部分，所述两个直线部分连接在所述弧形部分的两端。
进一步的是，所述漏极位于所述源极的两个直线部分之间。
本发明还提供一种显示装置，包括阵列基板、彩膜基板，以及填充在所述阵列基板与所述彩膜基板之间的液晶层；
所述阵列基板上形成有多个上述的薄膜晶体管。
优选的是，所述显示装置为手机或平板电脑。
优选的是，所述显示装置的PPI值在400以上。
本发明带来了以下有益效果：本发明提供的薄膜晶体管中，对半导体层的形状进行了改进，在半导体层中增加了一延伸部分。该延伸部分的平面投影超出栅极的边缘，且漏极覆盖着该延伸部分。因为半导体层的延伸部分位于栅极之外，所以避免了漏极的爬坡部分与栅极重叠。为了防止发生断线而在漏极中增加线宽的部分也不会与栅极重叠，从而降低了第一金属层与第二金属层之间的寄生电容，因此减弱了电容耦合效应和信号延迟效应，提高了液晶显示器的显示品质。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分的从说明书中变得显 而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚的说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图做简单的介绍：
图1是现有的薄膜晶体管的平面示意图；
图2是图1中沿A-A线的截面图；
图3是本发明实施例提供的薄膜晶体管的平面示意图；
图4是图3中沿B-B线的截面图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
实施例一：
本发明实施例提供一种薄膜晶体管，可应用于液晶显示器中。如图3和图4所示，本实施例以非晶硅(amorphous silicon，简称a-Si)薄膜晶体管为例进行扫描，该薄膜晶体管自下而上依次包括栅极21，覆盖在栅极21上的栅极绝缘层22，形成于栅极绝缘层22上的半导体层23，以及形成于半导体层23上的源极24和漏极25。其中，栅极21与扫描线210连接，源极24与数据线240连接。栅极21和扫描线210位于第一金属层，源极24、漏极25和数据线240位于第二金属层。半导体层具23有一延伸部分231，延伸部分231的平面投影超出栅极21的边缘，且漏极25覆盖延伸部分231。
从图3和图4中可以看出，本实施例中的漏极25呈直线形结构，源极24呈马蹄形结构。源极24包括一个弧形部分和两个直线部分，两个直线部分相互平行，分别连接在弧形部分的两端。漏极25位于源极24的两个直线部分之间，且也与源极24的两个直线部分平行。采用马蹄形结构的源极24，能够增大薄膜晶体管中沟道的面积，使薄膜晶体管具有更快的响应速度。
本实施例中，漏极25包括爬坡部分251和平铺部分252。其中，爬坡部分251覆盖着半导体层23的延伸部分231，漏极25的其余部分则为平铺部分252。为了降低在蚀刻过程中发生断线的风险，漏极25的爬坡部分251的宽度大于平铺部252分的宽度。
本发明实施例提供的薄膜晶体管中，对半导体层23的形状进行了改进，在半导体层23中增加了延伸部分231。延伸部分231的平面投影超出栅极21的边缘，且漏极25的爬坡部分251覆盖着半导体层23的延伸部分231。因为半导体层23的延伸部231分位于栅极21之外，所以避免了漏极25的爬坡部分251与栅极21重叠，则漏极25的爬坡部分251也不会与栅极21重叠。为了防止发生断线可以在漏极25的爬坡部分251增加线宽，而因为栅极21与漏极25的爬坡部分251不重叠，从而能够降低第一金属层与第二金属层之间的寄生电容，因此减弱了电容耦合效应和信号延迟效应，提高了液晶显示器的显示品质。
其中，电容耦合效应是指：考虑单独一个子像素，在薄膜晶体管的实际工作过程中，栅极21施加高电位，使导电沟道中产生电子的积累，薄膜晶体管处于导通状态。此时，数据线240向通过源极24、漏极25向像素电极写入电压。随后栅极21的电位由正转负，薄膜晶体管进入关闭状态。在不考虑漏电的情况下，薄膜晶体管的像素电极会保持先前写入的电压，直到下一次栅极1开启。然而，在栅极21与漏极25的重合面积增加，也就是耦合电容增加的情况下，当栅极21的电压突然关闭时，漏极25上的电压也会随之发生向下的突变，使得像素电极的实际电压小于写入的电压，造成显示效果的不良。
另一方面，信号延迟效应是指：考虑整个子像素阵列阵列，在液晶显示器的工作过程中，需要不停的切换各导线的电压，例如扫描线210的开启与关闭，数据240线由正负电位切换，因此扫描线210与数据线240传输的都是方波电压。考虑到每个子像素中的电阻与电容，扫描线210与数据线240所输入端的理想方波，在经过若干子像素之后方波的波形就会发生一定程度的变形。当这种变形的程度进一步加剧时，就会造成显示出的亮度、色度不均，甚至出现显示异常等不良现象。
利用模拟软件，将本发明实施例提供的薄膜晶体管与现有的薄膜晶体管的寄生电容进行仿真模拟，其对比结果如下表：
TFT结构 现有技术 本发明实施例
寄生电容大小 0.034374pF 0.032121pF
寄生电容比例 100.0％ 93.4％
可以看出，现有的薄膜晶体管中的寄生电容的大小为0.034374pF，本发明实施例提供的薄膜晶体管中的寄生电容的大小为0.032121pF。本发明实施例提供的薄膜晶体管中的寄生电容的大小仅为现有技术的93.4％。
因此，本发明实施例提供的薄膜晶体管中，因为漏极25中线宽较大的爬坡部分251与栅极21不重叠，从而能够降低第一金属层与第二金属层之间的寄生电容，因此减弱了显示过程中的电容耦合效应和信号延迟效应，提高了液晶显示器的显示品质。
实施例二：
本发明实施例提供一种显示装置，该显示装置优选为手机或平板电脑等高PPI(Pixels Per Inch)的显示装置，即每英寸的像素数量高的显示装置。本实施例中的显示装置的PPI值在400以上。
本发明实施例提供的显示装置包括阵列基板、彩膜基板，以及填充在阵列基板与彩膜基板之间的液晶层。其中，阵列基板上形成有阵列式排布的子像素，且每个子像素中都设置有上述实施例一提供的薄膜晶体管。
本发明实施例提供的显示装置，具有与实施例一提供的薄膜晶体管相同的技术特征，所以也能解决相同的技术问题，达到相同的技术效果。
另外，本发明实施例提供的技术方案特别适用于高PPI值的显示装置，PPI值越高的显示装置中，对于提高薄膜晶体管的充电效率即改善信号延迟的效果越明显。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种薄膜晶体管，包括：
    栅极；
    覆盖在所述栅极上的栅极绝缘层；
    形成于所述栅极绝缘层上的半导体层；
    形成于所述半导体层上的源极和漏极；
    所述半导体层具有一延伸部分，所述延伸部分的平面投影超出所述栅极的边缘，且所述漏极覆盖所述延伸部分。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述漏极呈直线形结构。
  3. 根据权利要求2所述的薄膜晶体管，其中，所述漏极包括爬坡部分和平铺部分，所述爬坡部分覆盖着所述半导体层的延伸部分。
  4. 根据权利要求3所述的薄膜晶体管，其中，所述爬坡部分的宽度大于所述平铺部分的宽度。
  5. 根据权利要求2所述的薄膜晶体管，其中，所述源极呈马蹄形结构。
  6. 根据权利要求5所述的薄膜晶体管，其中，所述源极包括一个弧形部分和两个直线部分，所述两个直线部分连接在所述弧形部分的两端。
  7. 根据权利要求6所述的薄膜晶体管，其中，所述漏极位于所述源极的两个直线部分之间。
  8. 一种显示装置，包括阵列基板、彩膜基板，以及填充在所述阵列基板与所述彩膜基板之间的液晶层；
    所述阵列基板上形成有多个薄膜晶体管；
    所述薄膜晶体管，包括：
    栅极；
    覆盖在所述栅极上的栅极绝缘层；
    形成于所述栅极绝缘层上的半导体层；
    形成于所述半导体层上的源极和漏极；
    所述半导体层具有一延伸部分，所述延伸部分的平面投影超出所述栅极的边缘，且所 述漏极覆盖所述延伸部分。
  9. 根据权利要求8所述的显示装置，其中，所述漏极呈直线形结构。
  10. 根据权利要求9所述的显示装置，其中，所述漏极包括爬坡部分和平铺部分，所述爬坡部分覆盖着所述半导体层的延伸部分。
  11. 根据权利要求10所述的显示装置，其中，所述爬坡部分的宽度大于所述平铺部分的宽度。
  12. 根据权利要求9所述的显示装置，其中，所述源极呈马蹄形结构。
  13. 根据权利要求12所述的显示装置，其中，所述源极包括一个弧形部分和两个直线部分，所述两个直线部分连接在所述弧形部分的两端。
  14. 根据权利要求13所述的显示装置，其中，所述漏极位于所述源极的两个直线部分之间。
  15. 根据权利要求8所述的显示装置，其中，所述显示装置为手机或平板电脑。
  16. 根据权利要求9所述的显示装置，其中，所述显示装置为手机或平板电脑。
  17. 根据权利要求10所述的显示装置，其中，所述显示装置为手机或平板电脑。
  18. 根据权利要求11所述的显示装置，其中，所述显示装置为手机或平板电脑。
  19. 根据权利要求12所述的显示装置，其中，所述显示装置为手机或平板电脑。
  20. 根据权利要求15所述的显示装置，其中，所述显示装置的PPI值在400以上。
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