WO2017219438A1 - Tft基板的制造方法 - Google Patents

Tft基板的制造方法 Download PDF

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WO2017219438A1
WO2017219438A1 PCT/CN2016/091810 CN2016091810W WO2017219438A1 WO 2017219438 A1 WO2017219438 A1 WO 2017219438A1 CN 2016091810 W CN2016091810 W CN 2016091810W WO 2017219438 A1 WO2017219438 A1 WO 2017219438A1
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manufacturing
pixel electrode
tft substrate
etching
mask
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French (fr)
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卢马才
赵书力
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
    • H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means

Definitions

  • the present invention relates to the field of flat panel display manufacturing technology, and in particular, to a method of manufacturing a TFT substrate.
  • flat panel displays have replaced bulky CRT displays in people's daily lives.
  • LCDs liquid crystal displays
  • OLED organic light-emitting diode
  • the flat panel display has the characteristics of small size, low power consumption, no radiation, and the like, and has occupied a dominant position in the current flat panel display market.
  • each pixel is provided with a switching unit for controlling the pixel, that is, a Thin Film Transistor (TFT), the TFT includes at least a gate electrode, a source, a drain, and a gate insulating layer and Source layer.
  • TFT Thin Film Transistor
  • Each pixel can be independently controlled by the driving circuit without causing crosstalk or the like to other pixels.
  • amorphous silicon A-Si
  • low temperature polysilicon low temperature polysilicon
  • metal oxide Metal Oxide
  • organic semiconductor materials As far as the process is concerned, the amorphous silicon semiconductor process is the simplest and mature technology, and is currently the mainstream semiconductor material.
  • the manufacturing process of amorphous silicon semiconductor usually adopts five masks or four mask processes;
  • an etch barrier structure is generally used, which generally adopts a six-mask process.
  • the process flow is complicated and the cost is high.
  • an object of the present invention is to provide a method for manufacturing a TFT substrate of a three-pass mask to improve process efficiency and reduce difficulty.
  • the present invention provides a method of fabricating a TFT substrate, comprising:
  • Step 10 forming a TFT gate pattern on the substrate by using a first mask process
  • Step 20 forming an active layer pattern and a source/drain metal electrode pattern on the substrate by using a second mask process
  • Step 30 depositing a passivation layer on the substrate, and coating the photoresist, defining a pixel electrode pattern by using a third mask process, performing etching and photoresisting, and then depositing the pixel electrode;
  • Step 40 forming a pixel electrode pattern by etching treatment or direct photoresist stripping.
  • the second mask is a halftone mask or a gray dimming cover.
  • the third reticle is a halftone reticle or a common reticle.
  • the step 30 includes: depositing a passivation layer on the substrate, and coating the photoresist, exposing and developing by using a third mask process to define a pixel electrode pattern, and exposing the gate pattern and the source/drain metal electrode pattern by etching And forming a pile on the photoresist by etching, and then depositing a pixel electrode.
  • the height of the raised peak on the photoresist is The maximum angle of the raised peak is greater than 80 degrees, and the distance between the raised peak and the raised peak is
  • the etching is dry etching.
  • the gas used for dry etching is a single or a mixture of SF6, CF4, C4F8, Ar, He or O2 gas, and the etching gas pressure is 5 mT to 10000 mT.
  • the active layer is A-Si or IGZO.
  • the passivation layer is SiNx or SiO.
  • the pixel electrode is ITO.
  • the invention also provides a method for manufacturing a TFT substrate, comprising:
  • Step 10 forming a TFT gate pattern on the substrate by using a first mask process
  • Step 20 forming an active layer pattern and a source/drain metal electrode pattern on the substrate by using a second mask process
  • Step 30 depositing a passivation layer on the substrate, and coating the photoresist, defining a pixel electrode pattern by using a third mask process, performing etching and photoresisting, and then depositing the pixel electrode;
  • Step 40 forming a pixel electrode pattern by etching treatment or direct photoresist stripping
  • the active layer is A-Si or IGZO;
  • the passivation layer is SiN x or SiO;
  • the pixel electrode is ITO.
  • the manufacturing method of the TFT substrate of the present invention provides an effective stripping method for depositing ITO on the PR for the 3Mask TFT process, which will greatly improve the process efficiency and reduce the difficulty, and effectively improve the 3Mask TFT process capability.
  • FIG. 1 is a flow chart showing a method of manufacturing a TFT substrate of the present invention
  • FIG. 2 is a schematic view showing a process of a first photomask according to a preferred embodiment of a method for fabricating a TFT substrate of the present invention
  • FIG. 3 is a schematic view showing a process of a second photomask according to a preferred embodiment of the method for fabricating a TFT substrate of the present invention
  • FIG. 4 is a schematic view showing a process of a third photomask according to a preferred embodiment of the method for fabricating a TFT substrate of the present invention
  • FIG. 5 is a schematic view showing a deposition of a pixel electrode in a third photomask process according to a preferred embodiment of the method for fabricating a TFT substrate of the present invention
  • FIG. 6 is a schematic diagram of forming a pixel electrode pattern in a preferred embodiment of a method of fabricating a TFT substrate of the present invention.
  • a flow chart of a method of fabricating a TFT substrate of the present invention mainly includes:
  • Step 10 forming a TFT gate pattern on the substrate by using a first mask process
  • Step 20 forming an active layer pattern and a source/drain metal electrode pattern on the substrate by using a second mask process
  • Step 30 depositing a passivation layer on the substrate, defining a pixel electrode pattern by using a third mask process, performing etching and photoresisting, and then depositing a pixel electrode;
  • Step 40 forming a pixel electrode pattern by etching treatment or direct photoresist stripping.
  • Step 10 of the present invention will be understood from top to bottom in conjunction with FIG.
  • FIG. 3 it is a second light of a preferred embodiment of the TFT substrate manufacturing method of the present invention.
  • a mask process schematic which is illustrated below with reference to Figure 3 from top to bottom.
  • the substrate 200 is deposited with a gate insulating layer 301, a semiconductor layer 302 such as A-Si, IGZO, etc., and a second metal layer 303, which is coated by the photoresist 304, using an HT/GT Mask (halftone mask or The gray dimming cover exposes, develops, and etches the photoresist 304 to form a semiconductor active layer pattern 305 and a source/drain metal electrode pattern 306.
  • HT/GT Mask halftone mask or The gray dimming cover exposes, develops, and etches the photoresist 304 to form a semiconductor active layer pattern 305 and a source/drain metal electrode pattern 306.
  • FIG. 4 is a schematic diagram of a third photomask process according to a preferred embodiment of the method for fabricating a TFT substrate of the present invention
  • the step 30 of the present invention will be understood from the top to the bottom in conjunction with FIG.
  • a PV layer (passivation layer) 401 is deposited on the substrate 200, and the material may be SiNx, SiO, or the like.
  • the substrate 200 is subjected to exposure and development of the photoresist 402 to form a pixel electrode pattern, and then the PV layer 401 and the gate insulating layer 301 are etched according to the pixel electrode pattern to remove the PV layer 401 and the gate insulating layer 301.
  • the portion of the photoresist 402 is not covered above to expose the portion of the source/drain metal electrode pattern 306 that is in contact with the pixel electrode pattern and the metal gate pattern 203; the etching process may be dry etching, ie, plasma etching, etching
  • the gas may be a single or a mixture of gases such as SF 6 , CF 4 , C 4 F 8 , Ar, He, O 2 , etc., and the etching gas pressure may be 5 mT to 10000 mT.
  • the photoresist 402 is subjected to photoresist haze/surface resist hardening treatment, and the photoresist of the passivation layer and the PR of the pixel region are atomized by etching or other methods to generate an increase in the pile surface. Surface roughness, the surface of the photoresist 402 appears suede.
  • the convex peak 403 (Taper) above the plane of the photoresist 402 can be The maximum angle of the convex peak 403 is greater than 80 degrees, and the distance between the convex peak 403 and the convex peak 403 may be
  • the third mask process can be a halftone mask or a conventional mask.
  • FIG. 5 it is a schematic diagram of depositing a pixel electrode in a third photomask process according to a preferred embodiment of the method for fabricating a TFT substrate of the present invention.
  • a pixel electrode 501 such as ITO or other conductive material is deposited on the substrate 200.
  • annealing annealing such as ITO or other conductive materials
  • step 40 of the present invention can be understood in conjunction with FIG.
  • the remaining portion of the deposited pixel electrode 501 in FIG. 5 forms a pixel electrode pattern 601 by an etching process or direct photoresist stripping.
  • the substrate 200 is directly subjected to photoresist stripping to form a pixel electrode pattern 601.
  • the substrate 200 is first etched (for example, wet-etched) by etching the pixel electrode 501 (FIG. 5) on the photoresist 402, and the pixel electrode pattern is completed.
  • 601 (as shown in FIG. 6) is only a small amount of etching; then photoresist stripping is performed to form a pixel electrode pattern 601.
  • the photoresist peeling ability can be enhanced by dry etching the pixel electrode 501 on the photoresist/wet photoresist 402 or the like.
  • the gate-drain metal electrode film layer may be deposited on the substrate 200, and the film layer may be a metal film layer such as molybdenum aluminum molybdenum (Mo/Al/Mo) or titanium aluminum titanium (Ti/Al/Ti).
  • Mo/Al/Mo molybdenum aluminum molybdenum
  • Ti/Al/Ti titanium aluminum titanium
  • the present invention provides a method of fabricating a general thin film transistor.
  • the present invention conserves a Mask by completing the PV layer with Pixel ITO in a single Mask.
  • the main feature is that after PV layer deposition and post-PV PR exposure development, PV etching and PR texturing are performed, and then Pixel ITO is deposited. At this time, the ITO of the non-pixel electrode pattern will be deposited on the PR after the velvet. Due to the shadow of the PR suede, the ITO will not cover the entire surface of the PR, so that when the PR is peeled off, the stripping liquid is easily contacted with the PR and efficiently stripped. .
  • the thickness of ITO deposited on the PR is much smaller than the ITO of the defined pixel electrode. If the ITO etching solution is passed, the ITO etching of the PR surface can be effectively completed. The ITO on the pixel electrode will only lose a small fraction.
  • the manufacturing method of the TFT of the present invention provides an effective stripping method for depositing ITO on the PR for the 3Mask TFT process, which will greatly improve the process efficiency and reduce the difficulty, and effectively improve the 3Mask TFT process capability.

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  • Thin Film Transistor (AREA)

Abstract

一种TFT基板的制造方法包括：步骤10、在基板（200）上利用第一道光罩形成TFT栅极图案（203）；步骤20、在该基板（200）上利用第二道光罩形成有源层图案（305）、源漏极金属电极图案（306）；步骤30、在该基板（200）上沉积钝化层（401），以及涂布光阻（402），利用第三道光罩工艺定义像素电极图案，进行刻蚀以及光阻制绒，然后沉积像素电极（501）；步骤40、通过刻蚀处理或直接光阻剥离，形成像素电极图案（601）。TFT基板的制造方法提供了PR上沉积ITO有效剥离方法用于3Mask TFT制程，将会提高制程效率及降低难度，有效提升3Mask TFT制程能力。

Description

TFT基板的制造方法 技术领域
本发明涉及平板显示器制造技术领域，特别涉及一种TFT基板的制造方法。
背景技术
近年来，显示技术得到快速的发展，平板显示器已取代笨重的CRT显示器日益深入人们的日常生活中。目前，常用的平板显示器包括液晶显示器(Liquid Crystal Display，LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)显示器。上述平板显示器具有体积小、功耗低、无辐射等特点，在当前的平板显示器市场中占据了主导地位。
而在平板显示器的阵列基板中，每一个像素配备了用于控制该像素的开关单元，即薄膜晶体管(Thin Film Transistor，TFT)，TFT至少包含栅电极，源、漏极以及栅绝缘层和有源层。通过驱动电路可以独立控制每一个像素，同时不会对其他像素造成串扰等的影响。
目前常见的TFT背板主要采用非晶硅(A-Si)、低温多晶硅、金属氧化物(Metal Oxide)和有机半导体等材料。就工艺而言，非晶硅半导体工艺最为简单，技术比较成熟，是目前主流的半导体材料，但采用非晶硅半导体的制造工艺中通常采用5道光罩(Mask)或4道光罩工艺；而采用金属氧化物半导体的制造工艺中通常采用刻蚀阻挡形结构，其一般要采用6道光罩工艺。在现有技术中，无论采用非晶硅半导体工艺还是采用金属氧化物半导体工艺，不但工艺流程复杂，而且成本高。
随着TFT技术的发展，TFT制程Mask需求从5/6Mask降到现在主流的4Mask，成本大大降低。每减少一道Mask，机器物料时间成本都会下降较多，大大提高产品竞争力。3Mask A-Si TFT因其节约一道Mask，较大幅度降低成本，相关技术较热门。
目前开发出的3Mask TFT技术大部分是通过把PV(钝化)与Pixel(像素)ITO(氧化铟锡)在一道Mask内完成，但所遇到PR(光阻)上的ITO剥离问题。通常PR上沉积Pixel ITO后剥离时间较长，影响Tact time(生产节拍时间)，以及PR剥离残留和毛边问题都会严重影响制程或产品性能。
发明内容
因此，本发明的目的在于提供一种三道光罩的TFT基板制造方法，以提高制程效率及降低难度。
为实现上述目的，本发明提供了一种TFT基板的制造方法，包括：
步骤10、在基板上利用第一道光罩工艺形成TFT栅极图案；
步骤20、在该基板上利用第二道光罩工艺形成有源层图案、源漏极金属电极图案；
步骤30、在该基板上沉积钝化层，以及涂布光阻，利用第三道光罩工艺定义像素电极图案，进行刻蚀以及光阻制绒，然后沉积像素电极；
步骤40、通过刻蚀处理或直接光阻剥离，形成像素电极图案。
其中，该第二道光罩为半色调光罩或灰色调光罩。
其中，该第三道光罩为半色调光罩或普通光罩。
其中，步骤30包括：在该基板上沉积钝化层，以及涂布光阻，利用第三道光罩工艺曝光、显影以定义像素电极图案，通过刻蚀露出栅极图案和源漏极金属电极图案，并通过刻蚀在所述光阻上形成绒面，然后沉积像素电极。
其中，该光阻上的凸起峰高度为
Figure PCTCN2016091810-appb-000001
凸起峰最大角度大于80度，凸起峰与凸起峰之间距离为
Figure PCTCN2016091810-appb-000002
其中，该刻蚀为干刻。
其中，用于干刻的气体为SF6、CF4、C4F8、Ar、He或O2气体中的单种或混合体，刻蚀气压为5mT～10000mT。
其中，该有源层为A-Si或IGZO。
其中，该钝化层为SiNx或SiO。
其中，该像素电极为ITO。
本发明还提供一种TFT基板的制造方法，包括：
步骤10、在基板上利用第一道光罩工艺形成TFT栅极图案；
步骤20、在该基板上利用第二道光罩工艺形成有源层图案、源漏极金属电极图案；
步骤30、在该基板上沉积钝化层，以及涂布光阻，利用第三道光罩工艺定义像素电极图案，进行刻蚀以及光阻制绒，然后沉积像素电极；
步骤40、通过刻蚀处理或直接光阻剥离，形成像素电极图案；
其中，该有源层为A-Si或IGZO；
其中，该钝化层为SiNx或SiO；
其中，该像素电极为ITO。
综上所述，本发明TFT基板的制造方法提供了PR上沉积ITO有效剥离方法用于3Mask TFT制程，将会大大提高制程效率及降低难度，有效提升3Mask TFT制程能力。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为本发明TFT基板的制造方法的流程图；
图2为本发明TFT基板的制造方法一较佳实施例的第一道光罩工艺示意图；
图3为本发明TFT基板的制造方法一较佳实施例的第二道光罩工艺示意图；
图4为本发明TFT基板的制造方法一较佳实施例的第三道光罩工艺示意图；
图5为本发明TFT基板的制造方法一较佳实施例的第三道光罩工艺中沉积像素电极的示意图；
图6为本发明TFT基板的制造方法一较佳实施例中形成像素电极图案的示意图。
具体实施方式
参见图1，其为本发明TFT基板的制造方法的流程图。该方法主要包括：
步骤10、在基板上利用第一道光罩工艺形成TFT栅极图案；
步骤20、在该基板上利用第二道光罩工艺形成有源层图案、源漏极金属电极图案；
步骤30、在该基板上沉积钝化层，利用第三道光罩工艺定义像素电极图案，进行刻蚀以及光阻制绒，然后沉积像素电极；
步骤40、通过刻蚀处理或直接光阻剥离，形成像素电极图案。
参见图2，其为本发明TFT基板的制造方法一较佳实施例的第一道光罩工艺示意图，下面结合图2由上至下所示来理解本发明步骤10。在玻璃基板200上沉积第一金属层201，经光阻202涂布曝光显影刻蚀后形成薄膜晶体管金属栅极图形203；
参见图3，其为本发明TFT基板的制造方法一较佳实施例的第二道光 罩工艺示意图，下面结合图3由上至下所示来理解本发明步骤20。对上述基板200进行沉积栅极绝缘层301、半导体层302，如A-Si，IGZO等，及沉积第二金属层303，通过光阻304涂布，采用HT/GT Mask(半色调光罩或灰色调光罩)对光阻304进行曝光，显影，刻蚀，形成半导体有源层图案305、源漏极金属电极图案306。
参见图4，其为本发明TFT基板的制造方法一较佳实施例的第三道光罩工艺示意图，下面结合图4由上至下所示来理解本发明步骤30。接着对上述基板200沉积PV层(钝化层)401，材料可以为SiNx、SiO等。接着再对上述基板200进行光阻402涂布曝光显影，形成像素电极图案，接着根据像素电极图案对PV层401、栅极绝缘层301进行刻蚀，移除PV层401、栅极绝缘层301上方未覆盖有光阻402的部分，以露出源漏极金属电极图案306与像素电极图案接触的部分及金属栅极图形203；此刻蚀过程，可以为干刻，即等离子体刻蚀，刻蚀气体可以为SF6、CF4、C4F8、Ar、He、O2等气体的单种或混合体，刻蚀气压可为5mT～10000mT。刻蚀后，对光阻402进行光阻制绒(PR Haze)/表层光阻硬化处理，通过刻蚀或其他方法使得定义钝化层光阻及像素区域的PR雾化以产生绒面增大表面粗糙度，光阻402表面出现绒面。所谓绒面指光阻表面粗糙度很大，光阻402平面上方凸起峰403(Taper)可为
Figure PCTCN2016091810-appb-000003
凸起峰403最大角度大于80度，凸起峰403与凸起峰403之间距离可以为
Figure PCTCN2016091810-appb-000004
该第三道光罩工艺可以为半色调光罩或普通光罩。
接下来参见图5，其为本发明TFT基板的制造方法一较佳实施例的第三道光罩工艺中沉积像素电极的示意图。光阻402进行制绒处理后，接着对上述基板200沉积像素电极501，如ITO或其他导电材料。沉积后，可进行退火处理(退火如ITO或其他导电材料)。
接下来参见图6，其为本发明TFT基板的制造方法一较佳实施例中形成像素电极图案的示意图，可结合图6来理解本发明步骤40。步骤40中通过刻蚀处理或直接光阻剥离，图5中沉积像素电极501剩余部分形成像素电极图案601。此较佳实施例中通过对上述基板200直接进行光阻剥离，以形成像素电极图案601。
或者在另一较佳实施例中，先对基板200进行刻蚀(例如湿刻)，此刻蚀程度为刚好把光阻402上的像素电极501(如图5)刻蚀完成，而像素电极图案601(如图6)则只是少量刻蚀；然后再进行光阻剥离，形成像素电极图案601。通过干刻光阻/湿刻光阻402上的像素电极501等方法可以增强光阻剥离能力。
接下来还可以选择在上述基板200上进行栅漏极金属电极膜层沉积，此膜层可以为钼铝钼(Mo/Al/Mo)、钛铝钛(Ti/Al/Ti)等金属膜层结构，接着进行光阻涂布曝光显影刻蚀及光阻剥离。
至此，整个薄膜晶体管基本架构已经完成，此薄膜晶体管制作过程也可以根据实际情况稍作改变。
本发明提供了一种适用于一般薄膜晶体管的制作方法。参照本发明的较佳实施例，本发明通过把PV层与Pixel ITO在一道Mask内完成而节约一道Mask。主要特征为，通过PV层沉积及PV后的PR曝光显影后，通过PV刻蚀及PR制绒，然后沉积Pixel ITO。此时非像素电极图案的ITO将会沉积在制绒后的PR上，由于PR绒面的阴影作用，ITO将无法全部覆盖PR表面，从而PR剥离时，剥离液很容易与PR接触而高效剥离。另一方面，由于PR制绒后表面积大大增大，因此沉积在PR上的ITO厚度比定义的像素电极的ITO小很多，如果经过ITO刻蚀液，可以有效把PR表面的ITO刻蚀完成而像素电极上的ITO将只会损失很少一部分。
综上，本发明TFT的制造方法提供了PR上沉积ITO有效剥离方法用于3Mask TFT制程，将会大大提高制程效率及降低难度，有效提升3Mask TFT制程能力。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (17)

  1. 一种TFT基板的制造方法，包括：
    步骤10、在基板上利用第一道光罩工艺形成TFT栅极图案；
    步骤20、在该基板上利用第二道光罩工艺形成有源层图案、源漏极金属电极图案；
    步骤30、在该基板上沉积钝化层，以及涂布光阻，利用第三道光罩工艺定义像素电极图案，进行刻蚀以及光阻制绒，然后沉积像素电极；
    步骤40、通过刻蚀处理或直接光阻剥离，形成像素电极图案。
  2. 如权利要求1所述的TFT基板的制造方法，其中，该第二道光罩工艺为半色调光罩或灰色调光罩。
  3. 如权利要求1所述的TFT基板的制造方法，其中，该第三道光罩工艺为半色调光罩或普通光罩。
  4. 如权利要求1所述的TFT基板的制造方法，其中，步骤30包括：在该基板上沉积钝化层，以及涂布光阻，利用第三道光罩工艺曝光、显影以定义像素电极图案，通过刻蚀露出栅极图案和源漏极金属电极图案，并通过刻蚀在所述光阻上形成绒面，然后沉积像素电极。
  5. 如权利要求4所述的TFT基板的制造方法，其中，该光阻上的凸起峰高度为
    Figure PCTCN2016091810-appb-100001
    凸起峰最大角度大于80度，凸起峰与凸起峰之间距离为
    Figure PCTCN2016091810-appb-100002
  6. 如权利要求4所述的TFT基板的制造方法，其中，该刻蚀为干刻。
  7. 如权利要求6所述的TFT基板的制造方法，其中，用于干刻的气体为SF6、CF4、C4F8、Ar、He或O2气体中的单种或混合体，刻蚀气压为5mT～10000mT。
  8. 如权利要求1所述的TFT基板的制造方法，其中，该有源层为A-Si或IGZO。
  9. 如权利要求1所述的TFT基板的制造方法，其中，该钝化层为SiNx或SiO。
  10. 如权利要求1所述的TFT基板的制造方法，其中，该像素电极为ITO。
  11. 一种TFT基板的制造方法，包括：
    步骤10、在基板上利用第一道光罩工艺形成TFT栅极图案；
    步骤20、在该基板上利用第二道光罩工艺形成有源层图案、源漏极金 属电极图案；
    步骤30、在该基板上沉积钝化层，以及涂布光阻，利用第三道光罩工艺定义像素电极图案，进行刻蚀以及光阻制绒，然后沉积像素电极；
    步骤40、通过刻蚀处理或直接光阻剥离，形成像素电极图案；
    其中，该有源层为A-Si或IGZO；
    其中，该钝化层为SiNx或SiO；
    其中，该像素电极为ITO。
  12. 如权利要求11所述的TFT基板的制造方法，其中，该第二道光罩工艺为半色调光罩或灰色调光罩。
  13. 如权利要求11所述的TFT基板的制造方法，其中，该第三道光罩工艺为半色调光罩或普通光罩。
  14. 如权利要求11所述的TFT基板的制造方法，其中，步骤30包括：在该基板上沉积钝化层，以及涂布光阻，利用第三道光罩工艺曝光、显影以定义像素电极图案，通过刻蚀露出栅极图案和源漏极金属电极图案，并通过刻蚀在所述光阻上形成绒面，然后沉积像素电极。
  15. 如权利要求14所述的TFT基板的制造方法，其中，该光阻上的凸起峰高度为
    Figure PCTCN2016091810-appb-100003
    凸起峰最大角度大于80度，凸起峰与凸起峰之间距离为
    Figure PCTCN2016091810-appb-100004
  16. 如权利要求14所述的TFT基板的制造方法，其中，该刻蚀为干刻。
  17. 如权利要求16所述的TFT基板的制造方法，其中，用于干刻的气体为SF6、CF4、C4F8、Ar、He或O2气体中的单种或混合体，刻蚀气压为5mT～10000mT。
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