WO2017217369A1 - Dispositif semi-conducteur de puissance - Google Patents

Dispositif semi-conducteur de puissance Download PDF

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Publication number
WO2017217369A1
WO2017217369A1 PCT/JP2017/021649 JP2017021649W WO2017217369A1 WO 2017217369 A1 WO2017217369 A1 WO 2017217369A1 JP 2017021649 W JP2017021649 W JP 2017021649W WO 2017217369 A1 WO2017217369 A1 WO 2017217369A1
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WIPO (PCT)
Prior art keywords
wire
solder layer
semiconductor device
power semiconductor
bump
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PCT/JP2017/021649
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English (en)
Japanese (ja)
Inventor
辰則 柳本
晋助 浅田
耕一 東久保
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to DE112017002961.9T priority Critical patent/DE112017002961B4/de
Priority to CN201780035418.8A priority patent/CN109314063B/zh
Priority to CN202210947454.4A priority patent/CN115274465A/zh
Priority to JP2018523895A priority patent/JP6487122B2/ja
Publication of WO2017217369A1 publication Critical patent/WO2017217369A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the present invention relates to a power semiconductor device, and more particularly to a power semiconductor device in which wire bumps made of a material capable of forming an alloy with a solder layer material are arranged at predetermined positions.
  • a wire bump is formed by wedge-bonding a wire mainly composed of Al or Cu on a copper plate, and the thickness of the solder layer (For example, Patent Documents 1 and 2).
  • an object of the present invention is to provide a power semiconductor device having high reliability and high thermal conductivity even in high temperature operation.
  • the present invention includes an insulating substrate having a conductor layer on at least a surface, a wire bump provided on the conductor layer, a semiconductor element placed on the wire bump, and a conductor layer and a semiconductor element on the conductor layer.
  • a power semiconductor device comprising a solder layer to be bonded and having an alloy made of a wire bump material and a solder layer material at an interface between the wire bump and the solder layer.
  • the present invention also provides a base plate, a plurality of wire bumps provided on the base plate, an insulating substrate placed on the wire bump and having a conductor layer on at least the back surface, and an insulating substrate on the base plate And a solder layer to which the conductor layer is bonded, and an alloy composed of the material of the wire bump and the material of the solder layer is formed at the interface between the wire bump and the solder layer.
  • the thickness of the solder layer can be made uniform by the wire bumps, the generation of voids (voids) in the solder layer can be prevented, and the crack of the solder layer can be further developed. Therefore, it is possible to provide a power semiconductor device having high reliability and high thermal conductivity.
  • FIG. 3 is an enlarged cross-sectional view of a part of the power semiconductor device of FIG. 2.
  • FIG. 3 is an enlarged cross-sectional view of a part of the power semiconductor device of FIG. 2.
  • FIG. 6B is a cross-sectional view of FIG. 6A when viewed in the AA direction.
  • FIG. 1 is a cross-sectional view of a power semiconductor device according to a first embodiment of the present invention, the whole being represented by 100.
  • 2 is an enlarged sectional view of a portion A surrounded by a broken line in FIG.
  • the power semiconductor device 100 includes a base plate 1.
  • the base plate 1 is made of Cu, for example.
  • An insulating substrate 3 is fixed to the upper surface of the base plate 1 by a solder layer 7.
  • the solder layer 7 is made of, for example, Sn.
  • the insulating substrate 3 includes an insulating member 3b and conductor layers 3a and 3c provided on the front and back surfaces, respectively.
  • the insulating member 3b is made of, for example, aluminum nitride
  • the conductor layers 3a and 3c are made of, for example, a metal such as copper.
  • a semiconductor element 4 is fixed on the conductor layer 3 a of the insulating substrate 3 by a solder layer 7.
  • the semiconductor element 4 is a power semiconductor element (power device) such as a MOSFET or IGBT.
  • a semiconductor element 4 made of, for example, a Schottky barrier diode is fixed on another conductor layer 3a.
  • the periphery of the base plate 1 is surrounded by a case 2 made of, for example, polyphenyl sulfide resin (PPS) or polybutylene terephthalate resin (PBT).
  • a lead-out terminal 8 is provided on the outer periphery of the case 2.
  • the terminal 8 is made of, for example, copper or aluminum.
  • the electrode (not shown) of the semiconductor element 4 and the terminal 8 are electrically connected by a bonding wire 6.
  • the bonding wire 6 is made of, for example, copper or aluminum.
  • the inside of the case 2 is filled with a sealing material 5 so as to bury the semiconductor element 4 and the bonding wire 6.
  • the sealing material 5 is made of, for example, silicon gel.
  • wire bumps 9 are provided as spacers in the solder layer 7 that connects the conductor layer 3 a and the semiconductor element 4.
  • the wire bump 9 is made of a material capable of forming an alloy with the material of the solder layer 7 under the joining condition of the solder layer 7.
  • the wire bump 9 only needs to be placed in the solder layer 7 that connects the conductor layer 3a and the semiconductor element 4.
  • the joints 9a and 9b at both ends of the wire loop 9d are formed. If it is bonded to the conductor layer 3a by wedge bonding, it is preferable because positional displacement does not occur.
  • FIG. 3B is a cross-sectional view of the wire bump 9 in a direction (hereinafter referred to as “longitudinal direction”) from the bonding portion 9a to the bonding portion 9b.
  • the wire bump 9 is preferably made of a bonding wire in which the joint portions 9a and 9b at both ends are joined to the conductor layer 3a.
  • the joint portion 9a , 9b is also preferably in contact with the conductor layer 3a.
  • the distance between the two wedge bond joints 9a and 9b is preferably 2.0 mm or less. This is because when the distance is longer than 2.0 mm, one end of the bonding wire is wedge-bonded to the conductor layer 3a, and then the other end is wedge-bonded. It is because it becomes difficult to arrange so that it may touch.
  • the distance between the wedge bond joint and the stitch bond joint and the distance between adjacent stitch bond joints are preferably less than 2.0 mm.
  • wire bump 9 may be bonded to the conductor layer 3a only by one bonding portion 9a (or 9b).
  • the upper part of the wire bump 9 is in contact with the back surface of the semiconductor element 4, and the wire bump 9 supports the semiconductor element 4.
  • 4A to 4C show the arrangement of the wire bumps 9 on the conductor layer 3a.
  • 4A to 4C are top views of the state in which the wire bumps 9 are bonded to the conductor layer 3a, and the portion above the solder layer 7 is omitted.
  • a broken line 10 is a semiconductor element mounting region in which the semiconductor element 4 is vertically projected on the conductor layer 3a, and the semiconductor element 4 is placed on this region.
  • the wire bumps 9 are arranged at the four corners of the semiconductor element mounting region 10 such that the longitudinal direction is the diagonal direction of the semiconductor element mounting region 10.
  • the wire bumps 9 may be arranged on a diagonal line of the semiconductor element mounting region 10 or may be arranged so as to be parallel to the diagonal line but not on the diagonal line.
  • the thickness of the solder layer 7 can be made more uniform.
  • wire bumps are conventionally formed from Al wires or the like that are not alloyed with the solder 7a, the solder material does not get wet around the wire bumps, and voids (voids) are generated in the solder layer 7.
  • the wire bump 9 can be alloyed with the solder material of the solder layer 7 under the formation conditions of the solder layer 7. Made of material. For this reason, the solder material spreads around the wire bump 9 and the generation of voids can be prevented. Further, an alloy can be formed at the interface between the wire bump 9 and the solder layer 7.
  • the diameter of the wire used for the wire bump 9 is preferably about 100 ⁇ m. However, in order to increase the solder layer 7 between the insulating substrate 3 and the semiconductor element 4 and improve the life of the joint, for example, the diameter is 150 ⁇ m. A wire may be used.
  • the solder layer 7 is preferably thin.
  • the solder layer 7 has a thickness of about 50 ⁇ m. Therefore, the diameter of the wire used for the wire bump 9 may be about 50 ⁇ m.
  • the wire bumps 9 are arranged at positions near or at the four corners of the semiconductor element mounting region 10 to prevent the inclination of the semiconductor element 4.
  • the film thickness of the solder layer 7 connecting the conductor layer 3a of the insulating substrate 3 and the semiconductor element 4 can be made more uniform.
  • wire bumps 19 may be provided on the diagonal line of the semiconductor element mounting region 10.
  • the four wire bumps 19 are preferably provided equidistant from the intersection of the diagonal lines.
  • the longitudinal direction of the wire bump 19 is a direction parallel to one side of the semiconductor element mounting region 10, but may be another direction.
  • the number of wire bumps 19 is not limited to four, but it is preferable to arrange them at equal intervals on a diagonal line.
  • the semiconductor element 4 when the semiconductor element 4 is die-bonded on the conductor layer 3a, the semiconductor element 4 may be warped by the applied heat. However, by providing the wire bump 19, the warp of the semiconductor element 4 is suppressed, The film thickness of the solder layer 7 can be made uniform.
  • the wire bumps 19 are only required to be arranged relatively uniformly in the semiconductor element mounting region 10, and there are no particular restrictions on the position, number, or arrangement direction.
  • the wire bumps 9 in FIG. 4B may be arranged so that the longitudinal direction is perpendicular to the diagonal line of the semiconductor element mounting region 10.
  • the stress generated in the solder layer 7 due to the difference in linear expansion coefficient between the semiconductor element 4 and the insulating substrate 3 during the operation of the semiconductor element 4 is concentrated near the four corners of the solder layer 7 in the semiconductor element mounting region 10. From this point, cracks start to develop in the solder layer 7.
  • the wire bump 9 is made of a material capable of forming an alloy with the solder material of the solder layer 7.
  • an alloy such as Cu 6 Sn 5 or Cu 3 Sn is formed at the interface between the solder layer 7 and the wire bump 9. These alloys have higher mechanical strength and higher fatigue resistance than the solder layer 7. Note that Cu may remain in the center of the wire bump 9 where these alloys are formed at the interface.
  • the wire bumps 9 formed on the surface with such an alloy having a high mechanical strength at the four corners of the semiconductor element mounting region 10 the progress of cracks generated at the four corners of the solder layer 7 can be stopped by the wire bumps 9.
  • the wire bumps 9 by arranging the wire bumps 9 so that the longitudinal direction of the wire bumps 9 is perpendicular to the diagonal line of the semiconductor element mounting region 10, the effect of stopping the cracks can be increased.
  • the arrangement of the wire bumps 9 can be appropriately selected from an arrangement in which the longitudinal direction of the wire bumps 9 is parallel to the diagonal line of the semiconductor element mounting region 10 (see FIG. 4A) to a vertical arrangement (see FIG. 4C).
  • the crack that has stopped after reaching the wire bump 9 may develop along the wire bump 9, but the stress generated in the solder layer 7 is generated from the four corners toward the center, so that the diagonal line is formed as shown in FIG. 4C.
  • By arranging with an angle to the crack it is possible to lengthen the crack propagation path, delay the destruction of the solder layer 7, and consequently delay the destruction of the semiconductor element 4.
  • the semiconductor element 4 when the semiconductor element 4 is square, it is most effective to set the longitudinal direction of the wire bump 9 perpendicular to the diagonal line of the semiconductor element mounting region 10 as described above.
  • the longitudinal direction of the wire bump 9 when the semiconductor element 4 is not square, the longitudinal direction of the wire bump 9 has a certain angle with respect to the diagonal line of the semiconductor element mounting region 10, that is, has an angle greater than 0 ° and 90 ° or less.
  • Wire bumps 9 may be disposed.
  • a plurality of wire bumps 9 may be arranged on the entire semiconductor element mounting region 10 so that the longitudinal direction of the wire bumps 9 has a certain angle with respect to the diagonal line of the semiconductor element mounting region 10.
  • the distance between the centers of the adjacent wire bumps 9 is preferably about twice the diameter of the wire bumps 9.
  • the width of the bonding portion of the wire bump 9 is considered to be expanded by ultrasonic bonding to about twice the diameter of the wire bump 9.
  • the material of the solder layer 7 and the wire bump 9 capable of forming an alloy will be described.
  • voids (voids) in the solder layer 7 can be prevented from being generated and generated in the semiconductor element 4. Heat can be efficiently radiated from the base plate 1 through the solder layer 7.
  • the wire bump 9 is reduced in a reducing atmosphere, for example, in a hydrogen atmosphere or a formic acid atmosphere, and then the solder layer 7 is melted.
  • solder layer 7 Sn-based solder, for example, pure Sn solder, Sn-Ag-Cu-based solder, Sn-Cu-based solder, and solder containing Ni as a main component and added with Ni or Sb are used.
  • Cu or Cu alloy is used as the material of the wire bump 9 as a material capable of forming an alloy with an Sn-based solder material under normal soldering conditions.
  • An alloy formed at the interface between the solder layer 7 and the wire bump 9 is, for example, Cu 6 Sn 5 or Cu 3 Sn.
  • Table 1 shows the melting point, Young's modulus, tensile strength, linear expansion coefficient, and thermal conductivity of Sn, Cu, Sn-0.7Cu, Cu 6 Sn 5 , and Cu 3 Sn.
  • the melting points of Cu 6 Sn 5 and Cu 3 Sn are higher than the melting point 232 ° C. of Sn, which is the base material of the solder layer 7, and are 415 ° C. and 676 ° C., respectively.
  • Young's modulus is 53.0 GPa, 110 GPa, and 140 GPa for Sn, Cu 6 Sn 5 and Cu 3 Sn, respectively, and tensile strength is Sn, Cu 6 Sn 5 and Cu 3 Sn. , 28.0 MPa, 310 MPa, and 507 MPa, respectively.
  • the alloys Cu 6 Sn 5 and Cu 3 Sn formed at the interface between the solder layer 7 and the wire bump 9 have a melting point higher than that of Sn or Sn—0.7Cu solder as the base material of the solder layer 7, High heat resistance and high reliability alloy with high mechanical strength.
  • a Zn-based solder material may be combined as the material of the solder layer 7, and Al or Al alloy may be combined as the material of the wire bump 9.
  • Insulating member 3b of insulating substrate 3 is not only ceramics such as Al 2 O 3 , AlN, Si 3 N 4 , but also a binder material such as epoxy or liquid crystal polymer is kneaded with fillers such as silica, alumina, and BN. An organic insulating material may be used.
  • the material of the conductor layers 3a and 3c of the insulating substrate 3 is preferably Cu, but may be a material obtained by applying Ni plating to Cu. Alternatively, a material obtained by applying Ni plating to Al may be used.
  • a Cu plate or an AlSiC plate is used as the base plate 1.
  • a structure without the base plate 1, that is, a conductor on the back side of the insulating substrate 3 is used.
  • a structure in which the layer 3c is exposed may be used.
  • the semiconductor element 4 includes SiC-MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) based on SiC capable of high-temperature operation, SiC-SBD (Schottky Barrier-Diode), Si-IGBT (Insulated Gate) based on Si. Bipolar Transistor) and Si-FWD (Free Wheeling Diode) are used.
  • SiC-MOSFET Metal-Oxide-Semiconductor-Field-Effect-Transistor
  • SiC-SBD Schottky Barrier-Diode
  • Si-IGBT Insulated Gate
  • Si-FWD Free Wheeling Diode
  • the bonding wire 6 is an Al wire, for example, and is bonded to the surface of the semiconductor element 4 by wedge bonding.
  • the bonding wire 6 may be a Cu wire, for example.
  • a plate-like conductor may be used instead of the bonding wire 6, a plate-like conductor.
  • the bonding with the semiconductor element 4 is not wedge bonding, for example, Ni / Au plating is performed on the upper surface of the semiconductor element 4, and then the plate-like conductor is formed by solder or Ag sintered material. Join.
  • the sealing material 5 is, for example, silicon gel, as long as it has sufficient insulating properties in use, and may be an epoxy material in which a filler is kneaded.
  • FIG. FIG. 5 is an enlarged sectional view of a part of the power semiconductor device 200 according to the second embodiment of the present invention.
  • the same reference numerals as those in FIG. 1 denote the same or corresponding parts.
  • a wire bump 29 capable of forming an alloy with the material of the solder layer 7 is provided between the base plate 1 and the conductor layer 3 c of the insulating substrate 3.
  • the wire bump 29 is basically the same as the arrangement of the first embodiment.
  • the wire bump 29 is mounted directly below the conductor layer 3 c of the insulating substrate 3, that is, a rectangular conductor layer mounted by vertically projecting the conductor layer 3 c on the base plate 1.
  • the wire bumps 29 may be formed in this way, the thickness of the solder layer 7 can be made uniform.
  • a plurality of wire bumps 29 may be provided as shown in FIG. 4B, for example.
  • the wire bumps 29 are formed at the four corners of the conductor layer mounting region or in the vicinity of the four corners at an angle greater than 0 ° and 90 ° or less with respect to the diagonal line of the conductor layer mounting region It may be provided at 90 °. Thereby, even when cracks propagate from the vicinity of the four corners to the solder layer 7 due to the difference in linear expansion coefficient between the base plate 1 and the insulating substrate 3, the progress of the cracks can be stopped by the wire bumps 29.
  • the wire bump 29 from a material capable of forming an alloy with the solder layer 7, it is possible to prevent the generation of voids (voids) in the solder layer 7, and the heat generated in the semiconductor element 4 is transferred to the solder layer 7. Can efficiently dissipate heat from the base plate 1.
  • the diameter of the wire bump 9 is preferably about 200 ⁇ m. However, if the thickness of the solder layer 7 between the insulating substrate 3 and the base plate 1 is set to 300 ⁇ m or more, the junction life structure can be improved. The diameter of the wire bump 9 may be about 300 ⁇ m. If the solder layer 7 is thinned to about 100 ⁇ m in order to efficiently dissipate heat from the semiconductor element 4 from the base plate 1, the diameter of the wire bump 9 may be about 100 ⁇ m.
  • FIG. 6A is a top view of the base plate 1 before the insulating substrate 3 is soldered.
  • FIG. 6B is a cross-sectional view of FIG. 6A when viewed in the AA direction.
  • a plurality of wire bumps 39 are provided in the solder layer forming region 20 on the base plate 1.
  • the wire bumps 39 are provided at a predetermined angle with the diagonal line of the solder layer forming region 20.
  • the wire bumps 39 arranged on one diagonal line are preferably parallel to each other and arranged at equal intervals.
  • the solder layer forming region 20 is surrounded by the photoresist 11 in order to prevent the solder from spreading outside the solder layer forming region 20 during soldering.
  • wire bumps are placed so as to surround the four sides, but this is placed so as to surround the four sides using a stitch bond with one wire. Since the solder spreads out in the area where the wire is not placed, each wire must be kept from contacting at the end.
  • the film thickness of the solder layer 7 is made uniform, and the material of the wire bumps 39 is formed of a material that can be alloyed with the material of the solder layer 7. Generation of voids (voids) can be prevented.
  • the wire bumps 39 are arranged as shown in FIG. 6A, even if cracks are formed at the four corners of the solder layer 7 due to the difference in linear expansion coefficient between the base plate 1 and the insulating substrate 3, the cracks are caused by the wire bumps 39. You can stop progress. In particular, by providing a plurality of wire bumps 39, the crack propagation path becomes longer and the life of the solder layer 7 is improved.
  • Cu has a thermal conductivity of 401 W / m ⁇ K, which is larger than that of Sn and Sn—Cu alloys having a thermal conductivity of 66.8 W / m ⁇ K. For this reason, the apparent thermal conductivity of the joint portion composed of the solder layer 7 and the wire bump 39 is increased, and the heat dissipation can be improved as compared with the case of only the solder layer 7 without the wire bump 39.
  • the wire bumps 39 as shown in FIGS. 6A and 6B, the regions where the solder contracts are delimited by the wire bumps 39, the occurrence of shrinkage cavities can be suppressed, and solder defects can be reduced.
  • the wire bumps 39 shown in FIG. 6A may be formed by bonding, for example, wire bumps 39 made of Cu wire having a diameter of 200 ⁇ m at intervals of 400 ⁇ m. This is because if the interval between the wire bumps 39 is narrowed, the wedge tool comes into contact with the adjacent wire bumps 39 at the time of bonding, and a desired joint cannot be obtained. For this reason, the interval between adjacent wire bumps 39 is preferably 1.5 times or more the diameter of the wire bumps 39.
  • both ends of one wire bump 39 are wedge-bonded to the base plate 1 and there are a plurality of stitch bond joints between them, a wire loop is formed by the tension of the wire, and the bump height is increased. It becomes difficult to control. For this reason, in order not to form a wire loop, it is preferable that the distance between the wedge bond joint and the stitch bond joint and the distance between adjacent stitch bond joints are each less than 2.0 mm.
  • the power semiconductor device 200 provided with the wire bumps in the solder layer 7 has been described.
  • one power semiconductor device may include both wire bumps.
  • solder layer 7 between the base plate 1 and the insulating substrate 3 described in the first embodiment and the solder layer 7 between the insulating substrate 3 and the semiconductor element 4 described in the second embodiment are: The same material or different materials may be used.

Abstract

La présente invention concerne un dispositif semi-conducteur de puissance comprenant un substrat isolant qui comporte une couche conductrice au moins dans la surface avant, une bosse de fil qui est disposée sur la couche conductrice, un élément semi-conducteur qui est disposé sur la bosse de fil, et une couche de soudure qui lie l'élément semi-conducteur sur la couche conductrice, et/ou comprenant une plaque de base, une pluralité de bosses de fil qui sont disposées sur la plaque de base, un substrat isolant qui est disposé sur les bosses de fil et qui comporte une couche conductrice au moins dans la surface arrière, et une couche de soudure qui lie la couche conductrice du substrat isolant sur la plaque de base. Le dispositif semi-conducteur de puissance comporte un alliage au niveau de l'interface entre chaque bosse de fil et la couche de soudure, ledit alliage étant composé des matériaux de la bosse de fil et des matériaux de la couche de soudure.
PCT/JP2017/021649 2016-06-14 2017-06-12 Dispositif semi-conducteur de puissance WO2017217369A1 (fr)

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CN201780035418.8A CN109314063B (zh) 2016-06-14 2017-06-12 电力用半导体装置
CN202210947454.4A CN115274465A (zh) 2016-06-14 2017-06-12 电力用半导体装置
JP2018523895A JP6487122B2 (ja) 2016-06-14 2017-06-12 電力用半導体装置

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US11677062B2 (en) 2018-12-25 2023-06-13 Nichia Corporation Method of manufacturing light source device having a bonding layer with bumps and a bonding member
CN113711349A (zh) * 2019-04-25 2021-11-26 京瓷株式会社 发光元件搭载用基板以及发光装置
WO2022209609A1 (fr) * 2021-03-31 2022-10-06 住友電気工業株式会社 Dispositif à semi-conducteur
WO2023195164A1 (fr) * 2022-04-08 2023-10-12 三菱電機株式会社 Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur

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JP2019110317A (ja) 2019-07-04
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CN115274465A (zh) 2022-11-01
JP6487122B2 (ja) 2019-03-20
CN109314063B (zh) 2022-08-16
CN109314063A (zh) 2019-02-05
JP6983187B2 (ja) 2021-12-17

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