JPWO2019116910A1 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JPWO2019116910A1 JPWO2019116910A1 JP2019559538A JP2019559538A JPWO2019116910A1 JP WO2019116910 A1 JPWO2019116910 A1 JP WO2019116910A1 JP 2019559538 A JP2019559538 A JP 2019559538A JP 2019559538 A JP2019559538 A JP 2019559538A JP WO2019116910 A1 JPWO2019116910 A1 JP WO2019116910A1
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- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K1/00—Soldering, e.g. brazing, or unsoldering
- B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
- B23K1/0016—Brazing of electronic components
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Abstract
Description
実施の形態1による半導体装置の構成について、図を参照しながら以下に説明する。なお、各図において、同一または同様の構成部分については同じ符号を付している。各図間の図示では、対応する各構成部のサイズおよび縮尺はそれぞれ独立しており、例えば構成の一部を変更した断面図の間で変更されていない同一構成部分の図示において、同一構成部分のサイズおよび縮尺が異なっている場合もある。また、半導体装置の構成は、実際にはさらに複数の部材を備えているが、説明を簡単にするため、説明に必要な部分のみを記載し、他の部分については省略している(例えば外部端子等)。さらに実際の構成は、同一の部材を並列で接続する場合、またはスイッチング素子とダイオードなどの整流素子を直列接続する場合があるが、これらも簡単のため省略している。
図16は、半導体装置101の製造工程を説明するための断面図である。
実施の形態1では、チップ下はんだ4およびチップ上はんだ6に、Agを0.3wt%以上、3wt%以下含み、Cuを0.5wt%以上、1wt%以下含み、Snを主成分とするはんだを用いて製造した場合を示したが、実施の形態2においては、Cuのみ0.5wt%以上、1wt%以下含み、Snを主成分とするはんだを用いて製造した場合について説明する。
実施の形態2では、チップ下はんだ4およびチップ上はんだ6に、Agを0.3wt%以上、2wt%以下含み、Snを主成分とするはんだを用いる場合に、絶縁基板1の電極パターン1cの上に、そのまま半導体素子を搭載した場合を示したが、実施の形態3においては、電極パターン1c上の半導体素子3a配置する以外の領域にレジストを設けた場合について説明する。
また、絶縁部材と冷却用フィンとが一体となった基板と、板状配線部材と、裏面側は前記基板の絶縁部材の配線パターン側に第一のはんだを介して接合され、表面側は前記板状配線部材に対応するように第二のはんだを介して接合された半導体素子とを備え、前記第一のはんだは、Agを0.3wt%以上、3wt%以下含み、Cuを0.5wt%以上、1wt%以下含み、Snを主成分とし、前記基板は、前記絶縁部材の配線パターン側に設けられ、前記半導体素子の裏面側と前記第一のはんだを介して接合された金属膜を備え、前記半導体素子は、裏面側に前記絶縁部材側と前記第一のはんだを介して接合された金属膜を備え、前記半導体素子の裏面側に設けられた金属膜と前記基板の前記配線パターン側に設けられた金属膜の少なくともいずれか一方が、Ag製またはCu製であることを特徴とする。
Claims (21)
- 絶縁部材と冷却用フィンとが一体となった基板と、
板状配線部材と、
裏面側は前記基板の絶縁部材の配線パターン側に第一のはんだを介して接合され、表面側は前記板状配線部材に対応するように第二のはんだを介して接合された半導体素子とを備え、
前記第一のはんだは、Agを0.3wt%以上、3wt%以下含み、Cuを0.5wt%以上、1wt%以下含み、Snを主成分とすることを特徴とする半導体装置。 - 前記第二のはんだは、Agを0.3wt%以上、3wt%以下含み、Cuを0.5wt%以上、1wt%以下含み、Snを主成分とすることを特徴とする請求項1に記載の半導体装置。
- 前記基板は、前記絶縁部材の配線パターン側に設けられ、前記半導体素子の裏面側と前記第一のはんだを介して接合された金属膜を備え、前記半導体素子は、裏面側に前記絶縁部材側と前記第一のはんだを介して接合された金属膜を備え、前記半導体素子の裏面側に設けられた金属膜と前記基板の前記配線パターン側に設けられた金属膜の少なくともいずれか一方が、Ag製またはCu製であることを特徴とする請求項1または請求項2に記載の半導体装置。
- 前記半導体素子の表面側には、前記板状配線部材と前記第二のはんだを介して接合された金属膜を備え、前記半導体素子の表面側に設けられた金属膜がAg製またはCu製であることを特徴とする請求項2または請求項3に記載の半導体装置。
- 前記半導体素子の裏面側にAl製の金属膜が設けられた場合、前記第一のはんだは、Agを0.3wt%以上、2wt%以下含み、Cuを0.5wt%以上、1wt%以下含み、Snを主成分とすることを特徴とする請求項1または請求項2に記載の半導体装置。
- 前記半導体素子の表面側にAl製の金属膜が設けられた場合、前記第二のはんだは、Agを0.3wt%以上、2wt%以下含み、Cuを0.5wt%以上、1wt%以下含み、Snを主成分とすることを特徴とする請求項5に記載の半導体装置。
- 前記基板と前記半導体素子は、スペーサを挟んで接合することを特徴とする請求項1から請求項6のいずれか1項に記載の半導体装置。
- 複数の前記半導体素子と、複数の前記半導体素子に対応する板状配線部材が各々複数あり、前記複数の配線部材である第一板状配線部材と第二板状配線部材とが樹脂からなる接続部材により接続されていることを特徴とする請求項1から請求項7のいずれか一項に記載の半導体装置。
- 前記基板は、前記絶縁部材と前記冷却用フィンとが鋳造により一体化されていることを特徴とする請求項1から請求項8のいずれか一項に記載の半導体装置。
- 前記基板は、前記絶縁部材と前記冷却用フィンとがろう付けにより一体化されていることを特徴とする請求項1から請求項9のいずれか一項に記載の半導体装置。
- 前記半導体素子は、ワイドバンドギャップ半導体材料で形成され、前記ワイドバンドギャップ半導体材料は、炭化ケイ素、窒化ガリウム系材料、およびダイヤモンドのうちのいずれかであることを特徴とする請求項1から請求項10のいずれか1項に記載の半導体装置。
- 半導体素子の裏面側と、絶縁部材と冷却用フィンとが一体となった基板の前記絶縁部材の配線パターン側とを、第一のはんだを介して第一のリフローにより接合する工程と、
前記半導体素子の表面側と、板状配線部材とを、前記半導体素子に前記板状配線部材が対応するように、第二のはんだを介して第二のリフローにより接合する工程とを含み、
前記第一のはんだは、Agを0.3wt%以上、3wt%以下含み、Cuを0.5wt%以上、1wt%以下含み、Snを主成分とすることを特徴とする半導体装置の製造方法。 - 前記第二のはんだは、Agを0.3wt%以上、3wt%以下含み、Cuを0.5wt%以上、1wt%以下含み、Snを主成分とすることを特徴とする請求項12に記載の半導体装置の製造方法。
- 前記半導体素子の裏面側にAl製の金属膜が設けられた場合、前記第一のはんだは、Agを0.3wt%以上、2wt%以下含み、Cuを0.5wt%以上、1wt%以下含み、Snを主成分とすることを特徴とする請求項12または請求項13に記載の半導体装置の製造方法。
- 前記半導体素子の表面側にAl製の金属膜が設けられた場合、前記第二のはんだは、Agを0.3wt%以上、2wt%以下含み、Cuを0.5wt%以上、1wt%以下含み、Snを主成分とすることを特徴とする請求項14に記載の半導体装置の製造方法。
- 半導体素子の裏面側に形成された金属膜と、絶縁部材と冷却用フィンとが一体となった基板の前記絶縁部材の配線パターン側に設けられた金属膜とを、第一のはんだを介して第一のリフローにより接合する工程と、
前記半導体素子の表面側に形成された金属膜と、板状配線部材とを、前記半導体素子に前記板状配線部材が対応するように、第二のはんだを介して第二のリフローにより接合する工程を含み、
前記第一のはんだを介して接合する工程では、前記第一のはんだとして、Cuを0.5wt%以上、1wt%以下含み、Snを主成分とするはんだを用い、前記半導体素子の裏面側に形成された金属膜と前記基板の絶縁部材の配線パターン側に設けられた電極パターン表面側の金属膜の少なくともいずれか一方をAg製にすることで、第一のリフローにより、前記第一のはんだを、Agを0.3wt%以上、3wt%以下含み、Cuを0.5wt%以上、1wt%以下含み、Snを主成分とするはんだにすることを特徴とする半導体装置の製造方法。 - 半導体素子の裏面側に形成された金属膜と、絶縁部材と冷却用フィンとが一体となった基板の絶縁部材の配線パターン側に設けられた電極パターン表面側の金属膜とを、第一のはんだを介して第一のリフローにより接合する工程と、
前記半導体素子の表面側に形成された金属膜と、板状配線部材とを、前記半導体素子に前記板状配線部材が対応するように、第二のはんだを介して第二のリフローにより接合する工程を含み、
前記第一のはんだを介して接合する工程では、前記第一のはんだとして、Agを0.3wt%以上、3wt%以下含み、Snを主成分とするはんだを用い、前記半導体素子の裏面側に形成された金属膜と前記基板の絶縁部材の配線パターン側に設けられた電極パターン表面側の金属膜の少なくともいずれか一方をCu製にすることで、第一のリフローにより、前記第一のはんだを、Agを0.3wt%以上、3wt%以下含み、Cuを0.5wt%以上、1wt%以下含み、Snを主成分とするはんだにすることを特徴とする半導体装置の製造方法。 - 複数の前記半導体素子と、複数の前記半導体素子に対応する板状配線部材が各々複数あり、前記複数の配線部材である第一板状配線部材と第二板状配線部材とが樹脂からなる接続部材により接続されていることを特徴とする請求項12から請求項17のいずれか一項に記載の半導体装置の製造方法。
- 前記第一のはんだを介して接合する工程および前記第二のはんだを介して接合する工程は、同時に行われることを特徴とする請求項12から請求項18のいずれか一項に記載の半導体装置の製造方法。
- 前記第一のはんだを介して接合する工程は、前記基板にケースを接着する工程と同時に行われることを特徴とする請求項12から請求項19のいずれか一項に記載の半導体装置の製造方法。
- 前記第二のはんだを介して接合する工程は、前記第二のリフローにより接合する代わりに、レーザーを用いたスポット加熱により接合することを特徴とする請求項12から請求項20のいずれか一項に記載の半導体装置の製造方法。
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