WO2017211105A1 - Dispositif à super-jonction, puce et procédé de fabrication s'y rapportant - Google Patents

Dispositif à super-jonction, puce et procédé de fabrication s'y rapportant Download PDF

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WO2017211105A1
WO2017211105A1 PCT/CN2017/076899 CN2017076899W WO2017211105A1 WO 2017211105 A1 WO2017211105 A1 WO 2017211105A1 CN 2017076899 W CN2017076899 W CN 2017076899W WO 2017211105 A1 WO2017211105 A1 WO 2017211105A1
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region
type
conductivity type
epitaxial layer
jfet
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曾大杰
肖胜安
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深圳尚阳通科技有限公司
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions

Definitions

  • the invention belongs to the field of semiconductors, and in particular relates to a super junction device, a chip and a manufacturing method thereof.
  • the appearance of super junction devices breaks the "silicon limit" problem between on-resistance and withstand voltage, which solves the problem of high-voltage device application.
  • the structure of the superjunction device is composed of alternately arranged N-type columns and P-type columns.
  • a super-junction structure is used to replace the N-type drift region in a Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) device, a conduction path is provided through the N-type pillar in an on state, and when conducting The P-type column does not provide a conduction path; in the off state, the PN column is subjected to a reverse bias voltage to form a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the super-junction MOSFET can significantly reduce the on-resistance of the device by using a low-resistivity epitaxial layer in the case where the reverse breakdown voltage is identical to that of a conventional VDMOS device.
  • Figure 1 shows the structure of a common super junction power device, taking an N-type super junction as an example, in which the gate 1 is usually composed of polysilicon and its thickness is between.
  • the gate oxide layer 2 is used to achieve isolation between the gate and the communication.
  • the thickness of the gate determines the withstand voltage of the gate.
  • Source 3 is formed by N-type heavily doped (N+) with a doping dose at the above.
  • the doping amount of the P-Body 5 is Between, its doping amount determines the threshold voltage of the device.
  • the higher the doping dose, the higher the threshold voltage of the device, and the surface of the P-type body region 5 covered by the gate 1 is used to form a channel, also called a trench. Road area.
  • the hole collecting region 4 is composed of a P-type heavily doped region (P+) formed on the surface of the P-type body region 5.
  • the doped body concentration of the N-type epitaxial layer 7 is Between the N-type epitaxial layer 7 serves as a drift region of the device, the thickness of which determines the breakdown voltage of the device.
  • the N-type columns composed of the P-type pillar 6 and the N-type epitaxial layer 7 are alternately arranged to form a super-junction structure.
  • each P-type pillar 6 and the corresponding N-type pillar are complementarily doped and realize the lateral consumption of the N-type pillar.
  • the N-type drift region depletion in the entire super-junction structure can be easily achieved, thereby achieving high doping concentration and high simultaneously. Breakdown voltage.
  • the P-type column 6 is usually implemented in two ways, one is formed by multiple epitaxy, and the other is formed by trenching and P-type silicon filling.
  • An N-type epitaxial layer 7 is formed on the semiconductor substrate 9, and the semiconductor substrate 9 is N-type highly doped, and its bulk concentration is Above, its high doping concentration is to reduce the electrical resistance of the semiconductor substrate 9.
  • the super junction power device is a MOSFET device
  • a drain region is formed of an N-type highly doped semiconductor substrate 9, and a drain composed of a back metal layer is formed on the back surface of the semiconductor substrate 9.
  • an N-type buffer layer 8 is usually formed at the bottom of the N-type epitaxial layer 7;
  • the type buffer layer 8 can be kept in conformity with the doping concentration of the N-type epitaxial layer 7, in which case both are composed of the same epitaxial layer, and the bottom of the P-type pillar 6 and the semiconductor layer 9 are separated by the N-type buffer layer 8.
  • the N-type buffer layer 8 After buffering by the N-type buffer layer 8, it is possible to prevent the doping impurities in the semiconductor substrate 9 from diffusing into the N-type pillar of the super-junction structure, that is, the N-type epitaxial layer 7, in the thermal process of the process, so that the drift region is not caused.
  • the doping concentration is increased and the breakdown voltage of the device is not lowered.
  • the JFET implant region 10 is formed on the top surface of the N-type pillar and between the adjacent two P-type body regions 5, and the JFET implant region 10 serves to lower the on-resistance of the device.
  • curve 101 is the electric field intensity distribution curve of the conventional super junction device shown in FIG. 1 along the corresponding AA' position, and the X axis in FIG. 3 represents the longitudinal depth along the AA' position in FIG. , 0 micron represents the interface between silicon and silicon dioxide, the unit is micron; Y The axis represents the electric field strength in V/cm. It can be seen that the peak of the maximum electric field is in the body, so that the EAS capability of the device is better.
  • this structure has a problem: in the direction along AA', the electric field strength increases from 0 to a relatively slow speed, so that the voltage subjected to a long distance is relatively low, that is, the area in the position corresponding to the broken line frame 103.
  • the electric field strength rises slowly with depth.
  • the positional area corresponding to the dashed box 103 is the top region of the superjunction structure. Since the electric field intensity is small, this also makes the area covered by the electric field intensity in the curve 101 small, and the breakdown voltage of the device is small.
  • An object of the embodiments of the present invention is to provide a super junction device, which aims to solve the problem of low breakdown voltage of the existing surge resistant super junction device.
  • Embodiments of the present invention are achieved by a superjunction device including a polysilicon gate, a gate oxide layer, a source region, a hole collection region, a first conductivity type body region, a first conductivity type pillar, and a second conductivity type epitaxial layer
  • the N-type buffer layer, the semiconductor substrate, the JFET implanted region, the plurality of first conductive type pillars and the second conductive type epitaxial layer are alternately arranged to form a super junction structure, and the super junction device further comprises:
  • the second conductivity type region is formed at a bottom of the JFET implantation region, and the second conductivity type region and the first conductivity type body region are at the second conductivity type epitaxial layer and Forming a top charge balance region on top of the first conductivity type pillar to increase electric field strength at the top of the super junction structure within a depth range of the first conductivity type body region and reduce on-resistance of the device
  • Another object of embodiments of the present invention is to provide a superjunction chip including the above super junction device.
  • Another object of the present invention is to provide a method for fabricating a superjunction device, including fabricating a polysilicon gate, a gate oxide layer, a source region, a hole collection region, a first conductivity type body region, a first conductivity type pillar, a second conductive type epitaxial layer, an N-type buffer layer, a semiconductor substrate, a JFET implanted region, a plurality of first conductive type pillars and a second conductive type epitaxial layer alternately arranged in a superjunction structure, characterized in that The method further includes, after the step of fabricating the JFET implant region:
  • the second conductive type region and the first conductive type body region form a top charge balance region on top of the second conductive type epitaxial layer and the first conductive type pillar to enhance the first conductive type
  • the electric field strength at the top of the superjunction structure within the depth of the body region reduces the on-resistance of the device.
  • a second conductivity type region is added at the bottom of the JFET implantation region to form a top charge balance region, thereby improving the breakdown voltage of the device, reducing the specific on-resistance, reducing the maximum reverse recovery current, and increasing the gate leakage capacitance. Reduce switching speed and improve EMI performance.
  • FIG. 1 is a cross-sectional structural view of a conventional super junction power device
  • FIG. 2 is a cross-sectional structural view of a super junction device according to an embodiment of the present invention.
  • FIG. 3 is a comparison diagram of electric field intensity distribution curves of the super junction device and the existing super junction device along the AA' position according to an embodiment of the present invention
  • FIG. 4 is a comparison diagram of doping concentration distribution curves of a super junction device and an existing super junction device along a BB' position according to an embodiment of the present invention
  • FIG. 5 is a comparison diagram of a reverse recovery simulation curve of a super junction device and an existing super junction device according to an embodiment of the present invention
  • FIG. 6 is a comparison diagram of a gate leakage capacitance simulation curve of a super junction device and an existing super junction device according to an embodiment of the present invention.
  • Embodiments of the present invention form a top by adding a second conductivity type region at the bottom of the JFET implant region
  • the charge balance region improves the breakdown voltage of the device, reduces the specific on-resistance, reduces the maximum reverse recovery current, increases the gate-drain capacitance, reduces the switching speed, and improves EMI performance.
  • the super junction device includes a polysilicon gate, a gate oxide layer, a source region, a hole collection region, a first conductivity type body region, a first conductivity type pillar, a second conductivity type epitaxial layer, and an N-type a buffer layer, a semiconductor substrate, a JFET implant region, a plurality of first conductive type pillars and a second conductive type epitaxial layer alternately arranged in a super junction structure, in particular, the super junction device further comprises:
  • the second conductivity type region is formed at a bottom of the JFET implantation region, and the second conductivity type region and the first conductivity type body region form a top charge balance on the top of the second conductivity type epitaxial layer and the first conductivity type pillar
  • the region increases the electric field strength at the top of the superjunction structure in the depth range of the first conductivity type body region and reduces the on-resistance of the device.
  • N-type super junction As an example. It can be understood that the present invention is equally applicable to a P-type super junction, and only needs to change the conductivity type and the doping type.
  • FIG. 2 shows a cross-sectional structure of a super junction device according to an embodiment of the present invention, and for convenience of explanation, only parts related to the present invention are shown.
  • the N-type super junction device comprises: a polysilicon gate 1, a gate oxide layer 2, a source region 3, a hole collection region 4, a P-type body region 5, a P-type column (corresponding to a first conductivity type column) 6, and an N-type An epitaxial layer (corresponding to a second conductivity type epitaxial layer) 7, an N-type buffer layer (corresponding to a second conductivity type buffer layer) 8, a semiconductor substrate 9, and a JFET implantation region 10.
  • the N-type epitaxial layer 7 may also be alternately arranged as an N-type pillar and P-type pillars 6 on both sides to form a super-junction structure, and an adjacent pair of P-type pillars 6 and N-type pillars 7 constitute a super-junction unit.
  • a superjunction device unit is formed in each super junction cell region.
  • An N-type epitaxial layer is formed on the semiconductor substrate 9, and the semiconductor substrate 9 is doped with N-type high to reduce the resistance of the semiconductor substrate 9, and the bulk concentration thereof the above.
  • an N-type buffer layer 8 is formed at the bottom of the super junction structure.
  • the N-type buffer layer 8 and the N-type pillar 7 are both composed of the N-type epitaxial layer. That is, the P-type pillar 6 does not pass through the N-type epitaxial layer 7, and the N-type buffer layer 8 is composed of an N-type epitaxial layer 7 located at the bottom of the P-type pillar 6.
  • the doping body concentration of the N-type epitaxial layer is usually Between the drift region of the N-type epitaxial layer 7 as a device, the thickness of the N-type epitaxial layer determines the breakdown voltage of the device.
  • P-type body regions 5 are formed on top of each of the P-type columns 6, and each of the P-type body regions 5 also extends laterally to the top of the adjacent N-type columns 7.
  • the doping amount of the P-type body region 5 is usually Between, the doping of the P-type body region 5 determines the threshold voltage of the device, and the higher the doping amount, the higher the threshold voltage of the device.
  • a gate dielectric layer such as a gate oxide layer 2 and a polysilicon gate 1 are sequentially formed on the surface of each of the P-type body regions 5, and a surface of the P-type body region 5 covered by the polysilicon gate 1 is used to form a channel.
  • the polysilicon gates 1 of two adjacent super junction device cells are a one-piece, unitary structure.
  • the N-type super junction device is further formed with a second N-type region (corresponding to the second conductivity type region) 11 at the bottom of the JFET implantation region 10, and the implantation region of the second N-type region 11 is light of the JFET implantation region 10.
  • the hood is defined such that the implantation energy of the second N-type region 11 is greater than the implantation energy of the JFET implantation region 10, and the same reticle can save process cost.
  • the implantation region of the second N-type region 11 can also be separately defined by a different mask than the mask of the JFET implantation region 10. At this time, the implantation region of the second N-type region 11 can be set larger than the JFET implantation region. 10. It can also be set smaller than the JFET injection region 10 to facilitate size adjustment of the second N-type region 11.
  • the second N-type region 11 and the P-type body region 5 form a top charge balance region on top of the N-type pillar 7 and the P-type pillar 6 to enhance the top of the super-junction structure located within the depth range of the P-type body region 5.
  • the electric field strength reduces the on-resistance of the device.
  • the difference between the total amount of the N-type impurities and the total amount of the P-type impurities in the top charge balance region is less than 20% of the total amount of the N-type impurities, and the total amount of the N-type impurities in the top charge balance region.
  • the difference in the total amount of P-type impurities is less than 20% of the total amount of P-type impurities.
  • the increase or decrease of 20% described above may be made according to the level of the balance of the N-type and P-type impurities.
  • the longitudinal depth of the second N-type region 11 should satisfy that the portion of the P-type body region 5 extending into the N-type pillar 7 and the N-type epitaxial layer at the bottom thereof constitute a PN graded junction, and the concentration peak of the second N-type region 11 Location and The PN graded junction is flush or within the depth range of plus or minus 1 micron of the PN graded junction.
  • the lateral width of the second N-type region 11 should satisfy that the lateral width of the second N-type region 11 is less than or equal to the width of the N-type pillar 7.
  • the lateral width of the second N-type region 11 is larger than the width of the N-type pillar 7, and the second N-type region 11 and the P-type body region 5 are overlapped in the lateral direction, both sides of the P-shaped body region 5 and adjacent After the second N-type regions 11 overlap, it should be ensured that the width of the non-overlapping regions of the P-type body regions 5 is greater than 1 micrometer.
  • the implantation energy of the JFET implantation region 10 is 60 eV
  • the implantation energy of the second N-type region 11 is 500 keV or more
  • the number of injections of the second N-type region 11 is one or more.
  • the implantation energy of the JFET implantation region 10 is 60 eV, the implantation dose is 2e12 cm -2 ; the implantation energy of the second N-type region 11 is 1000 keV to 1800 keV, and the implantation dose is 1e12 cm -2 to 2e12 cm -2 .
  • the injection energy of the second N-type region 11 is 1000 keV
  • the implantation dose is 1e12 cm ⁇ 2
  • the implantation energy of the second N-type region 11 is 1000 keV
  • the implantation dose is 2e12 cm ⁇ 2
  • the second N-type region 11 is The implantation energy was 1800 keV
  • the implantation dose was 1e12 cm -2
  • the implantation energy of the second N-type region 11 was 1800 keV
  • the implantation dose was 2e12 cm -2 .
  • the hole collection region 4 For the source region 3, the hole collection region 4, the interlayer film, the contact hole and the front metal layer;
  • the source region 3 is composed of an N-type heavily doped region formed on the surface of the P-type body region 5, and one side of the source region 3 and the edge of the adjacent polysilicon gate 1 are self-aligned.
  • the doping amount of the source region 3, that is, the implantation dose of the ion implantation doping is usually the above.
  • the hole collecting region 4 is composed of a P-type heavily doped region formed on the surface of the P-type body region 5.
  • the contact hole passes through the interlayer film, the front metal layer is patterned to form a source and a gate, the source is connected to the source region 3 and the hole collection region through the contact hole and the bottom, and the gate is connected to the polysilicon gate 1 at the bottom through the contact hole.
  • field oxide can also be formed in the surface of the N-type epitaxial layer for isolation between different superjunction devices.
  • a method for fabricating a superjunction device includes: fabricating a polysilicon gate, a gate oxide layer, a source region, a hole collection region, a first conductivity type body region, a first conductivity type column, and a second Conductive type epitaxial layer, N-type buffer layer, semiconductor substrate, JFET implantation region, multiple first conductive classes
  • the super-junction structure is composed of a column and a second conductivity type epitaxial layer alternately arranged, and the method further comprises: after the step of fabricating the JFET implantation region:
  • the second conductivity type region and the first conductivity type body region form a top charge balance region on the top of the second conductivity type epitaxial layer and the first conductivity type pillar to enhance the super junction structure in the depth range of the first conductivity type body region
  • the electric field strength at the top reduces the on-resistance of the device.
  • N-type super junction As an example. It can be understood that the present invention is equally applicable to a P-type super junction, and only needs to change the conductivity type and the doping type.
  • a method of fabricating a superjunction device includes the following steps:
  • Step S101 forming an N-type epitaxial layer
  • an N-type epitaxial layer is formed on a semiconductor substrate 9, and the semiconductor substrate 9 is made of N-type high doping to reduce the resistance of the semiconductor substrate 9, and the bulk concentration thereof. the above.
  • step S102 JFET implantation is performed on the surface of the N-type epitaxial layer 7 defined in the selected region by using a photomask to form the JFET implantation region 10.
  • the N-type implant having the same implant energy than the implant energy of the JFET implant region 10 is formed with the second N-type region 11 at the bottom of the JFET implant region 10.
  • the same mask can save process cost.
  • the implanted region of the second N-type region 11 can also be separately defined by a mask different from the mask of the JFET implant region 10, such that the implanted region of the second N-type region 11 can be set larger than
  • the JFET implant region 10 can also be disposed smaller than the JFET implant region 10 to facilitate size adjustment of the second N-type region 11.
  • the implantation energy of the JFET implantation region 10 is 60 eV
  • the implantation energy of the second N-type region 11 is 500 keV or more
  • the number of injections of the second N-type region 11 is one or more. More preferably, the implantation energy of the JFET implantation region 10 is 60 eV, and the implantation dose is 2e12 cm -2 .
  • the implantation energy of the second N-type region 11 is 1000 keV to 1800 keV, and the implantation dose is 1e12 cm -2 to 2e12 cm -2 ; for example, the injection energy of the second N-type region 11 is 1000 keV, and the implantation dose is 1e12 cm -2 ;
  • the implantation energy of the two N-type regions 11 is 1000 keV, the implantation dose is 2e12 cm -2 ;
  • the implantation energy of the second N-type region 11 is 1800 keV, the implantation dose is 1e12 cm -2 ;
  • the implantation energy of the second N-type region 11 is 1800 keV, injection The dose is 2e12 cm -2 .
  • the parameters of these specific embodiments are only for the purpose of illustrating the present invention more clearly, and other variations are possible, and the settings may be made according to actual needs.
  • Step S104 forming a super junction structure composed of a plurality of P-type pillars 6 and N-type pillars 7 alternately arranged in the N-type epitaxial layer 7, and the N-type pillars 7 is composed of an N-type epitaxial layer between the P-type pillars 6;
  • Step 201 Form a plurality of trenches in the N-type epitaxial layer by using a photolithography etching process.
  • Step 202 filling the trench with P-type silicon to form each P-type pillar 6.
  • an N-type buffer layer 8 is formed at the bottom of the super junction structure. Both the N-type buffer layer 8 and the N-type pillar 7 are composed of an N-type epitaxial layer.
  • the N-type buffer layer 8 composed of an N-type epitaxial layer located at the bottom of the P-type pillar 6 is formed by disposing the bottom of the P-type pillar 6 so as not to pass through the N-type epitaxial layer.
  • the doping body concentration of the N-type epitaxial layer is usually Between the drift region of the N-type epitaxial layer as a device, the thickness of the N-type epitaxial layer determines the breakdown voltage of the device.
  • Step S105 performing P-type body region 5 injection to form a P-type body region 5 on the top of each P-type column 6;
  • the doping amount of the P-type body region 5 is usually Between, the doping of the P-type body region 5 determines the threshold voltage of the device, and the higher the doping amount, the higher the threshold voltage of the device.
  • Step S106 performing a push trap, and after pushing the well, each P-type body region 5 also extends laterally to the top of the adjacent N-type pillar 7;
  • the JFET implant region 10 is located on the surface of the N-type pillar 7 between each adjacent P-type body region 5, and the JFET implant region 10 serves to reduce the on-resistance of the super junction device.
  • the second N-type region 11 and the P-type body region 5 form a top charge balance region at the top of the N-type pillar 7 and the P-type pillar 6 to enhance the electric field strength at the top of the super-junction structure in the depth range of the P-type body region 5. And reduce the on-resistance of the device.
  • the difference between the total amount of the N-type impurity and the total amount of the P-type impurity in the top charge balance region is less than 20% of the total amount of the N-type impurity and the total amount of the N-type impurity and the P-type in the top charge balance region.
  • the difference in the total amount of impurities is less than 20% of the total amount of the P-type impurities.
  • the increase or decrease of 20% described above may be made according to the level of the balance of the N-type and P-type impurities.
  • the longitudinal depth of the second N-type region 11 satisfies: a portion of the P-type body region 5 extending into the N-type pillar 7 and an N-type epitaxial layer at the bottom thereof constitute a PN graded junction, and a concentration peak position of the second N-type region 11 It is flush with the PN graded junction or within the depth range of plus or minus 1 micron of the PN graded junction.
  • the lateral width of the second N-type region 11 is such that the lateral width of the second N-type region 11 is less than or equal to the width of the N-type pillar 7.
  • the lateral width of the second N-type region 11 is larger than the width of the N-type pillar 7, and the second N-type region 11 and the P-type body region 5 are overlapped in the lateral direction, both sides of the P-shaped body region 5 and adjacent After the second N-type regions 11 overlap, it is required to ensure that the width of the non-overlapping regions of the P-type body regions 5 is greater than 1 micrometer.
  • S101, S102, and S103 in the above steps may be performed before step S104, or may be performed after step S104 or after step S105.
  • step S106 the method further includes:
  • step S107 a gate dielectric layer such as a gate oxide layer 2 and a polysilicon gate 1 are sequentially formed on the surface of each of the P-type body regions 5, and a surface of the P-type body region 5 covered by the polysilicon gate 1 is used to form a channel.
  • a gate dielectric layer such as a gate oxide layer 2 and a polysilicon gate 1 are sequentially formed on the surface of each of the P-type body regions 5, and a surface of the P-type body region 5 covered by the polysilicon gate 1 is used to form a channel.
  • the thickness of the polysilicon gate 1 is usually between.
  • the gate oxide layer 2 is used to realize the isolation of the polysilicon gate 1 and the communication.
  • the thickness of the gate oxide layer 2 determines the withstand voltage of the polysilicon gate 1. Generally, in order to ensure the withstand voltage of the polysilicon gate 1, the thickness of the gate oxide layer 2 Generally greater than
  • the field oxygen formation process can be placed after step S106 and before the gate oxide layer 2 of step S107 is formed. Field oxygen is used to achieve isolation between different superjunction devices.
  • step S108 an N-type heavily doped implant is performed to form a source region 3 on the surface of the P-type body region 5.
  • One side of the source region 3 and the edge of the adjacent polysilicon gate 1 are self-aligned.
  • the other side of the source region 3 can be defined by photolithography.
  • the doping amount of the source region 3, that is, the implantation dose of the ion implantation doping is usually the above.
  • step S109 an interlayer film is formed on the front surface of the N-type epitaxial layer; the interlayer film covers the source region 3, the body region, and the polysilicon gate 1.
  • step S110 openings of the contact holes are respectively formed at the top of the source region 3 and the polysilicon gate 1, and the contact holes pass through the interlayer film.
  • step S111 P-type heavily doping is performed at the bottom of the contact hole corresponding to the source region 3 to form a hole collecting region 4, and the hole collecting region and the P-shaped body region 5 are in contact.
  • Step S112 forming a front metal layer, patterning the front metal layer by a photolithography etching process to form a source and a gate, the source is connected to the source region 3 and the hole collection region through the contact hole and the bottom, and the gate passes through the contact hole. Connected to the polysilicon gate 1 at the bottom.
  • the method further includes:
  • step S113 an N-type heavily doped drain region is formed on the back surface of the semiconductor substrate 9; the drain region can be formed by backside ion implantation or directly thinned by the semiconductor substrate 9. A back metal layer is then formed, and the drain is drawn from the back metal layer.
  • the embodiment of the present invention enables the electric field at the top of the super junction structure to be rapidly increased, thereby ensuring a better breakdown voltage of the device.
  • the JFET implant region 10 can reduce the on-resistance of the device while the breakdown voltage of the device is not lowered, and is widely used in planar super junction devices to improve device performance.
  • the JFET implant region 10 is usually implanted only on the surface of the silicon wafer, and the injected energy is usually 40 keV to 60 keV, which is only for reducing the on-resistance and does not increase the breakdown voltage of the device.
  • the Mask of the JFET implant region 10 when the ion implantation of the JFET implant region 10 is performed, the original low energy is maintained, and one or more high-energy ion implantation is added to form the second.
  • the N-type region 11 can not only better reduce the specific on-resistance of the device, but also increase the electric field faster, thereby increasing the breakdown voltage of the device.
  • Table 1 For the TCAD simulation results, please refer to Table 1 below:
  • JFET injection means that no JFET implantation is performed, so as to correspond to the structure without the JFET implantation region 10 in the prior art device;
  • 60keV 2.0e12 indicates an implantation energy of 60 keV and an implantation dose of 2.0e12 cm -2 .
  • JFET injection it can be seen that the implantation is low energy injection, the injection condition of "60keV2.0e12” indicates that the corresponding JFET implantation region 10 is formed; "+” indicates that the subsequent process is performed after the "60keV2.0e12" implantation process.
  • An implantation process for high energy implantation and for forming a second N-type region 11, such as: "1000keV1.0e12" in the fourth row means that the implantation energy is 1000 keV, the implantation dose is 1.0e12 cm -2 ; and the fifth row is "1000 keV2".0e12" indicates an injection energy of 1000 keV and an implantation dose of 2.0e12 cm -2 ; "1800keV1.0e12” in the sixth row indicates an implantation energy of 1800 keV and an implantation dose of 1.0e12 cm -2 ; "1800keV2.0e12" in the seventh row indicates The implantation energy was 1800 keV and the implantation dose was 2.0e12 cm -2 .
  • the last four rows correspond to the process conditions of the low energy and high energy implantation in the embodiment of the present invention. It is obvious that the embodiment of the present invention can greatly reduce the specific on-resistance and increase the breakdown voltage.
  • the “60keV2.0e12+1800keV2.0e12" is used in the seventh row, and the embodiment of the present invention can significantly reduce the specific on-resistance and reduce the 9% while simultaneously hitting.
  • the wearing voltage can be increased by more than 30V.
  • the seventh row is 16% lower than the on-resistance compared to the second row without JFET injection.
  • the reason for increasing the breakdown voltage after high-energy JFET injection increases the breakdown voltage by using a high-energy JFET implant to add a second N-type region 11 based on the JFET implant 10, and the second N-type region 11 can
  • the impurity phase of the P-type body region 5 is balanced, that is, the second N-type region 11 and the P-type body region 5 form a top charge balance region at the top of the N-type column 7 and the P-type column 6,
  • the top charge balance region can increase the lateral depletion of the top of the superjunction structure, thereby enabling the electric field at the top of the superjunction structure to rise rapidly.
  • the curve 101 is an electric field intensity distribution curve of the conventional super junction device shown in FIG. 1 along the corresponding AA' position, and the curve 101 corresponds to the existing super junction device using only the JFET implantation region 10.
  • the JFET injection condition is "60keV 2.0e12" in the third row of Table 1.
  • the curve 102 is the electric field intensity distribution curve of the super junction device of the embodiment of the present invention shown in FIG. 2 along the corresponding AA' position, in the curve 102.
  • the JFET implantation conditions of the JFET implant region 10 and the second N-type region 11 are "60keV2.0e12+1800keV2.0e12" in the seventh row of Table 1;
  • the X-axis in FIG. 3 represents the position along the AA' position in FIG. Longitudinal depth, 0 micron represents the interface of silicon and silicon dioxide, the unit is micron;
  • the Y-axis represents the electric field strength in V/cm.
  • the curve 101 and the curve 102 coincide, and the maximum electric field of the curve 102, that is, the electric field intensity peak is still in the body, so the EAS capability of the device after the second N-type region 11 is increased will not be damaged;
  • the electric field of the device in the position region corresponding to the top region of the super junction structure, that is, the dotted line frame 103, rapidly increases from 0 V/cm to 1.6 e5 V/cm, which is why the breakdown voltage can be increased.
  • the dose of the JFET implanted in the second N-type region 11 cannot be too large, and the dose of the JFET implanted in the second N-type region 11 is too large to affect the BV of the device, if it is increased to 3.0e12 cm -2 or even more. High, the breakdown voltage will not increase, but will decrease. Therefore the optimal dose is 2.0e12 cm -2 .
  • Figure 4 shows a comparison of the doping concentration profiles of the superjunction device of the present invention with the existing superjunction device along the corresponding BB' position.
  • the X axis represents the longitudinal depth along the BB' position in Figure 2, and 0 ⁇ m represents the interface between silicon and silicon dioxide, the distance from the surface of the silicon wafer. The larger the value, the closer to the body, the unit is micron; the Y axis
  • the doping concentration representing the drift region is compared with the relative values of the two.
  • the curve 201 is a doping concentration distribution curve corresponding to the existing super junction device
  • the curve 202 is a doping concentration distribution curve corresponding to the super junction device of the embodiment of the present invention. It can be seen that in curve 202, after the high energy JFET injection, two peaks are generated in the drift region; one is close to the surface and the other is in the body.
  • the surface peak is formed by low energy implantation, corresponding to the doping of the JFET implant region 10; the high concentration is injected by high energy. As shown, it corresponds to the doping of the second N-type region 11.
  • the curve 201 since only low-energy implantation is performed in the prior art device, only one peak is formed near the surface, corresponding to the doping of the JFET implantation region 10, which is the same as the peak near the surface in the curve 202. of.
  • the longitudinal position of the second N-type region 11 needs to be set according to the graded junction at the bottom of the P-type body region 5, and the peak of the second N-type region 11 is substantially at a position or a gap with the graded junction at the bottom of the P-type body region 5. Within plus or minus 1 micron.
  • the structure of the embodiment of the present invention does not require the addition of an additional lithography plate, but merely adds a higher energy JFET implant to the original JFET implant. It not only reduces the on-resistance, but also reduces the breakdown voltage. It also reduces the maximum reverse recovery current of the device during reverse recovery. It also increases the Cgd capacitance. The larger Cgd capacitor can reduce the switching of the device. Speed is also beneficial for improving device EMI.
  • FIG. 5 shows a comparison of the reverse recovery simulation curves of the super junction device provided by the embodiment of the present invention and the existing super junction device.
  • the curve 301 is a reverse recovery simulation curve of the existing super junction device, and the JFET injection condition in the curve 301 is "60 keV 2.0e12" in the third row of Table 1.
  • the curve 302 is a super junction device provided by the embodiment of the present invention.
  • the reverse recovery simulation curve, the JFET injection condition of the JFET implant region 10 and the second N-type region 11 in the curve 302 is "60keV2.0e12+1800keV2.0e12" in the seventh row of Table 1;
  • the horizontal axis represents time and the vertical axis represents the current corresponding to the super-junction MOSFET device. It can be seen that the Irrm of the device is significantly reduced after the embodiment of the present invention is implanted with a high energy JFET. Low Irrm is not only In order to reduce the loss of the device, it can reduce the high current to the device's Stress and improve the reliability of the device.
  • FIG. 6 shows a comparison of a gate-drain capacitance, that is, a Cgd simulation curve, between a super junction device and an existing super junction device according to an embodiment of the present invention.
  • the curve 401 is a Cgd simulation curve of the existing super junction device, and the JFET injection condition in the curve 401 is "60 keV 2.0e12" in the third row of Table 1.
  • the curve 402 is the Cgd of the super junction device provided by the embodiment of the present invention.
  • the JFET implantation conditions of the JFET implant region 10 and the second N-type region 11 in the curve 402 are "60keV2.0e12+1800keV2.0e12" in the seventh row of Table 1;
  • the horizontal axis represents the drain voltage, the gate The voltage is 0V, the unit is V;
  • the vertical axis represents the capacitance, which is a logarithmic coordinate.
  • the doping impurities of the second N-type region and the P-type body region are balanced, so that a top charge balance region can be formed on the top of the N-type pillar and the P-type pillar;
  • the N-type pillar and the P-type pillar at the top of the super-junction structure have a good balance between the N-type impurity and the P-type impurity when the P-type body region is not formed, but After the formation of the P-type body region, the P-type impurity of the super-junction structure is increased, so that the charge balance at the top of the super structure is deteriorated, and the present invention balances the doping impurities of the second N-type region and the P-type body region by the present invention.
  • the top charge balance of the super junction structure can be optimized, thereby increasing the electric field strength at the top of the super junction structure, and finally, the breakdown voltage of
  • the photomask of the second N-type region of the embodiment of the present invention can adopt the same photomask as the JFET implantation region, and the second N-type region can be formed only by adding an ion implantation process after or before ion implantation in the JFET implantation region.
  • adding a mask can add a lot of cost, and since the invention does not require an increase in the mask, the invention also has a lower process cost.
  • the photomask of the second N-type region of the present invention can also be separately defined by a photomask different from the photomask of the JFET implantation region, so that the second N-type region can be set larger than the JFET implantation region and can be set smaller than JFET injection area for convenient second N type Adjustment of zone size.
  • the second N-type region of the embodiment of the present invention is located at the bottom of the JFET implant region in the longitudinal direction, which can further reduce the JFET parasitic resistance between the P-type body regions, thereby reducing the specific on-resistance of the device.
  • the maximum electric field strength at the time of device breakdown is still located in the body, that is, in the super-junction structure at the bottom of the second N-type region, so the device of the present invention still has a good EAS. .
  • Embodiments of the present invention can also reduce the maximum reverse recovery current of the device in reverse recovery.
  • the embodiment of the present invention can also increase the gate-drain capacitance of the device, thereby reducing the switching speed of the device, thereby reducing electromagnetic interference (EMI) of the device to other circuits.
  • EMI electromagnetic interference

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Abstract

L'invention concerne un dispositif à super-jonction, une puce et un procédé de fabrication s'y rapportant. Le dispositif comprend : une électrode de grille (1), une couche d'oxyde de grille (2), une électrode de source (3), une zone de collecte de trous (4), une zone de corps (5) d'un premier type de conductivité, une colonne (6) du premier type de conductivité, une couche épitaxiale (7) d'un second type de conductivité, une couche tampon du type N (8), un substrat semi-conducteur (9), une zone d'injection JFET (10), et une zone (11) du second type de conductivité formée au-dessous de la zone d'injection JFET (10). La zone (11) du second type de conductivité et la zone de corps (5) du premier type de conductivité forment une zone d'équilibrage de charges supérieure au-dessus de la couche épitaxiale (7) du second type de conductivité et de la colonne (6) du premier type de conductivité, afin de favoriser l'intensité du champ électrique en haut d'une structure de super-jonction dans une plage de profondeur de la zone du corps (5) du premier type de conductivité et de réduire la résistance à l'état passant du dispositif. Par disposition supplémentaire de la zone du second type de conductivité au-dessous de la zone d'injection JFET afin de former une zone d'équilibrage de charges supérieure, la tension de claquage du dispositif est améliorée, la résistance spécifique à l'état passant, le courant de recouvrement inverse maximum et la vitesse de commutation sont réduits, la capacité grille-drain est augmentée, et l'efficacité de résistance aux interférences électromagnétiques (EMI) est améliorée.
PCT/CN2017/076899 2016-06-08 2017-03-16 Dispositif à super-jonction, puce et procédé de fabrication s'y rapportant WO2017211105A1 (fr)

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CN111200008A (zh) * 2018-11-20 2020-05-26 深圳尚阳通科技有限公司 超结器件及其制造方法
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