WO2017208499A1 - 電力分配合成器 - Google Patents
電力分配合成器 Download PDFInfo
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- WO2017208499A1 WO2017208499A1 PCT/JP2017/003817 JP2017003817W WO2017208499A1 WO 2017208499 A1 WO2017208499 A1 WO 2017208499A1 JP 2017003817 W JP2017003817 W JP 2017003817W WO 2017208499 A1 WO2017208499 A1 WO 2017208499A1
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- power distribution
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P5/00—Coupling devices of the waveguide type
- H01P5/12—Coupling devices having more than two ports
- H01P5/16—Conjugate devices, i.e. devices having at least one port decoupled from one other port
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P5/00—Coupling devices of the waveguide type
- H01P5/12—Coupling devices having more than two ports
- H01P5/16—Conjugate devices, i.e. devices having at least one port decoupled from one other port
- H01P5/19—Conjugate devices, i.e. devices having at least one port decoupled from one other port of the junction type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/32—Non-reciprocal transmission devices
Definitions
- the present invention relates to a power distribution / combination synthesizer that mainly distributes or synthesizes microwave and millimeter wave high-frequency signals.
- power distribution / combiners are widely used to distribute or synthesize high-frequency signals.
- the Wilkinson power distribution combiner is used when it is necessary to ensure isolation between output terminals when functioning as a distributor or isolation between input terminals when functioning as a combiner. .
- the conventional Wilkinson power distribution combiner has one common terminal and two input / output terminals.
- the common terminal serves as an input terminal during signal distribution and serves as an output terminal during signal synthesis.
- the two input / output terminals serve as output terminals during signal distribution and serve as input terminals during signal synthesis.
- the common terminal and each input / output terminal are each connected by a quarter wavelength ( ⁇ / 4) impedance transformer. Further, the input / output terminals are connected via an isolation resistor called one absorption resistor.
- a half wavelength ( ⁇ / 2) or a half wavelength with respect to the operating frequency is provided between each input / output terminal and the isolation resistor.
- the structure which provides the transmission line used as the electrical length of an integral multiple is disclosed.
- the power distribution and synthesizer described in Patent Document 1 is a power propagation path that connects input and output terminals, a path in which two input and output terminals are connected via two quarter-wavelength impedance transformers, and an isolator.
- the transmission line is configured so that the phase difference from the path to which the two input / output terminals are connected via the transmission resistor (absorption resistor) is an odd multiple of 180 degrees, thereby improving the design flexibility.
- the integral multiple of the half wavelength is a frequency, it is strictly a natural number (1, 2, 3,...) Excluding 0 and negative (same below).
- Patent Document 2 discloses a Wilkinson power distribution synthesizer having a configuration in which a transmission line and a stub are provided between each input / output terminal and an isolation resistor.
- the power distribution synthesizer described in Patent Document 2 includes a distributed constant line as a transmission line between each input / output terminal and an isolation resistor.
- the power distribution synthesizer can reduce the line length of the distributed constant line and reduce the circuit size. Can be provided.
- the Wilkinson power distribution synthesizer composed of a multilayer substrate is provided with a strip conductor pattern such as a quarter-wavelength impedance transformer on the inner layer of the multilayer substrate, and a chip resistor as an isolation resistor on the surface layer.
- the pattern and the chip resistor are connected by an interlayer connection conductor called a via.
- the influence of the electrical length of the via and the impedance discontinuity generated in the via portion cannot be ignored as the board thickness increases and the strip conductor pattern is arranged deeper in the inner layer. , Reflection characteristics at each input / output terminal, and isolation between input / output terminals deteriorate.
- an electrical length (about 164 deg (approximately 164 deg) (approximately 164 deg) between each input / output terminal and the isolation resistor with respect to the operating frequency (2.16 GHz). Since a distributed constant line is provided as a transmission line having a physical length of 42.6 mm)), it is possible to absorb the influence of the electrical length of the via connecting the chip resistor for isolation on the surface layer and the strip conductor pattern on the inner layer. However, there is a problem that the reflection characteristics at each input / output terminal and the isolation between the input / output terminals deteriorate due to the influence of the impedance discontinuity generated in the via portion.
- the present invention has been made to solve the above-described problems.
- the present invention is a small and suitable structure for a laminated structure, as well as a common terminal and each input.
- An object of the present invention is to obtain a power distribution synthesizer with good reflection characteristics and isolation characteristics at the output terminal.
- the present invention includes a common terminal that inputs a high-frequency signal to be distributed or outputs a combined high-frequency signal, and first and second input / output terminals that input a high-frequency signal that outputs or combines the distributed high-frequency signal.
- a first quarter-wavelength impedance transformer having one end connected to the common terminal and the other end connected to the first input / output terminal; and one end connected to the common terminal and the other end connected to the first terminal. Interference between the second quarter-wavelength impedance transformer connected to the two input / output terminals and the high-frequency signal related to the first input / output terminal and the high-frequency signal related to the second input / output terminal.
- a second line having a length that is an integral multiple of a half wavelength connecting the terminal, and the first line and the second line are cascaded with at least two line portions having different impedances.
- the first line is provided with a first stub in the center of the line in the longitudinal direction or a line part located on the first input / output terminal side from the center
- the second line is a line Or a power distribution synthesizer or the like in which a second stub is provided in the line portion located closer to the second input / output terminal than the center.
- the power distribution when a power distribution synthesizer is configured using a multilayer substrate, the power distribution has a small size and is suitable for a laminated structure, and has good reflection characteristics and isolation characteristics at common terminals and input / output terminals.
- a synthesizer can be provided.
- FIG. 4 is an explanatory diagram showing a simulation result related to an even / odd mode operation of the power distribution synthesizer having the conventional structure configured by the multilayer substrate of FIG. 3 and the power distribution synthesizer having the structure of the present invention of FIG. 1;
- FIG. 4 is an explanatory diagram showing a simulation result related to an even / odd mode operation of the power distribution synthesizer having the conventional structure configured by the multilayer substrate of FIG. 3 and the power distribution synthesizer having the structure of the present invention of FIG. 1;
- FIG. 3 is an equivalent circuit diagram of a power distribution synthesizer having a conventional structure configured by a multilayer substrate. It is a see-through
- the power distribution synthesizer is configured as a Wilkinson power distribution synthesizer using a multilayer substrate.
- a strip conductor pattern constituting a quarter-wavelength ( ⁇ / 4) impedance transformer is provided on the inner layer of the multilayer substrate, and a chip resistor is provided on the surface layer as an isolation resistor.
- the strip conductor pattern and the chip resistor are connected by a transmission line that is an integral multiple of a half wavelength ( ⁇ / 2) composed of a via and a strip conductor.
- a stub is provided on the strip conductor disposed between the via and the input / output terminal.
- the strip conductor pattern and the chip resistor are connected by a transmission line that is an integral multiple of a half wavelength ( ⁇ / 2) composed of a via and a strip conductor and is an odd multiple of the half wavelength.
- the strip conductor pattern and the chip resistor are transmission lines that are integral multiples of a half wavelength ( ⁇ / 2) composed of vias and strip conductors, and transmission lines that are even multiples of half wavelengths. It may be tied with.
- the transmission line of an even multiple of a half wavelength ( ⁇ / 2) it is possible to realize the improvement in the reflection characteristics at the input / output terminals mainly during the even mode operation in the even / odd mode operation of the power combiner / distributor.
- the influence of the discontinuity of the impedance generated in the via is suppressed, and the reflection characteristics at the common terminal and the input / output terminals and the isolation between the input / output terminals can be kept good.
- FIG. 1 is a block diagram showing an example of a power distribution / combination combiner according to Embodiment 1 of the present invention, which is shown as a perspective view.
- a strip conductor pattern of a quarter wavelength ( ⁇ / 4) impedance transformer is provided on the inner layer of the multilayer substrate, and a chip resistor is provided as an isolation resistor on the surface layer.
- ⁇ / 4 quarter wavelength
- a chip resistor is provided as an isolation resistor on the surface layer.
- a Wilkinson type power distribution synthesizer having a structure in which a strip conductor pattern and a chip resistor are connected by a transmission line having an integral multiple of a half wavelength ( ⁇ / 2) composed of a via and a strip conductor will be described.
- common terminal 1001 input / output terminal 1011, input / output terminal 1012, quarter-wavelength impedance transformer strip conductor 2001, quarter-wavelength impedance transformer strip conductor 2002, transmission line strip conductor 2111, transmission line
- the strip conductor 2112, the transmission line strip conductor 2121, the transmission line strip conductor 2122, the stub 2401, and the stub 2402 are disposed between the dielectric layer 5001 and the dielectric layer 5002.
- the ground conductor 3002, the chip resistor mounting conductor pattern 2301, the chip resistor mounting conductor pattern 2302, and the chip resistor 4001 indicated by dot hatching are the surface of the dielectric layer 5002 on which the dielectric layer 5001 is disposed. Located on the opposite side.
- the ground conductor 3001 is disposed on the surface of the dielectric layer 5001 opposite to the surface on which the dielectric layer 5002 is disposed.
- Via 2201 and via 2202 are arranged through the dielectric layer 5002.
- the ⁇ / 4 impedance transformer strip conductor 2001 connects the common terminal 1001 and the input / output terminal 1011.
- the ⁇ / 4 impedance transformer strip conductor 2002 connects the common terminal 1001 and the input / output terminal 1012.
- the transmission line strip conductor 2111, stub 2401, transmission line strip conductor 2121, via 2201, and chip resistor mounting conductor pattern 2301 connect the input / output terminal 1011 and the chip resistor 4001.
- the transmission line strip conductor 2112, the stub 2402, the transmission line strip conductor 2122, the via 2202, and the chip resistor mounting conductor pattern 2302 connect the input / output terminal 1012 and the chip resistor 4001.
- the chip resistor mounting conductor pattern 2301 and the chip resistor mounting conductor pattern 2302 are arranged in a notch 6001 provided in the ground conductor 3002.
- the chip resistor 4001 as an isolation resistor connects the chip resistor mounting conductor pattern 2301 and the chip resistor mounting conductor pattern 2302, and one end of the chip resistor 4001 is placed on the chip resistor mounting conductor pattern 2301.
- the chip resistor 4001 is mounted so that the other end of the chip resistor 4001 is positioned on the chip resistor mounting conductor pattern 2302.
- the stub 2401 is provided between the transmission line strip conductor 2111 and the transmission line strip conductor 2121.
- the stub 2402 is provided between the transmission line strip conductor 2112 and the transmission line strip conductor 2122.
- FIG. 2 shows a power distribution synthesizer illustrated in a perspective view in FIG. 3 when the power distribution synthesizer having a conventional structure disclosed in Patent Document 1 is formed of a multilayer substrate, and the present invention shown in FIG. It is a figure which shows the simulation result shown with the Smith chart regarding the power distribution synthesizer by Embodiment 1 at the time of even-odd mode operation
- Patent Document 1 is indicated by A
- Embodiment 1 of the present invention is indicated by B.
- the power distribution / combining device includes the transmission line strip conductor 2111, the transmission line strip conductor 2121, the chip resistor mounting conductor pattern 2301, and the length of the via 2201, and the transmission line.
- the case where the total length of the strip conductor 2112, the transmission line strip conductor 2122, the chip resistor mounting conductor pattern 2302 and the via 2202 is an odd multiple of a half wavelength ( ⁇ / 2) will be described.
- the example of the conventional power distribution combiner of FIG. 3 and the power distribution combiner of the present invention of FIG. 1 are equally divided on the symmetry plane, and the divided plane is an electric wall (during odd mode operation). Or it is calculated as a magnetic wall (even mode operation).
- 2A is a reflection characteristic at the input / output terminal 1011 or the input / output terminal 1012 during the odd mode operation
- FIG. 2B is a reflection characteristic at the input / output terminal 1011 or the input / output terminal 1012 during the even mode operation
- (c) ) Shows the reflection characteristics at the common terminal 1001 during the even mode operation in the range of 20% of the relative bandwidth.
- the power distribution of the present invention of FIG. 1 is compared with the conventional power distribution combiner of FIG. It can be seen that the synthesizer has obtained characteristics close to the center of the Smith chart (reflection zero point). Further, the reflection characteristic at the input / output terminal 1011 or the input / output terminal 1012 during the even mode operation of (b) and the reflection characteristic at the common terminal 1001 during the even mode operation of (c) are the same as those of the conventional power distribution combination of FIG. It can be seen that there is no significant change between the power supply and the power distribution combiner of the present invention of FIG.
- FIG. 4 shows simulation results during power distribution related to reflection characteristics and isolation characteristics of the conventional power distribution synthesizer configured with the multilayer substrate of FIG. 3 and the power distribution synthesizer having the structure of the present invention of FIG.
- FIG. (a) shows the result of the conventional power distribution synthesizer of FIG. 3, and (b) shows the result of the power distribution synthesizer of the present invention of FIG. 4A and 4B
- the dotted line A is the reflection characteristic at the common terminal 1001
- the long broken line B is the reflection characteristic at the input / output terminal 1011 or the input / output terminal 1012
- the solid line C is the common terminal 1001 to the input / output terminal 1011.
- a passage characteristic (distribution characteristic) to the input / output terminal 1012 and an alternate long and short dash line D indicate an isolation characteristic between the input / output terminal 1011 and the input / output terminal 1012.
- the simulation results related to the conventional power distribution / combiner are degraded values of reflection amount -17 dB and isolation amount -16 dB, respectively. I understand that.
- the power distribution combiner in the first embodiment by providing the stub 2401 and the stub 2402, the transmission line strip conductor 2121, the via 2201, and the chip resistor mounting conductor Input / output terminals at the time of odd mode operation deteriorated due to the impedance discontinuity caused by the pattern 2301 and the impedance discontinuity caused by the transmission line strip conductors 2122 and vias 2202 and the chip resistor mounting conductor pattern 2302
- FIG. 5 is an equivalent circuit diagram of the power distribution combiner according to the first embodiment of the present invention shown in FIG.
- FIG. 6 is an equivalent circuit diagram of a conventional power distribution synthesizer composed of the multilayer substrate of FIG. Comparing the equivalent circuit diagrams of FIG. 5 and FIG. 6, the transmission lines 0131 and 0132 which are the transmission lines on the input / output terminals 0011 and 0012 side of FIG. 6 are shown in FIG. 0051, transmission line 0332, transmission line 0432, and stub 0052.
- the transmission line 0231 has an impedance different from that of the transmission line 0331 and the transmission line 0431
- the transmission line 0232 has an impedance different from that of the transmission line 0332 and the transmission line 0432, resulting in impedance discontinuity.
- the power distribution synthesizer is constituted by a multilayer substrate composed of two dielectric layers 5001 and 5002.
- the present invention is not limited to this, and a power distribution synthesizer composed of a multilayer substrate composed of three or more dielectric layers may be used.
- FIG. 7 is a block diagram showing a power distribution and synthesizer according to Embodiment 1 of the present invention, which is constituted by a multilayer substrate composed of four dielectric layers, and is shown as a perspective view.
- the dielectric layer 5003 is disposed on the opposite surface of the dielectric layer 5002 to the surface on which the dielectric layer 5001 is disposed, and the surface of the dielectric layer 5003 on which the dielectric layer 5002 is disposed is A dielectric layer 5004 is disposed on the opposite surface.
- a ground conductor 3011 is disposed between the dielectric layer 5002 and the dielectric layer 5003, and a ground conductor 3012 is disposed between the dielectric layer 5003 and the dielectric layer 5004.
- the ground conductor 3002, the chip resistor mounting conductor pattern 2301, the chip resistor mounting conductor pattern 2302, and the chip resistor 4001 are disposed on the surface of the dielectric layer 5004 opposite to the surface on which the dielectric layer 5003 is disposed. Yes.
- the ground conductor 3011 is provided with a notch 6111 and a notch 6112, and the ground conductor 3012 is provided with a notch 6121 and a notch 6122.
- the transmission line strip conductor 2111, the stub 2401, the transmission line strip conductor 2121, the via 2211, and the chip resistor mounting conductor pattern 2301 connect the input / output terminal 1011 and the chip resistor 4001.
- the transmission line strip conductor 2112, the stub 2402, the transmission line strip conductor 2122, the via 2212, and the chip resistor mounting conductor pattern 2302 connect the input / output terminal 1012 and the chip resistor 4001.
- the via 2201 and the via 2202 are manufactured by penetrating only the dielectric layer 5002, but the present invention is not limited to this, and the dielectric layer 5001 is penetrated as shown in FIG. It is good also as a manufactured structure.
- the via 2201 has a stub 2501
- the via 2202 has a stub 2502
- the stub 2501 and the stub 2502 are impedance discontinuities. Even in the case of operation, the same effect as the above-described example can be obtained.
- Dielectric layer 5011 is disposed on the surface of dielectric layer 5001 opposite to the surface on which dielectric layer 5002 is disposed.
- a ground conductor 3001 is disposed on the surface of the dielectric layer 5011 opposite to the surface on which the dielectric layer 5001 is disposed.
- This configuration can also be implemented in the configuration shown in FIG. 7, wherein the via 2201 has a stub 2501, the via 2202 has a stub 2502, and the stub 2501 and the stub 2502 have dielectric layers as shown in FIG. A structure manufactured through 5001 may be used.
- a dielectric layer 5011 is disposed on the surface of the dielectric layer 5001 opposite to the surface on which the dielectric layer 5002 is disposed.
- FIG. 9 is a block diagram showing a power distribution / combination combiner according to the first embodiment of the present invention using a via operating as a ground conductor.
- 9A is a perspective view similar to FIG. 1 and the like
- FIG. 9B is a diagram illustrating dielectric layers 5001 and vias operating as strip conductors and ground conductors disposed on the dielectric layers 5002, dielectric layers and ground. It is a top view shown without a conductor.
- a ground outer conductor via 7001 and a ground outer conductor via 7002 penetrate the dielectric layer 5001 and the dielectric layer 5002, and connect the ground conductor 3001 and the ground conductor 3002.
- a plurality of vias for grounding conductor 7001 are arranged in parallel with the via 2201 so as to surround the via 2201 in a plane orthogonal to the axial direction of the via 2201.
- a plurality of vias for outer ground conductor 7002 are arranged in parallel with the via 2202 so as to surround the via 2202 in a plane perpendicular to the axial direction of the via 2202.
- FIG. 10 is a configuration diagram showing a power distribution and synthesizer according to Embodiment 1 of the present invention in which an adjustable stub is provided only in each mode in even / odd mode operation, and is shown as a perspective view.
- a stub 2400 is disposed at a point where the ⁇ / 4 impedance transformer strip conductor 2001 and the ⁇ / 4 impedance transformer strip conductor 2002 are connected.
- FIG. 11 is a configuration diagram showing a power distribution / combining device using a microstrip line according to Embodiment 2 of the present invention, and is shown as a perspective view.
- the microstrip line has a structure in which the dielectric layer on the upper part of the inner conductor and the outer conductor are not necessary in the strip line of each example described above.
- the internal conductors indicated by the reference numerals 1001, 2001, 1011, 2111, 2121, 2121, 1222, 2402, 2112, 1012 and 2002 in the above-described examples are configured by microstrip lines. Accordingly, the ground conductor is not disposed on the surface of the dielectric layer 5002 opposite to the surface on which the dielectric layer 5001 is disposed.
- the control range of the impedance in each transmission line can be expanded, the degree of freedom in design can be improved, and the same as in the first embodiment. An effect is obtained.
- Embodiment 3 the power distribution synthesizer in which the common terminal 1001 and the input / output terminals 1011 and 1012 are each connected by the ⁇ / 4 impedance transformer has been described.
- one end of the ⁇ / 4 impedance transformer is connected to the common terminal 1001
- the other end of the ⁇ / 4 impedance transformer is connected to the input / output terminals 1011 and 1012 through the ⁇ / 4 transmission line.
- a distribution synthesizer may be used.
- FIG. 12 is a configuration diagram showing a power distribution synthesizer according to Embodiment 3 of the present invention, and is shown as a perspective view.
- a quarter wavelength ( ⁇ / 4) impedance transformer strip conductor 2010 is connected to the common terminal 1001, and the common terminal 1001 of the ⁇ / 4 impedance transformer strip conductor 2010 is connected to the common terminal 1001.
- the terminal opposite to the connected terminal and the input / output terminal 1011 are connected by a quarter wavelength ( ⁇ / 4) strip conductor 2011, and the common terminal 1001 of the ⁇ / 4 impedance transformer strip conductor 2010 is connected.
- a terminal opposite to the terminal and the input / output terminal 1012 are connected by a quarter wavelength ( ⁇ / 4) strip conductor 2012.
- a ⁇ / 4 impedance transformer is provided. Since the low-impedance transmission line can be configured by the unit strip conductor 2010, the design flexibility of the power distribution combiner can be improved, and the same effects as those of the first embodiment can be obtained. 10 may be provided between the ⁇ / 4 strip conductor 2011 and the ⁇ / 4 strip conductor 2012, as shown in FIG.
- FIG. 13 is a configuration diagram showing a power distribution synthesizer according to Embodiment 4 of the present invention, and is shown as a perspective view.
- the chip resistor 4001 is disposed in the dielectric layer 5003, and the ground conductor is disposed on the surface of the dielectric layer 5003 opposite to the surface on which the dielectric layer 5002 is disposed. 3003 is arranged.
- the fourth embodiment by disposing the chip resistor 4001 in the dielectric layer 5003, the area occupied by the surface layer of the multilayer substrate can be reduced, and the same effect as in the first embodiment can be obtained.
- the transmission line strip conductor 2111 and the transmission line strip conductor 2121 constitute a first conductor cascade line (2111, 2121).
- the transmission line strip conductor 2112 and the transmission line strip conductor 2122 constitute a second conductor cascade line (2112, 2122).
- the first conductor cascade line (2111, 2121) and the second conductor cascade line (2112, 2122) may be configured by cascading at least two line portions having different impedances.
- the first conductor cascade lines (2111, 2121) may be provided with the first stub (2401) at the center of the line in the longitudinal direction or at the line portion located closer to the first input / output terminal 1011 than the center.
- the second conductor cascade lines (2112, 2122) may be provided with the second stub (2402) at the center in the longitudinal direction of the line or at the line portion located closer to the second input / output terminal 1012 than the center.
- the vias 2201 and 2202 constitute a vertical connection conductor, and the grounding outer conductor via 7001 and the grounding outer conductor via 7002 constitute a grounding vertical conductor.
- Embodiment 5 FIG.
- a stub is mainly provided between the input / output terminal 1011 and the chip resistor mounting conductor pattern 2301 and between the input / output terminal 1012 and the chip resistor mounting conductor pattern 2302.
- two or more stubs may be provided.
- the length of the transmission line strip conductor 2111, the transmission line strip conductor 2121, the chip resistor mounting conductor pattern 2301, and the via 2201, and the transmission line strip conductor 2112, the transmission line strip conductor 2122, and the chip resistor mounting conductor pattern is an odd multiple of an integral multiple of a half wavelength ( ⁇ / 2), the reflection characteristics at the input / output terminals during odd mode operation can be adjusted, and power distribution operation.
- ⁇ / 2 2202 is an odd multiple of an integral multiple of a half wavelength ( ⁇ / 2)
- the combined length of the transmission line strip conductor 2111, the transmission line strip conductor 2121, the chip resistor mounting conductor pattern 2301 and the via 2201, and the transmission line strip conductor 2112, the transmission line strip conductor 2122, and the chip resistor mounting When the combined length of the conductor pattern 2302 and the via 2202 is an even multiple of an integral multiple of a half wavelength ( ⁇ / 2), the reflection characteristics at the input / output terminals during the even mode operation can be adjusted. There is an effect that it is possible to obtain a power distribution combiner having various reflection characteristics and isolation characteristics that are favorable during the distribution operation and the power combining operation. Note that the number of stubs in each case is the case where the length of the line is an odd multiple of the half wavelength ( ⁇ / 2) and the length of the line is an even multiple of the half wavelength ( ⁇ / 2). Can be one or more.
- the reflection characteristics at the input / output terminals during the even mode operation can be respectively adjusted, and there is an effect that it is possible to obtain a power distribution synthesizer having various reflection characteristics and isolation characteristics that are favorable during the power distribution operation and the power combining operation.
- a stub 2401 is provided in the center of the longitudinal direction or in the line portion located closer to the input / output terminal 1011 than the center, and the stub 2401 Further, a stub 2411 is provided in the line portion that is a quarter wavelength away from the input / output terminal 1011 side.
- a stub 2402 is provided at the center in the longitudinal direction or at the line portion located closer to the input / output terminal 1012 than the center, and a stub 2412 is provided at the line portion separated from the stub 2402 toward the input / output terminal 1012 by a quarter wavelength.
- FIG. 16 is a configuration diagram showing a power distribution / combining device using a microstrip line according to Embodiment 5 of the present invention, and is shown as a perspective view.
- the microstrip line has a structure in which the dielectric layer above the inner conductor shown as the ground conductor 3002 and the like and the outer conductor are not required in the strip line of each of the above examples.
- Common terminal 0001 is common terminal 1001
- transmission lines 0021 and 0022 are ⁇ / 4 impedance transformer strip conductors 2001 and 2002
- input / output terminals 0011 and 0012 are input and output terminals 1011 and 1012
- resistor 0041 is a chip resistor 4001.
- the transmission lines 0331, 0431, 0231 in FIG. 5 correspond to the transmission line strip conductors 2111, 2121, the chip resistor mounting conductor pattern 2301, and the via 2201, and in the case of FIGS. 15 and 16, the transmission line strip conductor 2131 is further provided. included.
- the transmission lines 0332, 0432, and 0232 correspond to the transmission line strip conductors 2112, 2122, the chip resistor mounting conductor pattern 2302, and the via 2202, and in the case of FIGS. 15 and 16, the transmission line strip conductor 2132 is further included.
- the stub 0051 corresponds to the stub 2401, and the stub 2411 is further included in the case of FIGS.
- the stub 0052 corresponds to the stub 2402 and further includes a stub 2412 in the case of FIGS.
- the present invention provides a common terminal (1001) for inputting a high-frequency signal to be distributed or outputting a synthesized high-frequency signal, First and second input / output terminals (1011, 1012) for inputting a high-frequency signal for outputting or synthesizing the distributed high-frequency signal; A first quarter-wavelength impedance transformer (2001) having one end connected to the common terminal and the other end connected to the first input / output terminal; A second quarter-wavelength impedance transformer (2002) having one end connected to the common terminal and the other end connected to the second input / output terminal; An isolation resistor (4001) for preventing interference between the high-frequency signal related to the first input / output terminal and the high-frequency signal related to the second input / output terminal; A first line (2111, 2121, 2201, 2301) having a length that is an integral multiple of a half wavelength connecting the isolation resistor and the first input / output terminal; A second line (2112, 2122, 2202, 2302) having a length that is an integral multiple of
- the second line (2112, 2122, 2202, 2302) is provided with a second stub (2402) at the center in the longitudinal direction of the line or at the line part located closer to the second input / output terminal than the center. Located in the power distribution combiner.
- the present invention also provides a common terminal (1001) for inputting a high frequency signal to be distributed or outputting a synthesized high frequency signal, First and second input / output terminals (1011, 1012) for inputting a high-frequency signal for outputting or synthesizing the distributed high-frequency signal; A quarter-wavelength impedance transformer (2010) with one end connected to the common terminal; A first quarter-wave line (2011) having one end connected to the impedance transformer and the other end connected to the first input / output terminal; A second quarter-wave line (2012) having one end connected to the impedance transformer and the other end connected to the second input / output terminal; An isolation resistor (4001) for preventing interference between the high-frequency signal related to the first input / output terminal and the high-frequency signal related to the second input / output terminal; A first line (2111, 2121, 2201, 2301) having a length that is an integral multiple of a half wavelength connecting the isolation resistor and the first input / output terminal; A second line (2112, 2122, 2202, 2302)
- the second line (2112, 2122, 2202, 2302) is provided with a second stub (2402) at the center in the longitudinal direction of the line or at the line part located closer to the second input / output terminal than the center. Located in the power distribution combiner.
- a third stub (2400) is provided between the first impedance transformer (2001) and the second impedance transformer (2002).
- a third stub (2400) is provided between the first quarter-wave line (2011) and the second quarter-wave line (2012).
- first line (2111, 2121, 2201, 2301) and the second line (2112, 2122, 2202, 2302) have a length that is an odd multiple of a half wavelength.
- the first lines (2111, 2121, 2201, 2301) and the second lines (2112, 2122, 2202, 2302) have a length that is an even multiple of a half wavelength.
- the first line (2111, 2121, 2201, 2301) is provided with a fourth stub (2411) in a line part between the first stub and the first input / output terminal side
- the second line (2112, 2122, 2202, 2302) is provided with a fifth stub (2412) in the line part between the second stub and the second input / output terminal side.
- the power distribution synthesizer according to the present invention can be applied to a power distribution synthesizer used in many fields.
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Description
ここで半波長の整数倍とは、周波数なので厳密には0と負を除いた自然数(1,2,3,…)倍となる(以下同様)。
図1はこの発明の実施の形態1による電力分配合成器の一例を示す構成図であり、透視斜視図として示されている。この実施の形態1では、主に多層基板から構成され、多層基板内層に四分の一波長(λ/4)インピーダンス変成器のストリップ導体パターンを設け、表層にはアイソレーション抵抗としてチップ抵抗器を設け、ストリップ導体パターンとチップ抵抗器がヴィアとストリップ導体からなる半波長(λ/2)の整数倍の伝送線路により結ばれる構造を有するウィルキンソン型電力分配合成器について説明する。
λ/4インピーダンス変成器ストリップ導体2002は、共通端子1001と入出力端子1012とを接続する。
伝送線路ストリップ導体2112、スタブ2402、伝送線路ストリップ導体2122、ヴィア2202、チップ抵抗器実装用導体パターン2302は、入出力端子1012とチップ抵抗器4001とを接続する。
また、(b)の偶モード動作時の入出力端子1011または入出力端子1012における反射特性、および(c)の偶モード動作時の共通端子1001における反射特性は、図3の従来の電力分配合成器と、図1のこの発明の電力分配合成器とで大きく変化していないことが分かる。
図4の(a)(b)において、点線Aは共通端子1001における反射特性、長めの破線Bは入出力端子1011または入出力端子1012における反射特性、実線Cは共通端子1001から入出力端子1011または入出力端子1012への通過特性(分配特性)、一点鎖線Dは入出力端子1011と入出力端子1012との間のアイソレーション特性、を示している。
図6は、図3の多層基板で構成された従来構造の電力分配合成器の等価回路図である。
図5と図6の等価回路図を比較すると、図6の入出力端子0011,0012側の伝送線路である伝送線路0131および伝送線路0132が、図5ではそれぞれ伝送線路0331、伝送線路0431、スタブ0051と、伝送線路0332、伝送線路0432、スタブ0052とに置き換えられている。
図7の例では、誘電体層5002における誘電体層5001が配置された面とは反対の面に誘電体層5003が配置され、誘電体層5003における誘電体層5002が配置された面とは反対の面に誘電体層5004が配置されている。
なおこの構成は、図7の構成においても実施可能であり、ヴィア2201がスタブ2501を有し、ヴィア2202がスタブ2502を有し、スタブ2501およびスタブ2502が図8に示すように、誘電体層5001を貫いて製造された構造としてもよい。また図8に示すように、誘電体層5001における誘電体層5002が配置された面とは反対の面には誘電体層5011が配置される。
上記実施の形態1では、ストリップ線路を用いた構成の電力分配合成器について説明したが、マイクロストリップ線路を用いた構成の電力分配合成器としてもよい。
図11はこの発明の実施の形態2によるマイクロストリップ線路を用いた電力分配合成器を示す構成図であり、透視斜視図として示されている。マイクロストリップ線路とは上述の各例のストリップ線路において内部導体の上部の誘電体層と外部導体を不要にした構造でなる。
図11の電力分配合成器では、上述の各例の符号1001,2001,1011,2111,2401,2121,2122,2402,2112,1012,2002で示す内部導体がマイクロストリップ線路で構成されている。従って誘電体層5002における誘電体層5001が配置された面と反対の面には接地導体が配置されていない。
上記実施の形態1および2では、共通端子1001と入出力端子1011および1012とを各々λ/4インピーダンス変成器で接続する電力分配合成器について説明した。この発明ではさらに、共通端子1001にλ/4インピーダンス変成器の一端を接続するとともに、λ/4インピーダンス変成器の他端と入出力端子1011および1012とを各々λ/4伝送線路で接続する電力分配合成器としてもよい。
図12は、この発明の実施の形態3による電力分配合成器を示す構成図であり、透視斜視図として示されている。
なお、図10の電力分配合成器と同様に、λ/4ストリップ導体2011とλ/4ストリップ導体2012との間に図14に示すようにスタブ2400を設けてもよい。
上記実施の形態1、2および3では、チップ抵抗器4001が多層基板の表層に実装された電力分配合成器について説明したが、チップ抵抗器4001は多層基板内層に実装された電力分配合成器としてもよい。
図13は、この発明の実施の形態4による電力分配合成器を示す構成図であり、透視斜視図として示されている。
例えば伝送線路ストリップ導体2111と伝送線路ストリップ導体2121は、第1の導体縦続線路(2111,2121)を構成する。
また例えば伝送線路ストリップ導体2112と伝送線路ストリップ導体2122は、第2の導体縦続線路(2112,2122)を構成する。
第1の導体縦続線路(2111,2121)および第2の導体縦続線路(2112,2122)は、ともにインピーダンスが異なる線路部を少なくとも2つ以上縦続接続させて構成されたものであればよい。
そして第1の導体縦続線路(2111,2121)は線路の長手方向の中心または中心よりも第1の入出力端子1011側に位置した線路部に第1のスタブ(2401)を設けていればよい。
また第2の導体縦続線路(2112,2122)は線路の長手方向の中心または中心よりも第2の入出力端子1012側に位置した線路部に第2のスタブ(2402)を設けていればよい。
またヴィア2201,2202は垂直接続導体、接地外導体用ヴィア7001および接地外導体用ヴィア7002は接地垂直導体を構成する。
上記各実施の形態の説明では主に、入出力端子1011からチップ抵抗器実装用導体パターン2301までの間、ならびに入出力端子1012からチップ抵抗器実装用導体パターン2302までの間にスタブをそれぞれ1つずつ設ける場合について説明したが、スタブを2つずつ以上設けてもよい。
伝送線路ストリップ導体2111と伝送線路ストリップ導体2121とチップ抵抗器実装用導体パターン2301とヴィア2201とを合わせた長さ、ならびに伝送線路ストリップ導体2112と伝送線路ストリップ導体2122とチップ抵抗器実装用導体パターン2302とヴィア2202とを合わせた長さが、半波長(λ/2)の整数倍のうち奇数倍である場合には、奇モード動作時の入出力端子における反射特性を調整でき、電力分配動作および電力合成動作時に良好な各種反射特性およびアイソレーション特性を有する電力分配合成器を得ることができる効果を奏する。
また、伝送線路ストリップ導体2111と伝送線路ストリップ導体2121とチップ抵抗器実装用導体パターン2301とヴィア2201とを合わせた長さ、ならびに伝送線路ストリップ導体2112と伝送線路ストリップ導体2122とチップ抵抗器実装用導体パターン2302とヴィア2202とを合わせた長さが、半波長(λ/2)の整数倍のうち偶数倍である場合には、偶モード動作時の入出力端子における反射特性を調整でき、電力分配動作および電力合成動作時に良好な各種反射特性およびアイソレーション特性を有する電力分配合成器を得ることができる効果を奏する。
なお、上述の線路の長さが半波長(λ/2)の奇数倍の場合でも、また線路の長さが半波長(λ/2)の偶数倍の場合でも、それぞれの場合にスタブの数を1個または複数個とすることができる。
共通端子0001は共通端子1001に、伝送線路0021、0022はλ/4インピーダンス変成器ストリップ導体2001,2002に、入出力端子0011、0012は入出力端子1011,1012に、抵抗0041はチップ抵抗器4001に、それぞれ相当する。
図5の、伝送線路0331,0431,0231は伝送線路ストリップ導体2111,2121、チップ抵抗器実装用導体パターン2301、ヴィア2201に相当し、図15,16の場合はさらに、伝送線路ストリップ導体2131が含まれる。
伝送線路0332,0432,0232は伝送線路ストリップ導体2112,2122、チップ抵抗器実装用導体パターン2302、ヴィア2202に相当し、図15,16の場合はさらに、伝送線路ストリップ導体2132が含まれる。
スタブ0051はスタブ2401に相当し、図15,16の場合はさらにスタブ2411が含まれる。スタブ0052はスタブ2402に相当し、図15,16の場合はさらにスタブ2412が含まれる。
分配された高周波信号を出力するまたは合成する高周波信号を入力する第1および第2の入出力端子(1011,1012)と、
一端が前記共通端子に接続され他端が前記第1の入出力端子に接続された第1の四分の一波長のインピーダンス変成器(2001)と、
一端が前記共通端子に接続され他端が前記第2の入出力端子に接続された第2の四分の一波長のインピーダンス変成器(2002)と、
前記第1の入出力端子に関わる高周波信号と前記第2の入出力端子に関わる高周波信号との干渉を防止するアイソレーション抵抗(4001)と、
前記アイソレーション抵抗と前記第1の入出力端子とを接続する半波長に対して整数倍の長さとなる第1の線路(2111,2121,2201,2301)と、
前記アイソレーション抵抗と前記第2の入出力端子とを接続する半波長に対して整数倍の長さとなる第2の線路(2112,2122,2202,2302)と、
を備え、
前記第1の線路(2111,2121,2201,2301)および前記第2の線路(2112,2122,2202,2302)は、それぞれインピーダンスが異なる線路部が少なくとも2つ以上縦続に接続されてなり、
前記第1の線路(2111,2121,2201,2301)は線路の長手方向の中心または中心よりも前記第1の入出力端子側に位置した線路部に第1のスタブ(2401)を設け、
前記第2の線路(2112,2122,2202,2302)は線路の長手方向の中心または中心よりも前記第2の入出力端子側に位置した線路部に第2のスタブ(2402)を設けた、
電力分配合成器にある。
分配された高周波信号を出力するまたは合成する高周波信号を入力する第1および第2の入出力端子(1011,1012)と、
一端が前記共通端子に接続された四分の一波長のインピーダンス変成器(2010)と、
一端が前記インピーダンス変成器に接続され他端が前記第1の入出力端子に接続された第1の四分の一波長の線路(2011)と、
一端が前記インピーダンス変成器に接続され他端が前記第2の入出力端子に接続された第2の四分の一波長の線路(2012)と、
前記第1の入出力端子に関わる高周波信号と前記第2の入出力端子に関わる高周波信号との干渉を防止するアイソレーション抵抗(4001)と、
前記アイソレーション抵抗と前記第1の入出力端子とを接続する半波長に対して整数倍の長さとなる第1の線路(2111,2121,2201,2301)と、
前記アイソレーション抵抗と前記第2の入出力端子とを接続する半波長に対して整数倍の長さとなる第2の線路(2112,2122,2202,2302)と、
を備え、
前記第1の線路(2111,2121,2201,2301)および前記第2の線路(2112,2122,2202,2302)は、それぞれインピーダンスが異なる線路部が少なくとも2つ以上縦続に接続されてなり、
前記第1の線路(2111,2121,2201,2301)は線路の長手方向の中心または中心よりも前記第1の入出力端子側に位置した線路部に第1のスタブ(2401)を設け、
前記第2の線路(2112,2122,2202,2302)は線路の長手方向の中心または中心よりも前記第2の入出力端子側に位置した線路部に第2のスタブ(2402)を設けた、
電力分配合成器にある。
また、前記第1の四分の一波長の線路(2011)と前記第2の四分の一波長の線路(2012)との間に第3のスタブ(2400)を設けた。
前記各端子、変成器、線路、スタブをそれぞれ形成する多層基板内層のストリップ導体と、
前記抵抗を形成する表面実装されたチップ抵抗器(4001)と、
前記ストリップ導体と前記チップ抵抗とを接続する垂直接続導体(2201,2202)と、
から構成される。
また、多層基板における、
前記各端子、変成器、線路、スタブをそれぞれ形成する多層基板内層のストリップ導体と、
前記抵抗を形成する多層基板内層に実装されたチップ抵抗器(4001)と、
前記ストリップ導体と前記チップ抵抗とを接続する垂直接続導体(2201,2202)と、
から構成される。
また、前記垂直接続導体(2201,2202)の周囲に接地垂直導体(7001,7002)を有する。
また、前記第1の線路(2111,2121,2201,2301)および前記第2の線路(2112,2122,2202,2302)は、半波長に対して偶数倍の長さを有する。
また、前記第1の線路(2111,2121,2201,2301)は、前記第1のスタブと前記第1の入出力端子側との間の線路部に第4のスタブ(2411)を設け、
前記第2の線路(2112,2122,2202,2302)は、前記第2のスタブと前記第2の入出力端子側との間の線路部に第5のスタブ(2412)を設けた。
Claims (10)
- 分配する高周波信号を入力するまたは合成された高周波信号を出力する共通端子と、
分配された高周波信号を出力するまたは合成する高周波信号を入力する第1および第2の入出力端子と、
一端が前記共通端子に接続され他端が前記第1の入出力端子に接続された第1の四分の一波長のインピーダンス変成器と、
一端が前記共通端子に接続され他端が前記第2の入出力端子に接続された第2の四分の一波長のインピーダンス変成器と、
前記第1の入出力端子に関わる高周波信号と前記第2の入出力端子に関わる高周波信号との干渉を防止するアイソレーション抵抗と、
前記アイソレーション抵抗と前記第1の入出力端子とを接続する半波長に対して整数倍の長さとなる第1の線路と、
前記アイソレーション抵抗と前記第2の入出力端子とを接続する半波長に対して整数倍の長さとなる第2の線路と、
を備え、
前記第1の線路および前記第2の線路は、それぞれインピーダンスが異なる線路部が少なくとも2つ以上縦続に接続されてなり、
前記第1の線路は線路の長手方向の中心または中心よりも前記第1の入出力端子側に位置した線路部に第1のスタブを設け、
前記第2の線路は線路の長手方向の中心または中心よりも前記第2の入出力端子側に位置した線路部に第2のスタブを設けた、
電力分配合成器。 - 分配する高周波信号を入力するまたは合成された高周波信号を出力する共通端子と、
分配された高周波信号を出力するまたは合成する高周波信号を入力する第1および第2の入出力端子と、
一端が前記共通端子に接続された四分の一波長のインピーダンス変成器と、
一端が前記インピーダンス変成器に接続され他端が前記第1の入出力端子に接続された第1の四分の一波長の線路と、
一端が前記インピーダンス変成器に接続され他端が前記第2の入出力端子に接続された第2の四分の一波長の線路と、
前記第1の入出力端子に関わる高周波信号と前記第2の入出力端子に関わる高周波信号との干渉を防止するアイソレーション抵抗と、
前記アイソレーション抵抗と前記第1の入出力端子とを接続する半波長に対して整数倍の長さとなる第1の線路と、
前記アイソレーション抵抗と前記第2の入出力端子とを接続する半波長に対して整数倍の長さとなる第2の線路と、
を備え、
前記第1の線路および前記第2の線路は、それぞれインピーダンスが異なる線路部が少なくとも2つ以上縦続に接続されてなり、
前記第1の線路は線路の長手方向の中心または中心よりも前記第1の入出力端子側に位置した線路部に第1のスタブを設け、
前記第2の線路は線路の長手方向の中心または中心よりも前記第2の入出力端子側に位置した線路部に第2のスタブを設けた、
電力分配合成器。 - 前記第1のインピーダンス変成器と前記第2のインピーダンス変成器との間に第3のスタブを設けた、請求項1に記載の電力分配合成器。
- 前記第1の四分の一波長の線路と前記第2の四分の一波長の線路との間に第3のスタブを設けた、請求項2に記載の電力分配合成器。
- 多層基板における、
前記各端子、変成器、線路、スタブをそれぞれ形成する多層基板内層のストリップ導体と、
前記抵抗を形成する表面実装されたチップ抵抗器と、
前記ストリップ導体と前記チップ抵抗とを接続する垂直接続導体と、
から構成される請求項1から4までのいずれか1項に記載の電力分配合成器。 - 多層基板における、
前記各端子、変成器、線路、スタブをそれぞれ形成する多層基板内層のストリップ導体と、
前記抵抗を形成する多層基板内層に実装されたチップ抵抗器と、
前記ストリップ導体と前記チップ抵抗とを接続する垂直接続導体と、
から構成される請求項1から4までのいずれか1項に記載の電力分配合成器。 - 前記垂直接続導体の周囲に接地垂直導体を有する、請求項5または6に記載の電力分配合成器。
- 前記第1の線路および前記第2の線路は、半波長に対して奇数倍の長さを有する請求項1から7までのいずれか1項に記載の電力分配合成器。
- 前記第1の線路および前記第2の線路は、半波長に対して偶数倍の長さを有する請求項1から7までのいずれか1項に記載の電力分配合成器。
- 前記第1の線路は、前記第1のスタブと前記第1の入出力端子側との間の線路部に第4のスタブを設け、
前記第2の線路は、前記第2のスタブと前記第2の入出力端子側との間の線路部に第5のスタブを設けた、
請求項1から9までのいずれか1項に記載の電力分配合成器。
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PCT/JP2016/066555 WO2017208432A1 (ja) | 2016-06-03 | 2016-06-03 | 電力分配合成器 |
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JP2021514540A (ja) * | 2018-02-28 | 2021-06-10 | レイセオン カンパニー | アディティブ製造技術(amt)低プロファイル信号分割器 |
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WO2019187872A1 (ja) | 2018-03-27 | 2019-10-03 | 株式会社村田製作所 | アンテナモジュール |
JP6760553B1 (ja) | 2019-01-22 | 2020-09-23 | 株式会社村田製作所 | アンテナモジュールおよび通信装置 |
CN111540997B (zh) * | 2020-04-29 | 2022-04-01 | 西南电子技术研究所(中国电子科技集团公司第十研究所) | 集成垂直过渡功分器 |
US11177547B1 (en) * | 2020-05-05 | 2021-11-16 | Raytheon Company | Three-dimensional branch line coupler |
JP2022121965A (ja) * | 2021-02-09 | 2022-08-22 | 住友電気工業株式会社 | ウィルキンソン分配器、ウィルキンソン合成器、及び増幅器 |
CN115588833A (zh) * | 2021-07-05 | 2023-01-10 | 中兴通讯股份有限公司 | 内层带状功分器电路及功分器系统 |
CN117280541A (zh) * | 2022-02-09 | 2023-12-22 | 株式会社藤仓 | 分离器-组合器和级联连接电路 |
CN114976554A (zh) * | 2022-06-21 | 2022-08-30 | 中国电子科技集团公司第五十五研究所 | 一种基于P波段的小型化大功率Wilkinson功分器 |
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JP2016052111A (ja) | 2014-09-02 | 2016-04-11 | 株式会社東芝 | インピーダンス変換器 |
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- 2017-02-02 CN CN201780032824.9A patent/CN109314300B/zh active Active
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JP2000106501A (ja) | 1998-09-28 | 2000-04-11 | Matsushita Electric Ind Co Ltd | 電力分配回路、電力合成回路 |
JP2000307313A (ja) * | 1999-04-16 | 2000-11-02 | Mitsubishi Electric Corp | 電力分配合成器 |
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JP7000589B2 (ja) | 2018-02-28 | 2022-01-19 | レイセオン カンパニー | アディティブ製造技術(amt)低プロファイル信号分割器 |
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EP3444892A1 (en) | 2019-02-20 |
EP3444892A4 (en) | 2019-04-24 |
JP6395980B2 (ja) | 2018-09-26 |
CN109314300A (zh) | 2019-02-05 |
JPWO2017208499A1 (ja) | 2018-11-29 |
EP3444892B1 (en) | 2021-03-24 |
US20200235456A1 (en) | 2020-07-23 |
WO2017208432A1 (ja) | 2017-12-07 |
CN109314300B (zh) | 2021-06-01 |
US10930995B2 (en) | 2021-02-23 |
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